Low temperature n-type contact epitaxial growth

Abstract

A method for forming a semiconductor structure and the semiconductor structure are described. The method includes non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source / drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400° C. The method can be performed in a processing chamber without breaking vacuum.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device fabrication. More particularly, embodiments of the present disclosure relate to an integrated method for n-type contact formation. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased.

[0003] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to the transistor's gate width, so faster transistors generally require larger gate widths. This creates a tradeoff between transistor size and speed, and "fin" field effect transistors (finFETs) have been developed to address the conflicting goals of transistors with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that significantly increases the size of a transistor without significantly increasing the transistor's footprint, and are currently being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0004] As transistor device feature sizes continue to shrink to achieve higher circuit density and higher performance, there is a need to improve transistor device structures to improve capacitive coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (finFET) structures, and gate-all-around (GAA) structures. Logic gate performance is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, challenges arise as some gate characteristics are adjusted to accommodate device scaling.

[0005] To form the n-type contact, an n-type epitaxial layer growth may be used after the contact trench is etched. For this epitaxial layer, a multi-step (multi consisting of between 1 and 5 cycles) cyclic process is used to selectively form the n-type contact. The throughput of this cyclic process is determined by the trade-off between the deposition rate and the selective amorphous silicon etch rate. Lower temperatures result in a reduction in both the deposition rate and the etch rate, and therefore the cyclic process needs to be performed at a temperature of at least 470° C. Thus, there is a need in the art for a method of forming n-type contacts at lower temperatures. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method of forming a semiconductor device, the method including non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one feature on a substrate at a temperature less than or equal to 400° C. and a crystalline silicon layer on a bottom surface of at least one feature, and selectively removing the amorphous silicon layer from the top surface and the sidewall surface at a temperature less than or equal to 400° C., wherein the method is performed in a processing chamber without breaking vacuum.

[0007] Another embodiment of the present disclosure is directed to a method of forming a logic device, the method including non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source / drain material, and selectively removing the amorphous silicon layer from the top surface and the sidewall surface at a temperature less than or equal to 400° C., wherein the method is performed in a process chamber without breaking vacuum.

[0008] Further embodiments of the present disclosure are directed to a processing tool comprising a preclean chamber having a substrate support therein, a non-selective silicon deposition chamber, a selective etch chamber, a robot configured to access the preclean chamber, the non-selective deposition chamber, and the selective etch chamber, and a controller connected to the preclean chamber, the non-selective deposition chamber, and the selective etch chamber, the controller having one or more configurations selected from cleaning the substrate, non-selectively forming amorphous and crystalline silicon layers, and selectively etching the substrate, wherein the non-selective deposition chamber and the selective etch chamber are continuously held at a vacuum.

[0009] So that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be made by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a process flow diagram of a method according to one or more embodiments of the present disclosure. [Diagram 2] FIG. 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Diagram 3] FIG. 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 illustrates a semiconductor structure in accordance with one or more embodiments of the present disclosure. [Diagram 5] FIG. 1 illustrates a cluster tool in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the accompanying figures, similar components and / or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. When only a first reference label is used in this specification, the description is applicable to any of the similar components that have the same first reference label, regardless of the second reference label.

[0012] Before describing several example embodiments of the invention, it is to be understood that the invention is not limited to the details of construction or process steps set forth in the following description, as the invention is capable of other embodiments and of being practiced or of being carried out in various ways.

[0013] As used herein, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. Those skilled in the art will also understand that a reference to a substrate may also refer to only a portion of the substrate, unless the context clearly dictates otherwise. Additionally, a reference to depositing on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0014] Additionally, the term "substrate" as used herein refers to a substrate or material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces on which treatment may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, dielectric materials, other conductive materials, or combinations thereof, depending on the application. In some embodiments, the substrate is silicon (Si), ruthenium (Ru), cobalt (Co), tungsten (W), silicon phosphide (SiP), titanium silicon (TiSi), titanium nitride (TiN), titanium aluminide (TiAl), silicon germanium (SiGe), silicon germanium boron (SiGeB), hafnium oxide (HfO), or the like. 2 ), aluminum oxide (Al 2 O 3 ) or combinations thereof. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to film treatments performed directly on the substrate surface itself, in the present disclosure, any of the disclosed film treatment steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include underlayers as the context dictates.

[0015] According to one or more embodiments, the term "on" with respect to a film or layer of a film includes that the film or layer is directly on a surface, e.g., a substrate surface, as well as that there are one or more underlayers between the film or layer and the surface, e.g., the substrate surface. Thus, in one or more embodiments, the phrase "on the substrate surface" is intended to include one or more underlayers. In other embodiments, the phrase "directly on" refers to a layer or film in contact with a surface, e.g., a substrate surface, without an intervening layer. Thus, the phrase "a layer directly on the substrate surface" refers to a layer in direct contact with the substrate surface, without an intervening layer.

[0016] As used herein, the term "substrate surface" refers to any substrate surface on which a layer may be formed. A substrate surface may have one or more features formed therein, one or more layers formed thereon, and combinations thereof. The shape of a feature may be any suitable shape, including, but not limited to, a peak, a trench, and a cylindrical via. As used in this regard, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, a trench having a top, two sidewalls, and a bottom, a peak having a top and two sidewalls extending upward from the surface, and a via having a sidewall extending downward from the surface with an open bottom.

[0017] As used herein, the term "processing chamber" includes a portion of the processing chamber adjacent to the substrate surface without encompassing the entire internal volume of the processing chamber. For example, in spatially separated processing chamber sectors, the portion of the processing chamber adjacent to the substrate surface is purged by any suitable technique, including, but not limited to, moving the substrate through a gas curtain to a portion or sector of the processing chamber that contains no or substantially no reactive compounds.

[0018] As used herein, the term "atomic layer deposition" or "cyclic deposition" refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or portions of the substrate surface, are sequentially exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. The sequential exposure of the reactive gases prevents or minimizes gas-phase reactions between the reactive gases. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay to allow each compound to attach to and / or react on the substrate surface. In a spatial ALD process, different portions of the substrate surface or materials on the substrate surface are simultaneously exposed to two or more reactive compounds such that a given point on the substrate is not substantially exposed to two or more reactive compounds at the same time. The term "substantially" used in this respect, as used herein and in the appended claims, means that it is possible that small portions of the substrate may be exposed to multiple reactive gases at the same time due to diffusion, as would be understood by one of ordinary skill in the art, and that simultaneous exposure is not intended.

[0019] In one aspect of a time-domain ALD process, a first reactive gas (in other words, a first precursor or compound A) is pulsed into the reaction zone, followed by a first time delay. Then, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the process chamber to purge the reaction zone or otherwise remove residual reactive compounds or byproducts from the reaction zone. Alternatively, the purge gas can flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either scenario, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle can begin with either compound A or compound B, and continue with each order of the cycle until a film with a desired thickness is achieved. In one or more embodiments, a time-domain ALD process can be performed with three or more reactive compounds in a predetermined order.

[0020] In aspects of spatial ALD processes, a first reactive gas and a second reactive gas are simultaneously supplied to a reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply such that a given point on the substrate is exposed to the first reactive gas and the second reactive gas. In one or more embodiments, a spatial ALD process can be performed with three or more reactive compounds in a predetermined order.

[0021] In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially continuously. As used herein throughout this specification, "substantially continuously" means that the majority of the duration of the first reactive compound exposure does not overlap with the second reactive compound exposure, although there may be some overlap.

[0022] As used herein, the term "chemical vapor deposition" refers to the exposure of at least one reactive compound to deposit a layer of material on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive compounds in a processing chamber to allow for gas phase reaction and deposition of the reactive compounds. In some embodiments, the CVD process includes exposing the substrate surface to two or more reactive compounds simultaneously. In some embodiments, the CVD process includes exposing the substrate surface to a first reactive compound continuously with intermittent exposure to a second reactive compound. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a film having a predetermined thickness. In a CVD process, the film may be deposited in one exposure to the mixed reactive compounds or may be multiple exposures to the mixed reactive compounds with purges in between. In some embodiments, the substrate surface is exposed to the first reactive compound and the second reactive compound substantially simultaneously.

[0023] As used herein throughout the specification, "substantially simultaneously" means that the majority of the duration of the first reactive compound exposure overlaps with the second reactive compound exposure.

[0024] As used herein, the term "purging" includes any suitable purging process that removes unreacted precursors, reaction products, and by-products from the process region. A suitable purging process includes moving the substrate through a gas curtain to a portion or sector of the processing region that contains no or substantially no reactants. In one or more embodiments, purging the processing chamber includes applying a vacuum. In some embodiments, purging the processing region includes flowing a purge gas over the substrate. In some embodiments, the purge process includes flowing an inert gas. In one or more embodiments, the purge gas is nitrogen (N 2), helium (He), and argon (Ar). In some embodiments, the first reactive compound is purged from the reaction chamber for a duration in the range of 0.2 to 30 seconds, 0.2 to 10 seconds, 0.2 to 5 seconds, 0.5 to 30 seconds, 0.5 to 10 seconds, 0.5 to 5 seconds, 1 to 30 seconds, 1 to 10 seconds, 1 to 5 seconds, 5 to 30 seconds, 5 to 10 seconds, or 10 to 30 seconds prior to exposing the substrate to the second reactive compound.

[0025] As used herein, the term "liner" or "barrier layer" refers to a layer conformally formed along at least a portion of the sidewall and / or lower surface of an opening such that a substantial portion of the opening prior to deposition of the layer remains unfilled after deposition of the layer. The liner may be formed along the entirety of the sidewall and lower surface of the opening. The liner may be formed by any process known to one of skill in the art. In some embodiments, the liner comprises a metal nitride, a PVD metal, or a combination thereof.

[0026] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). A MOSFET has an insulated gate, the voltage across which determines the conductivity of the device. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals.

[0027] Generally, a transistor includes a gate formed between a source region and a drain region. The source and drain regions may include doped regions of a substrate and may exhibit a doping profile suitable for a particular application. The gate is disposed above a channel region and may include a gate dielectric interposed in the substrate between the gate electrode and the channel region.

[0028] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Field effect transistors generally exhibit extremely high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, created by the voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel, the drain (D), through which carriers exit the channel, and the gate (G), the terminal that modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is known as I S The current entering the channel at the drain (D) is I D The drain-source voltage is expressed as V DS By applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0029] A metal oxide semiconductor field effect transistor (MOSFET) is a type of field effect transistor (FET) used in integrated circuits and high speed switching applications. A MOSFET has an insulated gate, the voltage across which determines the conductivity of the device. This ability to change the conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal oxide semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body, insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to an individual highly doped region separated by a body region. These regions can be either p-type or n-type, but they are both of the same type, opposite the type of the body region. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the type of doping.

[0030] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; analogously, the drain is where the charge carriers exit the channel.

[0031] An nMOS FET consists of an n-type source and drain and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is carried by electrons from source to drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three modes of operation called cutoff, triode, and saturation. Because DC current flows through the logic gate when the output is low, circuits with NMOS logic gates dissipate static power when the circuit is idling.

[0032] A pMOS FET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage is applied between the gate and source), a p-type channel is formed between the source and drain with the opposite polarity. Current is carried by holes from the source to the drain through the induced p-type channel. A high voltage on the gate causes the PMOS to not conduct, and a low voltage on the gate causes the PMOS to conduct. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low cost and has good noise immunity.

[0033] In NMOS, the carriers are electrons, whereas in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts and PMOS does not. Moreover, when a low voltage is applied at the gate, NMOS does not conduct and PMOS conducts. Since the carriers in NMOS, which are electrons, travel twice as fast as the holes, which are the carriers in PMOS, NMOS is considered to be faster than PMOS. However, PMOS devices are less susceptible to noise than NMOS devices. Moreover, NMOS can provide half the impedance provided by PMOS (with the same geometry and operating conditions), so NMOS ICs can be smaller than PMOS ICs (giving the same functionality).

[0034] As used herein, the term "fin field effect transistor (FinFET)" refers to a MOSFET transistor constructed on a substrate in which the gate is placed on two, three, or four sides of the channel or wrapped around the channel to form a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form "fins" on the substrate. FinFET devices have fast switching times and high current densities.

[0035] As used herein, the term "gate-all-around (GAA)" is used to refer to an electronic device, e.g., a transistor, in which a gate material surrounds a channel region on all sides. The channel region of a GAA transistor may comprise a nanowire or nanoslab or nanosheet, a bar-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has multiple horizontal nanowires or bars spaced apart vertically, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0036] The embodiments of the present disclosure provide semiconductor structures and methods for forming semiconductor structures. In one or more embodiments, since an exchange metal gate is formed before the contact epi, a lower temperature (400° C. or less) n-type contact epi (SiP) is desired for NMOS source / drain contact epi formation using the exchange metal gate scheme. At temperatures below 400° C., the amorphous silicon selective etchback rate is almost zero, so the current baseline two-step cyclic process has no selectivity. This results in amorphous silicon on the sidewalls and top of the contact trench that needs to be removed later. At 400° C.-500° C., the amorphous silicon etchback rate is extremely slow, causing etch times to be several hours. Such throughput is not acceptable for customers. Thus, in one or more embodiments, an integrated solution for n-type contact epi formation at low temperatures (<400° C.) with reasonable throughput is advantageously provided. One or more embodiments provide a selective etch process for selectively etching amorphous SiP relative to crystalline SiP at low temperatures (below 400° C.) for better etch rate and process optimization. In one or more embodiments, non-selective low temperature n-type SiP epi and selective etch are integrated in one cluster tool system for better throughput and to enable cyclic processes. The system of one or more embodiments advantageously allows the user to choose between crystalline to amorphous selectivity or amorphous to crystalline selectivity. In one or more embodiments, a method is provided for etching an amorphous layer without etching a crystalline layer. In other embodiments, etching a crystalline layer without etching an amorphous layer is provided.

[0037] The embodiments of the present disclosure are described through diagrams illustrating a process for forming an nFET.

[0038] FIG. 1 illustrates a process flow diagram of a method 10 of fabricating an electronic device according to one or more embodiments of the present disclosure. With reference to FIG. 1, the method begins in operation 15 by providing a substrate. As used herein, the term "provided" means that the substrate is made available for processing (e.g., placed in a processing chamber). In operation 20, an amorphous silicon layer is non-selectively deposited on a top surface and a sidewall surface of at least one feature on the substrate, and a crystalline silicon layer is non-selectively deposited on a bottom surface of the at least one feature. In operation 25, the amorphous silicon layer is selectively removed from the top surface and the sidewall surface of the at least one feature.

[0039] 2-4 are cross-sectional views of an electronic device (e.g., a transistor, such as a FinFET or GAA) 100 according to one or more embodiments. The electronic device 100 shown in FIGS. 2-4 may be fabricated by the method 10 shown in FIG.

[0040] In one or more embodiments, the electronic device 100 comprises a semiconductor substrate 102. The semiconductor substrate 102 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 102 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the semiconductor substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Several examples of materials from which the substrate 102 may be formed are described herein, however, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

[0041] In one or more embodiments, the semiconductor substrate 102 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to a well of positive charge (or holes). In contrast to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the semiconductor substrate 102 is an n-type substrate.

[0042] In one or more embodiments, the source / drain region 105 is on an upper surface of the semiconductor substrate 102. In one or more embodiments, the source / drain region 105 can be any suitable material known to one of ordinary skill in the art. In one or more embodiments, the source / drain region 105 can have two or more layers. For example, the source / drain region 105 can independently comprise three layers. In one or more embodiments, the source / drain region 105 can independently include one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorous (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source / drain regions 105 may independently comprise a bottom layer of silicon (e.g., SiGe, SiP, etc.) with doped epi, a second layer of a silicide that may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal such as, but not limited to, cobalt, tungsten, ruthenium, etc. In some embodiments, the source / drain regions 105 may be raised source / drain regions formed by epi growth.

[0043] In one or more embodiments, the source / drain material 105 may have two or more layers. In some embodiments, the source / drain material 105 comprises a layer of silicon (e.g., SiGe, SiP, etc.) with doped epi, a second layer of a silicide that may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third or top layer that may be a metal, such as, but not limited to, cobalt, tungsten, ruthenium, etc.

[0044] In one or more particular embodiments, the source / drain material 105 of the n-transistor comprises silicon (Si) doped with phosphorus (P). In one or more embodiments, the source / drain material 105 of the n-transistor 102 has a bandgap in the range of about 1.0 eV to about 1.2 eV.

[0045] 2-4 show the substrate 102 with a single feature 112 for purposes of illustration, but one of ordinary skill in the art will understand that there can be more than one feature. The shape of the feature 112 can be any suitable shape, including, but not limited to, trenches and cylindrical vias. As used in this regard, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, and peaks having a top and two sidewalls. The features can have any suitable aspect ratio (ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0046] In one or more embodiments, the substrate 102 has a substrate surface. At least one feature 112 forms an opening in the substrate surface. At least one feature 112 extends from the substrate surface toward a feature depth to a bottom surface. At least one feature 112 has a first sidewall and a second sidewall that define a width W of the at least one feature 112. The open area formed by the sidewall and the bottom is also referred to as a gap. In one or more embodiments, the width W is uniform along the depth of the at least one feature 112. In other embodiments, the width (W) is greater at the top of the at least one feature 112 than the width (W) at the bottom surface of the at least one feature 112.

[0047] In one or more embodiments, at least one feature 112 comprises a source / drain trench. The first and second sidewalls may comprise one or more of a replacement metal gate 104, a dielectric gate cap 106, a gate liner 108, and a low-k spacer 110. In one or more embodiments, the replacement metal gate 104 includes a high-k dielectric and metal layer required to set the metal gate work function. In one or more embodiments, the dielectric gate cap 106 provides protection for the metal gate layer against polishing and plasma etch steps. The dielectric gate cap 106 may include any suitable dielectric material known to those skilled in the art. In one or more embodiments, the dielectric gate cap 106 is made of a material such as, but not limited to, silicon nitride (SiN) or silicon oxide (SiO x In one or more embodiments, the gate liner 110 comprises a thin silicon oxide or silicon nitride. In one or more embodiments, the low-k spacer 110 comprises one or more of silicon oxycarbonitride (SiOCN), boron-doped silicon oxycarbonitride (SiOCBN), and silicon oxynitride (SiON).

[0048] 3, in one or more embodiments, an amorphous silicon layer 114 is non-selectively deposited on a top surface and sidewall surfaces of at least one contact trench 112 on a substrate 102. In one or more embodiments, a crystalline silicon layer 116 is non-selectively deposited on a bottom surface of at least one contact trench 112, the bottom surface including the source / drain material 105. In one or more embodiments, the non-selective deposition is performed at a temperature less than or equal to 400° C. In other embodiments, the non-selective deposition is performed at a temperature less than or equal to 400° C., including in a range of 0° C. to 375° C., or in a range of 10° C. to 350° C., or in a range of 350° C. to 400° C.

[0049] In one or more particular embodiments, the amorphous silicon layer 114 is doped with an n-type dopant. In one or more embodiments, the n-type dopant includes phosphorus (P). Thus, in one or more embodiments, the amorphous silicon layer 114 includes silicon (Si) or silicon phosphide (SiP) doped with phosphorus (P). In one or more particular embodiments, the crystalline silicon layer 116 is doped with an n-type dopant. In one or more embodiments, the n-type dopant includes phosphorus (P). Thus, in one or more embodiments, the crystalline silicon layer 116 includes silicon (Si) or silicon phosphide (SiP) doped with phosphorus (P), silicon doped with arsenic (As), or silicon doped with antimony (Sb).

[0050] 4, in one or more embodiments, the amorphous silicon layer 114 is selectively removed from the top and sidewall surfaces of the contact trench 112, and the crystalline silicon layer 116 remains on the source / drain region 105. In one or more embodiments, the amorphous silicon layer 114 is selectively removed at a temperature less than or equal to 400° C. In one or more embodiments, the amorphous silicon layer 114 is selectively removed at a temperature in the range of 50° C. to 200° C. In one or more embodiments, the amorphous silicon layer 114 is selectively removed at a temperature in the range of 0° C. to 20° C.

[0051] The amorphous silicon layer 114 may be removed at any suitable pressure and power. In some embodiments, the selective removal of the amorphous crystalline layer is performed at a pressure in the range of 1 Torr to 10 Torr and at a power in the range of 100 W to 500 W.

[0052] In one or more embodiments, the amorphous silicon layer 114 may be selectively removed by any suitable means known to those of skill in the art. In one or more embodiments, the amorphous silicon layer 114 may be selectively removed by flowing hydrogen (H2 ) and ammonium fluoride (NF 3 In another embodiment, the selective removal is achieved by etching with a gas flow containing a mixture of ammonium fluoride (NF 3 The method includes etching using a gas flow containing a mixture of nitrogen (N) and helium (He) and argon (Ar).

[0053] In one or more particular embodiments, the amorphous silicon layer 114 is selectively removed at a temperature in the range of 50° C. to 200° C., at a pressure in the range of 1 Torr to 10 Torr, and at a power in the range of 100 W to 500 W, where the selective removal is performed by removing hydrogen (H 2 ) and ammonium fluoride (NF 3 ) in a gas flow containing a mixture of

[0054] In another particular embodiment, the amorphous silicon layer 114 is selectively removed at a temperature in the range of 0° C. to 20° C., at a pressure in the range of 1 Torr to 10 Torr, and at a power in the range of 100 W to 500 W, where the selective removal is performed by using ammonium fluoride (NF 3 The method includes etching using a gas flow containing a mixture of nitrogen (N) and helium (He) and argon (Ar).

[0055] The amorphous silicon layer 114 may be removed using any suitable removal technique known to one of ordinary skill in the art, including, but not limited to, wet etching, steam etching, isotropic plasma etch, or any other selective removal process (SRP). In one or more embodiments, the amorphous silicon layer 114 is removed with a selectivity to the crystalline silicon layer 116 in a ratio ranging from 2:1 to 20:1. This results in an etch rate of the amorphous silicon layer 114 ranging from more than two times faster (2:1) to more than twenty times faster (20:1) compared to the etch rate of the crystalline silicon layer 116.

[0056] In one or more embodiments, the method is performed in a processing chamber without breaking vacuum, whereby the non-selective deposition and selective removal processes are performed in the processing chamber without breaking vacuum.

[0057] In that case, processing may proceed according to standard procedures involving the formation of source / drain contacts on the crystalline silicon layer 116. In one or more embodiments, the source / drain contacts may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source and / or drain contacts is performed by any suitable process known to those of skill in the art, including, but not limited to, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those of skill in the art.

[0058] Additional embodiments of the present disclosure are directed to a processing tool 300 for the formation of the described GAA devices and methods, shown in FIG. 5. A variety of multi-processing platforms may be utilized, including Reflexion® CMP, Selectra® Etch, Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®, as well as other processing systems. The cluster tool 300 includes at least one central transfer station 314 with multiple sides. A robot 316 is disposed within the central transfer station 314 and configured to move the robot blade and wafer to each of the multiple sides.

[0059] The cluster tool 300 includes multiple processing chambers 308, 310, and 312, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing regions separated from adjacent process stations. The processing chambers can be any suitable chambers, including, but not limited to, pre-clean chambers, non-selective deposition chambers, selective removal chambers, and the like. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the present disclosure. In one or more embodiments, the non-selective deposition chambers and the selective etch chambers are continuously held at vacuum.

[0060] 5, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading to a front 319 of the factory interface 318.

[0061] The size and shape of the loading and unloading chambers 302 may vary depending on, for example, the substrate being processed in the cluster tool 300. In the embodiment shown, the loading and unloading chambers 302 are sized to hold a wafer cassette with multiple wafers disposed within the cassette.

[0062] A robot 304 resides in a factory interface 318 and can move between the loading and unloading chambers 302. The robot 304 can transfer wafers from a cassette in the loading chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 can also transfer wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unloading chamber 302.

[0063] The robot 316 in some embodiments is a multi-arm robot capable of independently moving two or more wafers at a time. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Individual wafers are carried on a wafer transport blade located at the distal end of the first robotic mechanism.

[0064] A system controller 357 is in communication with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 can be a computer that includes a central processing unit (CPU) 392, memory 394, input / output 396, suitable circuitry 398, and storage.

[0065] The processes may generally be stored in the memory of the system controller 357 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may be implemented in hardware. Thus, the processes may be implemented in software and executed using a computer system, or may be implemented in hardware, for example, as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the chamber operation so that the processes are performed.

[0066] In some embodiments, the system controller 357 has a configuration for controlling the non-selective deposition chamber to deposit an amorphous silicon layer and a crystalline silicon layer.

[0067] In one or more embodiments, the processing tool comprises a central transfer station comprising a robot configured to move the wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations comprising pre-clean chambers, non-selective deposition chambers, selective removal chambers, etc.; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between the process stations and to control the process performed at each of the process stations.

[0068] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the claims below) should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. The recitation of ranges of values ​​herein is only intended to serve as a shorthand method of individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by the context. The use of any and all examples or illustrative language (e.g., "etc.") provided herein is only intended to better illuminate the materials and methods, and does not impose limitations on the scope, unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0069] References throughout this specification to "one embodiment," "some embodiments," "one or more embodiments," or "embodiments" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Moreover, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0070] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Thus, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, the method comprising: non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one feature on a substrate and a crystalline silicon layer on a bottom surface of said at least one feature at a temperature less than or equal to 400° C.; selectively removing the amorphous silicon layer from the top surface and the sidewall surface at a temperature less than or equal to 400° C.; Including, wherein the method is carried out in a processing chamber without breaking vacuum; method.

2. 10. The method of claim 1, wherein the selective removal is performed at a power in the range of 100 W to 500 W and a pressure in the range of 1 Torr to 10 Torr.

3. The method of claim 2, wherein the temperature is in the range of 50° C. to 200° C.

4. 3. The method of claim 2, wherein the temperature is in the range of 0°C to 20°C.

5. The selective removal of hydrogen (H ２ ) and ammonium fluoride (NF ３ 3. The method of claim 2, further comprising etching with a gas flow comprising a mixture of

6. The selective removal includes removing ammonium fluoride (NF ３ 5. The method of claim 4, further comprising etching with a gas flow comprising a mixture of nitrogen (N), helium (He) and argon (Ar).

7. 2. The method of claim 1, wherein the selective removal is selective to the amorphous silicon layer in a ratio within a range of 2:1 to 20:

1.

8. The method of claim 1 , wherein one or both of the amorphous silicon layer and the crystalline silicon layer are doped with an n-type dopant.

9. The method of claim 8 , wherein the n-type dopant comprises phosphorus (P).

10. 1. A method of forming a logic device, the method comprising: non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400° C., the bottom surface including a source / drain material; selectively removing the amorphous silicon layer from the top surface and the sidewall surface at a temperature less than or equal to 400° C.; Including, wherein the method is carried out in a processing chamber without breaking vacuum; method.

11. 11. The method of claim 10, wherein the selective removal is performed at a power in the range of 100 W to 500 W and a pressure in the range of 1 Torr to 10 Torr.

12. The method of claim 11 , wherein the temperature is in the range of 50° C. to 200° C.

13. 12. The method of claim 11, wherein the temperature is in the range of 0°C to 20°C.

14. The selective removal of hydrogen (H ２ ) and ammonium fluoride (NF ３ 12. The method of claim 11, comprising etching with a gas flow comprising a mixture of

15. The selective removal includes removing ammonium fluoride (NF ３ 14. The method of claim 13, comprising etching with a gas flow comprising a mixture of nitrogen (N), helium (He) and argon (Ar).

16. 11. The method of claim 10, wherein the selective removal is selective to the amorphous silicon layer in a ratio within a range of 2:1 to 20:

1.

17. The method of claim 10 , wherein one or both of the amorphous silicon layer and the crystalline silicon layer are doped with an n-type dopant.

18. The method of claim 17 , wherein the n-type dopant comprises phosphorus (P).

19. The method of claim 10 , wherein the logic device comprises an nMOS.

20. a pre-clean chamber having a substrate support therein; a non-selective silicon deposition chamber; a selective etching chamber; a robot configured to access the pre-clean chamber, the non-selective silicon deposition chamber, and the selective etch chamber; a controller connected to the pre-clean chamber, the non-selective silicon deposition chamber, and the selective etching chamber, the controller having one or more configurations selected from cleaning a substrate, non-selectively forming amorphous and crystalline silicon layers, and selectively etching the substrate; Equipped with wherein the non-selective silicon deposition chamber and the selective etching chamber are continuously maintained at a vacuum. Processing tools.

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