Support shield structure for trench type semiconductor devices

Abstract

The power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface between the sidewalls. A bottom shielding structure of a second conductivity type is disposed below the bottom surface of the gate trench. First and second supporting shielding structures of the second conductivity type extend into the drift region on either side of the gate trench and are spaced apart from the sidewalls of the gate trench. The material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and / or dopant concentration of the bottom shielding structure may differ from that of the first and second supporting shielding structures. Related devices and methods of manufacture are also discussed.

Description

[Technical field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 703,708, filed March 24, 2022, the disclosure of which is incorporated herein by reference.

[0002] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices. [Background technology]

[0003] A power semiconductor device refers to a device that includes one or more "power" semiconductor dies that are designed to pass large currents (e.g., tens or hundreds of amperes) and / or can block high voltages (e.g., hundreds, thousands, or tens of thousands of volts). A wide variety of power semiconductor devices are known in the art, including, for example, power metal-insulator-semiconductor field effect transistors ("MISFETs," including metal-oxide-semiconductor FETs ("MOSFETs")), bipolar junction transistors ("BJTs"), insulated-gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS-controlled thyristors, and various other devices. These power semiconductor devices are typically fabricated from wide bandgap semiconductor materials, such as silicon carbide ("SiC") or Group III-nitride (e.g., gallium nitride ("GaN")-based semiconductor materials. Here, wide bandgap semiconductor materials refer to semiconductor materials having a bandgap greater than about 1.40 eV, e.g., greater than about 2 eV.

[0004] A conventional power semiconductor device typically has a semiconductor substrate having a first conductivity type (e.g., n-type substrate) on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. A portion of this epitaxial layer structure (which may include one or more separate layers) serves as the drift layer or drift region of the power semiconductor device. The device typically includes an "active region" that includes one or more "unit cell" structures having junctions, e.g., p-n junctions. The active region may be formed on and / or within the drift region. The active region serves as a primary junction to block voltage in a reverse bias direction and provide current in a forward bias direction. The power semiconductor device may also have edge terminations in a termination region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, with each power semiconductor device typically having its own edge termination. After the substrate is fully processed, the resulting structure may be cut to separate the individual edge-terminated power semiconductor devices.

[0005] A power semiconductor device may have a unit cell configuration, in which many individual unit cell structures of an active region are electrically connected (e.g., in parallel) to function as one power semiconductor device. In high power applications, such a power semiconductor device may include thousands or tens of thousands of unit cells packaged in one chip or "die." A die or chip may include a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. For example, a plurality of individual power semiconductor devices may be formed on a relatively large semiconductor substrate (e.g., by growing epitaxial layers thereon, doping selected regions with dopants, forming insulating and metal layers thereon, etc.), and the completed structure may then be cut (e.g., by a sawing or dicing process) into a plurality of individual dies, each die being a power semiconductor device.

[0006] A power semiconductor device can have a lateral or vertical structure. In a device having a lateral structure, the terminals of the device (e.g., drain, gate and source terminals for a power MOSFET device) are on the same major surface (e.g., top or bottom) of a semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each major surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include an underlying substrate. Herein, the term "semiconductor layer structure" refers to a structure that includes one or more semiconductor layers, including a semiconductor substrate and / or a semiconductor epitaxial layer.

[0007] Vertical power semiconductor devices, such as MOSFET or IGBT devices, may have a standard gate electrode design, where the gate electrode of the transistor is formed on the top side of a semiconductor layer structure, or alternatively, may have the gate electrode buried in a trench in the semiconductor layer structure. Devices with a buried gate electrode are usually called gate trench devices. In the case of a standard gate electrode design, the channel region of each unit cell transistor is horizontally located under the gate electrode. In contrast, in a gate trench design, the channel is vertically located. Gate trench devices may offer improved performance, but usually require more complicated manufacturing processes.

[0008] Power semiconductor devices are designed to block (forward or reverse blocking state) or pass (forward operating state) large voltages and / or currents. For example, in the blocking state, a power semiconductor device may be designed to maintain a potential of hundreds or thousands of volts. When the applied voltage approaches or exceeds the voltage level that the device is designed to block, a non-trivial level of current (called leakage current) may begin to flow in the power semiconductor device. The blocking capability of the device may be a function of the doping density / concentration and the drift region thickness, among other things. Leakage current may also result from other reasons, such as failure of edge terminations and / or primary junctions of the device. When the voltage applied to the device is increased beyond the breakdown voltage to a critical level, the increasing electric field may cause undesirable uncontrolled runaway generation of charge carriers in the semiconductor device, leading to a condition known as avalanche breakdown.

[0009] Also, the relatively thin gate insulating layer (e.g., a gate oxide layer) that separates the gate electrode from the semiconductor layer structure can degrade when the gate insulating layer is exposed to high electric field levels during on-state (conducting) or off-state (blocking) operation. This degradation of the gate insulating layer can eventually lead to dielectric breakdown of the gate insulating layer, at which point the gate electrode can short to the semiconductor layer structure, which can destroy the device. Summary of the Invention [Means for solving the problem]

[0010] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type, a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls, a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench, and first and second supporting shielding structures of the second conductivity type extending into the drift region on either side of the gate trench and spaced apart from the sidewalls of the gate trench.

[0011] In some embodiments, one or more of the first and second supporting shielding structures extend into the drift region to a depth relative to a surface of the semiconductor layer structure that is different from a depth of the bottom shielding structure.

[0012] In some embodiments, the first and second supporting shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 micron.

[0013] In certain embodiments, at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure comprises a material that is different from a material of the drift region.

[0014] In some embodiments, the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0015] In certain embodiments, at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure further comprises an implanted portion of the drift region.

[0016] In some embodiments, the bottom shielding structure includes a first concentration of a dopant of a second conductivity type, and the first and second supporting shielding structures include a second concentration of a dopant of the second conductivity type that is different from the first concentration.

[0017] In some embodiments, the second concentration is greater than the first concentration.

[0018] In some embodiments, the semiconductor layer structure further includes a substrate having a drift region thereon and a well region of a second conductivity type in or on the drift region opposite the substrate, the first and second supporting shielding structures extending through the well region and beyond the bottom shielding structure and spaced apart from the substrate.

[0019] In some embodiments, the first and second supporting shielding structures have a different concentration of dopants of the second conductivity type than the well region.

[0020] In certain embodiments, the first and second supporting shielding structures are spaced from the substrate by about 1 to about 100 microns.

[0021] In some embodiments, the bottom shielding structure extends along a portion of the bottom surface of the gate trench.

[0022] In some embodiments, the bottom shielding structure extends along the entire bottom surface of the gate trench.

[0023] According to some embodiments, a power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type, a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls, a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench, and first and second supporting shielding structures of the second conductivity type extending into the drift region on either side of the gate trench and spaced apart from the sidewalls of the gate trench, the bottom shielding structure having a material composition, a distance of extension into the drift region relative to a surface of the semiconductor layer structure, and / or a dopant concentration different from that of the first and second supporting shielding structures.

[0024] In some embodiments, one or more of the first and second supporting shielding structures extend a greater distance into the drift region than the bottom shielding structure relative to a surface of the semiconductor layer structure.

[0025] In some embodiments, the first and second supporting shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 micron.

[0026] In certain embodiments, a material composition of at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure differs from a material composition of the drift region.

[0027] In some embodiments, the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0028] In certain embodiments, at least one of the bottom shielding structure, the first supporting shielding structure, or the second supporting shielding structure further comprises an implanted region of the drift region.

[0029] In some embodiments, the dopant concentration of the first and second supporting shielding structures is less than the dopant concentration of the bottom shielding structure.

[0030] In some embodiments, the dopant concentration of the first and second supporting shielding structures is greater than the dopant concentration of the bottom shielding structure.

[0031] In certain embodiments, the semiconductor layer structure further comprises a substrate having a drift region thereon, and the first and second supporting shielding structures are spaced apart from the substrate by about 1 to about 100 microns.

[0032] According to some embodiments, a method of manufacturing a power semiconductor device includes providing a semiconductor layer structure including a drift region of a first conductivity type; forming a bottom shielding structure and first and second supporting shielding structures of a second conductivity type extending into the drift region; and forming a gate trench extending into the drift region and spaced from the first and second supporting shielding structures, the bottom shielding structure underlying the gate trench.

[0033] In some embodiments, forming the gate trench is performed after forming the bottom shielding structure.

[0034] In some embodiments, forming the bottom shielding structure and the first and second supporting shielding structures includes forming one or more of the first and second supporting shielding structures to extend into the drift region to a depth different from a depth of the bottom shielding structure relative to a surface of the semiconductor layer structure.

[0035] In some embodiments, the first and second supporting shielding structures extend beyond the bottom shielding structure into the drift region by about 0.1 to about 1 micron.

[0036] In certain embodiments, forming at least one of the bottom shielding structure or the first and second supporting shielding structures includes performing one or more etching steps to form a respective shielding trench in the drift region and performing one or more deposition steps to form a material in the respective shielding trench that is different from a material of the drift region.

[0037] In some embodiments, the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shielding structure or the first and second supporting shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0038] In certain embodiments, forming at least one of the bottom shielding structure or the first and second supporting shielding structures further includes performing one or more ion implantation steps to implant dopants of the second conductivity type into portions of the drift region beneath the respective shielding trenches.

[0039] In some embodiments, forming at least one of the bottom shielding structure or the first and second supporting shielding structures includes performing one or more ion implantation steps to implant dopants of the second conductivity type into the drift region.

[0040] In some embodiments, in response to the one or more ion implantation steps, the bottom shielding structure includes a first concentration of the dopant of the second conductivity type, and the first and second supporting shielding structures include a second concentration of the dopant of the second conductivity type that is different from the first concentration, and the second concentration may be greater than the first concentration.

[0041] According to some embodiments, a method of manufacturing a power semiconductor device includes providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second support shielding structures of a second conductivity type extending into the drift region; forming a gate trench extending into the drift region and spaced from the first and second support shielding structures and including sidewalls and a bottom surface between the sidewalls; and forming a bottom shielding structure of the second conductivity type below the bottom surface of the gate trench.

[0042] In some embodiments, forming the bottom shielding structure includes forming the gate trench and then performing one or more ion implantation and / or deposition steps to form a bottom shielding structure extending into the drift region to a first depth relative to a surface of the semiconductor layer structure.

[0043] In some embodiments, the material composition, the distance that it extends into the drift region relative to a surface of the semiconductor layer structure, and / or the dopant concentration of the bottom shielding structure differs from that of the first and second supporting shielding structures.

[0044] In certain embodiments, forming the first and second support shielding structures includes forming one or more of the first and second support shielding structures to extend into the drift region to a second depth relative to a surface of the semiconductor layer structure, the second depth being different from the first depth, prior to forming the gate trench.

[0045] In some embodiments, the second depth is greater than the first depth by about 0.1 to about 1 micron.

[0046] In some embodiments, forming the first and second supporting shielding structures includes performing one or more etching steps to form respective shielding trenches in the drift region prior to forming the gate trenches, and performing one or more deposition steps to form a material in the respective shielding trenches that is different from a material of the drift region.

[0047] In some embodiments, the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shielding structure or the first and second supporting shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0048] In certain embodiments, forming the first and second supporting shielding structures further includes performing one or more ion implantation steps to implant dopants of the second conductivity type into portions of the drift region beneath the respective shielding trenches prior to forming the gate trenches.

[0049] In some embodiments, forming the first and second supporting shielding structures includes performing one or more ion implantation steps to implant dopants of the second conductivity type into the drift region prior to forming the gate trench.

[0050] In some embodiments, in response to the one or more ion implantation processes, the first and second supporting shielding structures include a second concentration of dopants of a second conductivity type that is different from the first concentration of dopants of the second conductivity type in the bottom shielding structure, the second concentration being greater than the first concentration.

[0051] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following figures and detailed description, and all such additional embodiments, in addition to any and all combinations of the above embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims. [Brief description of the drawings]

[0052] [Figure 1A] 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including a shielding region disposed beneath the gate trench. [Figure 1B] 1 is a schematic cross-sectional view illustrating an exemplary unit cell of a gate trench power semiconductor device including a shielding region disposed beneath the gate trench and along one sidewall of the gate trench. [Diagram 2] 1 is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device including a bottom shielding structure beneath the gate trench and a supporting shielding structure spaced from a sidewall of the gate trench, in accordance with some embodiments of the present invention. [Figure 3A]1A-1C are schematic cross-sectional views illustrating example unit cells of a gate trench power semiconductor device including bottom shielding structures and supporting shielding structures in various combinations of different dopant concentrations, depths, and / or material compositions in accordance with some embodiments of the present invention. [Figure 3B] 1A-1C are schematic cross-sectional views illustrating example unit cells of a gate trench power semiconductor device including bottom shielding structures and supporting shielding structures in various combinations of different dopant concentrations, depths, and / or material compositions in accordance with some embodiments of the present invention. [Figure 3C] 1A-1C are schematic cross-sectional views illustrating example unit cells of a gate trench power semiconductor device including bottom shielding structures and supporting shielding structures in various combinations of different dopant concentrations, depths, and / or material compositions in accordance with some embodiments of the present invention. [Figure 3D] 1A-1C are schematic cross-sectional views illustrating example unit cells of a gate trench power semiconductor device including bottom shielding structures and supporting shielding structures in various combinations of different dopant concentrations, depths, and / or material compositions in accordance with some embodiments of the present invention. [Figure 4A] 1A-1C are schematic cross-sectional views illustrating an example unit cell of a gate trench power semiconductor device including bottom and supporting shielding structures of different dopant concentrations and different material compositions in accordance with some embodiments of the present invention. [Figure 4B] 1A-1C are schematic cross-sectional views illustrating an example unit cell of a gate trench power semiconductor device including bottom and supporting shielding structures of different dopant concentrations and different material compositions in accordance with some embodiments of the present invention. [Figure 4C] 1A-1C are schematic cross-sectional views illustrating an example unit cell of a gate trench power semiconductor device including bottom and supporting shielding structures of different dopant concentrations and different material compositions in accordance with some embodiments of the present invention. [Figure 4D]1A-1C are schematic cross-sectional views illustrating an example unit cell of a gate trench power semiconductor device including bottom and supporting shielding structures of different dopant concentrations and different material compositions in accordance with some embodiments of the present invention. [Figure 5A] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 5B] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 5C] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 5D] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 5E] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 5F] 1A-1C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with some embodiments of the present invention. [Figure 6A]10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6B] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6C] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6D] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6E] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6F] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6G] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 6H]10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7A] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7B] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7C] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7D] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7E] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7F] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7G]10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 7H] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8A] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8B] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8C] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8D] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8E] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8F]10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8G] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. [Figure 8H] 10A-10C are schematic cross-sectional views illustrating exemplary manufacturing steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench in accordance with a further embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Some embodiments of the present invention relate to improvements in power semiconductor devices (e.g., MOSFETs, IGBTs, and other gate-controlled power devices). Many power semiconductor devices include so-called deep or "buried" shielding semiconductor regions, also called shielding structures, of a different conductivity type than the layer of semiconductor material beneath the well region and / or gate electrode of the device. For example, in devices having a gate electrode and gate insulating layer formed within a trench in a semiconductor layer structure, high electric fields may degrade the gate insulating layer over time, ultimately resulting in failure of the device. Thus, deep shielding structures may be provided beneath the gate trench to reduce the electric field levels in the gate insulating layer, especially at the corners of the gate trench where the electric field levels may be more concentrated. The shielding structures may have the same conductivity type as the well region, but opposite to the conductivity type of the drift region.

[0054] The deep shielding structure may typically include a heavily doped semiconductor region having the same conductivity type as the channel region. Methods for doping a semiconductor material with n-type and / or p-type dopants include (1) doping the semiconductor material during growth of the semiconductor material, (2) diffusing the dopants into the semiconductor material, and (3) using ion implantation to selectively implant the dopants into the semiconductor material. When silicon carbide is doped during epitaxial growth, the dopants tend to accumulate non-uniformly, which may cause the dopant concentration to vary, for example, by ±15%, which may adversely affect device operation and / or reliability. In addition, doping by diffusion may not be an option in silicon carbide, gallium nitride, and various wide bandgap semiconductor devices because n-type and p-type dopants tend not to diffuse well (or at all) in those materials, even at high temperatures.

[0055] In light of the above, ion implantation is often used to dope wide bandgap semiconductor materials such as silicon carbide. However, in gate-trench vertical power devices (also referred to herein as trench vertical power devices or trench-gate devices), it may be desirable to form deep shielding structures under the well regions and / or gate electrodes of the device, and these deep shielding structures often extend into the device to a depth of about 1-3 microns or more. The depth to which ions are implanted is directly related to the energy of the implantation, i.e., ions implanted into a semiconductor layer at higher energies tend to penetrate deeper into the layer.

[0056] Thus, forming deep shielding structures by ion implantation may require high energy implants. However, when dopant ions are implanted into a semiconductor layer, the ions damage the crystal lattice of the semiconductor layer. This lattice damage can usually only be partially repaired by a thermal annealing process; that is, the lattice damage caused by the ion implantation process may not be completely repaired. Furthermore, the amount of lattice damage may also be directly related to the implantation energy, with higher energy implants tending to produce more lattice damage than lower energy implants. The uniformity of the dopant concentration also tends to decrease as the implantation depth increases.

[0057] A variety of approaches can be used to form trench vertical power semiconductor devices, and Figures 1A and 1B show schematic examples of two different such approaches.

[0058] 1A and 1B are schematic cross-sectional views illustrating an exemplary unit cell of a trench vertical power device (shown as power MOSFETs 100a and 100b, respectively) that includes deeply buried P-type shielding regions 140a and 140b. As shown in FIGS. 1A and 1B, the power MOSFETs 100a and 100b each include a heavily doped (e.g., N + ) a first conductivity type (e.g., n-type) substrate 110. -) A first conductivity type drift layer or region 120 is provided on the substrate 110, for example by epitaxial growth. The drift region 120 may be a wide bandgap semiconductor material (such as silicon carbide (SiC)) in some embodiments. For example, the substrate 110 may be a 4H-SiC substrate and the drift region 120 may be a 4H-SiC n-type epitaxial layer formed on the substrate 110. A portion of the drift region 120 may include a current spreading layer ("CSL") 185 of the first conductivity type having a higher dopant concentration than a lower portion of the drift region 120. A moderately doped second conductivity type (e.g., p-type) layer is formed on or in the drift region 120 (e.g., by epitaxial growth or implantation) and serves as a well region (e.g., "P-type well") 170 for the devices 100a, 100b. Heavily doped second conductivity type (e.g., P + A current spreading layer 185 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 186 is formed in the well region 170. A current spreading layer 185 ...

[0059] 1A and 1B, trenches 180 are formed in the semiconductor layer structure 106, for example in a "striped" gate trench layout in which the trenches 180 extend continuously parallel to one another in a longitudinal direction. The trenches 180 are spaced apart laterally across (e.g., perpendicular to) the longitudinal direction and extend vertically into the drift region 120 towards the substrate 110. The trenches 180 (in which gate electrodes 184 are formed) may be formed to extend through the moderately doped layer 170 to define respective P-type wells. The heavily doped (e.g., P +) Second conductivity type shielding structures 140a, 140b are formed in the drift region 120, for example, by ion implantation. The shielding structures 140a, 140b may be in electrical communication with the P-type well 170. A gate insulating layer 182 (e.g., a gate oxide) is conformally formed on the bottom and sidewalls of each trench 180. Corners of the gate trenches 180 and the overlying gate insulating layer 182 may be rounded, even if shown otherwise.

[0060] A gate electrode 184 (or "gate") is formed on each gate insulating layer 182 to fill the respective gate trench. The portion of drift region 120 under and / or adjacent to gate electrode 184 may be referred to as the "JFET region" 175. A vertical transistor channel region (conduction 178 indicated by dashed arrow) is defined in well region 170 adjacent gate insulating layer 182. A first conductivity type (e.g., N + A heavily doped source region 160 of a second conductivity type (e.g., P + ) contacts well region 170. Source contacts 190 are formed on source region 160, on heavily doped region 174, and (in FIG. 1B) on deep shielding structure 140b. Source contacts 190 may be a resistive metal in some embodiments. Drain contacts 192 are formed on the bottom surface of substrate 110. A gate contact (not shown) may be electrically connected to each gate electrode 184, for example, by a conductive gate bus (not shown). An intermetal dielectric layer 186 may be formed on gate 184, and a metal (e.g., aluminum) layer 196 may be formed on intermetal dielectric layer 186 to contact source contact 190. Source contacts 190 may extend to intermetal dielectric layer 186 in some embodiments and may include, for example, a diffusion barrier and / or an adhesion layer.

[0061] As mentioned above, some devices may be susceptible to premature oxide breakdown due to electric field crowding effects near the corners of the gate trench 180. In the examples of Figures 1A and 1B, deep buried semiconductor regions or shielding patterns 140a, 140b of opposite conductivity type to the drift region 120 are configured to prevent degradation of the trench MOSFETs 100a, 100b at high electric fields. In particular, in the example devices 100a and 100b, the shielding patterns 140a, 140b at the bottom (in Figure 1A) or at the bottom and along one sidewall (in Figure 1B) of the gate trench 180 are configured to provide electric field (e.g., voltage and / or current) blocking through connections to respective source contacts 190 that are grounded. The shielding connection patterns may be connected to source contacts 190 on the top side of the devices 100a, 100b (or may be otherwise connected to the deep shielding patterns 140a, 140b) to electrically ground the deep shielding patterns 140a, 140b.

[0062] The shielding patterns 140a, 140b may extend to one (in FIG. 1B) or both (in FIG. 1A) lower corner regions at the bottom of the gate trench 180. Because the gate insulating layer 182 may be susceptible to dielectric breakdown, especially at the corner regions, the shielding patterns 140a, 140b may help protect the gate insulating layer 182 at the lower corner regions of the gate trench 180 from high electric fields during reverse blocking operation.

[0063] FIG 1A illustrates a bottom-gate shielding (BPS_TMOS) configuration of shielding pattern 140a that may enable aggressive cell pitch reduction and increased sidewall conductivity utilization. In particular, in FIG 1A, conduction 178 (indicated by dotted arrows) occurs along both sides of the channel in device 100a. However, the structure of device 100a illustrated in FIG 1A may be difficult to manufacture due to required masking and / or other steps to block or protect the sidewalls of trench 180 during the implantation steps used to form shielding pattern 140a.

[0064] 1B shows a contacting scheme with an asymmetric shielding (APS_TMOS) configuration, where the shielding pattern 140b extends only along one sidewall of the trench 180, thereby leaving the other sidewall of the trench 180 free from the shielding pattern 140b. However, this configuration may limit the active conduction area of ​​the device 100b by blocking conduction 178 on one side of the channel.

[0065] An embodiment of the present invention relates to a power semiconductor device including a layout and design arrangement that further improves reliability by forming a shielding region 240a, 340a, 340a' (also referred to herein as bottom shielding structure 240a, 340a, 340a') at the bottom of the gate trench 180 in combination with additional supporting shielding structures or regions 240b, 340b, 340b' on either side of the gate trench 180 spaced from the sidewalls of the gate trench 180. The shielding structures 240a / 240b, 340a / 340b, 340a' / 340b' are of a second conductivity type or an opposite conductivity type (e.g., p-type) to the first conductivity type (e.g., n-type) of the drift region 120. Although described and illustrated herein with reference to regions of particular first and second conductivity types (i.e., n-type and p-type) by way of example, it should be understood that the conductivity types of the regions in any of the illustrated examples may be reversed (i.e., p-type and n-type) in accordance with embodiments of the present invention. Similarly, although described herein primarily with respect to MOSFET implementations, it should be recognized that the same techniques may be used in other vertical power semiconductor devices, such as insulated gate bipolar transistors (IGBTs), and / or other related power devices utilizing trench-type structures.

[0066] In some embodiments, a supporting shielding structure or region underlying and / or adjacent to the gate trench 180 is provided adjacent the JFET portion 175 of the drift region 120. Figure 2 is a schematic cross-sectional view illustrating an exemplary unit cell of a power semiconductor device 200 including a bottom shielding structure 240a underlying the gate trench 180 and a supporting shielding structure 240b spaced from the sidewalls of the gate trench 180, according to some embodiments of the present invention. Elements, layers, or regions similar to those of the semiconductor layer structure 106 described herein are indicated by the same numbers.

[0067] 2, in the trench type vertical power semiconductor device 200, the JFET region 175 may include an upper portion of the drift region 120 adjacent to the gate trench 180 and below the well region. A primary bottom shielding structure 240a is disposed below the bottom surface of the gate trench 180, and first and second supporting shielding structures 240b are disposed on either side of the gate trench 180 and spaced apart from the sidewalls of the gate trench 180, such that the JFET region 175 extends at least partially between the respective supporting shielding structures 240b and the bottom shielding structure 240a. The bottom and supporting shielding structures 240a and 240b (collectively referred to as the shielding structures) extend beyond the gate trench 180 toward the substrate 110 (i.e., extend closer to the substrate 110 than the gate trench 180). The shielding connection pattern may be connected to the shielding structures 240a, 240b and the source contact 190 (e.g., on the top of the device 200), or the source contact 190 may be otherwise connected to the shielding structures 240a, 240b to electrically ground the shielding structures 240a, 240b.

[0068] The supporting shielding structure 240b may differ from the bottom shielding structure 240a (e.g., in material composition, distance or depth of extension from the surface S of the semiconductor layer structure 106 toward the substrate 110, and / or dopant concentration) to provide greater protection for the gate insulating layer 182 along the gate trench 180 (e.g., at the bottom corners of the gate trench 180), for example, by providing a lower resistance current path under avalanche breakdown conditions. In some embodiments, the supporting shielding structure 240b may extend toward the substrate 110 to a depth D2 substantially equal to the depth D1 of the bottom shielding structure 240a (i.e., D2=D1). In some embodiments, the supporting shielding structure 240b may extend toward the substrate 110 to a depth D2 greater than the depth D1 of the bottom shielding structure 240a. For example, the support shielding structure 240b may extend toward the substrate 110 beyond the bottom shielding structure 240a by a depth ΔD of about 0.1 microns to about 1 micron (e.g., about 0.3 microns to about 0.7 microns, e.g., about 0.5 microns). That is, the difference ΔD between the depth D2 of the support shielding structure 240b and the depth D1 of the bottom shielding structure 240a may be less than about 0.1 microns to about 1 micron. The depth or distance of the extension into the drift region 120 as described herein may be along a vertical direction in the drawing and may be relative to the surface (top surface) S of the semiconductor layer structure 106. The depth D2 of the support shielding structure 240b may be sufficient to reduce or prevent avalanche breakdown at the bottom of the gate trench 180. In some embodiments, the supporting shielding structure 240b may extend from the surface S of the semiconductor layer structure 106 toward the substrate 110 to a depth D2 of about 1 micron to about 10 microns (eg, about 3 microns to about 7 microns, for example, about 5 microns).

[0069] Additionally, the shape of supporting shielding structure 240b may differ from the bottom shielding structure 240a and / or trench 180 in some embodiments. For example, the width of supporting shielding structure 240b (along the horizontal or lateral direction) may differ from the width of trench 180 (and / or bottom shielding structure 240a extending below trench 180). That is, although shown with substantially similar widths, first and second supporting shielding structures 240b may be wider or narrower than gate trench 180 in some embodiments.

[0070] The supporting shielding structure 240b may define a pn junction (e.g., a body diode) with the drift region 120. A spacing T between the supporting shielding structure 240b and the substrate 110 (e.g., as defined by the portion of the drift region 120 therebetween) may correspond to a breakdown voltage of the device 200. For example, the supporting shielding structure 240b and / or the bottom shielding structure 240a may be separated from the substrate 110 by a spacing T of about 1 micron to about 100 microns (e.g., about 30 microns to about 70 microns, e.g., about 50 microns). The spacing T may vary based on, for example, the materials and / or dopant concentrations of the shielding structures 240a, 240b.

[0071] In some embodiments, the support shielding structure 240b may have a lower resistance than the bottom shielding structure 240a. For example, the support shielding structure 240b may contact the source contact 190 over a greater length (e.g., along a direction into the page) than the bottom shielding structure 240a (which may only be connected to the source intermittently along its length), thereby reducing resistance. The support shielding structure 240b may be formed of the same or different material as the bottom shielding structure 240a and / or may have a similar or different dopant concentration as the bottom shielding structure 240a. In some embodiments, the shielding structures 240a, 240b may be defined by one or more implantation steps with a substantially uniform concentration or a step or continuous gradient, and may extend to contact the source contact 190 for connection to electrical ground within the unit cell. The support shielding structure 240b may have a dopant concentration of about 1×10 17 ~About 10×10 20 cm -3 , for example, about 5 x 10 17 ~Approx. 5×10 19 cm -3 , or about 1 × 10 18 ~Approx. 1×10 19 cm -3 The dopant concentration of the supporting shielding structure 240b may be higher than that of the well region 170 (e.g., more than about 10 times higher, e.g., about 100 times higher) and may be similar to or higher than the dopant concentration of the bottom shielding structure 240a. The dopant concentration of the shielding structures 240a, 240b may vary based on manufacturing process and / or device design implementations, for example, as shown in the shielding structures 340a, 340b of the method embodiments of Figures 5A-5F and 6A-6H.

[0072] In some embodiments, the shielding structures 240a, 240b may be formed of a different material than the drift region 120, e.g., a semiconductor material having a lower resistivity than the semiconductor material of the drift region 120. For example, in embodiments where the drift region 120 is an n-type material (e.g., SiC), the support shielding structure 240b and / or the bottom shielding structure 240a may be a p-type material (e.g., nickel oxide (p-NiO), polysilicon (poly-Si), gallium nitride (p-GaN), gallium oxide (p-Ga2O3)). In embodiments where the drift region 120 is a p-type material, the support shielding structure 240b and / or the bottom shielding structure 240a may be an n-type material (e.g., n-SiC, n-Si, n-GaN). Forming shielding structures 240a and / or 240b of a different material of opposite conductivity type than drift region 120 may thus define respective pn heterojunctions or body diodes in drift region 120.

[0073] Shielding structures formed from different materials that define heterojunctions with drift region 120 may also differ in their ability to withstand repeated breakdown events (compared to implanted shielding structures). For example, heterojunction-based shielding structures (also described herein with respect to shielding structures 340a' and 340b') may be formed to provide lower resistance and / or extend to greater depths than implanted-based shielding structures (e.g., shielding structures 340a and 340b) to enhance their effectiveness. That is, relative to implanted-based shielding regions, heterojunction-based shielding structures may provide advantages in terms of resistance and / or depth control (i.e., they may be formed with lower resistance and / or greater depths than implanted shielding structures).

[0074] Additionally or alternatively, the support shielding structure 240b may be formed from a different material than the bottom shielding structure 240a. For example, the bottom shielding structure 240a may be an implanted region of the drift region 120 (and thus may be made of the same material as the drift region 120), while the support shielding structure 240b may be formed from a different material than the drift region 120, or vice versa, as shown in the shielding structures 340a, 340b and 340a', 340b' of the device embodiments of Figures 3C-3D and 4A-4D. Forming the shielding structures 240a and / or 240b from different materials may provide improved protection of the gate insulating layer 182. For example, forming the support shielding structure 240b from a different material of the second conductivity type (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3) may provide a lower resistance (in some instances, orders of magnitude lower) than some implanted bottom shielding structures 240a of the second conductivity type (e.g., P+ regions), and therefore may provide a lower resistance current path under avalanche breakdown conditions. That is, the shielding structures 240a, 240b may be formed from a different material than the drift region 120 and / or from each other.

[0075] The shape and / or depth of the supporting shielding structure 240b may also tolerate variations in the shape and / or depth of the bottom shielding structure 240a while still providing the desired avalanche breakdown characteristics. For example, in some embodiments, due to the greater protection of the gate oxide 182 provided by the supporting shielding structure 240b, the bottom shielding structure 240a may extend along only a portion of the bottom surface of the gate trench 180 (i.e., may be narrower than the bottom surface of the gate trench 180), which may increase the available area for conduction 178 at the bottom corners of the gate trench 180 (so that the JFET region 175 may extend below the outer edge of the gate trench 180 as well as along the trench sidewalls). In contrast, in some embodiments, bottom shielding structure 240a may extend along the entire bottom surface of gate trench 180 (or may extend laterally beyond or wider than the bottom surface of gate trench 180), and the dopant concentration of JFET region 175 may be increased to maintain the desired conduction 178. The width of bottom shielding structure 240a (i.e., along the bottom of gate trench 180) may vary based on the masking, implantation, deposition, and / or other manufacturing steps used to form shielding structures 240a and 240b.

[0076] More generally, the supporting shielding structures 240b may be formed with a different depth, dopant concentration, and / or material than the bottom shielding structures 240a, one or more of which may be configured to reduce or prevent avalanche breakdown at the bottom of the gate trench 180. Exemplary unit cells of power semiconductor devices 300a-300d and 400a-400d including various combinations of bottom shielding structures 340a, 340a' and supporting shielding structures 340b, 340b' are illustrated in Figures 3A-3D and 4A-4D.

[0077] In the illustrative examples of Figures 3A-3D and 4A-4D, a simplified semiconductor layer structure 106 (e.g., without JFET region 175, CSL 185, etc.) is shown for ease of explanation, but these and other well-known elements may be understood to be present even though not specifically shown. Similarly, elements, layers, and / or regions of devices 300a-300d and 400a-400d similar to those described above are indicated by the same numbers, and descriptions of such elements, layers, and / or regions may be omitted for brevity. Bottom shielding structures 340a, 340a' and supporting shielding structures 340b, 340b' may include similar characteristics to those of bottom shielding structure 240a and supporting shielding structure 240b, respectively, unless otherwise noted.

[0078] 3A, power semiconductor device 300a includes bottom shielding structure 340a and supporting shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type) in drift region 120 of a first conductivity type (e.g., n-type). Supporting shielding structure 340b may differ from bottom shielding structure 340a (e.g., in depth of extension into substrate 110 and / or dopant concentration) depending on the manufacturing process used. For example, a first ion implantation step may be performed to define bottom shielding structure 340a with a first depth D1 and a first concentration of dopant of the second conductivity type, and a second ion implantation step may be performed to define supporting shielding structure 340b with a second depth D2 (e.g., greater than or equal to first depth D1) and a second concentration of dopant of the second conductivity type (e.g., less than or equal to the first concentration). In embodiments in which supporting shielding structure 340b is an implanted region (as shown in FIGS. 3A, 3C, and 4A), supporting shielding structure 340b may effectively provide heavily doped region 174 of the second conductivity type that may be omitted. 3A, bottom shielding structure 340a is shown narrower than the bottom of gate trench 180 (i.e., extending only partially along the bottom of gate trench 180) by way of example, but may be equal to or wider than the bottom of gate trench 180 depending on the manufacturing process used. A method of fabricating device 300a including implanted bottom shielding structure 340a and supporting shielding structure 340b is described below with reference to Figures 5A-5F and 6A-6H.

[0079] 3B, the power semiconductor device 300b includes a bottom shielding structure 340a' and a supporting shielding structure 340b' of one or more materials different from the drift region 120. In particular, the bottom shielding structure 340a' and the supporting shielding structure 340b' include a material of a second conductivity type (e.g., p-type) thereby forming respective heterojunctions with the drift region 120 of a first conductivity type (e.g., n-type). For example, the drift region 120 may be formed from an n-type material (e.g., SiC) and the bottom shielding structure 340a' and the supporting shielding structure 340b' may be formed from a p-type material (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3), for example, using one or more deposition processes. Support shielding structure 340b' may differ from bottom shielding structure 340a' (e.g., in depth of extension toward substrate 110 and / or material composition) depending on the fabrication process used. For example, in some embodiments, bottom shielding structure 340a' may be formed from a first material at a first depth D1 using a first etching and deposition process, and supporting shielding structure 340b' may be formed from a second material (e.g., the same or different from the first material) at a second depth D2 (e.g., greater than or equal to the first depth D1) using a second etching and deposition process, such that shielding structures 340a' and 340b may be formed from different materials and / or at different depths (e.g., bottom shielding structure 340a' may be p-poly-Si and supporting shielding structure 340b' may be p-NiO). In embodiments in which supporting shielding structure 340b' defines a heterojunction with drift region 120 (such as in Figures 3B, 3D, 4B, 4C, and 4D), supporting shielding structure 340b', heavily doped region 174, and source region 160 may each have contacts (e.g., ohmic contacts) with source contact 190.A method of fabricating device 300b including bottom shielding structure 340a' and supporting shielding structure 340b' that define a heterojunction with drift region 120 is described below with reference to Figures 7A-7F and 8A-8H.

[0080] 3C illustrates a power semiconductor device 300c including a support shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type) combined with a bottom shielding structure 340a' of a material different from the drift region 120 of the first conductivity type (e.g., n-type), i.e., a material different from the implanted support shielding structure 340b. The bottom shielding structure 340a' defines a heterojunction with the drift region 120 below the bottom surface of the gate trench 180'. The support shielding structure 340b and the bottom shielding structure 340a' may be formed using different manufacturing processes (e.g., ion implantation and deposition, respectively), and thus the depth D2 of the support shielding structure 340b may be the same as or different from the depth D1 of the bottom shielding structure 340a' depending on the respective manufacturing processes used.

[0081] 3D illustrates a power semiconductor device 300d including a bottom shielding structure 340a provided by an implanted region of a second conductivity type (e.g., p-type) combined with a supporting shielding structure 340b' of a material of a second conductivity type different from the drift region 120 of the first conductivity type (e.g., n-type). The supporting shielding structure 340b' defines a heterojunction with the drift region 120 on either side of the gate trench 180 and spaced from the sidewall of the gate trench 180. The supporting shielding structure 340b' and the bottom shielding structure 340a may be formed using different manufacturing processes (e.g., deposition and ion implantation, respectively), and thus the depth D2 of the supporting shielding structure 340b' may be the same as or different from the depth D1 of the bottom shielding structure 340a, depending on the respective manufacturing processes used. In FIG. 3D, bottom shielding structure 340a is shown as being wider than the bottom of gate trench 180 (i.e., extending laterally beyond the bottom of gate trench 180) by way of example, but may be equal to or narrower than the bottom of gate trench 180 depending on the manufacturing process used.

[0082] FIG. 4A illustrates a power semiconductor device 400a including a support shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type), a first bottom shielding structure portion 340a provided by an implanted region of a second conductivity type, and a second bottom shielding structure portion 340a' of a material of a second conductivity type different from the drift region 120. The second bottom shielding structure portion 340a' defines a heterojunction with the drift region 120 below a bottom surface of the gate trench 180'. The support shielding structure 340b and the second bottom shielding structure portion 340a' may be formed using different fabrication processes (e.g., ion implantation and deposition, respectively). The support shielding structure 340b and the first bottom shielding structure portion 340a may be formed using the same or different implantation processes. Thus, the depth D2 and / or dopant concentration of support shielding structure 340b may be the same or different than the depth D1 and / or dopant concentration of first bottom shielding structure portion 340a, depending on the fabrication process used. Similarly, in FIG. 4A, first bottom shielding structure portion 340a is shown narrower than the bottom surface of gate trench 180' by way of example, but may be equal to or wider than the bottom surface of gate trench 180', depending on the fabrication process used.

[0083] 4B illustrates a power semiconductor device 400b including a first support shielding structure portion 340b provided by an implanted region of a second conductivity type. The second support shielding structure portion 340b' and the bottom shielding structure 340a' include a material of a second conductivity type different from the drift region 120 of the first conductivity type. The bottom shielding structure 340a' and the second support shielding structure portion 340b' define a heterojunction with the drift region 120 (spaced laterally below the bottom surface of the gate trench 180' and from opposite sidewalls of the gate trench 180', respectively). The bottom shielding structure 340a' and the second support shielding structure portion 340b' may be formed using the same or different manufacturing processes (e.g., the same or different deposition steps) and thus may be the same as each other or different from each other (e.g., in terms of depth of extension into the substrate 110 and / or material composition) depending on the manufacturing process used. First support shielding structure portion 340b may be formed using a different manufacturing process (e.g., one or more ion implantation processes) than shielding structures 340a', 340b'. Depth D2 of first support shielding structure portion 340b may be the same as or different from depth D1 of bottom shielding structure 340a', depending on the manufacturing process used.

[0084] 4C illustrates a power semiconductor device 400c including a bottom shielding structure and a supporting shielding structure, each including an implanted region and a heterojunction region. In particular, the bottom shielding structure and the supporting shielding structure each include a first portion 340a and 340b provided by the implanted region of a second conductivity type and a second portion 340a' and 340b' of a material of a second conductivity type different from the drift region 120. The second portions 340a' and 340b' define a heterojunction with the drift region 120 (spaced laterally below the bottom surface of the gate trench 180' and from opposite sidewalls of the gate trench 180', respectively). The first portions 340a and 340b extend from the second shielding structure portions 340a' and 340b', respectively, toward the substrate 110 to depths D1 and D2. The first portions 340a and 340b may be formed using the same or different manufacturing processes (e.g., the same or different ion implantation processes) and may therefore be the same as or different from each other (e.g., in depth of extension towards the substrate 110 and / or in dopant concentration) depending on the manufacturing process used. The second portions 340a' and 340b' may be formed using the same or different manufacturing processes (e.g., the same or different deposition steps) and may therefore be the same as or different from each other (e.g., in depth of extension towards the substrate 110 and / or in material composition) depending on the manufacturing process used. Thus, the depth D2 of the first and second portions 340b and 340b' of the support shielding structure may be the same as or different from the depth D1 of the first and second portions 340a and 340a' of the bottom shielding structure. In FIG. 4C , first portion 340a of bottom shielding structure is shown as being wider than the bottom surface of gate trench 180′ (i.e., extending laterally beyond the bottom surface of gate trench 180′) by way of example, but may be equal to or narrower than the bottom surface of gate trench 180′ depending on the manufacturing process used.

[0085] 4D illustrates a power semiconductor device 400d including a bottom shielding structure 340a provided by an implanted region of a second conductivity type (e.g., p-type). A first support shielding structure portion 340b is provided by an implanted region of a second conductivity type, and a second support shielding structure portion 340b' is formed from a material of a second conductivity type different from the drift region 120 of the first conductivity type. The second support shielding structure portion 340b' defines a heterojunction with the drift region 120 laterally spaced from opposite sidewalls of the gate trench 180. The bottom shielding structure 340a and the first support shielding structure portion 340b may be formed using the same or different fabrication processes (e.g., the same or different ion implantation processes) and thus may be the same or different from each other (e.g., in depth of extension into the substrate 110 and / or dopant concentration) depending on the fabrication process used. The second supporting shielding structure portion 340b' may be formed using a different manufacturing process (e.g., one or more ion implantation processes) than the shielding structures 340a, 340b. The depth D2 of the first and second supporting shielding structure portions 340b and 340b' may be the same as or different from the depth D1 of the bottom shielding structure 340a.

[0086] 5A-5F are schematic cross-sectional views illustrating exemplary fabrication steps for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench, according to some embodiments of the present invention. In particular, FIGs. 5A-5F illustrate a method of forming the shielding structures 340a, 340b as implanted regions, in which the bottom shielding structure 340a is formed prior to forming the gate trench 180, which may be referred to herein as a pre-trench shield implant step.

[0087] As shown in FIG. 5A, a semiconductor layer structure 106 is provided. The semiconductor layer structure 106 includes a drift region 120 of a first conductivity type (e.g., n-type), a current spreading layer 185, a JFET region 175, a well region 170, and a source region 160, as described above. A highly doped region 174 of a second conductivity type is shown, but may be omitted in embodiments in which the support shielding structure 340b is formed as an implanted region. The semiconductor layer structure 106 may include a substrate 110 and / or other layers. A mask layer 501 is formed on a surface S of the semiconductor layer structure 106, and a patterning layer 502 is formed on the mask layer 501.

[0088] In Fig. 5B, a mask layer 501 is patterned (e.g., by photolithography) with a patterning layer 502 to form an implantation mask pattern 501' that includes openings that expose portions of the surface S of the semiconductor layer structure 106. In Fig. 5C, one or more ion implantation steps 500 are performed to implant dopants of a second conductivity type (e.g., p-type) into the exposed portions of the surface S using the mask pattern 501' as an implantation mask to form shielding structures 340a and 340b that extend into the drift region 120 toward the substrate 100. The dose and / or implantation energy of the implantation step 500 may be controlled (e.g., a higher implantation energy results in a greater depth) to form the shielding structures 340a and 340b with a desired dopant concentration and / or depth (e.g., D1 and D2) relative to the surface S. The dopant concentration of shielding structures 340a and / or 340b may be substantially uniform or graded (eg, stepped or continuous).

[0089] 5A-5C illustrate a single mask 501′ and high energy ion implantation process 500 for forming the bottom shielding structure 340a and the supporting shielding structure 340b simultaneously or in the same processing step, such that the shielding structures 340a, 340b may have the same dopant concentration and / or the same depth (i.e., D1=D2) relative to the surface S of the semiconductor layer structure 106. However, it will be understood that the embodiments described herein are not limited to a single masking and / or implantation process, and multiple masking and implantation processes may be performed sequentially using different mask shapes, different implant energies, and / or different doses to expose different portions of the surface S (e.g., one or more of FIGS. 5A, 5B, or 5C may be repeated or repeated) such that the bottom shielding structure 340a and the supporting shielding structure 340b may have different shapes, different depths (i.e., D1≠D2) and / or different dopant concentrations from one another.

[0090] In FIG. 5D, the mask 501′ is removed, an etching mask layer 503 (e.g., an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterning layer 504 is formed on the etching mask layer 503. In FIG. 5E, the etching mask layer 503 is patterned with the patterning layer 504 to form an etch mask pattern 503′ including openings that expose portions of the surface S of the semiconductor layer structure 106 between the supporting shielding structures 340b. In FIG. 5F, an etching step 550 is performed to selectively etch the portions of the surface S exposed by the etching mask pattern 503′, thereby forming a gate trench 180 between and spaced apart from the supporting shielding structures 340b and extending into the drift region 120. A bottom shielding structure 340a extends below and at least partially along the bottom surface of the gate trench 180. Mask pattern 503' may be removed and gate oxide layer 182, gate electrode 184, source contact 190, intermetal dielectric 186, and metal layer 196 may be formed in sequence to provide device 300a of FIG. 3A.

[0091] 5A-5F, the support shielding structure 340b and the bottom shielding structure 340a are formed using the same implantation process 500 prior to forming the gate trench 180. The support shielding structure 340b and the bottom shielding structure 340a may thereby have the same or substantially similar depths and dopant concentrations. However, due to the etching of the gate trench 180 into the bottom shielding structure 340a formed by the pre-trench implantation step, the distribution of dopants in the bottom shielding structure 340a (from the bottom surface of the trench 180 toward the substrate 110) may be more abrupt than that of the support shielding structure 340b (from the surface S toward the substrate 110).

[0092] 6A-6H are schematic cross-sectional views illustrating an exemplary manufacturing process for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench, according to further embodiments of the present invention. In particular, FIGs. 6A-6H illustrate a method of forming the shielding structures 340a, 340b as implanted regions, where the bottom shielding structure 340a is formed after the gate trench 180, which may be referred to herein as a post-trench shield implant process.

[0093] As shown in FIG. 6A, a semiconductor layer structure 106 is provided. The semiconductor layer structure 106 includes a drift region 120 of a first conductivity type (e.g., n-type), a current spreading layer 185, a JFET region 175, a well region 170, and a source region 160, as described above. A highly doped region 174 of a second conductivity type is shown, but may be omitted in embodiments in which the support shielding structure 340b is formed as an implanted region. The semiconductor layer structure 106 may include a substrate 110 and / or other layers. A mask layer 601 is formed on a surface S of the semiconductor layer structure 106, and a patterning layer 602 is formed on the mask layer 601.

[0094] In FIG. 6B, the mask layer 601 is patterned (e.g., by photolithography) using the patterning layer 602 to form an implantation mask pattern 601′ that includes openings that expose portions of the surface S of the semiconductor layer structure 106. In FIG. 6C, one or more ion implantation steps 600 are performed to implant dopants of a second conductivity type (e.g., p-type) into the exposed portions of the surface S using the mask pattern 601′ as an implantation mask to form a support shielding structure 340b that extends into the drift region 120 toward the substrate 100. The dose and / or implantation energy of the implantation step 600 may be controlled to form a support shielding structure 340b having a desired dopant concentration and / or a desired depth (e.g., D2) relative to the surface S. The dopant concentration of the support shielding structure 340b may be substantially uniform or graded (e.g., stepped or continuous).

[0095] In Fig. 6D, the mask 601' is removed, an etch mask layer 603 (e.g., an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterning layer 604 is formed on the etch mask layer 603. In Fig. 6E, the etch mask layer 603 is patterned with the patterning layer 604 to form an etch mask pattern 603' including openings that expose portions of the surface S of the semiconductor layer structure 106 between the support shielding structures 340b. In Fig. 6F, an etching step 650 is performed to selectively etch the portions of the surface S exposed by the etch mask pattern 603', thereby forming gate trenches 180 extending into the drift region 120 between and spaced apart from the support shielding structures 340b.

[0096] 6G, a mask 655 (e.g., an oxide mask) is formed on the sidewalls and bottom surface of gate trench 180. For example, trench 180 may be oxidized and / or a coating may be deposited along the sidewalls and bottom surface of gate trench 180 to form mask 655. In some embodiments, the portion of mask 655 on the sidewalls may be formed thicker than the portion of mask 655 on the bottom surface of gate trench 180 to protect the conducting sidewalls of trench 180 from, for example, an implantation step to form shielding structure 340a.

[0097] In FIG. 6H, one or more ion implantation steps 600′ are performed to implant dopants of the second conductivity type into the bottom surface of the trench 180 using the mask 655 as an implantation mask to form a bottom shielding structure 340a extending below and at least partially along the bottom surface of the gate trench 180. The dose and / or implantation energy of the implantation step 600′ may be controlled to form a bottom shielding structure 340a having a desired dopant concentration and / or a desired depth (e.g., D1) relative to the surface S and / or having a substantially uniform or graded dopant concentration. The mask 655 is removed and the gate oxide layer 182, the gate electrode 184, the source contact 190, the intermetal dielectric 186, and the metal layer 196 may be sequentially formed to provide the device 300a of FIG. 3A.

[0098] In the exemplary process of FIGS. 6A-6H, a first high energy implant 600 is used to form the support shielding structure 340b prior to forming the gate trench 180, and the bottom shielding structure 340a is formed using a second high energy implant 600'. The dose and / or implant energy of the second implant 600' may be the same as or different from the first implant 600. The process illustrated in FIGS. 6A-6H may thus be advantageous with regard to ease of forming the support shielding structure 340b with a different depth, concentration, and / or material than the bottom shielding structure 340a. For example, the use of multiple implantation steps 600 and 600' may allow for the selection of different implant energies and / or dopant profiles for each of the first and second implantation steps, for example, to form the support shielding structure 340b extending to a greater depth than the bottom shielding structure 340a and / or with a different dopant concentration than the bottom shielding structure 340a. For example, bottom shield structure 340a may be formed separately with a similar or lower dopant concentration than support shield structure 340b. Formation of bottom shielding structure 340a after formation of gate trench 180 may also result in a similar (Gaussian) distribution of dopant across the depth of shielding structures 340a and 340b (from the bottom of trench 180 towards substrate 110 and from surface S towards substrate 110, respectively).

[0099] 7A-7H are schematic cross-sectional views illustrating an exemplary manufacturing process for forming a power semiconductor device including a bottom shielding structure beneath a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench, according to further embodiments of the present invention. In particular, FIGs. 7A-7H illustrate a method of forming shielding structures 340a', 340b' of a different material than drift region 120, where bottom shielding structure 340a' is formed prior to forming gate trench 180', which may be referred to herein as a pre-trench heterojunction shield process.

[0100] As shown in Fig. 7A, a semiconductor layer structure 106 is provided as described with respect to any of the embodiments above. A mask layer 701 is formed on a surface S of the semiconductor layer structure 106, and a patterning layer 702 is formed on the mask layer 701. In Fig. 7B, the mask layer 701 is patterned (e.g., by photolithography) with the patterning layer 702, thereby forming a first etch mask pattern 701' that includes openings that expose portions of the surface S of the semiconductor layer structure 106.

[0101] In Fig. 7C, one or more etching steps 700 are performed using the first mask pattern 701' as an etch mask to form shield trenches 780 into the exposed portions of the surface S. The etching steps 700 can be controlled to provide shield trenches 780 having a desired depth (e.g., D1, D2). In Fig. 7D, one or more deposition steps are performed to form a material of a second conductivity type (e.g., p-type) in the shield trenches 780, and the material of the second conductivity type can be removed (e.g., by one or more planarization steps) from the surface S of the semiconductor layer structure 106, thereby forming shielding structures 340a' and 340b' that extend into the drift region 120 toward the substrate 100. For example, drift region 120 may be formed from an n-type material (e.g., SiC), and shielding structures 340a' and 340b' may be formed from one or more p-type materials (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0102] The examples of Figures 7A-7D show a single mask 701', etching process 700, and deposition process for forming the bottom shielding structure 340a' and the supporting shielding structure 340b' simultaneously or in the same processing step, such that the shielding structures 340a', 340b' may be formed from the same material and / or have the same depth relative to the surface S of the semiconductor layer structure 106 (i.e., D1 = D2). It will be understood, however, that the embodiments described herein are not limited to a single masking and / or etching step, and that multiple masking and etching steps may be performed sequentially (e.g., one or more of Figures 7A, 7B, 7C, or 7D may be repeated or iterated) using different mask shapes to expose different portions of surface S, different etching steps to form shield trenches 780 of different depths, and / or different deposition steps, such that bottom shielding structure 340a' and supporting shielding structure 340b' may have different shapes, different depths (i.e., D1 ≠ D2), and / or be formed from different materials (e.g., bottom shielding structure 340a' may be p-poly-Si and supporting shielding structure 340b' may be p-NiO).

[0103] In FIG. 7E, a mask layer 703 (e.g., an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterning layer 704 is formed on the mask layer 703. In FIG. 7F, the mask layer 703 is patterned with the patterning layer 704 to form a second etch mask pattern 703' that includes openings that expose portions of the surface S of the semiconductor layer structure 106 (including the surface of the bottom shielding structure 340a') between the supporting shielding structures 340b'. In FIG. 7G, an etching step 750 is performed to selectively etch the portions of the surface S exposed by the etch mask pattern 503', thereby forming a gate trench 180 extending into the drift region 120 between and spaced apart from the supporting shielding structures 340b'. The bottom shielding structure 340a' remains below and at least partially along the bottom surface of the gate trench 180. In Figure 7H, mask pattern 503' is removed. Gate oxide layer 182, gate electrode 184, source contact 190, intermetal dielectric 186, and metal layer 196 may be formed, in sequence, to provide device 300b of Figure 3B.

[0104] 8A-8H are schematic cross-sectional views illustrating an exemplary manufacturing process for forming a power semiconductor device including a bottom shielding structure below a gate trench and a supporting shielding structure spaced from a sidewall of the gate trench, according to further embodiments of the present invention. In particular, FIGs. 8A-8H illustrate a method of forming shielding structures 340a', 340b' of a different material than drift region 120, where bottom shielding structure 340a' is formed after gate trench 180', which may be referred to herein as a post-trench heterojunction shield process.

[0105] As shown in Fig. 8A, a semiconductor layer structure 106 is provided as described in any of the above embodiments. A mask layer 801 is formed on a surface S of the semiconductor layer structure 106, and a patterning layer 802 is formed on the mask layer 801. In Fig. 8B, the mask layer 801 is patterned (e.g., by photolithography) with the patterning layer 802 to form a first etch mask pattern 801' that includes openings that expose portions of the surface S of the semiconductor layer structure 106.

[0106] In Figure 8C, one or more etching steps 800 are performed using the first mask pattern 801' as an etch mask to form support shield trenches 880 extending into the exposed portions of surface S. The etching step 800 may be controlled to form support shield trenches 880 having a desired depth (e.g., D2) relative to surface S. In Figure 8D, one or more deposition steps are performed to form a material of a second conductivity type (e.g., p-type) in support shield trenches 880, and the material of the second conductivity type is removed (e.g., by one or more planarization steps) from surface S, thereby forming support shielding structures 340b' that extend into drift region 120 toward substrate 100. For example, the drift region 120 may be formed from an n-type material (eg, SiC) and the support shielding structure 340b' may be formed from a p-type material (eg, p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0107] In Figure 8E, an etch mask layer 803 (e.g., an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterning layer 804 is formed on the etch mask layer 803. In Figure 8F, the etch mask layer 803 is patterned with the patterning layer 804 to form a second etch mask pattern 803' that includes openings that expose portions of the surface S of the semiconductor layer structure 106 between the supporting and shielding structures 340b'.

[0108] 8G, an etching process 850 is performed to selectively etch portions of surface S exposed by etch mask pattern 803′, thereby forming gate trenches 180′ extending into drift region 120 between and spaced from supporting shielding structures 340b′. The etching process 850 may be controlled to form supporting gate trenches 180′ having a desired depth (e.g., D1) relative to surface S, which may be the same as or different from depth D2 of supporting shield trenches 880.

[0109] 8H, one or more selective deposition steps are performed to form a material of a second conductivity type (e.g., p-type) in the gate trench 108', thereby forming a bottom shielding structure 340a' that extends into the drift region 120 toward the substrate 100. The bottom shielding structure 340a' may partially fill the gate trench 180', such that the depth of the gate trench 180' may define the depth D1 of the bottom shielding structure 340a'. Different deposition steps may be performed such that the bottom shielding structure 340a' and the supporting shielding structure 340b' may have different shapes, different depths (i.e., D1 ≠ D2), and / or be formed from different materials. The second mask pattern 803' is removed and the gate oxide layer 182, gate electrode 184, source contact 190, intermetal dielectric 186, and metal layer 196 may be sequentially formed to provide the device 300b of FIG. 3B.

[0110] In the exemplary process of Figures 8A-8H, a first etch and deposition process is used to form the support shield structure 340b' prior to forming the gate trench 180', and a second etch and deposition process is used to fill a portion of the gate trench 180' to form the bottom shield structure 340a'. The process illustrated in Figures 8A-8H may thus be advantageous with regard to the ease of forming the support shield structure 340b' having a different depth and / or material than the bottom shield structure 340a'. For example, the use of multiple etch steps 800, 850 and / or multiple deposition steps may allow for the selection of different depths and / or materials such that the support shield structure 340b' extends to a greater depth and / or is formed from a lower resistivity material than the bottom shield structure 340a'.

[0111] It will be understood that any of the steps illustrated in Figures 5A-8H may be combined in various embodiments herein. For example, one or more of the pre-trench shield implant steps of Figures 5A-5F may be performed between one or more of the pre-trench heterojunction shield steps of Figures 7A-7H, or vice versa. Similarly, one or more of the post-trench shield implant steps of Figures 6A-6H may be performed between one or more of the post-trench heterojunction shield steps of Figures 8A-8H, or vice versa. More generally, although the fabrication steps illustrated in Figures 5A-8H are illustrated with respect to forming implanted shielding regions 340a, 340b of Figure 3A or heterojunction shielding regions 340a', 340b of Figure 3B, by way of example, it will be understood that any of the illustrated steps may be utilized in combination to provide any desired combination of implanted and heterojunction shielding regions, such as any of the structures illustrated in Figures 3C-4D, for example, with similar or different shapes, similar (i.e., D1=D2) or different (i.e., D1≠D2) depths, and / or the same or different materials.

[0112] The embodiments described herein thus illustrate various examples of different combinations of bottom shielding structures (e.g., 240a, 340a, 340a') and supporting shielding structures (e.g., 240b, 340b, 340b') according to the present invention that may be useful for protecting the gate oxide 182, particularly at the bottom and edges / corners of the gate trenches 180, 180'. However, it will be understood that embodiments of the present invention may include any and all combinations of the features described herein and are not limited to the illustrated examples. Embodiments of the present invention may be used in trench type vertical semiconductor power transistors, including but not limited to MOSFETs, IGBTs, or other power devices that include transistor terminals in the trench region.

[0113] In the above description, each exemplary embodiment is described with respect to regions of a particular conductivity type. It will be appreciated that devices of the opposite conductivity type may be formed by simply reversing the conductivity types of the n-type and p-type layers in each of the above embodiments. It will thus be appreciated that the present invention covers both n-type and p-type channel devices for each of the different device structures (e.g., MOSFETs, IGBTs, etc.).

[0114] The present invention has been described above primarily with respect to silicon carbide-based power semiconductor devices. However, silicon carbide is used herein as an example, and it will be appreciated that the devices described herein may be formed in any suitable wide bandgap semiconductor material system. By way of example, gallium nitride-based semiconductor materials (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide in any of the embodiments described above. More generally, although described with respect to silicon carbide devices, embodiments of the present invention are not limited thereto and may have applicability to devices formed using other wide bandgap semiconductor materials, such as gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor materials.

[0115] Embodiments of the present invention are described above with reference to the accompanying drawings, in which embodiments of the invention are shown. It will be appreciated, however, that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth above. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

[0116] Although terms such as first, second, etc. are used throughout this specification to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0117] The terms used herein are only for the purpose of describing particular embodiments and are not intended to limit the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, processes, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.

[0118] When an element, such as a layer, region, or substrate, is described as being "on" or extending "upon" another element, it will be understood that the element can be directly on or extending directly onto the other element, or that intervening elements may be present. In contrast, when an element is described as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is described as being "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0119] Relative terms such as "below" or "above" or "upper" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region when illustrated in the drawings. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted.

[0120] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, variations from the shapes of the illustrations are expected as a result, for example, of manufacturing techniques and / or tolerances. Embodiments of the invention are also described in terms of manufacturing processes. It will be appreciated that the steps illustrated in the manufacturing processes do not have to be performed in the order depicted.

[0121] Some embodiments of the invention are described in terms of semiconductor layers and / or regions characterized as having a conductivity type, such as n-type or p-type, which refers to the majority carrier concentration in the layer and / or region. Thus, n-type material has a majority equilibrium concentration of negatively charged electrons, while p-type material has a majority equilibrium concentration of positively charged holes. Some materials may be designated with a "+" or "-" (as in n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region. However, such designations do not imply the presence of a particular concentration of majority or minority carriers in a layer or region.

[0122] In the drawings and specification, exemplary embodiments of the invention have been disclosed and specific terms have been employed, but these terms are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being indicated in the following claims.

Claims

1. a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls; a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench; first and second supporting shielding structures of the second conductivity type extending into the drift region on either side of the gate trench and spaced apart from sidewalls of the gate trench; A power semiconductor device comprising:

2. 2. The power semiconductor device of claim 1 , wherein one or more of the first and second supporting shielding structures extend into the drift region to a depth relative to a surface of the semiconductor layer structure that is different from a depth of the bottom shielding structure.

3. 3. The power semiconductor device of claim 2, wherein the first and second supporting shielding structures extend into the drift region beyond the bottom shielding structure by about 0.1 to about 1 micron.

4. 4. The power semiconductor device of claim 1 , wherein at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises a material different from a material of the drift region.

5. 5. The power semiconductor device of claim 4, wherein the drift region comprises a wide bandgap semiconductor material and the at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

6. 5. The power semiconductor device of claim 4, wherein the at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure further comprises an implanted portion of the drift region.

7. 4. The power semiconductor device of claim 1, wherein the bottom shielding structure includes a first concentration of dopant of the second conductivity type, and the first and second supporting shielding structures include a second concentration of dopant of the second conductivity type that is different from the first concentration.

8. The power semiconductor device of claim 7 , wherein the second concentration is greater than the first concentration.

9. the semiconductor layer structure further comprises a substrate having the drift region thereon, and a well region of the second conductivity type in or on the drift region opposite the substrate; 9. The power semiconductor device of claim 1 , wherein the first and second supporting shielding structures extend through the well region, beyond the bottom shielding structure, and are spaced from the substrate.

10. 10. The power semiconductor device of claim 9, wherein the first and second supporting shielding structures have a different concentration of dopants of the second conductivity type than the well region.

11. 10. The power semiconductor device of claim 9, wherein the first and second supporting shielding structures are spaced from the substrate by about 1 to about 100 microns.

12. 12. The power semiconductor device of claim 1, wherein the bottom shielding structure extends along a portion of the bottom surface of the gate trench.

13. 12. The power semiconductor device according to claim 1, wherein the bottom shielding structure extends along the entire bottom surface of the gate trench.

14. a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls; a bottom shielding structure of a second conductivity type below the bottom surface of the gate trench; first and second supporting shielding structures of the second conductivity type extending into the drift region on either side of the gate trench and spaced from the sidewalls of the gate trench; wherein a material composition, a distance of extension into the drift region relative to a surface of the semiconductor layer structure, and / or a dopant concentration of the bottom shielding structure differs from that of the first and second supporting shielding structures.

15. 15. The power semiconductor device of claim 14, wherein the distance of extension of one or more of the first and second supporting shielding structures into the drift region is greater than that of the bottom shielding structure relative to the surface of the semiconductor layer structure.

16. 16. The power semiconductor device of claim 15, wherein the first and second supporting shielding structures extend into the drift region beyond the bottom shielding structure by about 0.1 to about 1 micron.

17. 17. The power semiconductor device of claim 14, wherein the material composition of at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure differs from a material composition of the drift region.

18. 20. The power semiconductor device of claim 17, wherein the drift region comprises a wide bandgap semiconductor material and the at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

19. 20. The power semiconductor device of claim 18, wherein the at least one of the bottom shielding structure, the first support shielding structure, or the second support shielding structure further comprises an implanted region of the drift region.

20. 17. The power semiconductor device of claim 14, wherein the dopant concentration of the first and second support shielding structures is lower than the dopant concentration of the bottom shielding structure.

21. 21. The power semiconductor device of claim 20, wherein the dopant concentration of the first and second supporting shielding structures is greater than the dopant concentration of the bottom shielding structure.

22. 22. The power semiconductor device of claim 14, wherein the semiconductor layer structure further comprises a substrate having the drift region thereon, and the first and second supporting shielding structures are spaced apart from the substrate by about 1 to about 100 microns.

23. 1. A method for manufacturing a power semiconductor device, comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming a bottom shielding structure of a second conductivity type and first and second supporting shielding structures extending into the drift region; forming a gate trench extending into the drift region and spaced from the first and second supporting shielding structures; wherein the bottom shielding structure underlies the gate trench.

24. 24. The method of claim 23, wherein forming the gate trench is performed after forming the bottom shielding structure.

25. Forming the bottom shielding structure and the first and second supporting shielding structures includes: forming one or more of the first and second supporting shielding structures extending into the drift region to a depth relative to a surface of the semiconductor layer structure different from a depth of the bottom shielding structure; 24. The method of claim 23, comprising:

26. 26. The method of claim 25, wherein the first and second supporting shielding structures extend into the drift region beyond the bottom shielding structure by about 0.1 to about 1 micron.

27. Forming at least one of the bottom shielding structure or the first and second supporting shielding structures includes: performing one or more etching steps to form respective shielding trenches in the drift region; performing one or more deposition steps to form a material in each of the shielding trenches that is different from a material in the drift region; 24. The method of claim 23, comprising:

28. 28. The method of claim 27, wherein the drift region comprises a wide bandgap semiconductor material and the at least one of the bottom shielding structure or the first and second supporting shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

29. forming the at least one of the bottom shielding structure or the first and second supporting shielding structures includes: performing one or more ion implantation steps to implant dopants of the second conductivity type into portions of the drift region beneath the respective shielding trenches.

28. The method of claim 27, further comprising:

30. Forming at least one of the bottom shielding structure or the first and second supporting shielding structures includes: performing one or more ion implantation steps to implant dopants of the second conductivity type into the drift region; 24. The method of claim 23, comprising:

31. 31. The method of claim 30, wherein in response to the one or more ion implantation steps, the bottom shielding structure comprises a first concentration of the dopant of the second conductivity type and the first and second supporting shielding structures comprise a second concentration of the dopant of the second conductivity type that is different from the first concentration.

32. 31. The method of claim 30, wherein the second concentration is greater than the first concentration.

33. 1. A method for manufacturing a power semiconductor device, comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming first and second supporting shielding structures of a second conductivity type extending into the drift region; forming a gate trench extending into the drift region and spaced from the first and second supporting shielding structures, the gate trench including sidewalls and a bottom surface between the sidewalls; forming a bottom shielding structure of the second conductivity type below the bottom surface of the gate trench; A method comprising:

34. forming the bottom shielding structure performing one or more ion implantation and / or deposition steps after forming the gate trench to form the bottom shielding structure extending into the drift region to a first depth relative to a surface of the semiconductor layer structure.

34. The method of claim 33, comprising:

35. 35. The method of claim 34, wherein a material composition, a distance of extension into the drift region relative to the surface of the semiconductor layer structure, and / or a dopant concentration of the bottom shielding structure differs from that of the first and second supporting shielding structures.

36. Forming the first and second supporting shielding structures includes: forming one or more of the first and second supporting shielding structures extending into the drift region to a second depth relative to the surface of the semiconductor layer structure prior to forming the gate trench.

35. The method of claim 34, comprising:

37. 37. The method of claim 36, wherein the second depth is greater than the first depth by about 0.1 to about 1 micron.

38. Forming the first and second supporting shielding structures includes: performing one or more etching steps to form respective shielding trenches in the drift region prior to forming the gate trenches; and performing one or more deposition steps to form a material in the respective shielding trenches that is different from a material of the drift region.

35. The method of claim 34, comprising:

39. 40. The method of claim 38, wherein the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shielding structure or the first and second supporting shielding structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

40. Forming the first and second supporting shielding structures includes: performing one or more ion implantation steps to implant dopants of the second conductivity type into portions of the drift region beneath the respective shielding trenches prior to forming the gate trenches.

40. The method of claim 38, further comprising:

41. Forming the first and second supporting shielding structures includes: performing one or more ion implantation steps to implant dopants of the second conductivity type into the drift region prior to forming the gate trench; 35. The method of claim 34, comprising:

42. 42. The method of claim 41 , wherein in response to the one or more ion implantation steps, the first and second supporting shielding structures include a second concentration of dopants of the second conductivity type that is different from the first concentration of dopants of the second conductivity type of the bottom shielding structure.

43. 43. The method of claim 42, wherein the second concentration is greater than the first concentration.

Images