Activating and deactivating cores in multi-core processors

Abstract

Core activation and deactivation for a multi-core processor is described. According to the described technique, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. In response to the request, switching from the first core configuration to the second core configuration is performed by adjusting the number of active cores of the processor without rebooting.

Description

[Technical field]

[0001] (Related Applications) This application claims priority to U.S. patent application Ser. No. 17 / 708,453, entitled "Core Activation and Deactivation for a Multi-Core Processor," filed March 30, 2022, the entire disclosure of which is incorporated herein by reference. [Background technology]

[0002] A processor with multiple cores (e.g., two or more separate processing units) on a single integrated circuit is commonly referred to as a "multi-core processor." Manufacturers typically integrate multiple cores on a single integrated circuit die or on multiple dies within a single chip package. Multi-core processors are widely used across many application domains, including general purpose, embedded, digital signal processing (DSP), networking, and graphics processing unit (GPU).

[0003] The detailed description will now be made with reference to the accompanying drawings. [Brief description of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of a non-limiting example system having a processor with multiple cores and a controller for activating and deactivating cores without rebooting. [Diagram 2] FIG. 2 illustrates a non-limiting example of a controller adjusting the number of active cores of a processor without rebooting. [Diagram 3] FIG. 1 illustrates a non-limiting example of a user interface in one or more embodiments. [Figure 4] FIG. 1 illustrates another non-limiting example of a user interface in one or more embodiments. [Diagram 5] FIG. 1 illustrates another non-limiting example of a user interface in one or more embodiments. [Figure 6] FIG. 2 illustrates a procedure in an exemplary embodiment for adjusting the number of active cores of a multi-core processor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] (overview) It is often beneficial to deactivate some cores of a multi-core processor by removing slower cores, removing higher power cores, removing hot cores, etc. However, conventional systems require a system reboot to reinitialize the desired cores and reset the operating system's perception of the available cores. However, rebooting the system is intrusive to the end user experience, interrupts active work, and subjects the system and end user to the time and stress of the reboot cycle.

[0006] To solve these problems, the described techniques allow for selective activation and deactivation of a processor's cores "on the fly" and without rebooting the system. Additionally, the system coordinates the processor's active cores and also informs the operating system of the currently active cores, thereby allowing the operating system to inform various applications of the currently active cores. By doing so, applications and the operating system are prevented from scheduling tasks on deactivated cores, and instead, the system is forced to utilize only activated cores to perform tasks.

[0007] The ability to dynamically change the number of active cores without rebooting the system reduces interruptions to active work while also improving the end-user experience compared to conventional systems. Additionally, activating and deactivating cores "on the fly" allows the system to optimize the number of active cores for a variety of different usage scenarios and system conditions by deactivating cores that are too hot or too slow, optimizing the number of active cores for different applications or workflows, etc.

[0008] In some aspects, the techniques described herein relate to a method that includes operating a processor having a plurality of cores using a first core configuration; receiving a request to switch from the first core configuration to a second core configuration; and, in response to the request, switching from the first core configuration to the second core configuration by adjusting a number of active cores of the processor without rebooting.

[0009] In some aspects, the techniques described herein relate to a method, where switching from the first core configuration to the second core configuration further includes deactivating one or more cores of the processor without rebooting.

[0010] In some aspects, the techniques described herein relate to a method, where switching from the first core configuration to the second core configuration further includes activating one or more cores of the processor without rebooting.

[0011] In some aspects, the techniques described herein relate to a method, where a first core configuration has a different number of active cores than a second core configuration.

[0012] In some aspects, the techniques described herein relate to a method, where a first core configuration has a different selection of active cores than a second core configuration.

[0013] In some aspects, the techniques described herein relate to a method, further including notifying an operating system of the number of active cores.

[0014] In some aspects, the techniques described herein relate to a method, wherein the informing includes providing an active core report to an operating system, the active core report formatted in accordance with an Advanced Configuration and Power Interface (ACPI) specification.

[0015] In some aspects, the techniques described herein relate to a method, whereby the informing causes an operating system to provide an indication of active cores to one or more applications.

[0016] In some aspects, the techniques described herein relate to a method, further including notifying at least one of an operating system or an application of the brand configuration of the processor that corresponds to the second core configuration.

[0017] In some aspects, the techniques described herein relate to a method, where the request is received via a user input to a user interface selecting one or more cores to deactivate.

[0018] In some aspects, the technology described herein relates to a method, where the request is received via a user input to a user interface selecting one or more cores to activate.

[0019] In some aspects, the technology described herein relates to a method, where the request is received from an application or an operating system.

[0020] In some aspects, the technology described herein relates to a system including a memory, a processor having a plurality of cores, and a controller configured to selectively activate and deactivate cores of the processor without rebooting.

[0021] In some aspects, the techniques described herein relate to a system in which a controller is configured to deactivate a core of a processor without rebooting by communicating a signal to the processor to power gate or clock gate the core to be deactivated.

[0022] In some aspects, the techniques described herein relate to a system, where a controller is configured to selectively activate and deactivate cores of a processor without rebooting by switching from a first core configuration to a second core configuration.

[0023] In some aspects, the techniques described herein relate to a system, where a first core configuration has a different number of active cores than a second core configuration.

[0024] In some aspects, the techniques described herein relate to a system, where a first core configuration has a different selection of active cores than a second core configuration.

[0025] In some aspects, the technology described herein relates to a system, wherein the controller is further configured to inform an operating system of the number and selection of active cores of the processor.

[0026] In some aspects, the techniques described herein relate to a method, including displaying a user interface including controls for activating or deactivating cores of a processor having multiple cores, receiving user input via the user interface to deactivate one or more cores of the processor, and deactivating one or more cores of the processor without rebooting.

[0027] In some aspects, the technology described herein relates to a method, where a user interface includes a control component for activating or deactivating each of a plurality of cores of a processor.

[0028] 1 is a block diagram of a non-limiting exemplary system 100 having a processor with multiple cores and a controller for activating and deactivating the cores without rebooting. In particular, system 100 includes a processor 102 having multiple cores 104. A processor having multiple cores (e.g., two or more individual processing units) on a single integrated circuit is commonly referred to as a "multi-core processor." System 100 also includes a controller 106 and a memory 108. Processor 102, controller 106, and memory 108 are operable to implement an operating system 110 and one or more applications 112.

[0029] According to the described techniques, the processor 102, the controller 106, and the memory 108 are coupled to each other via wired or wireless connections. Exemplary wired connections include, but are not limited to, a system bus connecting two or more of the processor 102, the controller 106, and the memory 108. Examples of devices in which the system 100 may be implemented include, but are not limited to, servers, personal computers, laptops, desktops, game consoles, set-top boxes, tablets, smartphones, mobile devices, virtual and / or augmented reality devices, wearables, medical devices, systems-on-chips, and other computing devices or systems.

[0030] Memory 108 is a device or system used to store information, such as for immediate use within the device, by processor 102, for example. In one or more embodiments, memory 108 corresponds to a semiconductor memory in which data is stored in memory cells on one or more integrated circuits. In at least one example, memory 108 corresponds to or includes a volatile memory, examples of which include random-access memory (RAM), dynamic random-access memory (DRAM), synchronous dynamic random-access memory (SDRAM), and static random-access memory (SRAM). Alternatively or additionally, memory 108 corresponds to or includes non-volatile memory, examples of which include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electronically erasable programmable read-only memory (EEPROM). Memory 108 can be configured in various ways to support dynamically adjusting the number and selection of active cores in processor 102 without departing from the spirit or scope of the described technology.

[0031] Generally, the controller 106 communicates with the operating system 110 to coordinate the operation of hardware components, including the operation of the processor 102. By way of example and not limitation, the controller 106 sends signals to components (e.g., the processor 102) to adjust the operation of those components, such as by adjusting the power consumption of the components, adjusting the speed of cooling fans, and sending signals to activate and / or deactivate components. This includes sending signals to adjust the operation of components to prevent overheating and excessive energy usage. In one or more variations, the controller 106 is implemented using hardware, software, firmware, or a combination thereof. One example of a controller 106 is a system management unit (SMU) with SMU firmware.

[0032] According to the described techniques, the controller 106 is configured to selectively activate and deactivate the cores 104 of the processor 102 without rebooting the system 100. For example, the controller 106 is configured to signal the processor 102 to activate or deactivate the cores 104 individually without rebooting the system 100. Alternatively or additionally, the controller 106 is configured to signal the processor 102 to activate or deactivate multiple cores 104 at once without rebooting the system 100. In one or more embodiments, the controller 106 communicates signals to the processor 102 to power-gate and / or clock-gate the cores 104 that are to be deactivated. Such signals communicated by the controller 106 to the processor 102 to adjust the number of active cores 104 and / or which cores 104 are activated or deactivated are shown as core adjustment signals 114.

[0033] Adjusting which cores of a multi-core processor are active "on the fly" (e.g., without rebooting) contrasts with conventional techniques. For example, conventional approaches include rebooting the system. During the reboot, an adjusted number or selection of cores are activated. Additionally, the operating system is notified of the number or selection of active cores as part of the reboot. However, in accordance with the described techniques, the controller 106 adjusts the number or selection of active cores 104 without rebooting and notifies the operating system which cores are currently active.

[0034] In the illustrated example, the controller 106 is shown receiving a request 116 from the operating system 110. The controller 106 is also shown as informing the operating system 110 of the number of active cores. In this example, the controller 106 informs the operating system 110 of the number of active cores by providing an active cores report 118 to the operating system 110. Generally, the request 116 indicates an adjustment to the number or selection of cores 104 of the processor 102 such that how many and / or which cores 104 to activate or deactivate are indicated in or determinable from the request 116. The active cores report 118 indicates the adjustment to the active cores 104 to the operating system 110, e.g., the active cores report 118 indicates which cores 104 are to be activated (or deactivated) in association with the adjustment. In this manner, the controller 106 informs the operating system 110 and the application 112 of the current core count, e.g., the number of cores 104 that are active. In one or more embodiments, active cores report 118 includes a brand string that identifies the brand configuration of processor 102. In this manner, controller 106, in at least one embodiment, informs operating system 110 and applications 112 about the brand configuration of processor 102. As a result, through active cores report 118, operating system 110 is made “aware” of the throttling implemented by controller 106, which is implemented by power gating and / or clock gating one or more of cores 104.

[0035] In one or more embodiments, the controller 106 shapes the active cores report 118 to inform the operating system 110 about which cores 104 are to be activated (or deactivated) in conjunction with throttling. For example, the controller 106 shapes the active cores report 118 according to a specification associated with a power setting. In one or more embodiments, the controller 106 shapes the active cores report 118 according to an Advanced Configuration and Power Interface (ACPI) specification. In at least one such embodiment, the controller 106 is configured to (e.g., erroneously) indicate to the operating system 110 via the active cores report 118 that selective cores 104 (e.g., requested to be deactivated) are too hot (e.g., hotter than a threshold) or unavailable, even if the physical temperatures of those cores 104 do not actually exceed the threshold. If the operating system 110 is informed that the cores 104 are too hot, the operating system 110 is configured to programmatically take the cores 104 “offline” so that they cannot be used. As a result, a scheduler (not shown) of the operating system 110 avoids scheduling threads, processes and / or data flows using the core 104 that has been taken offline.

[0036] In at least one exemplary embodiment, the operating system 110 and / or one or more of its components are configured to monitor thermal zones (e.g., of the processor 102) and are further configured to instruct the controller 106 (e.g., via request 116) to control the state (e.g., power consumption and cooling fan speed) in which hardware components in those thermal zones operate based on the monitoring. In this example, the operating system 110 and / or one or more of its components are not configured to monitor the cores 104 themselves or to instruct the controller 106 to specifically activate or deactivate a particular core 104. This may be the case when communication between the operating system 110 and the controller 106 is governed by a specification, such as the ACPI specification. At least one version of the ACPI specification defines communication protocols for controlling the operating state of hardware components on a per-thermal zone basis rather than a per-core basis. Thus, in at least one such embodiment, the described techniques utilize these communication protocols to activate and deactivate the cores 104 without rebooting the system, and further, such that the operating system 110 is aware of the active cores 104.

[0037] By way of example, in one or more embodiments in which communications between the operating system 110 and the controller 106 are governed at least in part by such a specification, the controller 106 includes a table (not shown) that maps thermal zones to cores 104. For example, the table maps each core 104 to a respective thermal zone such that there is a one-to-one mapping between cores 104 and thermal zones. Thus, when the controller 106 receives an indication (via request 116) that a thermal zone is "too hot," the controller 106 identifies the respective core 104 based on the mapping between thermal zones and cores 104 in the table, and then deactivates the respective core 104.

[0038] In embodiments that further involve outputting a user interface and allowing a user to select which cores 104 of the processor 102 to activate or deactivate via the user interface, the application 112 or firmware corresponding to the user interface maps the selected cores 104 to thermal zones, e.g., by using a table similar to that included in the controller 106. Based on the mapping, the application 112 or firmware is configured to communicate to the operating system 110 an indication of which thermal zone to control, since the operating system 110 receives a type of information that allows it to communicate with the controller 106, e.g., thermal zone-based information rather than core-based information.

[0039] While the examples described above utilize a protocol for structuring communications between the operating system 110 and the controller 106 (e.g., requests 116 and active core reports 118) based on thermal zones, in one or more embodiments, the communications between the operating system 110 and the controller 106 are structured based on cores. In such embodiments, it is not necessary to use a mapping between cores and thermal zones (e.g., maintained in one or more tables). The requests 116 and active core reports 118 can be structured in a variety of ways that allow the controller 106 to activate and deactivate cores 104 on a per-core basis “on the fly” and allow the operating system 110 to inform applications 112 of how many cores are “online” and when a core 104 goes “offline” without rebooting, without departing from the spirit or scope of the described technology.

[0040] Upon being notified of the adjusted configuration of active cores 104, operating system 110 provides an indication of active cores 104 to application 112. In the illustrated example, core indication 120 indicates to application 112 the number of active cores 104 of processor 102 that are operational. Based on the number of active cores 104, a scheduler of operating system 110 schedules tasks 122 for processing by, e.g., on, active cores 104 of processor 102. These tasks 122 include threads, processes, and data flows for implementing application 112 and operating system 110.

[0041] In one or more embodiments, system 100 allows a user to provide input for adjusting active cores 104, such as how many active cores and / or which particular cores 104 are activated and deactivated. Exemplary user interfaces that allow a user to request adjustments to active cores are described in more detail in connection with Figures 3-5. In such examples, request 116 is based on and responsive to the user input.

[0042] Alternatively or additionally, system 100 may enable one or more of applications 112 to request adjustments to the active cores, such as how many active cores and / or which particular cores 104 are activated and deactivated. In such an example, request 116 is based on or responsive to a communication from application 112. Alternatively or additionally, operating system 110 (or a process of operating system 110) may be configured to request adjustments to the activated cores for various applications 112. For example, when a particular application 112 associated with a particular core configuration is launched, system 100 may enable operating system 110 or a process controlling the core configuration of the various applications to request an adjustment of the core configuration of processor 102 to the particular core configuration associated with the particular application.

[0043] In one or more embodiments, how many and / or which cores 104 are activated and deactivated are based on thermal optimization and / or power optimization. When active cores 104 are adjusted based on thermal optimization, for example, the number and selection of cores 104 for at least one configuration are adjusted such that each activated core 104 is sufficiently separated from other activated cores on an integrated circuit of the processor 102. In other words, there is sufficient space between the physical location of each active core 104 on the integrated circuit.

[0044] Consider an example where the processor 102 includes eight cores, where the eight cores 104 are arranged substantially along an axis, e.g., they are arranged "in-line." Also consider in this example that three of the eight cores 104 are activated. To minimize the thermal effect of the cores 104 on each other, one exemplary core configuration corresponds to activating the first core 104, the eighth core 104, and either the third or fourth core 104, and deactivating the other cores 104.

[0045] In one or more embodiments, at least one of the controller 106, the operating system 110, or the application 112 is configured to determine (or specify) which cores 104 to activate based on the number of cores 104 to be activated and based on thermal optimization. As an example, the controller 106, the operating system 110, or the application 112 references a table that specifies which cores 104 of the processor 102 to activate based on the number of active cores 104 and the type of optimization (e.g., thermal). Alternatively or additionally, the controller 106, the operating system 110, and / or the application 112 may request to switch from using activated cores 104 at a given time to using deactivated (and potentially cooled relative to the activated cores) cores 104 at a given time, e.g., by activating one or more of those deactivated cores.

[0046] In at least one embodiment in which active cores 104 are adjusted based on power optimization, the number and selection of cores 104 in at least one configuration are adjusted to minimize the amount of power consumed by the cores 104 in association with performing tasks 122 (e.g., threads, processes, and data flows). Consider an example in which an application 112 requires only one of the multiple cores 104 of the processor 102 to optimally perform the task of the application 112. In this example, without consideration of other applications 112 or tasks 122 associated with the operating system 110, an exemplary core configuration corresponds to only one core 104 being activated and the other cores 104 being deactivated.

[0047] In one or more embodiments, at least one of the controller 106, the operating system 110, or the applications 112 is configured to determine (or specify) which cores to activate based on optimizing power consumption. By way of example, the controller 106 and / or the operating system 110 are configured to determine the number and selection of cores 104 to activate based on the specified core requirements of the active applications 112, the tasks 122 of those applications, and / or the tasks 122 of the operating system 110. In other words, the core requirements of the applications 112 and the operating system 110 are taken into account when determining the number and selection of cores 104 to activate in order to optimize power consumption while still favorably processing the tasks 122.

[0048] Additionally, in one or more embodiments, the system 100 adjusts the configuration of active cores 104 based on one or more characteristics of the applications 112 actively using the processor 102, e.g., license fees for the applications associated with different numbers of cores. When a particular application 112 launches, for example, the controller 106 adjusts the active cores 104 on the fly (e.g., without rebooting), resulting in a particular number of cores 104 being activated. In at least one variation, a "brand string" for the processor 102 is communicated to the particular application 112 by another component of the system 100 (e.g., the operating system 110), the brand string being based on the number of cores 104 that are activated while the particular application 112 is running. In one or more variations, for example, the brand string communicated when eight cores 104 of the processor 102 are activated is different than the brand string communicated when one core 104 or sixteen cores 104 are activated. Thus, the brand string may indicate different brand configurations of the processor in relation to different numbers of active cores, even if the brand string includes the number of total cores 104 as the processor 102 is physically configured.

[0049] Consider an example in which an application 112 is associated with a first (cheaper) license fee to operate on a processor having a first (fewer) number of cores (e.g., an 8-core processor) and a second (higher) license fee to operate on a processor having a second (higher) number of cores (e.g., a 16-core processor). In accordance with the described techniques, the processor 102 can be adjusted on-the-fly to operate using the first fewer number of cores 104, and the operating system 110 can be configured to provide the application 112 with a brand string that is appropriate for the processor having the first fewer number of cores 104. In the context of adjusting the active cores of a processor "on-the-fly" (e.g., without rebooting), consider the following description of FIG. 2.

[0050] 2 illustrates a non-limiting example 200 in which a controller adjusts the number of active cores of a processor without rebooting. Example 200 includes processor 102, controller 106, and operating system 110 of FIG. 1. It should be understood that processor 102 includes multiple cores 104, although cores 104 are not shown in this example due to space constraints.

[0051] Example 200 includes various exemplary communications and actions over time between processor 102, controller 106, and operating system 110. In this example 200, the communications and actions are arranged vertically based on time (as shown in the left portion of the example), with communications and actions closer to the top of the example occurring before communications or actions further from the top of the example, and communications or actions closer to the bottom of the example occurring after communications or actions further from the bottom. Example 200 also illustrates various phases and / or states of system 100 or portions of system 100. These phases and / or states are also arranged vertically based on time in example 200, with phases or states closer to the top of the example occurring before phases, states, or communications further from the top.

[0052] Here, the illustrated example 200 shows a power off phase 202 and a boot phase 204 of the system 100. During the power off phase 202, the system 100 (and the processor 102) is powered off, examples of which include a soft off (e.g., a G2 / S5 state as specified by the Advanced Configuration and Power Interface (ACPI)) and a hard off (e.g., a G3 state as specified by ACPI), which require a reboot to return to a running state (e.g., a G0 / S0 state as specified by ACPI). During the boot phase 204, the system 100 performs various operations, such as hardware initialization, to advance the system 100 to a running state.

[0053] In accordance with the described techniques, boot phase 204 includes initialization 206 of processor 102. During boot phase 204, firmware such as, by way of example, a basic input / output system (BIOS) or unified extensible firmware interface (UEFI) initializes and tests processor 102 and other hardware of system 100 (e.g., memory 108). Additionally, the firmware (e.g., BIOS or UEFI) performs one or more tasks associated with initializing operating system 110, for example, by loading or executing a boot loader or operating system kernel that initializes operating system 110. The firmware then hands off to operating system 110, which then controls the hardware components.

[0054] During the boot phase 204, the processor 102 is initialized or otherwise adjusted to operate using a number of active cores 104 of the processor 102. For example, the processor is initialized to operate using a first core configuration 208. In the first core configuration 208, a number of cores of the processor 102 are activated such that the cores are operable to perform tasks 122 provided to it by the operating system 110. The number of cores 104 activated in connection with the boot phase 204 may vary from one core 104 to all cores 104. Additionally, the first core configuration 208 includes a particular selection of cores 104, including the number of cores. In an embodiment in which the processor 102 includes eight cores 104, there may be a number of different selections of, for example, four cores 104. Specifically, in an eight-core processor, there are 70 different possible selections of four activated cores 104, such as a first selection (first, second, third and fourth cores), a second selection (first, second, third and fifth cores), a third selection (first, second, third and sixth cores), a fourth selection (first, second, third and seventh cores), a fifth selection (first, second, third and eighth cores), a sixth selection (second, third, fourth and fifth cores), etc. It should be understood that the number and selection of active cores 104 that fall into the first core configuration 208 may vary without departing from the techniques described.

[0055] In accordance with the described techniques, the controller 106 receives a request 116 from the operating system to adjust the active cores 104, such as to switch from a first core configuration 208 to a second core configuration 210. By way of example, the request 116 may indicate switching to a different number of active cores 104 than the first core configuration 208. Alternatively or additionally, the request 116 may indicate switching to a different selection of active cores 104 from the first core configuration 208. The different selection of active cores 104 may correspond to the same or a different number of cores 104 as the first core configuration 208.

[0056] Based on the request 116, the controller 106 provides a core adjustment signal 114 to the processor 102, such as by power gating and / or clock gating the cores 104 of the processor 102. The core adjustment signal 114 is configured to adjust which cores 104 are active, such as by activating and deactivating various cores 104 to obtain a second core configuration 210. In response to the core adjustment signal 114, the processor 102 is adjusted to operate using a second core configuration 210 having at least one of a different number or selection of active cores 104 than the first core configuration 208. In the illustrated example 200, the processor 102 operates using the second core configuration 210 after operating using the first core configuration 208. In particular, the processor 102 is shown in the example 200 operating using the first core configuration 208 and being adjusted to operate using the second core configuration 210 without rebooting. Adjusting without rebooting means that no additional boot phases are indicated when the processor 102 switches to the second core configuration 210 while operating in the first core configuration 208 or while the processor 102 is operating in the second core configuration 210.

[0057] In addition to throttling active cores 104 without rebooting, system 100 notifies operating system 110 of the adjustments made to cores 104, which allows operating system 110 to notify applications 112 (not shown in this example) that active cores 104 have been throttled, for example, providing current core count and / or brand configuration information. In this manner, applications 112 and operating system 110 do not schedule any tasks 122 on deactivated cores 104, but instead use only activated cores 104 to perform tasks 122. As discussed above, controller 106 notifies operating system 110 about active cores 104 using active core report 118, which in one or more embodiments indicates activated and deactivated cores using "thermal zones."

[0058] The illustrated example 200 is also shown as including tasks 122. The operating system 110 schedules one or more of the tasks 122 to be performed by the processor 102 (e.g., its active cores 104) while the processor 102 is operating using the first core configuration 208. As described above, examples of the tasks 122 include threads, processes, and data flows. In at least one example, the processor 102 requests and obtains data from the memory 108 to fulfill the tasks 122 while operating using the first core configuration 208. The operating system 110 also schedules one or more of the tasks 122 to be performed by the processor 102 (e.g., its active cores 104) while the processor 102 is operating using the second core configuration 210. According to the described techniques, the controller 106 can cause the processor 102 to switch from operating using the second core configuration 210 to operating using the first core configuration 208 or using a different core configuration without rebooting. Consider the following description of Figures 3-5 in the context of allowing a user to request the number and / or selection of active cores 104 and adjusting which cores 104 are active to operate the processor 102 using the requested cores 104.

[0059] 3 illustrates a non-limiting example of a user interface 300 in one or more embodiments. The example 300 includes a display device 302 that outputs a core control user interface 304 that allows a user to control which cores 104 are active and to selectively activate and deactivate cores 104 without rebooting.

[0060] In the depicted example 300, the user interface 304 is shown displaying indicia of multiple cores 104 of the processor 102. In one or more embodiments, the indicia of the multiple cores 104 are displayed in a manner that indicates or substantially corresponds to their physical location on an integrated circuit of the processor 102.

[0061] Here, the user interface 304 includes a respective control component 306 for each of the cores 104. The control components 306 are selectable by a user to request activation or deactivation of the respective core 104. For example, if a core 104 is active, the respective control component 306 is selectable to request that the core 104 be deactivated. However, if a core 104 is not active (e.g., deactivated), the respective control component 306 is selectable to request that the core 104 be activated.

[0062] In this example 300, the user interface 304 also includes mode control components 306 that are selectable to request a particular operating mode of the processor 102 or that are transitioned to (and visually highlighted) based on a user selection of one or more of the respective control components 308. In one or more variations, the different modes correspond to different numbers of active cores 104, such as a mode in which all cores 104 are active, and various modes in which different subsets of the cores 104 are active. Although not shown, in one or more embodiments, the user interface 304 includes control components that allow a user to select various optimizations of the processor, such as to optimize which cores are activated to optimize for power consumption, thermal conditions, and performance, to name a few.

[0063] In one or more embodiments, system 100 throttles active cores 104 in response to a selection of a single respective control component 306. For example, in response to a selection of a single respective control component 306, operating system 110 submits a request 116 to controller 106 indicating to throttle (e.g., activate or deactivate) each respective core 104. In response, controller 106 throttles (e.g., activates or deactivates) each respective core 104 in accordance with request 116 without rebooting. Controller 106 then communicates active core report 118 to operating system 110 to inform operating system 110 of the throttle.

[0064] Alternatively, system 100 may adjust the active cores 104 in response to a selection of a single mode control component 308, in response to a selection of one or more of the respective control components 306 and a selection of the application control component 310, and / or in response to a selection of a mode control component 308 and a selection of the application control component 310. Once a mode control component 308 is selected, in one or more embodiments, a component of system 100 (e.g., application 112, operating system 110, or controller 106) adjusts the active cores 104 and determines which cores 104 to activate or deactivate to enable processor 102 to operate using the requested mode. In one example, for example, application 112, operating system 110, or controller 106 may reference a table indicating the configuration of active cores 104 such that the cores to activate and deactivate can be determined based on a difference between the indicated configuration and the currently active cores. Alternatively or additionally, application 112, operating system 110, or controller 106 determines which cores to activate or deactivate based at least in part on the state of core 104, such as whether core 104 is currently running, whether core 104 was running in the previous time interval, the temperature of core 104, the amount of time core 104 has been running, etc.

[0065] In either case, the user interface 304 supports receiving user input (e.g., one or more tap inputs) to request adjustments to the active cores 104 of the processor 102 on the fly, for example, without rebooting. Thus, according to the described technique, in response to receiving user input via the user interface 304, the operating system 110 submits a request 116 to the controller 106 indicating to adjust (e.g., activate or deactivate) the cores 104, the controller 106 adjusts (e.g., activate or deactivate) one or more of the cores 104 in accordance with the request 116 without rebooting, and the controller 106 communicates an active core report 118 to the operating system 110 to inform the operating system 110 of the adjustments. In one or more embodiments, the adjustments to the different active cores 104 (e.g., from a first core configuration 208 to a second core configuration 210) do not substantially affect a user's interaction with the respective computing device. For example, a user may continue to interact with the computing device without experiencing any significant "downtime" since the computing device is not rebooted and operating system 110 is notified of the adjustment.

[0066] Note that in this example 300, all of the respective control components 306 include the text "deactivate," which indicates that all of the respective cores 104 will be active when the user interface 304 is output. Additionally, the mode control component 308 having the text "all core mode" is visually highlighted relative to the other mode control components 308. This indicates that "all core mode" is the "active" mode, e.g., the mode upon which the processor 102 will be configured when the user interface 304 is displayed. In this example, "all core mode" corresponds to operating the processor 102 with all of its cores 104 active. In the context of adjusting active cores 104 based on user input, consider the following example.

[0067] 4 illustrates another non-limiting example of a user interface 400 in accordance with one or more embodiments. The example 400 includes a display device 302 that displays the user interface 304 of FIG.

[0068] In contrast to the example shown in FIG. 3, the illustrated example 400 illustrates a scenario in which not all of the cores are indicated as active within the user interface 304. Instead, the illustrated example 400 depicts, at 402, any of the cores 104 of the processor 102 being deactivated. In one example, the core 104 was previously deactivated based on a user input selecting the respective control component 306, for example, where the respective control component 306 included the text "deactivated." In this example 400, the indicia of the cores 104 and respective control components 306 at 402 are displayed with one or more characteristics that distinguish the indicia and / or control components from the indicia and / or control components of activated cores. Here, for example, the indicia of the deactivated cores 104 and respective control components 306 at 402 are shown with a different visual emphasis than the activated cores. It should be appreciated that the user interface 304 can be configured in various ways to distinguish between activated and deactivated cores without departing from the spirit or scope of the described technology. The control components 306 of each of the activated and deactivated cores can be configured in various ways (e.g., in addition to or different from text) for the activated and deactivated cores 104 without departing from the spirit or scope of the described technology.

[0069] 5 illustrates another non-limiting example 500 of a user interface in accordance with one or more embodiments. The example 500 also includes a display device 302 that displays the user interface 304 of FIG.

[0070] 4, the illustrated example 500 illustrates a scenario in which multiple cores 104 are shown as being deactivated in the user interface 304. In particular, the illustrated example 400 depicts, at 502, 504, 506, 508, multiple cores 104 of the processor 102 being deactivated based on, for example, user input on respective control components 306 selecting those cores 104 to be deactivated.

[0071] While user interface 304 is shown as displayed, in one or more embodiments, a user interface that enables receiving user input to request adjustments to active cores of a processor is configured, at least in part, in a variety of ways. In one or more embodiments, for example, the user interface is at least in part voice-based, e.g., the user interface receives voice commands and initiates actions based on those commands, and / or the user interface audibly outputs information regarding the active cores. It should be understood that a user interface that enables adjustments to various numbers of active cores without rebooting may be configured differently than illustrated and described herein without departing from the spirit or scope of the described technology.

[0072] Having described an example system and user interface for activating and deactivating cores of a multi-core processor, consider the following example procedure.

[0073] FIG. 6 illustrates a procedure in an exemplary embodiment 600 for adjusting the number of active cores of a multi-core processor.

[0074] A processor having multiple cores operates using a first core configuration (block 602). As an example, during the boot phase 204, the processor 102 is initialized or otherwise adjusted to operate using a number of active cores 104 of the processor 102. For example, the processor operates using a first core configuration 208. In the first core configuration 208, a number of cores of the processor 102 are activated such that the cores are operable to perform tasks 122 provided to it by the operating system 110. The number of cores 104 activated in connection with the boot phase 204 can vary from one core 104 to all cores 104. Additionally, the first core configuration 208 includes a particular selection of cores 104, including the number of cores. In an embodiment in which the processor 102 includes eight cores 104, there are a number of different selections of, for example, four cores 104.

[0075] A request to switch from the first core configuration to the second core configuration is received (block 604). By way of example, the controller 106 receives a request 116 from the operating system to adjust the active cores 104, such as to switch from the first core configuration 208 to the second core configuration 210. By way of example, the request 116 indicates switching to a different number of active cores 104 than the first core configuration 208. Alternatively or additionally, the request 116 indicates switching to a different selection of active cores 104 from the first core configuration 208. The different selection of active cores 104 may correspond to the same or a different number of cores 104 as the first core configuration 208.

[0076] In response to the request, a switch from the first core configuration to the second core configuration is performed by adjusting the number of active cores of the processor without rebooting (block 606). By way of example, based on the request 116, the controller 106 provides a core adjustment signal 114 to the processor 102, such as by power gating and / or clock gating the cores 104 of the processor 102. The core adjustment signal 114 is configured to adjust which cores 104 are active, such as by activating and deactivating various cores 104 to obtain the second core configuration 210. In response to the core adjustment signal 114, the processor 102 is adjusted to operate using a second core configuration 210 having at least one of a different number or selection of active cores 104 than the first core configuration 208. In particular, the processor 102 is adjusted to operate using the second core configuration 210 without rebooting.

[0077] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in specific combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0078] The various functional units illustrated in the figures and / or described herein (including, where appropriate, the processor 102 having multiple cores 104, the controller 106, the memory 108, the operating system 110, and the application 112) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be implemented in any of a variety of devices, such as a general purpose computer, a processor, or a processor core. Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine.

[0079] In one or more embodiments, the methods and procedures provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method comprising: operating a processor having multiple cores using a first core configuration; receiving a request to switch from the first core configuration to a second core configuration; and switching from the first core configuration to the second core configuration in response to the request by adjusting a number of active cores of the processor without rebooting. method.

2. switching from the first core configuration to the second core configuration includes deactivating one or more cores of the processor without rebooting.

2. The method of claim 1.

3. switching from the first core configuration to the second core configuration includes activating one or more cores of the processor without rebooting.

2. The method of claim 1.

4. the first core configuration has a different number of active cores than the second core configuration.

2. The method of claim 1.

5. the first core configuration has a different selection of active cores than the second core configuration.

2. The method of claim 1.

6. and notifying an operating system of the number of active cores.

2. The method of claim 1.

7. The notifying includes providing an active cores report to the operating system; the active core report is formatted according to the Advanced Configuration and Power Interface (ACPI) specification; The method of claim 6.

8. and wherein the notifying causes the operating system to provide an indication of the active cores to one or more applications. The method of claim 6.

9. and informing at least one of an operating system or an application of a brand configuration of the processor that corresponds to the second core configuration.

2. The method of claim 1.

10. the request is received via a user input to a user interface selecting one or more cores to deactivate; 2. The method of claim 1.

11. the request is received via a user input to a user interface selecting one or more cores to activate; 2. The method of claim 1.

12. The request is received from an application or an operating system.

2. The method of claim 1.

13. 1. A system comprising: Memory, A processor having multiple cores; a controller configured to selectively activate and deactivate cores of the processor without rebooting; system.

14. the controller is configured to deactivate a core of the processor without rebooting by communicating a signal to the processor to power-gate or clock-gate the core to be deactivated; The system of claim 13.

15. the controller is configured to selectively activate and deactivate cores of the processor without rebooting by switching from a first core configuration to a second core configuration. The system of claim 13.

16. the first core configuration has a different number of active cores than the second core configuration.

16. The system of claim 15.

17. the first core configuration has a different selection of active cores than the second core configuration.

16. The system of claim 15.

18. The controller is configured to inform an operating system of a number and selection of active cores of the processor. The system of claim 13.

19. 1. A method comprising: Displaying a user interface including controls for activating or deactivating cores of a processor having multiple cores; receiving a user input via the user interface to deactivate one or more cores of the processor; deactivating one or more cores of the processor without rebooting. method.

20. the user interface includes a control component for activating or deactivating each of the plurality of cores of the processor; 20. The method of claim 19.

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