Substrates for Electronic Devices

Abstract

The invention relates to a substrate for a power or high frequency electronic device comprising a free-standing support substrate (30) made of polycrystalline silicon carbide having a front surface (10) and a rear surface (20), and a surface layer (1) of monocrystalline silicon carbide extending over the front surface (10) of the support substrate (30), said substrate being characterized in that the support substrate (30) has at least one porous portion (3) extending from the rear surface (20), the porous portion (3) having a porosity greater than 5%.

Description

[Technical field]

[0001] The present invention relates to a substrate for electronic devices, in particular for high frequency or power electronic applications. The present invention also relates to an electronic device comprising such a substrate, and to a process for manufacturing such a substrate. [Background technology]

[0002] Silicon carbide (SiC) is widely used for the manufacture of high frequency or power electronic components.

[0003] Substrates for creating such components typically comprise a support substrate, which may be made of polycrystalline SiC (p-SiC), and a surface layer of monocrystalline SiC (m-SiC) extending over the support substrate. The electronic components are manufactured in or on the layer of monocrystalline SiC. The structures are cut in the form of chips, each of which comprises one or more electronic components. Each chip is brazed to a direct bond copper stack comprising a metal layer, a thermally conductive ceramic, and a heat sink.

[0004] Therefore, heat is dissipated primarily through the direct bond copper stack, which entails significant thermal stresses on the filler that connects the electronic component to the upper metal layer of the direct bond copper stack by brazing.

[0005] However, the coefficients of thermal expansion (CTE) and Young's modulus of the SiC and direct bond copper stacks, especially of copper, are quite different, and therefore temperature fluctuations cause non-uniform deformation of the various layers below and above the braze.

[0006] As a result, the filler is subjected to high loads which can cause cracking, delamination or flaking at the braze interface, which can shorten the life of the device.

[0007] To reduce these mechanical stresses, it is known to thin the layers of the composite structure, in particular the layers of the base substrate made of polycrystalline SiC. However, thinning such a base substrate requires a lot of time and effort, which results in an increase in the cost of the electronic component. Furthermore, thinning entails the risk of fractures that would render the composite structure unusable.

[0008] Another solution would be to change the materials used to create the braze, which is difficult to implement, especially while maintaining the mechanical stability and electrical and thermal conductivity of the braze. Summary of the Invention

[0009] The aim of the present invention is to propose a composite structure for producing electronic devices with better resistance to temperature cycling while avoiding cracks, delamination and flaking at the brazed interface.

[0010] For this purpose, the present invention comprises: a free-standing support substrate made from polycrystalline silicon carbide having a front surface and a rear surface; a surface layer of monocrystalline silicon carbide extending over a front surface of said support substrate; A substrate for a high frequency or power electronic device is proposed, comprising: The substrate is characterized in that a support substrate has at least one porous portion extending from a rear surface thereof, the porous portion having a porosity greater than 5%.

[0011] The support substrate has a thickness greater than 50 μm, preferably greater than 80 μm, more preferably greater than 100 μm, and even more preferably greater than 150 μm.

[0012] The porous portion preferably comprises a layer of porosified SiC.

[0013] In some embodiments, the support substrate comprises a non-porous portion between a surface layer of single crystal SiC and the porous portion.

[0014] In some embodiments, the porous portion has a rear portion having a first porosity and a front portion having a second porosity that is less than the first porosity.

[0015] The porous portion may have a porosity gradient that decreases from the rear surface to the front surface.

[0016] The porous portion may have pores filled with a material having a Young's modulus lower than that of silicon carbide.

[0017] Suitably the average distance between the pores is greater than 10 nm, preferably greater than 50 nm.

[0018] The present invention also relates to an electronic device comprising the substrate described above and at least one high frequency or power electronic component formed in or on the surface layer of monocrystalline silicon carbide.

[0019] The electronic device preferably further comprises a heat dissipation device, and the substrate is brazed to the heat dissipation device through the filler such that the filler is in integral contact with at least a portion of the porous portion on the rear surface of the support substrate.

[0020] Another subject of the invention is a free-standing support substrate made from polycrystalline silicon carbide having a front surface and a rear surface; a surface layer of monocrystalline silicon carbide extending over a front surface of said support substrate; A process for manufacturing a high frequency or power electronic device comprising: The process includes forming at least one porous portion in a support substrate extending from a rear surface, the porous portion being characterized by a porosity greater than 5% and a thickness greater than 100 nm, preferably greater than 1 μm, and more preferably greater than 3 μm.

[0021] The process may further include the step of assembling the surface layer with a support substrate.

[0022] The support substrate preferably has a thickness greater than 50 μm, preferably greater than 80 μm, more preferably greater than 100 μm, even more preferably greater than 150 μm.

[0023] Preferably, forming the support substrate includes porosifying at least a portion of a non-porous silicon carbide base substrate to form a porous portion.

[0024] In some embodiments, porosification is performed on all of the base substrate to form a completely porous support substrate.

[0025] The porosification may be performed to create a decreasing porosity gradient in the porous portion from the rear surface to the front surface.

[0026] The porosification may be carried out to form a bonding zone on the front surface of the support substrate having a porosity of less than 40%.

[0027] In some embodiments, the process includes filling at least some of the pores of the porous portion with a material having a Young's modulus lower than that of silicon carbide.

[0028] The process may further include thinning the support substrate through the rear surface such that the thickness of the porous portion remains 100 nm or greater.

[0029] Other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0030] [Figure 1] FIG. 1 shows a device comprising two electronic components made from a substrate and a direct bond copper stack according to the present invention. [Diagram 2]FIG. 1 shows a substrate according to the invention comprising a surface layer made of monocrystalline silicon carbide and a support substrate comprising a porous portion. [Diagram 3] FIG. 2 shows a substrate according to the invention comprising a surface layer made from monocrystalline silicon carbide and a support substrate comprising porous and non-porous portions made from porosified polycrystalline SiC. [Figure 4] FIG. 2 shows a substrate according to one embodiment comprising a surface layer made from monocrystalline silicon carbide and a support substrate comprising porous and non-porous portions made from sintered SiC. [Diagram 5] FIG. 2 shows a substrate according to another embodiment comprising a surface layer made of monocrystalline silicon carbide and a support substrate comprising a non-porous portion and a porous portion including two zones of different porosity. [Figure 6] 1 is a graph for measuring the resistance to fracture of substrates made from porous silicon carbide as a function of the porosity of said substrate. [Figure 7A] 1A-1D illustrate steps of one embodiment of a process for manufacturing a substrate according to the present invention. [Figure 7B] 1A-1D illustrate steps of one embodiment of a process for manufacturing a substrate according to the present invention. [Figure 7C] 1A-1D illustrate steps of one embodiment of a process for manufacturing a substrate according to the present invention. [Figure 7D] 1A-1D illustrate steps of one embodiment of a process for manufacturing a substrate according to the present invention. [Figure 8A] 5A-5D illustrate steps of another embodiment of a process for manufacturing a substrate according to the present invention. [Figure 8B] 5A-5D illustrate steps of another embodiment of a process for manufacturing a substrate according to the present invention. [Figure 8C] 5A-5D illustrate steps of another embodiment of a process for manufacturing a substrate according to the present invention. [Figure 8D] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 8E] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 8F] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 8G] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 8H] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 8I] 8A-8C depict steps of a variation of the embodiment of the process shown in FIG. [Figure 9A] 5A-5D show steps of a third embodiment of a process for manufacturing a substrate according to the invention. [Figure 9B] 5A-5D show steps of a third embodiment of a process for manufacturing a substrate according to the invention. [Figure 10A] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 10B] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 10C] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 10D] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 10E] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 10F] 5A-5D show steps of a fourth embodiment of a process for manufacturing a substrate according to the invention. [Figure 11A] 5A-5D show steps of a fifth embodiment of a process for manufacturing a substrate according to the invention. [Figure 11B] 5A-5D show steps of a fifth embodiment of a process for manufacturing a substrate according to the invention. [Figure 11C] 5A-5D show steps of a fifth embodiment of a process for manufacturing a substrate according to the invention. [Figure 11D] 5A-5D show steps of a fifth embodiment of a process for manufacturing a substrate according to the invention. [Figure 11E] 5A-5D show steps of a fifth embodiment of a process for manufacturing a substrate according to the invention. [Figure 12] 1 is a graph of Young's modulus for various specimens made from porous silicon carbide as a function of the porosity of the sample. [Figure 13] 1 is a graph of Young's modulus for various samples made from silicon carbide. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] For ease of reading the drawings, the structures shown are not necessarily drawn to scale.

[0032] Figure 1 shows a high frequency or power electronic device comprising one or more electronic chips 11, 12 produced from a substrate according to the invention. The chips may be linked by interconnects. In the case of a high frequency device, the electronic chip may support a lateral device made from gallium nitride.

[0033] The electronic chips 11, 12 are mounted on a direct bond copper structure via brazing 21, 22. This direct bond copper (DBC) structure comprises two copper metallizations 17, 19 and a substrate 18 made of a thermally conductive and electrically insulating ceramic, for example made of aluminum nitride. Electrical connections 27, 28 are fixed to the copper metallization 17 via brazing 25, 26.

[0034] Braze 29 secures the device to the heat sink 34 and base plate 32. A layer of thermal grease 31 ensures thermal contact between the heat sink 34 and the base plate 32. High frequency or power electronic devices are enclosed in a casing 39, typically made from plastic.

[0035] Each chip is formed from a substrate that includes a support substrate made from silicon carbide and a surface layer of single crystal silicon carbide having at least one power or high frequency electronic component formed therein or thereon.

[0036] The surface layer made of monocrystalline silicon carbide typically has a thickness ranging from 100 nm to 1500 nm, on which it is possible to epitaxially deposit a monocrystalline layer made of silicon carbide having a thickness ranging from 1 μm to 150 μm, on which at least part of the electronic component is formed.

[0037] The support substrate has a front surface along which the surface layer extends and a rear surface opposite the front surface.

[0038] The surface layer may be assembled on a support substrate, which may be polycrystalline, according to embodiments described later.

[0039] The support substrate may be integral or may be composed of a stack of at least two layers. The thickness of the support substrate is preferably selected so that the support substrate is free-standing without a surface layer, i.e., the support substrate is mechanically stable enough to be manipulated alone without the addition of additional handling substrates or supports. For this purpose, the support substrate typically has a thickness of more than 150 μm, preferably more than 100 μm, more preferably more than 80 μm, and even more preferably more than 50 μm. The use of a free-standing support substrate preferably facilitates the step of manufacturing the substrate.

[0040] In some cases, electronic devices can be manufactured from a supporting substrate that is not necessarily freestanding, without any limitations on thickness. In this case, a heat dissipation device allows the electronic components to be mechanically stabilized. The manufacture of such a substrate may require a handling support. However, the supporting substrate can be produced according to the same embodiments as the freestanding supporting substrate.

[0041] For power electronic devices, good electrical conductivity between the thin layer and the supporting substrate is necessary. For such devices, the supporting substrate has, for example, an electrical resistivity of 50 mΩ.cm or less, in particular 20 mΩ.cm or less.

[0042] For high frequency devices, the supporting substrate preferably has a high electrical resistivity, for example greater than 500 Ω.cm.

[0043] The support substrate has at least one porous portion extending from the rear surface. In contrast, the surface layer is non-porous, i.e., has a porosity of less than 5% or zero.

[0044] The porosity of silicon carbide is defined as the unoccupied volume fraction in silicon carbide that can be filled with air or another gas or solid inclusions of another material. For example, the pores of a layer of porous silicon carbide can be filled with carbon inclusions.

[0045] The pores may be interconnected or separate from one another, depending in particular on the method for forming the porous layer. Typically, the pores resulting from electrochemical porosification of silicon carbide are at least partially interconnected and generally filled with air. In the case of porous silicon carbide obtained by sintering, the pores are typically separate from one another and may be at least partially filled with carbon inclusions.

[0046] In the case of air-filled interconnected pores, the porosity can be measured gravimetrically. In other cases, the porosity can be measured by the reflectivity of the porous surface of the silicon carbide. It is also possible to measure the porosity by observing a cross-section of the porous silicon carbide using an optical microscope or electron beam scanning and estimating the quotient of the surface area occupied by the pores and / or inclusions and the surface area occupied by the silicon carbide.

[0047] The porosity of the porous portion of the support substrate preferably ranges from 5% to 30%, and more preferably from 5% to 20% for substrates made from porous silicon carbide. The porosity may be constant throughout the thickness of the porous portion or may vary gradually or continuously along a gradient, according to embodiments described later.

[0048] The presence of such porosity makes it possible to reduce the Young's modulus of silicon carbide. Figure 12 shows the Young's modulus (elastic modulus, E) of silicon carbide as a function of the porosity Φ according to LLSnead et al. It should be noted that, despite the wide dispersion, the reduction in Young's modulus is evident even at low porosities, especially from a porosity of about 5%.

[0049] When the pores are filled with inclusions of a solid material, the solid material preferably has a Young's modulus less than that of silicon carbide so as not to offset the reduction in Young's modulus caused by the porosity of silicon carbide. Furthermore, the solid material is preferably an electrical conductor so as not to adversely affect the electrical conductivity of the support substrate. For example, the inclusions may include carbon, silicon, a metal or a metal alloy.

[0050] A porosity of 30% or less makes it possible to maintain an acceptable strength at break in the face of the mechanical stresses likely to be applied to the chip, especially when the support substrate is entirely porous. Figure 6 shows the measured strength at break in MPa m as a function of the porosity of the porous silicon carbide samples. 1 / 2For porosity up to about 25%, the change in strength at break is negligible with respect to the behavior of the electronic chip.

[0051] In some embodiments, the porous portion extends through the entire thickness of the support substrate.

[0052] In other embodiments, the porous portion extends through only a portion of the thickness of the support substrate, with a non-porous intermediate portion extending between the porous portion and the surface layer. Such a configuration typically has better resistance to substrate breakage.

[0053] In all cases the porous portion has a total thickness greater than 100 nm, preferably greater than 1 μm or even greater than 3 μm.

[0054] Thanks to such a thickness, combined with the aforementioned porosity, the porous portion of the support substrate has a Young's modulus significantly lower than that of non-porous silicon carbide and therefore has a more favorable behavior for the reduction of the mechanical stresses exerted on the braze filler when the device is subjected to temperature fluctuations.

[0055] FIG. 13 is a graph (obtained by computer simulation) of the relative stress at the fatigue point in the braze as a function of the Young's modulus E of various substrates made from silicon carbide with porous portions of various thicknesses. The total thickness of each substrate is 350 μm. Curve 1 corresponds to a substrate without a porous portion, curve 2 to a thickness of 1 μm, curve 3 to a thickness of 5 μm, curve 4 to a thickness of 10 μm, curve 5 to a thickness of 25 μm, curve 6 to a thickness of 50 μm and curve 7 to a thickness of 100 μm. Each curve presents the stress in the braze at the outermost contact point between the braze and the porous SiC divided by the stress if the porous layer were not present.

[0056] The stress at the fatigue point of the braze decreases as the thickness of the porous part increases. In the simulation, it is assumed that the Young's modulus of porous SiC depends on the porosity, as shown in Figure 12. For example, for a porosity of 5%, the Young's modulus is 400 GPa. For a layer with a thickness of 10 μm (curve 4), a relative stress at the fatigue point of 0.93 is obtained, i.e. the stress is reduced by 7% compared to a substrate without a porous part. For a porosity of 15%, which corresponds to a Young's modulus of 300 GPa, and a porous layer with a thickness of 20 μm, the relative stress at the fatigue point is 0.8, thus reduced by 20% compared to a substrate without a porous part.

[0057] The Young's modulus of the porous part of the support substrate located at the brazing interface is closer to that of the DBC structure than to that of the surface layer. This means that the deformations caused by temperature fluctuations are less significant and closer to the deformations of the DBC structure and the brazing. As a result, the mechanical stresses exerted on the brazing by these deformations are less significant than in known chips. The reduction of these stresses increases the life of the brazing and of the high frequency or power electronic device.

[0058] Finally, the presence of such a porous portion on the rear surface of the substrate does not adversely affect the electrical conductivity of the substrate in power applications.

[0059] EXEMPLARY EMBODIMENTS Figure 2 shows a first substrate according to the invention, comprising a support substrate 30 and a surface layer 1. The support substrate 30 is composed of a single porous portion 3 made of porous silicon carbide with uniform porosity. This porous portion is made of sintered silicon carbide, porosified polycrystalline silicon carbide or porosified monocrystalline silicon carbide. The porous portion extends from the rear face 20 to the front face 10 of the support substrate 30. The surface layer 1 is made of non-porous monocrystalline silicon carbide. This layer is composed on the front face of the support substrate 30. In some embodiments, the porous portion and the surface layer are integrally formed from a single substrate of monocrystalline silicon carbide.

[0060] 3 shows a second embodiment in which the support substrate 30 comprises a portion 3A made of porous silicon carbide extending from the rear face 20 of the substrate. The porosity of this portion 3A is uniform. The pores are interconnected and filled with air. The support substrate 30 further comprises a non-porous portion 2A made of polycrystalline silicon carbide arranged between the porous portion and the front face 10 of the support substrate 30. A surface layer 1 made of non-porous monocrystalline silicon carbide is arranged on the front face 10 of the support substrate 30.

[0061] FIG. 4 shows a third embodiment in which the support substrate 30 comprises a portion 3B made of sintered silicon carbide extending from the rear face 20 of the substrate. Sintered silicon carbide contains carbon inclusions that may be separate from one another. The pores are therefore filled with carbon and are typically not interconnected. The porosity of this portion is uniform. The support substrate 30 further comprises a non-porous portion 2B made of polycrystalline silicon carbide arranged between the porous portion 3B and the front face 10 of the support substrate 30. A surface layer 1 made of non-porous monocrystalline silicon carbide is arranged on the front face 10 of the support substrate 30.

[0062] FIG. 5 shows a fourth embodiment in which the support substrate 30 comprises, from the rear side 20 to the front side of the support substrate 30, a first porous part 3C made of porosified silicon carbide, a second porous part 2D made of sintered silicon carbide and a non-porous part 2C. The pores of the first porous part 3C are interconnected and filled with air. The pores of the second porous part 2D are filled with carbon inclusions and are separated from each other. The porosity of the layer 3C made of porosified silicon carbide is greater than the porosity of the part 2D made of sintered silicon carbide. A surface layer 1 made of non-porous monocrystalline silicon carbide is arranged on the front side 10 of the support substrate 30.

[0063] In another embodiment not shown, the porous portion made from porosified silicon carbide has a porosity gradient such that the porosity decreases in a direction from the rear surface to the front surface of the support substrate.

[0064] In other embodiments not shown, several sections made of sintered or porous silicon carbide may be superimposed to form the support substrate 30 or parts of the support substrate 30. The size and shape of the pores may be similar or different in the various porous sections. Advantageously, the average distance between the pores is greater than 10 nm, preferably greater than 50 nm, in each porous section present in the substrate to avoid possible formation of depletion zones in the SiC.

[0065] In some embodiments, a support substrate, which may be non-freestanding, is used to form a high frequency or power electronic device. The substrate comprises a support substrate made of polycrystalline silicon carbide having a front surface and a rear surface, and a surface layer of monocrystalline silicon carbide extending over the front surface of the support substrate, the substrate being characterized in that the support substrate has at least one porous portion extending from the rear surface, the porous portion having a porosity greater than 5%. At least one high frequency or power electronic component is formed in or on the layer of monocrystalline silicon carbide.

[0066] The device may further include a heat dissipation device, the substrate being brazed to the heat dissipation device through the filler such that the filler is in integral contact with at least a portion of the porous portion on the rear surface of the support substrate. Substrate manufacturing Next, various embodiments of steps for manufacturing a substrate are described.

[0067] Formation of a substrate in accordance with the present invention involves the formation of at least one porous portion.

[0068] The porous portion may be formed by porosifying a silicon carbide substrate. Known methods for porosifying silicon carbide, some of which are described or referenced in the publications by Y. Shishkin et al. and Gautier et al., may be applied to form the porous portion. Porosification may be performed from the front or rear side of the substrate.

[0069] The porosification step can be carried out, for example, by acid bath immersion or electrochemically or photoelectrochemically. Electrochemical porosification can be electrochemical anodization, in which the part to be porosified is placed in an electrolyte, such as a solution containing hydrofluoric acid and / or ethanol. The anode and cathode, immersed in the electrolyte, are connected to a power source to apply an electric current between said electrodes. The anodization electrochemically decomposes, to a certain extent, the silicon carbide crystals in the region of the porous layer of silicon carbide. Instead of dissolving the silicon crystals uniformly, the electrochemical decomposition can locally remove silicon atoms from the silicon carbide crystal lattice, thus forming small holes or pores in the silicon carbide crystals. At the end of the treatment, the porosified part is rinsed to remove any electrolyte residues.

[0070] During the porosification step, it is possible to maintain the non-porous structure of a portion of the substrate, in which case said portion is kept outside the electrolytic bath.

[0071] In some cases, the porosity thus formed is uniform throughout the support substrate, except for the surface layer. In other embodiments, a decreasing porosity gradient is created from the rear surface to the front surface, such that the porosity is lower near the surface layer and higher near the rear surface. Porosity can also be gradually increased by first setting the porosification parameters for a particular thickness of substrate, and continuing this porosification in portions of decreasing thickness extending from the rear surface of the substrate. For each successive portion, the porosification parameters can be changed to produce a greater porosity than in the previous step.

[0072] It is possible to modify the porosity and generate gradients by varying different parameters of the substrate, such as the doping, and of the porosification process, such as the applied current and voltage, temperature, composition of the electrolyte, and in some cases the intensity and wavelength of the irradiated light.

[0073] Alternatively, the porous portion may be formed by sintering the silicon carbide before assembling the substrate. Sintering is a heat treatment of a structure made of silicon carbide at temperatures ranging from 1600°C to 2400°C in an atmosphere that may be, for example, argon, nitrogen or an inert gas. Such a heat treatment may modify the distribution of carbon and silicon present in the substrate and thus form inclusions made of carbon in the silicon carbide.

[0074] In some embodiments, the porous zone may be formed directly in a substrate of monocrystalline silicon carbide comprising a surface layer by porosifying said substrate over a portion of the thickness of the substrate, where the porosification is performed from the rear surface.

[0075] In other embodiments, forming the substrate may include assembling a support substrate and a surface layer, the porous zone of the support substrate may be formed before or after said assembling.

[0076] In some embodiments, forming the support substrate may include one or more steps of assembling two or more porous portions, and / or a porous portion with a non-porous portion.

[0077] Said layers or parts of the substrate can be assembled, for example, by bonding, from a donor substrate in which weakened zones have been created to define the layers to be assembled. In this case, a Smart Cut™ type process is typically used. The weakened zones to define the layers to be assembled on the support substrate are formed in a donor substrate made of monocrystalline silicon carbide. The weakened zones are typically created by irradiation with ions, for example hydrogen and / or helium ions. The donor substrate is then bonded to the front side of the support substrate, and the layers defined by the weakened zones are arranged in direct contact with the front side of the support substrate. The donor substrate is then separated along the weakened zones in order to transfer the layers of monocrystalline silicon carbide to the support substrate, for example by using a heat treatment.

[0078] Another technique for weakening the donor substrate is to create a weakened zone with a higher porosity than the porosity of the material in the vicinity of this zone. In such a case, after bonding to the support substrate, the donor substrate can be separated by applying a mechanical stress. Such a mechanical stress is, for example, the insertion of a blade or another angled tool, or the application of a jet of air or a jet of water. This technique can be used during the transfer of a porous layer or for a thinning operation, as described below.

[0079] Another embodiment of the assembly is deposition, for example chemical vapor deposition (CVD) or physical vapor deposition (PVD) on a provided portion of the substrate. For example, by CVD or PVD, a layer of polycrystalline silicon carbide can be deposited on a surface layer of monocrystalline silicon carbide or on another layer of (porous or non-porous) polycrystalline silicon carbide, making all or part of the deposited layer porous.

[0080] The step of assembling the support substrate and the surface layer of monocrystalline silicon carbide can be performed on a base substrate intended to form the support substrate, on a completed support substrate, or at the end of one or more steps of forming the support substrate.

[0081] When joining two porous parts, or a porous part and a non-porous part, the porosity of the joining interface is preferably less than 40%, preferably less than 15%, more preferably less than 5% to ensure good adhesion between the two parts.

[0082] To set the thickness of the support substrate or a part of the support substrate and the porosity of its rear side, one or more optional thinning steps can be performed. To perform this thinning step, it is possible to generate a weakened zone from the rear side of the porous zone to be formed, at a determined depth corresponding to the thickness of the porous part to be formed, with a porosity of more than 10%, preferably more than 15%, particularly preferably more than 30% relative to the porosity of the porous zone to be formed. Then, or after a step of assembly with one or more layers on the front side of the substrate, the substrate can be cut along the weakened zone generated. The cutting can be performed by applying a mechanical stress, for example by inserting a blade or by applying a jet of air or a jet of water. The stress must be adapted to diffuse the breaking waves along the weakened zone, which has a mechanical strength less than that of the zone surrounding the weakened zone. Preferably, such a weakened zone is surrounded by a part made of polycrystalline silicon carbide, which has a lower porosity than the weakened zone, for example a porosity of 1% or 5% less, preferably a porosity of 10% less.

[0083] In some embodiments, the substrate is thinned by breaking the porous portion, which leaves a porous zone on the surface that is secured to the solder of the electronic component. Such thinning avoids a polishing step, which can be time consuming and expensive.

[0084] The thinning step may also be performed by chemical etching or mechanical abrasion techniques.

[0085] By preference, a porous part having a thickness of more than 100 nm, preferably more than 1 μm, particularly preferably more than 3 μm is maintained. The thickness of the layer influences the deformation caused by temperature fluctuations. Thus, the mechanical stress applied to the soldering of the electronic chip is further reduced as the thickness of the porous part increases.

[0086] It is also possible to apply one or more thinning steps at the end of the production of a porous part in order to set the thickness of said porous part before assembly with another porous or non-porous part.

[0087] In order to avoid direct contact between the silicon carbide and the ambient air and, as a consequence, the creation of depletion zones with associated reduced electrical conductivity of the rear surface, an optional step of passivation or other treatment of the rear surface can be carried out, for example by deposition of a dielectric layer such as silicon oxide, forming a barrier layer.

[0088] EXEMPLARY EMBODIMENTS 7A-7D show a process for manufacturing a substrate according to the invention, in which the surface layer and the support substrate are produced from a single starting substrate 40 made from single crystal silicon carbide.

[0089] 7A, a front surface 410, preferably a silicon surface, is selected. A treatment, for example polishing, may be applied to the front surface 410. The portion extending from this front surface 410 is intended to form the surface layer 41.

[0090] Then, referring to FIG. 7B, porosity is formed from the rear surface 420 in the portion intended to form the support substrate 43, such that no porosity is formed in the portion intended to form the surface layer 41.

[0091] Optionally, one or more additional layers 43B, 43C can then be assembled on the rear face of the support substrate 43. The assembly of the first layer 43B is shown in FIG. 7C. The first layer 43B has a higher porosity than the part 43 extending from the rear face 420 of the single porous substrate. Such a layer is, for example, a layer made of sintered silicon carbide or a layer made of porous silicon carbide, or a combination of two or more porous layers. The layer made of sintered silicon carbide can be obtained, for example, by reactive sintering at a temperature of about 2000° C. This forms the new rear face 421 of the support substrate 430 to be formed.

[0092] The optional assembly of a second layer 43C is shown in Figure 7D. This assembly forms the new rear surface 422 of the formed substrate. The second layer 43C has a higher porosity than the rear surface of the first layer 43B. This forms a new support substrate 431, the porosity of which increases continuously from the front surface 410 to the rear surface 422 of the formed support substrate 431.

[0093] It is also possible to assemble one or more layers 43B, 43C on the rear side 420 of the substrate and / or to carry out an additional porosity after assembly (not shown). For example, it is possible to first bond a layer made of sintered silicon carbide to the rear side of the starting substrate and then to deposit a layer of polycrystalline silicon carbide on the rear side of the layer made of sintered silicon carbide and to carry out a step of porositying the layer made of polycrystalline silicon deposited on the layer made of sintered silicon carbide.

[0094] A preferred embodiment is shown in Figures 8A to 8C. First of all, a support substrate 530 is formed and then assembled with a surface layer 51 made from monocrystalline silicon.

[0095] With reference to Fig. 8A, a support substrate is formed from a substrate 50 made from polycrystalline silicon carbide. With reference to Fig. 8B, a portion 53 intended to form a porous portion extending from the rear face 520 of the substrate to be formed is porosified. With reference to Fig. 8C, the support substrate on the front face 510 is assembled with a surface layer 51 of monocrystalline silicon carbide, typically using a process of the Smart Cut™ type described above.

[0096] To illustrate such an embodiment variant, a more complex process is shown in Figures 8D to 8I, in which a support substrate is first formed and then assembled with a surface layer 51 made from monocrystalline silicon carbide.

[0097] To form the support substrate, a substrate 50 of polycrystalline silicon carbide can be taken as a basis, with reference to FIG. 8D. Said substrate can then be porosified as explained above to form a porous zone 53 extending from the rear face 520 of the substrate 50. With reference to FIG. 8E, the porosification can be performed such that only the portion 53 extending from the rear face 520 of the substrate has porosity, by keeping the portion 52 extending from the front face 510 in a non-porous original state. Alternatively, it is possible to create a porosity gradient such that the porosity increases continuously or gradually from the front face 510 to the rear face 520 of the substrate 50. In other cases, with reference to FIG. 8F, the porosification is performed uniformly throughout the thickness of the substrate as shown in FIG. 8B.

[0098] Then, referring to FIG. 8G, it is possible to carry out an optional step of bonding a layer 53B with a greater porosity to the rear face 520 of the substrate, thus generating a new support substrate 531 with a new rear face 521. The layer 53B has a higher porosity than the portion 53 extending from the rear face 520 of the single porosified substrate. Such a layer is, for example, a layer made of sintered silicon carbide, or a layer made of porosified silicon carbide with a porosity greater than that of the previously porosified portion 53, or a combination of two or more porous layers. This forms the new rear face 521 of the support substrate 531 to be formed. Referring to FIG. 8H, it is possible to optionally carry out an additional porosification step in the portion 53C extending from the new rear face 521 of the substrate to be formed. For this additional porosification step, parameters are selected such that the portion 53C has a higher porosity than the porous layer 53B in the initial state of the portion 53C. As a result, the porosity of the support substrate 532 gradually increases from the front surface 510 to the rear surface 522 of the support substrate.

[0099] Optionally, one or more bonding operations of another layer having greater porosity can be performed to the rear side (not shown) of the substrate.

[0100] Optionally, it is possible to fabricate one or more layers having a lower porosity on the front side (not shown) of the substrate.

[0101] Referring to FIG. 8I, on its front side 510 a support substrate is assembled with a surface layer 51 of single crystal silicon carbide.

[0102] If no layer is assembled on the front side of the substrate 532 , the surface layer 51 made from monocrystalline silicon carbide may be assembled with the support substrate 532 between any two steps of the procedure for forming the support substrate 532 .

[0103] In some embodiments not shown, a portion of the support substrate and a surface layer made of monocrystalline silicon carbide are assembled while the support substrate is being formed, before all steps of forming said support substrate are completed.

[0104] Another embodiment is shown in Figures 9A-9B. Referring to Figure 9A, the support substrate may be formed from a substrate 60 made from sintered silicon carbide. Sintered silicon carbide generally contains carbon inclusions and is therefore a porous material whose pores are filled with these inclusions.

[0105] 9B, a support substrate 60 of sintered silicon carbide can be assembled with a surface layer 61 of single crystal silicon carbide on a front surface 610 of the support substrate 60. As a result, a substrate made from sintered silicon carbide forms a single porous zone 60 extending from a rear surface 620 of the substrate.

[0106] Alternatively, referring to FIG. 10A, the same starting substrate 60 made from sintered silicon carbide is taken as a basis. Referring to FIG. 10B, a layer 62 of polycrystalline silicon carbide can be deposited on the front surface 610 of the substrate 60 made from sintered silicon carbide. Such deposition can be carried out, for example, by physical vapor deposition (PVD). The substrate 60 made from sintered silicon carbide is thus used as a support and crystallization seed for the polycrystalline silicon carbide. As shown in FIG. 10C, it is optionally possible to generate porosity in the layer 62 of silicon carbide thus deposited. In this case, the porosity generated in the portion 62 deposited on the front surface 610 is smaller than the porosity in the initial substrate 60 made from sintered silicon carbide. In some cases, said layer 62 is kept in its non-porous initial state.

[0107] Optionally, referring to Figure 10D, a second layer 63 of polycrystalline silicon carbide can be deposited on the rear face 620 of the substrate made from sintered silicon carbide to form a new support substrate 630 having a new rear face 621. Then, referring to Figure 10E, a step is performed to porosify the layer 63 made from polycrystalline silicon carbide on the rear face 620, such that the layer 63 on the rear face has a greater porosity than the substrate 60 made from sintered silicon carbide.

[0108] An optional step (not shown) can then be performed of bonding and / or assembling one or more layers having a greater porosity to or on the rear surface of the substrate, and / or one or more layers having a lower porosity to or on the front surface of the substrate.

[0109] With reference to FIG. 10F, the support substrate thus produced is assembled with a surface layer 61 made of monocrystalline silicon carbide on the front side 611 of the support substrate.

[0110] In another embodiment, referring to Fig. 11A, a donor substrate 70 made from monocrystalline silicon carbide is taken as a basis, one portion 71 on the front surface 710 of the donor substrate 70 intended to form a surface layer. Referring to Fig. 11B, a weakened zone 77 is formed so as to define the portion 71 intended to form the front surface of the substrate to be formed. The weakened zone is preferably created by implanting hydrogen and / or helium atoms into the donor substrate.

[0111] 11C, a part 73 made of polycrystalline silicon carbide is assembled on the front side 710. The porosity of part 73 can be formed before or after part 73 is assembled on the front side 71 of the donor substrate 70. For example, part 73 can be made of silicon carbide that has been subjected to porosification or sintering before the bonding operation. Alternatively, part 73 made of polycrystalline silicon carbide can be deposited, for example by CVD or PVD, on a donor substrate 70 made of monocrystalline silicon carbide, with a porosification step being performed on part 73 after the deposition step.

[0112] The porosity of portion 73 may be uniform, in a gradient or step form, or it may affect only a particular thickness of the substrate.

[0113] With reference to Figure 11D, donor substrate 70 is separated from portion 71, for example by a heat treatment. With reference to Figure 11E, portion 73 forms the support substrate made from porous silicon carbide and portion 71 forms the surface layer made from monocrystalline silicon carbide of the finished substrate.

[0114] In some embodiments, a substrate made of monocrystalline silicon carbide, intended to form a surface layer, is taken as a base. In that case, a support substrate is formed on the substrate made of monocrystalline silicon carbide, so that the front side of the substrate is in contact with the substrate made of monocrystalline silicon carbide. The formation of the support substrate may include one or more steps of deposition, porosity, sintering and assembly of the parts forming the support substrate. The substrate made of monocrystalline silicon carbide can then be thinned as described above.

[0115] It is then possible to form chips from such substrates for high frequency and / or power electronics applications. When devices are designed for high frequency applications, electronic chips can be formed in layers of silicon carbide or layers of nitrides from III-N groups, for example stacks of GaN / AlGaN / AlGanInN layers that define a two-dimensional electron gas. Such layers or such stacks are supported by a surface layer made of monocrystalline silicon carbide.

[0116] References Y. Shishkin et al., Photoelectrochemical etching of n-type 4H silicon carbide, Journal of Applied Physics 96, 2311, 2004 Gautier et al.,Electrochemical formation of porous silicon carbide for micro-device applications,Materials science forum,ISSN:1662-9752,vol.924,pages 943-946,2018 LLSnead et al., Journal of Nuclear Materials 371(2007)329-377

Claims

1. a free-standing support substrate (30) made of polycrystalline silicon carbide having a front surface (10) and a rear surface (20); a surface layer (1) of monocrystalline silicon carbide extending over said front surface (10) of said support substrate (30); A substrate for a high frequency or power electronic device comprising: The substrate, characterized in that the support substrate (30) has at least one porous portion (3) extending from the rear surface (20), the porous portion (3) having a porosity greater than 5%.

2. The substrate of claim 1, wherein the support substrate (30) has a thickness greater than 50 μm, preferably greater than 80 μm, more preferably greater than 100 μm, even more preferably greater than 150 μm.

3. The substrate according to claim 1 or 2, wherein the porous portion (3) comprises a layer (3, 3A, 3C) of porosified SiC.

4. The substrate according to any one of claims 1 to 3, wherein the support substrate (30) comprises a non-porous portion (2A, 2B, 2C) between the surface layer (1) of monocrystalline SiC and the porous portion (3).

5. The substrate according to any one of claims 1 to 4, wherein the porous portion (3) has a rear portion (3A, 3B, 3C) with a first porosity and a front portion (2A, 2B, 2C) with a second porosity smaller than the first porosity.

6. The substrate according to any one of the preceding claims, wherein the porous portion (3) has a decreasing porosity gradient from the rear face (20) to the front face (10).

7. The substrate according to any one of the preceding claims, wherein the porous portion (3) has pores filled with a material having a Young's modulus lower than that of the silicon carbide.

8. The substrate according to any one of the preceding claims, wherein the porous portion (3) comprises pores, the average distance between said pores being greater than 10 nm, preferably greater than 50 nm.

9. An electronic device comprising a substrate according to any one of claims 1 to 8 and at least one high frequency or power electronic component formed in or on said surface layer (1) of monocrystalline silicon carbide.

10. 10. The electronic device of claim 9, further comprising a heat dissipation device, the substrate being brazed to the heat dissipation device through the filler such that the filler is in integral contact with at least a portion of the porous portion (3) on the rear surface (20) of the support substrate (30).

11. a free-standing support substrate (30) made of polycrystalline silicon carbide having a front surface (10) and a rear surface (20); a surface layer (1) of monocrystalline silicon carbide extending over said front surface (10) of said support substrate (30); 1. A process for manufacturing a high frequency or power electronic device comprising: The process includes forming at least one porous portion (3) in the support substrate (30) extending from the rear face (20), the porous portion (3) having a porosity greater than 5%.

12. The process of claim 11, further comprising the step of assembling said surface layer (1) and said support substrate (30).

13. The process according to claim 11 or 12, wherein the support substrate (30) has a thickness greater than 50 μm, preferably greater than 80 μm, more preferably greater than 100 μm, even more preferably greater than 150 μm.

14. The process according to any one of claims 11 to 13, wherein the forming of the support substrate (30) comprises porosifying at least a portion of a non-porous silicon carbide base substrate to form the porous portion (3).

15. The process of claim 14, wherein the porosifying step is performed on all of the base substrate to form a completely porous support substrate (30).

16. 16. The process according to claim 14 or 15, wherein the porosifying step is performed so as to form a decreasing porosity gradient in the porous portion (3) from the rear face (20) to the front face (10).

17. The process according to any one of claims 14 to 16, wherein the porosifying step is performed so as to form a bonding zone on the front side (10) of the support substrate (30) having a porosity of less than 40%.

18. The process according to any one of claims 11 to 17, comprising the step of filling at least some of the pores of the porous portion (3) with a material having a lower Young's modulus than the Young's modulus of the silicon carbide.

19. The process according to any one of claims 11 to 18, further comprising the step of thinning the support substrate (30) via the rear face (20) such that the thickness of the porous portion (3) remains 100 nm or more.

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