Techniques for processing access operations with ordering constraints.

Abstract

A processing circuit is provided for performing the operations together with an instruction decoder circuit that decodes instructions and controls the processing circuit to perform operations specified by the instructions. A set of registers is used to hold data values ​​for access by the processing circuit. The instruction decoder circuit is used to access a plurality of data values ​​and, in response to ordering constrained access instructions providing register representation information and memory address information, controls the processing circuit to perform a sequence of access operations, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register representation information and an associated memory address determined from the memory address information. Furthermore, the ordering representation is derived from the ordering constrained access instruction and is used to determine the order in which the plurality of data values ​​are accessed when performing the sequence of access operations, thereby ensuring that visibility conditions required when implementing the ordering constrained access instruction are met.

Description

[Technical field]

[0001] The present technique relates to processing access operations with ordering constraints.

[0002] Within modern data processing systems, there are various types of consistency models that can be used when performing accesses to memory. One common approach is to employ a relatively weak consistency model, where a sequence of accesses to memory performed by a given processing element in the system may not necessarily be observed as occurring in the same order by other processing elements in the system that observe those accesses (i.e., one observing processing element may observe a different order than another observing processing element). Such an approach can provide a great deal of flexibility as to how various accesses are reordered by individual processing elements in order to improve execution.

[0003] However, in some situations it may be necessary to adopt a stricter consistency model that guarantees that each observing processing element observes the accesses of other processing elements as occurring in the same order. Two examples of such stricter consistency models are sometimes called total store ordering (TSO) and release consistency, processor consistency (RCpc).

[0004] It is possible to emulate the requirements of such stricter consistency models in systems that support weaker consistency models by using access instructions with single access ordering constraints, such as load acquire and store release instructions. When such a load acquire or store release instruction is executed by a given processing element, the processing element is constrained when performing the required load or store operations to ensure that the visibility requirements for the ordering of access operations dictated by the stricter consistency model are met.

[0005] However, within a data processing system it is often desirable to improve code density in order to try to improve execution, which can become a problem when using such ordering-constrained access instructions. Summary of the Invention

[0006] In one exemplary configuration, an apparatus is provided including a processing circuit for performing operations; an instruction decoder circuit for decoding instructions and controlling the processing circuit to perform the operations specified by the instructions; and a set of registers for holding data values ​​for access by the processing circuit, wherein the instruction decoder circuit is used to access a plurality of data values ​​and in response to ordering constrained access instructions providing register indication information and memory address information, controls the processing circuit to perform a sequence of access operations, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register indication information and an associated memory address determined from the memory address information, the ordering indication being derived from the ordering constrained access instruction and being used to determine an order in which the plurality of data values ​​are accessed when performing the sequence of access operations.

[0007] In another exemplary configuration, a method is provided for processing ordering constrained access operations in an apparatus having processing circuitry for performing operations, the method including using an instruction decoder circuit to decode an instruction and control the processing circuit to perform the operation specified by the instruction; using a set of registers to hold data values ​​for access by the processing circuit; having the instruction decoder circuit control the processing circuit to perform a sequence of access operations in response to ordering constrained access instructions used to access a plurality of data values ​​and providing register indication information and memory address information, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register indication information and an associated memory address determined from the memory address information; and determining an order in which the plurality of data values ​​are to be accessed when performing the sequence of access operations in response to an ordering indication derived from the ordering constrained access instructions.

[0008] In yet another exemplary configuration, a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program including processing program logic for performing operations, instruction decode program logic for decoding instructions and controlling the processing program logic to perform the operations specified by the instructions, and register emulation program logic for emulating a set of registers for holding data values ​​for access by the processing program logic, the instruction decode program logic is used to access a plurality of data values, and in response to ordering constrained access instructions providing register representation information and memory address information, controls the processing program logic to perform a sequence of access operations, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register representation information and an associated memory address determined from the memory address information, the ordering representation being derived from the ordering constrained access instruction and being used to determine an order in which the plurality of data values ​​are accessed when performing the sequence of access operations. [Brief description of the drawings]

[0009] The present technique will now be further described, by way of example only, with reference to examples of the technique illustrated in the accompanying drawings, in which:

[0010] [Figure 1] 1 is a block diagram of a system incorporating an apparatus according to one exemplary implementation. [Figure 2A] FIG. 2 illustrates a schematic diagram of fields provided within an ordering-constrained access instruction used to access multiple data values, according to one exemplary implementation. [Figure 2B] FIG. 2 illustrates a schematic diagram of fields provided within an ordering-constrained access instruction used to access multiple data values, according to one exemplary implementation. [Diagram 3]4 is a flow diagram illustrating how an ordering-constrained access instruction used to access multiple data values ​​is processed according to one exemplary implementation. [Figure 4A] FIG. 1 illustrates a schematic diagram of how visibility requirements are met when processing ordering-constrained access instructions used to access multiple data values, according to one exemplary implementation. [Figure 4B] FIG. 1 illustrates a schematic diagram of how visibility requirements are met when processing ordering-constrained access instructions used to access multiple data values, according to one exemplary implementation. [Diagram 5] 1 is a flow diagram illustrating how an ordered display is processed according to one exemplary implementation. [Figure 6] 1 is a flow diagram illustrating one exemplary implementation in which a decoder circuit decomposes an ordering-constrained access instruction used to access multiple data values ​​into a sequence of single-access ordering-constrained access instructions. [Figure 7] 1 illustrates a simulator implementation that may be used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In one exemplary implementation, an apparatus is provided having a processing circuit for performing operations and an instruction decoder circuit for decoding instructions to control the processing circuit to perform operations specified by those instructions. A set of registers is provided, each of which can be used to hold a data value for access by the processing circuit. It should be noted that a data value can include one or more data elements, and that the term "data value" as used herein is used to refer to a block of data that can be held within a single register.

[0012] As mentioned above, when trying to adopt a certain consistency model, it is known to provide an access instruction with a single access ordering constraint, such as a load acquire instruction or a store release instruction. When such an access instruction with a single access ordering constraint is executed, a single register is accessed (as a source of a store operation or as a destination of a load operation). Furthermore, the processing circuitry ensures that an ordering constraint is satisfied to meet a certain visibility requirement. For example, with respect to a load acquire instruction, the processing circuitry ensures that any access instruction (either a load or a store) that appears in program order after the load acquire instruction is only observed (e.g., by any other processing element in the system) as being executed after the execution of the load acquire instruction is completed. In other words, the load operation associated with the load acquire instruction is ordered before any access operation associated with another access instruction that appears in program order after the load acquire instruction.

[0013] Similarly, in the case of a storage release instruction, the processing circuitry ensures that any access instruction that is observed to have completed execution before the storage release instruction is observed to be executing is an access instruction that appears in program order before the storage release instruction, or stated another way, any access instruction that appears in program order before the storage release instruction will have its associated access operation ordered before the store operation associated with the storage release instruction.

[0014] When trying to improve code density, it is often desirable to replace two or more instructions with a single instruction when possible, as this can often enable significant execution improvements. However, this is problematic when considering the single access ordering constrained access instructions described above, due to the visibility requirements that need to be met when performing the associated access operations.

[0015] However, according to the techniques described herein, this problem is addressed by providing new instructions that can be treated to take such visibility requirements into account. In particular, an ordering-constrained access instruction used to access multiple data values ​​is provided, and an instruction decoder circuit is responsive to such an instruction to control a processing circuit to execute a sequence of access operations. Each access operation moves a data value from among the multiple data values ​​between an associated register (determined from register indication information provided by the instruction) and an associated memory address (determined from memory address information provided by the instruction). Furthermore, an ordering indication is derived from the ordering-constrained access instruction and is used to determine the order in which the multiple data values ​​are accessed when executing the sequence of access operations. By using such an ordering indication, it is possible to ensure that the individual accesses are externally observable in the required order, and in particular, can satisfy the same visibility requirements that would be satisfied if multiple single-access ordering-constrained access instructions were executed instead of the new ordering-constrained access instruction used to access the multiple data values.

[0016] In particular, it will be appreciated that if a series of single-access ordering constrained access instructions are provided, each of which identifies a single data value and is used to move that data value between an associated register and its address in memory, any observing entity in the system will observe the accesses performed by the series of instructions in a particular order, i.e., in the order in which the single-access ordering constrained access instructions appear in program order. However, when attempting to replace such a series of single-access ordering constrained access instructions with one instruction, it is important that the original order of visibility of the accesses is maintained. This is achieved by providing the above-mentioned ordering information derived from the ordering constrained access instructions, thereby ensuring that the required visibility constraints continue to be met.

[0017] The ordering indication may be determined by the instruction decoder circuitry when decoding the ordering-constrained access instruction in one exemplary implementation, however, in alternative implementations the ordering indication may be determined by the processing circuitry based on information provided to the processing circuitry by the instruction decoder circuitry.

[0018] The ordering indication can take a variety of forms. In one exemplary implementation, the ordering indication is used to identify the order in which memory addresses associated with the multiple data values ​​are accessed, thereby determining the order in which the multiple data values ​​are accessed. As an example, the ordering indication may identify whether the lowest memory address should be accessed first or the highest memory address should be accessed first. By providing such an ordering indication, this can provide significant flexibility since it can allow the above-mentioned ordering-constrained access instruction for accessing multiple data values ​​to be used in place of a series of single-access ordering-constrained access instructions, because regardless of whether the series caused the lowest memory address to be accessed first or the highest memory address to be accessed first, both options can be addressed by the instruction.

[0019] In one exemplary implementation, the instruction decoder circuit is configured to control the processing circuit to ensure, for an observation circuit coupled to the device and capable of observing access operations performed by the processing circuit, that a given access operation in a sequence of access operations performed when executing the ordering-constrained access instruction is observed by the observation circuit as completed before the execution of any subsequent access operation following the given access operation in the sequence of access operations is observed by the observation circuit. Thus, by way of example, if a sequence of access operations includes an access operation A followed by an access operation B, then if an observer is able to observe any portion of access operation B, then the above requirement ensures that the entirety of access operation A can also be observed. Note that this also implies the reverse observation condition, i.e., if an observer is unable to observe the entirety of access operation A, then no portion of access operation B can be observed.

[0020] In one exemplary implementation, each data value may include multiple data elements. In such a scenario, if the execution of a given access operation requires multiple accesses to be performed to access multiple data elements of the associated data value, the processing circuitry may be configured to ensure that all of the multiple accesses forming the given access operation are observable by the observation circuitry as completed before the execution of any subsequent access operation following the given access operation in the sequence of access operations is observable by the observation circuitry. Thus, even in situations where the execution of a given access operation needs to be implemented by multiple accesses and thus the given access operation is not itself an atomic operation, the above requirement of ensuring that any subsequent access operation is not observable until the given access operation is completed may still be implemented. While there are various reasons why a given access operation may need to be performed by multiple accesses, one particular example is when the data being accessed crosses a cache line boundary and thus separate accesses to multiple cache lines may be required.

[0021] In one exemplary implementation, the ordering indication may be directly encoded within a field of the ordering constrained access instruction, and therefore the ordering indication may be determined from an analysis of that field. However, in alternative implementations, it may not be necessary to provide a separate field for the ordering indication, and instead the ordering indication may be derived from other information encoded in the ordering constrained access instruction.

[0022] For example, in one exemplary implementation, the ordering-constrained access instruction is configured to specify an addressing mode used to determine memory addresses for multiple data values ​​from the memory address information, and an ordering indication may be derived depending on the addressing mode.

[0023] As an example, the memory address information may be configured to provide a memory address indication used to determine one memory address (which may be, but need not be, a first memory address accessed according to the ordering indication, for example), the addressing mode may identify an alignment direction to be used during the determination of at least each of the other memory addresses, and the ordering indication may be determined depending on the alignment direction.

[0024] In some implementations, the addressing mode can provide information that allows for the determination of the adjustment amount as well as identifying the adjustment direction. The adjustment direction and adjustment amount information can then be used to determine each memory address in the sequence. For example, based on such addressing mode information, it may be possible to build a sequence of increasing or decreasing memory addresses, each separated from each other by an adjustment amount. In some implementations, the adjustment direction and adjustment amount can also be used when determining one memory address determined from a memory address representation, for example, when the addressing mode identifies a pre-decrement mechanism that causes the memory address to be determined by decrementing the memory address determined from the memory address representation by the adjustment amount.

[0025] While in some implementations the order in which memory addresses are accessed to satisfy a visibility constraint may differ from the way in which the sequence of addresses is determined based on the addressing mode, it has been found that there is often an inherent link between the ordering of accesses required to satisfy a visibility constraint and the adjustment direction provided by the addressing mode, and therefore the addressing mode information can often be reused, either by itself or in combination with other information provided by the instruction, to determine the ordering representation.

[0026] As another example of information provided by an ordering constrained access instruction that may also be used when determining an ordering indication, in one exemplary implementation, the ordering indication may be derived depending on the instruction type of the ordering constrained access instruction. In one particular exemplary implementation, this instruction type information may be used in combination with the addressing mode information described above.

[0027] In one exemplary implementation, the instruction type is configured to identify whether the ordering-constrained access instruction is a load instruction that attempts to load multiple data values ​​from memory to multiple registers, or a store instruction that attempts to store multiple data values ​​from multiple registers to memory.

[0028] In one exemplary implementation, the ordering indication is derived from information encoded in the ordering constrained access instruction that identifies whether the ordering constrained access instruction should be used to perform a stacked access operation or a non-stacked access operation. This may be explicitly identified in the instruction, for example, by identifying that the ordering constrained access instruction uses a stack pointer to identify the required memory address, or the fact that the ordering constrained access instruction is being used to perform a stacked access operation may be inferred from other information in the instruction, for example, if a particular addressing mode is reserved for use when performing a stacked access operation. For example, in one particular implementation, a pre-decrement addressing mode may be reserved for use when performing a stacked store operation, and thus the ordering indication may be determined based on whether the ordering constrained access instruction is performing a store operation and whether the store operation is a stacked operation. If so, one form of ordering indication may be determined, and if not, the opposite ordering indication may be determined.

[0029] While the techniques described above may be used to enable an ordering-constrained access instruction to be used to access any number of multiple data values, in one particular exemplary implementation, an ordering-constrained access instruction is configured to access a pair of data values ​​and provides sufficient register representation information to identify a register associated with each data value in the pair of data values. In particular, it has been found that there are many cases in which it is desirable to store the contents of two registers to (typically consecutive) addresses in memory, or to load data from (typically consecutive) addresses in memory into a pair of registers, and that providing an ordering-constrained access instruction as defined herein makes it possible to achieve this by executing a single instruction, rather than having to execute two instances of the single-access ordering-constrained access instruction discussed above.

[0030] When an ordering-constrained access instruction is used to access a pair of data values, the memory address information may be configured to provide a memory address representation used to determine a memory address to be associated with one of the data values ​​in the pair of data values, and then a further memory address to be associated with the other data value in the pair may be derived from the one memory address. For example, the further memory address may be inferred based on the addressing mode information from which the one memory address is determined.

[0031] The ordering constrained access instruction used to access multiple data values ​​can take a variety of forms. In one exemplary implementation, the ordering constrained access instruction is a store release instruction used to store multiple data values ​​in memory, and the instruction decoder circuit, upon decoding the store release instruction, - any access instruction that is observed to have completed execution before a memory release instruction is observed to be executing is an access instruction that appears in program order before the memory release instruction; and - configured to control the processing circuitry to ensure that a given store operation in a sequence of store operations used to store a plurality of data values ​​in a memory during execution of a store release instruction is observable as completed before execution of any subsequent store operation following the given store operation in the sequence of store operations is observable.

[0032] Thus, the requirements of the storage release operation are satisfied with respect to other access instructions appearing in the program as well as with respect to the individual storage operations performed to execute the storage release instruction.

[0033] As another example, the ordering-constrained access instruction may be a load-get instruction used to load multiple data values ​​into associated registers in the set of registers, and the instruction decoder circuit, upon decoding the load-get instruction, - a given load operation in a sequence of load operations used to load multiple data values ​​into associated registers during execution of a load acquire instruction is observable as completed before any subsequent load operation following the given load operation in the sequence of load operations is observable executing; and - configured to control the processing circuitry to ensure that any access instruction which appears in program order after the load acquire instruction is only observed as being executed after execution of the load acquire instruction has completed.

[0034] Thus, the requirements of the load obtain operation are met both with respect to other access instructions appearing in the program, and with respect to the individual load operations performed to execute the load obtain instruction.

[0035] There are various ways in which the instruction decoder circuit can process the ordering constrained access instruction to appropriately control the processing circuit to perform the specified access operation while satisfying the required visibility condition. In one particular exemplary implementation, the instruction decoder circuit is configured to decompose an ordering constrained access instruction used to access multiple data values ​​into a sequence of single-access ordering constrained access instructions, each single-access ordering constrained access instruction configured to access one of the data values ​​in the multiple data values. According to such an approach, the instruction decoder circuit is configured to determine an order for controlling the processing circuit to execute each single-access ordering constrained access instruction in the sequence according to the ordering indication. Thus, it can decompose the ordering constrained access instruction into a series of single-access ordering constrained access instructions, and then cause the processing circuit to execute the series of instructions in a default order or in a reverse order according to the ordering indication determined from the ordering constrained access instruction.

[0036] Specific example implementations will now be described with reference to the accompanying drawings.

[0037] FIG. 1 is a block diagram of a system incorporating an apparatus according to one exemplary implementation. The apparatus may take the form of either processor core 10 or processor core 20 in the example of FIG. 1, and as is evident from FIG. 1, both of these processor cores may be configured in the same manner. For the purposes of the following description, it is assumed that processor core 10 is executing a sequence of instructions including one or more instances of the previously described ordering-constrained access instructions used to access multiple data values, and that processor core 20 is an observing entity to those accesses. However, it will be appreciated that there may be cases where processor core 20 is executing such instructions and processor core 10 is an observer, and indeed both situations may occur within the same system. Furthermore, while only two processor cores 10, 20 are shown for simplicity, it will be appreciated that several additional processing elements may also be provided within the system that may operate to execute such instructions and / or may be observers of accesses made by other processing elements.

[0038] The processor cores 10, 20 are coupled to an interconnect 30 that shares access to a memory 45. The interconnect can take a variety of forms, but in the example shown is a coherent interconnect that may include a system cache 35 accessible to both processor cores 10, 20 and associated cache coherency circuitry 40 for ensuring that each of the processor cores has a coherent view of data stored in the system's cache. As shown in FIG. 1, in addition to the system cache 35, there may be one or more other levels of cache, such as one or more levels of local caches 15, 25 accessible to each processor core 10, 20. As will be appreciated by those skilled in the art, the cache coherency circuitry 40 may use any of several known cache coherency schemes to ensure that each processor core 10, 20 accesses the most recent version of data cached in the system in response to issuing a request to access that data.

[0039] 1, processor core 10 may include an instruction decoder 50 for decoding instructions fetched from one of the memory or caches to generate control signals that are then used to control processing circuits 52 to perform operations required by those instructions. During the performance of such operations, processing circuits 52 has access to a set of registers 54 in which data values ​​used as inputs to the operations may be stored, and in which output results generated by those operations may be stored.

[0040] Some of the instructions executed by processor core 10 may cause access operations to be performed by processing circuitry 52 to load data values ​​from memory / cache into registers 54 (in which case the access operation is a load operation) and / or to store data values ​​from registers 54 into memory / cache (in which case the access operation is a store operation). As store operations are executed, they may be temporarily buffered in a store buffer 56, and processor core 10 may be able to perform some reordering of the store operations held in the store buffer to try to improve execution. Also, as shown in FIG. 1, in some cases a load buffer 58 may be provided to temporarily buffer load operations executed by the processor core. In out-of-order processors, it may be possible to reorder certain load operations in situations where address calculation times may vary between different load instructions, in which case the presence of a load buffer 58 may be useful.

[0041] In the example of FIG. 1, processor core 20 is assumed to be constructed in the same manner as processor core 10 and therefore includes an instruction decoder 60, processing circuitry 62, a set of registers 64, a store buffer 66, and optionally a load buffer 68.

[0042] In addition to the aforementioned cache coherency mechanisms used to ensure that each of the processors has a coherent view of data that may be cached within the system, the system also typically uses a memory consistency model for memory to ensure that the results of memory reads, writes, or updates are predictable. Some systems may employ a relatively weak consistency model to allow flexibility in how accesses to memory may be reordered by particular processing elements within the system, but in some cases it may be desirable to emulate the behavior of a stronger consistency model than is inherently supported by the system. As mentioned above, one way to attempt to achieve this is by using load obtain and store release instructions instead of standard load and store instructions, and in particular, when a processing element executes a load obtain or store release instruction, certain visibility constraints are guaranteed such that other processing elements within the system that observe the accesses performed by a given processing element will observe those accesses as having occurred in a particular program order, even if some local reordering is performed by the given processing element.

[0043] According to the techniques described herein, in order to improve code density, new forms of load acquire and store release instructions (referred to herein as ordering-constrained access instructions used to access multiple data values) are provided that can specify multiple data values ​​to be accessed and, in particular, when executed, cause a sequence of access operations to be performed on multiple registers, each access operation moving a data value from among the multiple data values ​​between an associated register and an associated memory address (from register to memory in the case of a store release instruction, and from memory to register in the case of a load acquire instruction). According to the techniques described herein, an ordering indication is derived from the ordering-constrained access instruction and is used to determine the order in which the multiple data values ​​are accessed when performing the sequence of access operations. By using such an ordering indication, it is possible to ensure that the individual accesses are externally observable in the required order and, in particular, can satisfy the same visibility requirements that would be met if multiple single-access ordering-constrained access instructions (i.e., a sequence of conventional load acquire or store release instructions, each accessing one data value) were executed instead of the new ordering-constrained access instruction used to access multiple data values.

[0044] 2A is a schematic diagram of fields that may be provided in an ordering-constrained access instruction 100 of a type used to access multiple data values, according to one exemplary implementation. A first field 105 is used to specify the instruction type, and thus may identify, for example, whether the instruction is a load or store instruction. Optionally, additional information may also be specified, such as whether the instruction is operating on a stack in memory, or instead on a non-stack region of memory.

[0045] Further field 110 provides an addressing mode and is used in combination with the memory address information in memory address field 125 to determine a memory address associated with each of the data values ​​to be accessed. The memory address information in field 125 may provide sufficient information to allow one of the addresses to be determined, for example, by providing a stack pointer indication used to identify a stack pointer, or by identifying a register whose contents may be used to determine the memory address. In this latter case, for example, it may be the case that the data value in the identified register is used as an offset to add to some base address to determine the memory address.

[0046] The addressing mode information may then be used to calculate each of the other addresses required, and indeed in some instances may even be taken into account when calculating the first memory address from the memory address information in field 125. The addressing mode may indicate the direction of the adjustment, such as, for example, whether each subsequent address should be determined by incrementing the previously determined address or by decrementing the previously determined address. The addressing mode may also, in some implementations, provide an amount of adjustment to allow configurability regarding the amount of adjustment made when calculating each subsequent address.

[0047] A register indication field 120 is also provided for storing register indication information. This information can be used to determine a register identifier for each register accessed when executing an ordering-constrained access instruction. In one exemplary implementation, each register may be explicitly identified in the register indication field 120. However, in alternative implementations, one register may be identified and each additional register may be inferred, for example in situations where an instruction operates on a set of adjacent registers or registers separated by a predetermined amount.

[0048] 2A, according to this first exemplary implementation, an ordering indication field 115 is provided as an explicit field in which ordering indication information may be stored to identify the order in which each of the access operations required to execute an ordering-constrained access instruction are executed. This provides great flexibility as it allows an ordering-constrained access instruction used to access multiple data values ​​to be used in place of or to replace a sequence of standard ordering-constrained access instructions each of which operates on a single data value (i.e., moves data in either direction between a register and an address in memory) while ensuring that visibility requirements between the individual access operations are met.

[0049] In the example of Fig. 2A, an explicit ordering indication field is used, but in an alternative exemplary implementation, as shown in Fig. 2B, there may be no need for an explicit ordering indication field, and instead, it may be possible to derive the ordering indication from other information provided within the instruction. In particular, in the example of Fig. 2B, the ordering-constrained access instruction 130 used to access multiple data values ​​includes the aforementioned fields 105, 110, 120, 125, but does not include an explicit ordering indication field 115. Instead, in this alternative implementation, it is possible to infer the ordering indication from other information within the instruction, and in particular, in one exemplary implementation, this is achieved by reference to both the instruction type information in field 105 and the addressing mode information in field 110.

[0050] 3 is a flow diagram illustrating how an ordering-constrained access instruction may be processed according to one exemplary implementation. If, in step 200, it is determined that an ordering-constrained access instruction for accessing multiple data values ​​has been encountered, in step 205 it is determined what type of instruction is being executed, for example, whether the instruction is a load-acquire instruction or a storage-release instruction.

[0051] In step 210, an ordering indication is determined, and as explained above this may be determined by reference to an explicit field in the instruction, or may alternatively be derived from other information, for example an indication of the addressing mode and / or instruction type.

[0052] In step 215, a memory address for each data value is determined using the memory address information in field 125 and the addressing mode information in addressing mode field 110. Additionally, in step 220, the register associated with each data value is determined using the information in register representation field 120.

[0053] Once all of the above information has been determined, the processing circuitry may be constrained to perform accesses to each data value in the order indicated by the ordering indication, in step 225. In this manner, visibility requirements may be met not only with respect to other access instructions being executed by the processor core (as required by known load acquire and store release instructions), but also with respect to the individual access operations required to implement the ordering-constrained access instruction.

[0054] For example, if the ordering-constrained access instruction being executed is a store release instruction used to store multiple data values ​​in memory, the instruction decoder 50, upon decoding the store release instruction, may - any access instruction that is observed to have completed execution before a memory release instruction is observed to be executing is an access instruction that appears in program order before the memory release instruction; and - the processing circuitry 52 may be configured to control the execution of the storage release instruction to ensure that a given store operation in a sequence of store operations used to store multiple data values ​​in memory during execution of the storage release instruction is observable as completed before any subsequent store operation following the given store operation in the sequence of store operations is observable executing.

[0055] Similarly, if the ordering-constrained access instruction is a load-obtain instruction used to load multiple data values ​​into associated registers in a set of registers, the instruction decoder 50, upon decoding the load-obtain instruction, - a given load operation in a sequence of load operations used to load multiple data values ​​into associated registers during execution of a load acquire instruction is observable as completed before any subsequent load operation following the given load operation in the sequence of load operations is observable executing; and may be configured to control the processing circuitry 52 to ensure that any access instruction which appears in program order after the load acquire instruction is only observed as executing after the load acquire instruction has completed execution.

[0056] 3, steps 205, 210, 215, and 220 are shown sequentially, it will be appreciated that one or more of these steps may be performed in parallel depending on the implementation. Additionally, which steps are performed by the decoder and which steps are performed by the processing circuitry may vary depending on the implementation. In one particular exemplary implementation, the decoder may be configured to determine which register operands are to be used and the addressing mode. The processing circuitry may then be configured to implement the addressing mode to perform the required access operations while implementing the required ordering determined from the ordering indication.

[0057] 4A and 4B are diagrams illustrating how visibility requirements are met between the individual access operations required to execute the ordering-constrained access instructions described above. In each case, assume that the ordering-constrained access instruction accesses a pair of data values, which are moved from memory to the paired register in the case of a load-acquire instruction, or from the paired register to memory in the case of a store-release instruction. The two access operations required to access each data value in the pair of data values ​​are referred to as access operations 1 and 2 in FIGS. 4A and 4B.

[0058] 4A, when each access operation may be performed atomically, the processing circuitry is constrained to process the two access operations such that if any observing entity in the system can observe any portion of the result of access operation 2, then it is guaranteed that the observing entity can also observe all portions of the result of access operation 1. In other words, this also means that if an observer cannot observe the entirety of access operation 1, then he or she cannot observe any portion of access operation 2.

[0059] 4B illustrates a scenario in which access operation 1 needs to be decomposed into multiple separate accesses, specifically a first access and a second access in this example. There are various reasons why this may occur, but in the example of FIG. 4B, it is assumed that the required data value to be accessed is distributed across two cache lines, and therefore a separate access to each of those cache lines is required. This means that the execution of access operation 1 is not itself atomic. Nevertheless, even in that scenario, the processing circuitry is constrained to ensure that the above visibility constraint between access operation 1 and access operation 2 is satisfied.

[0060] 5 is a flow diagram illustrating a particular exemplary implementation used to determine an ordering indication from other information present in an ordering-constrained access instruction. Assume that an ordering-constrained access instruction used to access multiple data values ​​is encountered in step 300, and it is determined whether the instruction is a storage release instruction. In this exemplary implementation, if the instruction is not a storage release instruction, the process proceeds directly to step 315, where an ordering indication is determined to identify that the lowest memory address should be accessed first.

[0061] However, if in step 300 it is determined that the instruction is a storage freeing instruction, then in step 305 it is determined whether the instruction is performing a stack-type operation. This requirement may be implemented in a variety of ways. For example, it may be explicitly identified in the instruction by identifying that the storage freeing instruction uses a stack pointer to identify the required memory address. Alternatively, it may be possible to infer this information from other information provided in the instruction. For example, if a particular addressing mode is reserved for use when performing stack-type storage operations, then in step 305 the presence of that addressing mode may be used to determine that the instruction is intended to perform a stack-type operation.

[0062] If it is determined that the instruction is not used to perform a stack type operation, the process again proceeds to step 315 where an ordering indication is determined to identify that the lowest memory address should be accessed first.

[0063] If, at step 305, it is determined that the instruction is to perform a stacked operation, in one exemplary implementation, the process may proceed directly to step 320, where an ordering indication is determined to identify that the highest memory address is to be accessed first. However, in an implementation in which more than one addressing mode may be used to perform stacked operations, as indicated by dotted box 310, it may first be determined at step 310 whether the addressing mode is a pre-decrement addressing mode. If not, the process may proceed to step 315, where an ordering indication is determined to identify that the lowest memory address is to be accessed first, but if the addressing mode is pre-decrement, the process proceeds to step 320, where an ordering indication is determined to identify that the highest memory address is to be accessed first.

[0064] By using the techniques described herein, it is possible to significantly reduce code density by allowing the use of a single instruction where previously multiple separate instructions were required. For example, given an existing storage free instruction, multiple previous storage free instructions may have been required, such as the following instruction pair: STLR X1 [SP, -8]]! STLR X0[SP,-8]]!

[0065] Execution of the first storage release instruction causes the data in register X1 to be stored in a location in the stack in memory determined by pre-decrementing the provided stack pointer value by 8 bytes to generate a new stack pointer value. Execution of the second storage release instruction then causes the data in register X0 to be stored in a location in the stack in memory determined by pre-decrementing the stack pointer value generated through execution of the first STLR instruction, again by 8 bytes, to create an updated stack pointer value.

[0066] According to the techniques described herein, these two storage release instructions can be replaced by a single new instruction of the following form: STLP X0,X1,[SP,-16]!

[0067] In particular, "P" indicates that a store release instruction is to be performed on a pair of registers, namely identified registers X0 and X1, and the ordering indication derived from the instruction identifies that the highest memory address is to be accessed first (in one embodiment, this may be determined from a combination of the instruction being a store release instruction and the pre-decrement addressing mode being used). In this case, the pre-decrement amount is 16 bytes, and therefore the stack pointer is pre-decremented by 16 bytes, allowing the first 8 bytes of data from register X0 to be stored on the stack, followed by the second 8 bytes of data from register X1. However, to meet the required visibility ordering, the stores are processed such that the store of X1 is ordered before the store of X0. Two separate store operations may be performed to implement the execution of this instruction, with the processing circuitry being constrained to ensure that the aforementioned visibility requirements between the individual store operations are met.

[0068] While the above are examples of situations where the ordering indication indicates the highest memory address first, the following are examples of situations where a new form of memory release instruction may be configured to specify an ordering indication that indicates that the lowest memory address should be accessed first. In particular, there are two standard memory release instructions: STLR X0, [X2] STLR X1, [X2, 8] This can be replaced by a single new free instruction of the form: STLP X0,X1,[X2]

[0069] In this case, the addressing mode can identify a post-incremental change to the address by 8 bytes, and a first storage access operation is used to store data in register X0 to a memory address determined from the contents of register X2, and a second storage access operation is used to store data in register X1 to a memory address determined by incrementing the address determined for the first access operation by 8 bytes. As with the previous example, an ordering indication can be derived, in one embodiment, from the addressing mode and can indicate that the access should be performed first to the lowest memory address. As with the previous example, when executing this new form of storage release instruction, the processing circuitry is constrained to ensure that the aforementioned visibility requirements between individual storage operations are met.

[0070] There are several ways in which the instruction decoder 50 can process ordering-constrained access instructions of the above type in order to appropriately control the processing circuitry to perform the specified access operation while satisfying the required visibility conditions. In one particular exemplary implementation, as shown in FIG. 6, the decoder can be configured in step 400 to decompose an ordering-constrained access instruction used to access multiple data values ​​into a sequence of single-access ordering-constrained access instructions, each used to access one of the data values. Thus, in such an implementation, a new form of load-acquire or store-release instruction used to access multiple data values ​​can be decomposed into a series of existing load-acquire or store-release instructions, each instruction performing an access with respect to a data value associated with a single register.

[0071] Next, in step 405, an ordering indication may be determined using any of the techniques described above. Based on the determined ordering indication, the decoder may then determine, in step 410, an order in which to control the processing circuitry to execute each of the single-access ordering constrained access instructions. Thus, in one exemplary implementation, for example, if the ordering indication indicates that the lowest memory address should be accessed first, the sequence of instructions may be executed in the determined decomposition order first, but if instead the ordering indication indicates that the highest memory address should be accessed first, the decoder may reverse the order in which the single-access ordering constrained access instructions are executed. This provides a particularly simple and efficient mechanism for implementing the processing of these new load acquire and release instructions.

[0072] FIG. 7 illustrates a simulator implementation that may be used. While the above examples implement the invention in terms of apparatus and methods for operating specific processing hardware that supports the technique, it is also possible to provide an instruction execution environment according to the examples described herein, which is implemented through the use of a computer program. Such computer programs are often referred to as simulators insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 515, which optionally runs a host operating system 510 and supports the simulator program 505. In some arrangements, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide a simulator implementation that runs at a reasonable speed, but such an approach may be justified in certain situations, such as when it is desired to run code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment that has additional functionality not supported by the host processor hardware, or that is typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques", Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0073] To the extent that examples have been described above with reference to particular hardware constructs or features, in the simulated implementations, equivalent functionality may be provided by suitable software constructs or features. For example, particular circuits may be provided as computer program logic in the simulated implementations. Similarly, memory hardware such as registers or caches may be provided as software data structures in the simulated implementations. Also, the physical address space used to access memory in the hardware device may be emulated as a simulated address space, which is mapped by simulator 505 to a virtual address space used by host operating system 510. In arrangements where one or more of the hardware elements referred to in the preceding examples are present in host hardware (e.g., host processor 515), some simulated implementations may use the host hardware, if suitable.

[0074] The simulator program 505 may be stored in a computer-readable storage medium (which may be a non-transitory medium) and provides a virtual hardware interface (instruction execution environment) to the target code 500 (which may include applications, operating systems, and hypervisors), the virtual hardware interface being the same as the hardware interface of the hardware architecture modeled by the simulator program 505. Thus, the program instructions of the target code 500 may be executed from within the instruction execution environment using the simulator program 505, so that the host computer 515, which does not actually have the hardware features of the aforementioned devices, can emulate these features. The simulator program may include processing program logic 520 that emulates the operation of the processing circuits 52, 62, instruction decode program logic 525 that emulates the operation of the instruction decoders 50, 60, and register emulation program logic 522 that maintains a data structure to emulate the set of registers 54, 64. Thus, the techniques described herein for processing ordering-constrained access operations may be implemented in software by the simulator program 505 in the example of FIG. 7.

[0075] From the above, it will be appreciated that the techniques described herein provide a particularly efficient mechanism for handling ordering-constrained access operations, such as load acquire and store release operations, and enable improving code density, and therefore execution, by enabling specification of individual load acquire or store release instructions that cause data values ​​associated with multiple registers to be accessed, while ensuring that required visibility behavior between the individual access operations required to implement the load acquire or store release instruction is met.

[0076] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0077] Although illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it will be understood that the invention is not limited to those precise embodiments, and that various changes, additions, and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, various combinations of the features of the dependent claims may be made with the features of the independent claims without departing from the scope of the invention.

Claims

1. An apparatus comprising: processing circuitry for performing operations; an instruction decoder circuit for decoding instructions and controlling said processing circuitry to perform the operations specified by said instructions; a set of registers for holding data values ​​for access by said processing circuitry; the instruction decoder circuitry is used to access a plurality of data values, and in response to ordering-constrained access instructions providing register representation information and memory address information, controls the processing circuitry to perform a sequence of access operations, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register representation information and an associated memory address determined from the memory address information; An ordering indication is derived from said ordering-constrained access instruction and is used to determine an order in which said plurality of data values ​​are accessed when performing said sequence of access operations.

2. 2. The apparatus of claim 1, wherein the ordering indication is used to identify an order in which the memory addresses associated with the plurality of data values ​​are accessed, thereby determining the order in which the plurality of data values ​​are accessed.

3. 3. The apparatus of claim 1, wherein the instruction decoder circuit is configured to control the processing circuit to ensure, to an observation circuit coupled to the apparatus and capable of observing the access operations performed by the processing circuit, that a given access operation in the sequence of access operations is observable by the observation circuit as completed before execution of any subsequent access operation following the given access operation in the sequence of access operations is observable by the observation circuit.

4. Each data value includes a plurality of data elements; 4. The apparatus of claim 3, wherein if performance of the given access operation requires multiple accesses to be performed to access the multiple data elements of the associated data value, the processing circuitry is configured to ensure that all of the multiple accesses forming the given access operation are observable by the observation circuitry as completed before performance of any subsequent access operation following the given access operation in the sequence of access operations is observable by the observation circuitry.

5. Apparatus according to any preceding claim, wherein the ordering indication is derived from other information encoded in the ordering constrained access instruction.

6. 6. The apparatus of claim 5, wherein the ordering-constrained access instruction specifies an addressing mode to be used to determine the memory addresses for the plurality of data values ​​from the memory address information, and the ordering indication is derived depending on the addressing mode.

7. 7. The apparatus of claim 6, wherein the memory address information is configured to provide a memory address representation used to determine one memory address, the addressing mode identifies an alignment direction used during determination of at least each other memory address, and the ordering representation is determined in dependence on the alignment direction.

8. The apparatus according to any one of claims 5 to 7, wherein the ordering indication is derived depending on an instruction type of the ordering-constrained access instruction.

9. 9. The apparatus of claim 8, wherein the instruction type is configured to identify whether the ordering-constrained access instruction is a load instruction that attempts to load the plurality of data values ​​from memory into a plurality of the registers, or a store instruction that attempts to store the plurality of data values ​​from the plurality of registers to memory.

10. 10. Apparatus according to any of claims 5 to 9, wherein the ordering indication is derived from information encoded in the ordering constrained access instruction that identifies whether the ordering constrained access instruction should be used to perform a stacked access operation or a non-stacked access operation.

11. 11. An apparatus as claimed in any preceding claim, wherein the ordering-constrained access instruction is configured to access a pair of data values ​​and provides register representation information sufficient to identify a register associated with each data value in the pair of data values.

12. 12. The apparatus of claim 11, wherein the memory address information is configured to provide a memory address representation used to determine one memory address to be associated with one of the data values ​​in the pair of data values, and a further memory address to be associated with the other data value in the pair is derived from the one memory address.

13. The ordering constrained access instruction is a store release instruction used to store a plurality of data values ​​in a memory, and the instruction decoder circuit, upon decoding the store release instruction, any access instruction that is observed to have completed execution before said storage release instruction is observed to be executed is an access instruction that appears in program order before said storage release instruction; and 13. An apparatus as claimed in any preceding claim, configured to control the processing circuitry to ensure that a given store operation in a sequence of store operations used to store the plurality of data values ​​to memory during execution of the storage release instruction is observable as completed before execution of any subsequent store operation following the given store operation in the sequence of store operations is observable.

14. The ordering constrained access instruction is a load obtain instruction used to load a plurality of data values ​​into associated registers in the set of registers, and the instruction decoder circuit, upon decoding the load obtain instruction, a given load operation in a sequence of load operations used to load the plurality of data values ​​into the associated register during execution of the load obtain instruction is observable as completed before any subsequent load operation following the given load operation in the sequence of load operations is observable executing; and 13. An apparatus as claimed in any preceding claim, configured to control the processing circuitry to ensure that any access instructions which appear in program order after the load acquire instruction are only observed as being executed after execution of the load acquire instruction has completed.

15. the instruction decoder circuitry is configured to decompose the ordering constrained access instructions used to access a plurality of data values ​​into a sequence of single-access ordering constrained access instructions, each single-access ordering constrained access instruction configured to access one of the data values ​​among the plurality of data values; the instruction decoder circuitry is configured to determine the order for controlling the processing circuitry to execute each single-access ordering constrained access instruction in the sequence in response to the ordering indication. An apparatus according to any one of claims 1 to 14.

16. 1. A method of processing ordering constrained access operations in an apparatus having processing circuitry for performing the operations, the method comprising: using an instruction decoder circuit for decoding instructions and controlling said processing circuitry to perform said operations specified by said instructions; using a set of registers to hold data values ​​for access by said processing circuitry; causing the instruction decoder circuit to control the processing circuit to perform a sequence of access operations in response to ordering-constrained access instructions used to access a plurality of data values, the access instructions providing register indication information and memory address information, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register indication information and an associated memory address determined from the memory address information; determining an order in which the plurality of data values ​​are to be accessed when performing the sequence of access operations in response to an ordering indication derived from the ordering-constrained access instruction.

17. 1. A computer program for controlling a host data processing apparatus to provide an instruction execution environment, comprising: processing program logic for performing operations; instruction decode program logic for decoding instructions and controlling said processing program logic to perform said operations specified by said instructions; register emulation program logic for emulating a set of registers for holding data values ​​for access by said processing program logic; the instruction decode program logic is responsive to ordering-constrained access instructions used to access a plurality of data values ​​and providing register representation information and memory address information to control the processing program logic to perform a sequence of access operations, each access operation moving a data value from among the plurality of data values ​​between an associated register determined from the register representation information and an associated memory address determined from the memory address information; An ordering indication is derived from said ordering constrained access instruction and is used to determine an order in which said plurality of data values ​​are accessed when performing said sequence of access operations.

Images