Semiconductor processing apparatus and method

Abstract

The present invention relates to a semiconductor processing apparatus and method. The semiconductor processing method includes the steps of moving the second cavity to an ON position relative to the first cavity, loading a semiconductor wafer to be processed between the first and second cavities, moving the second cavity to an OFF position relative to the first cavity, injecting a corrosive mixed gas into the sealed passage to corrode the surface of the semiconductor wafer with the corrosive mixed gas, and then discharging the waste gas in the sealed passage, and injecting a predetermined amount of extraction liquid into the sealed passage, causing the extraction liquid in the sealed passage to flow in the sealed passage under pressure and then discharging it to the outside of the sealed passage, thereby extracting metal contaminants. This can greatly reduce the amount of chemical products used and avoid problems such as poor etching uniformity and poor etching surface roughness caused by the inability to accurately control the roughness of the etching surface and the volume of the extraction liquid when using the conventional chemical etching method.

Description

[Technical field]

[0001] The present invention relates to surface treatment techniques for semiconductor wafers or similar parts, and more particularly to semiconductor processing equipment and methods. [Background technology]

[0002] During wafer processing, various metal impurities may adhere to the wafer. If the metal impurities are left on the wafer, they may be converted into very small amounts of metal ion contaminants. Metal ion contaminants have strong mobility and may have a significant impact on the life, performance, and stability of parts. Therefore, measuring the content of metal impurities on the wafer surface is of great significance in the field of semiconductor part processing. Commonly used metal element analysis techniques can be realized by VPD (Vapor Phase Decomposition) and ICPMS (Inductively Coupled Plasma-Mass Spectrometry).

[0003] Traditional VPD technology only dissolves the SiO2 surface layer of the wafer, which is either native oxide or thermal oxidation. Traditional metal element analysis methods usually use traditional chemical etching methods, which require a large amount of chemicals and may cause excessive corrosion of the wafer due to the residual chemical liquid.

[0004] Therefore, there is a need to provide a new solution that can solve the above problems. Summary of the Invention [Problem to be solved by the invention]

[0005] It is an object of the present invention to provide a semiconductor processing apparatus and method that significantly reduces the amount of chemicals used in measuring metals and provides precise control over the area of ​​corrosion, the depth of corrosion, the roughness and uniformity of the etched surface. [Means for solving the problem]

[0006] In order to achieve the above object, a first embodiment of the present invention provides a semiconductor processing apparatus, the semiconductor processing apparatus including a first cavity and a second cavity that can move between an on position and an off position relative to the first cavity, a microcavity is formed between the first cavity and the second cavity when the second cavity moves to the off position relative to the first cavity, and a semiconductor wafer to be processed is accommodated in the microcavity, and when the second cavity moves to the on position relative to the first cavity, the semiconductor wafer to be processed can be removed or accommodated. The first cavity and / or the second cavity includes a recessed passage formed by recessing from an inner wall surface facing the microcavity, and when the second cavity is moved to the off position relative to the first cavity and the semiconductor wafer to be processed is accommodated in the microcavity, at least one surface of the semiconductor wafer to be processed contacts and closely abuts against the inner wall surface of the first or second cavity constituting the recessed passage, and the recessed passage and the surface of the semiconductor wafer to be processed form a sealed passage. When performing the corrosion operation, a corrosive mixed gas is injected into the sealed passage, and the corrosive mixed gas flows in the sealed passage to corrode the surface of the semiconductor wafer exposed in the sealed passage. Then, the waste gas remaining in the sealed passage is discharged. The above steps are repeated to increase the depth of corrosion. When performing the extraction operation, a predetermined amount of extraction liquid is injected into the sealed passage, and the extraction liquid in the sealed passage flows in the sealed passage under pressure and is then discharged to the outside of the sealed passage. Thereby, the extracting liquid extracts metal contaminants on the surface of the semiconductor wafer exposed within the sealed passage.

[0007] In a second embodiment of the present invention, there is further provided a semiconductor processing method using the semiconductor processing apparatus. moving the second cavity relative to the first cavity to an on position; loading a semiconductor wafer to be processed between the first cavity and the second cavity; moving the second cavity relative to the first cavity to an off position; a corrosion operation including injecting a corrosive mixed gas into the sealed passage, causing the corrosive mixed gas to flow within the sealed passage to corrode the surface of the semiconductor wafer exposed within the sealed passage, and then discharging waste gas from within the sealed passage; An extraction operation includes a step of injecting a predetermined amount of extraction liquid into the sealed passage, the extraction liquid in the sealed passage flowing within the sealed passage by pressure and then being discharged to the outside of the sealed passage, and the extraction liquid extracts metal contaminants on the surface of the semiconductor wafer exposed in the sealed passage. Effect of the Invention

[0008] Compared with the prior art, the present invention forms a recess passage on the inner wall surface of one cavity, and the recess passage and the semiconductor wafer to be processed form a sealed passage. A processing fluid can flow through the sealed passage to process the surface of the semiconductor wafer to be processed. This makes it possible to accurately control the corrosion of the semiconductor wafer surface and greatly reduce the amount of chemicals used. The present invention performs the corrosion operation by using a corrosive mixed gas instead of a corrosive liquid. This makes it possible to accurately control the corrosion process and the extraction process, accurately adjust the volume of the extraction liquid, and accurately perform quantitative detection. In addition, it is possible to avoid the problems of the roughness of the corrosion surface caused by the remaining chemical solution and the inability to accurately control the quality of the extraction liquid when using the chemical corrosion method of the prior art. [Brief description of the drawings]

[0009] The present invention can be readily understood by reference to the following drawings and detailed description, in which like reference numbers generally refer to like structures, and in which: [Figure 1a] 1 is a cross-sectional view showing a semiconductor processing apparatus according to an embodiment of the present invention. [Figure 1b] FIG. 1B is an enlarged view showing part A in FIG. [Figure 1c] FIG. 1B is an enlarged view showing part B in FIG. [Figure 2a] FIG. 2 is a plan view showing a lower cavity according to an embodiment of the present invention. [Figure 2b] FIG. 2b is an enlarged view showing part C in FIG. 2a. [Figure 2c] FIG. 2b is an enlarged view showing part D in FIG. 2a. [Figure 2d] FIG. 2b shows a cross-section of the lower cavity of the present invention of FIG. 2a. [Figure 2e] FIG. 2C is an enlarged view showing part E in FIG. 2D. [Figure 2f] FIG. 2b is an enlarged view showing part F in FIG. 2a. [Figure 3a] FIG. 2 is a plan view showing an upper cavity according to an embodiment of the present invention. [Figure 3b] FIG. 3b is an enlarged view showing part G in FIG. 3a. [Figure 3c] FIG. 3B is an enlarged view showing part H in FIG. 3A. [Figure 3d] FIG. 3b shows a cross-section of the upper cavity of the present invention of FIG. 3a. [Figure 3e] FIG. 3D is an enlarged view showing part I in FIG. [Figure 3f] FIG. 3b is an enlarged view showing part J in FIG. 3a. [Figure 4a] FIG. 11 is a cross-sectional view showing a semiconductor processing apparatus according to another embodiment of the present invention. [Figure 4b] FIG. 4b is an enlarged view showing part K in FIG. 4a. [Figure 5a] FIG. 2 is a plan view showing an upper cavity according to an embodiment of the present invention. [Figure 5b] FIG. 5b is a cross-sectional view taken along line CC in FIG. 5a. [Figure 5c]FIG. 5b is an enlarged view showing part L in FIG. [Figure 6a] FIG. 11 is a plan view showing a lower cavity according to another embodiment of the present invention. [Figure 6b] FIG. 6b is an enlarged view showing part M in FIG. 6a. [Figure 7] 1 is a flow diagram illustrating a semiconductor processing method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to make the objects, features and effects of the present invention more clearly understood, the present invention will be described in more detail below with reference to the drawings and specific examples.

[0011] As used herein, "an embodiment" or "an embodiment" may include a given feature, structure, or characteristic according to at least one embodiment of the present invention. The term "an embodiment" as used in various places in this specification is not intended to refer to the same embodiment, nor is it intended to refer to a separate embodiment or to a specific embodiment that excludes other embodiments. As used herein, the terms "a plurality" and "some" mean two or more than two, and the term "and / or" as used herein means "and" or "or."

[0012] By providing a semiconductor processing apparatus in the present invention, the flow direction and flow speed of the processing fluid can be precisely controlled, and the amount of processing fluid used can be greatly reduced.

[0013] Fig. 1a is a cross-sectional view of a semiconductor processing apparatus 100 according to an embodiment of the present invention, Fig. 1b is an enlarged view of part A in Fig. 1a, and Fig. 1c is an enlarged view of part B in Fig. 1a. As shown in Fig. 1a, the semiconductor processing apparatus 100 includes an upper cavity 110 and a lower cavity 120.

[0014] The upper cavity 110 includes an upper cavity plate 111 and a first protrusion 112 extending downward from the periphery of the upper cavity plate 111. The lower cavity 120 includes a lower cavity plate 121 and a first recess 122 recessed downward from the periphery of the lower cavity plate 121.

[0015] The upper cavity 110 can be moved between an ON position and an OFF position relative to the lower cavity 120. When the upper cavity 110 is moved to the ON position relative to the lower cavity 120, a semiconductor wafer to be processed can be placed on the inner wall surface of the lower cavity 120 or the semiconductor wafer to be processed can be removed from the inner wall surface of the lower cavity 120. When the upper cavity 110 is moved to the OFF position relative to the lower cavity 120, the first protrusion 112 is coupled to the first recess 122 to form a sealed microcavity between the upper cavity plate and the lower cavity plate. In this case, the semiconductor wafer to be processed can be stored in the microcavity and then wait for subsequent processing.

[0016] One of the upper cavity 110 and the lower cavity 120 may be referred to as a first cavity, and the other of the upper cavity 110 and the lower cavity 120 may be referred to as a second cavity. The upper cavity 110 and the lower cavity 120 may move relative to each other. That is, the upper cavity 110 may move relative to the lower cavity 120 as the upper cavity 110 moves, or the upper cavity 110 may move relative to the lower cavity 120 as the lower cavity 120 moves.

[0017] Figure 2a is a plan view of a lower cavity 120 according to an embodiment of the present invention. Figure 2b is an enlarged view of part C in Figure 2a. Figure 2c is an enlarged view of part D in Figure 2a. Figure 2d is a cross-sectional view of the lower cavity of the present invention in Figure 2a. Figure 2e is an enlarged view of part E in Figure 2d. Figure 2f is an enlarged view of part F in Figure 2a.

[0018] As shown in Figures 2a to 2f, the lower cavity 120 includes a recess passage 124 formed by recessing the lower cavity 120 into an inner wall surface 123 facing the microcavity, a first through hole 125 penetrating the lower cavity in a direction facing the lower cavity from the outside and communicating with a first position of the recess passage 124, and a second through hole 126 penetrating the lower cavity in a direction facing the lower cavity from the outside and communicating with a second position of the recess passage 124. The cross-sectional shape of the recess passage 124 can be U-shaped, V-shaped, semicircular, or other shapes. The number of through holes in the recess passage 124 can be one or more, or one.

[0019] In another embodiment of the present invention, each recess passage 124 is formed to correspond to a plurality of through holes, each recess passage 124 is divided into a plurality of segments by the plurality of through holes, and each recess passage 124 is formed at both ends with one through hole communicating with each end of the both ends.

[0020] As shown in FIG. 1a, FIG. 1b and FIG. 1c, when the upper cavity 110 is moved to the on position relative to the lower cavity 120 and the unprocessed semiconductor wafer 200 is accommodated in the microcavity, one surface (lower surface) of the unprocessed semiconductor wafer 200 abuts against the inner wall surface 123 of the recess passage 124. At this time, the recess passage 124 forms a sealed passage through blocking the surface of the unprocessed semiconductor wafer 200. The sealed passage communicates with the outside through a first through hole 125 and a second through hole 126. In application, a processing fluid can flow into the sealed passage through the first through hole 125, and the fluid in the sealed passage can flow forward along the sealed passage. At this time, the processing fluid can process a predetermined area by contacting the predetermined area of ​​the surface of the unprocessed semiconductor wafer 200, and the fluid on the processed surface of the unprocessed semiconductor wafer 200 can flow out from the second through hole 126 and be collected. This makes it possible to accurately control the flow direction and flow speed of the processing fluid and greatly reduce the amount of processing fluid used.

[0021] In one embodiment of the present invention, as shown in Figures 2a, 2b and 2c, the recess passage 124 is formed in a circular spiral shape, a first through hole 125 is formed in a central region (region D) of the spiral recess passage, and a second through hole 126 is formed in a peripheral region (region C) of the spiral recess passage 124. The first through hole 125 can be used as an inlet, and the second through hole 126 can be used as an outlet. In another embodiment, the first through hole 125 can be used as an outlet, and the second through hole 126 can be used as an inlet.

[0022] In one embodiment of the present invention, as shown in Figures 2d, 2e and 2f, the first through-hole 125 includes a first buffer inlet 125a that is directly connected to the recess passage 124 and is deeper and wider than the recess passage 124, and a first through-hole body 125b that is directly connected to the first buffer inlet 125a. The first buffer inlet 125a is formed to prevent the central area of ​​the semiconductor wafer from being over-processed due to the initial speed of the processing fluid flowing in from the first through-hole 125 being too fast. The second through-hole 126 includes a second buffer inlet 126a that is directly connected to the recess passage 124 and is deeper and wider than the recess passage 124, and a second through-hole body 126b that is directly connected to the second buffer inlet 126a. The second buffer inlet 126a is formed to prevent the processing fluid from being effectively discharged from the second through-hole 126. Preferably, the first buffer inlet 125a is a conical recess and the second buffer inlet 126a is a cylindrical recess.

[0023] Figure 3a is a plan view showing an upper cavity 110 according to an embodiment of the present invention. Figure 3b is an enlarged view showing part G in Figure 3a. Figure 3c is an enlarged view showing part H in Figure 3a. Figure 3d is a cross-sectional view of the upper cavity of the present invention shown in Figure 3a. Figure 3e is an enlarged view showing part I in Figure 3d. Figure 3f is an enlarged view showing part J in Figure 3a.

[0024] 3a to 3f, the upper cavity 110 includes an upper cavity plate 111 and a first protrusion 112 extending downward from the periphery of the upper cavity plate 111. The upper cavity 110 has a recess passage 114 formed by recessing from the upper cavity to an inner wall surface 113 facing the microcavity. The recess wall surface (a portion between adjacent recess passages 114) of the recess passage 114 formed on the inner wall surface 113 of the upper cavity corresponds to the recess wall surface (a portion between adjacent recess passages 124) of the recess passage 124 formed on the inner wall surface 123 of the lower cavity 120 (FIGS. 1b and 1c). When the upper cavity 110 is moved to the off position relative to the lower cavity 120 and the unprocessed semiconductor wafer 200 is accommodated in the microcavity, the recessed wall surface of the recessed passage 114 of the upper cavity 110 abuts against a predetermined position of the unprocessed semiconductor wafer 200, thereby making the unprocessed semiconductor wafer 200 abut tightly against the recessed wall surface of the recessed passage 124 of the lower cavity 120, and forming a sealed passage with better sealing. In another embodiment, the recessed wall surface (a portion between adjacent recessed passages 114) of the recessed passage 114 formed on the inner wall surface 113 of the upper cavity 110 and the recessed wall surface (a portion between adjacent recessed passages 124) of the recessed passage 124 formed on the inner wall surface 123 of the lower cavity 120 may be disposed at an intersection.

[0025] In another modified embodiment of the present invention, the upper cavity 110 and the lower cavity 120 may have interchangeable structures or the same structure. In this case, a sealed passage is formed by the upper surface of the semiconductor wafer 200 to be processed and the recessed passage of the upper cavity 110. The processing fluid flowing in the sealed passage can process the upper or lower surface of the semiconductor wafer 200 to be processed, or can process the upper and lower surfaces simultaneously.

[0026] FIG. 4a is a cross-sectional view showing a semiconductor processing apparatus 400 according to another embodiment of the present invention. FIG. 4b is an enlarged view showing a portion K in FIG. 4a. Comparing the semiconductor processing apparatus 400 in FIG. 4a with the semiconductor processing apparatus in FIG. 1a, the difference is that the structure of the upper cavity 410 in FIG. 4a is different from that of the upper cavity 110 in FIG. 1a. FIG. 5a is a plan view showing an upper cavity 410 according to an embodiment of the present invention. FIG. 5b is a cross-sectional view showing a cross section along line CC in FIG. 5a. FIG. 5c is an enlarged view showing a portion L in FIG. 5a. As shown in FIGS. 5a to 5c, the upper cavity 410 includes an upper cavity plate 411, a first protrusion 412, a first inner wall surface 413 facing the microcavity, a second recess 414, a second protrusion 415 located between the first inner wall surface 413 and the second recess 414, and a passage 416 located in the center of the first inner wall surface 413. A sealed space is formed by the second protrusion 415 abutting against the unprocessed semiconductor wafer 200 and the first inner wall surface 413, and the sealed space is in communication with the outside through a passage 416. A predetermined pressure is generated in the sealed space by injecting a fluid into the sealed space through the passage 416. As a result, the unprocessed semiconductor wafer 200 abuts tightly against the recess wall surface of the recess passage 124 of the lower cavity 120, forming a sealed passage with good sealing properties.

[0027] FIG. 6a is a plan view of a lower cavity 620 according to another embodiment of the present invention. FIG. 6b is an enlarged view of part M in FIG. 6a. The number of recess passages 624 formed by recessing from the lower cavity 620 to the inner wall surface 623 of the microcavity is plural. Although five recess passages 624 are shown in FIG. 6a, a different number of recess passages 624 can be formed in other embodiments. Each recess passage 624 has one first through hole 625 and one second through hole 626 formed therein. Other recess passages 624 of the lower cavity 620 are formed in other areas of the inner wall surface 623. This allows a certain process to be performed on a certain area, and each process can be performed separately.

[0028] The present invention further provides a semiconductor processing method using the semiconductor processing apparatus. As shown in Figure 7, the semiconductor processing method 700 includes the following steps.

[0029] In step 710, the second cavity is moved to an on position relative to the first cavity.

[0030] In step 720, a semiconductor wafer to be processed is loaded between the first cavity and the second cavity.

[0031] In step 730, the second cavity is moved relative to the first cavity to an off position.

[0032] In step 740, a corrosion operation is performed. Specifically, a corrosive mixed gas is injected into the sealed passage, and the corrosive mixed gas flows through the sealed passage to corrode the surface of the semiconductor wafer exposed in the sealed passage. Next, a gas or liquid is injected into the sealed passage to exhaust the reaction gas and reaction product gas remaining in the sealed passage. The reaction gas and reaction product gas remaining in the sealed passage can also be called waste gas.

[0033] The corrosive mixed gas includes a corrosive gas, and the corrosive gas may be one or more of hydrofluoric acid gas and nitric acid gas. The corrosive mixed gas further includes ozone or a carrier gas, and the carrier gas may be one or more of nitrogen and an inert gas.

[0034] In an embodiment of the present invention, the corrosive mixed gas includes two kinds of corrosive mixed gases. The first corrosive mixed gas is a mixed gas formed by adding ozone to a corrosive liquid and containing a corrosive gas and ozone, and the second corrosive mixed gas is a mixed gas formed by adding ozone to a corrosive liquid and containing a corrosive gas and a carrier gas. The corrosive mixed gas can be called a corrosive vapor, such as hydrofluoric acid vapor, nitric acid vapor, etc.

[0035] In a preferred embodiment of the present invention, the corrosion operation includes a first corrosion step and a second corrosion step, which are performed alternately. In the first corrosion step, a first corrosive mixed gas containing the corrosive gas and ozone is injected into the sealed passage, and the state is maintained for a first preset time. In the second corrosion step, a second corrosive mixed gas containing the corrosive gas and a carrier gas is injected into the sealed passage, and the state is maintained for a second preset time. In the example of the present invention, the first preset time is 20 seconds, the second preset time is 10 seconds, and the number of times performed alternately is 22. When the second corrosion step is performed, the first corrosive mixed gas is still left in the sealed passage, and the corrosive gas in the second corrosive mixed gas can enter the sealed passage by diffusion.

[0036] In a specific embodiment of the present invention, the corrosion principle is O3+Si=SiO2+O2SiO2+4HF=SiF4+2H2O.

[0037] In the first etching step, silicon oxide is formed by the reaction of ozone with silicon on the surface of the semiconductor wafer, and silicon fluoride gas is formed by the reaction of hydrofluoric acid gas with silicon oxide. This allows the silicon to be corroded to a certain depth, and ensures that the original silicon surface and metal impurities in the reaction layer remain on the surface of the semiconductor wafer. In the second etching step, hydrofluoric acid gas is replenished to react with ozone, thereby eliminating excess ozone. In the present example, the rate of the corrosion reaction is about 1-6 um / H.

[0038] During the etching process, the flow direction of the corrosive gas mixture in the sealed passage can be changed continuously, and the depth of the etched silicon layer can be controlled by controlling the reaction time and the direction of the gas flow.

[0039] The etching operation further includes the step of continuously injecting a second corrosive mixed gas into the sealed passage after the first and second etching steps are cyclically repeated, and the injection is performed for a third preset time, so as to further etch the silicon oxide on the surface of the semiconductor wafer.

[0040] The corrosion operation further includes a step of continuously injecting a carrier gas into the sealed passage for a fourth preset time after the second corrosive mixed gas is kept flowing in the sealed passage for a third preset time, thereby discharging the reactant gas and the reaction product gas remaining in the sealed passage. In another embodiment, the reactant gas and the reaction product gas remaining in the sealed passage can be discharged by injecting a liquid into the sealed passage.

[0041] In step 750, an extraction operation is performed. A predetermined amount of extraction liquid is injected into the sealed passage, and the extraction liquid in the sealed passage flows in the sealed passage under pressure and is discharged to the outside of the sealed passage. As a result, the extraction liquid can extract metal contaminants on the surface of the semiconductor wafer exposed in the sealed passage. Specifically, when the extraction liquid flows in the sealed passage under pressure, the extraction liquid reacts with the metal contaminants remaining on the surface of the semiconductor wafer, so that the metal contaminants can be dissolved in the extraction liquid.

[0042] As the extraction liquid moves on the surface of the semiconductor wafer, the extraction liquid can collect metal contaminants in the flow area. Then, the extraction liquid on the surface of the semiconductor wafer is collected in a collection bottle. The extraction liquid can be moved by driving a driving gas. The driving gas can be any one or more of nitrogen and an inert gas. The extraction liquid can be any one or more of nitric acid, HF, and a hydrogen peroxide solution.

[0043] In a preferred embodiment of the present invention, the sealed passage can be formed in a spiral structure. As described above, each recess passage is divided into a plurality of segments by a plurality of through holes, and a plurality of sealed passage segments are formed by forming a plurality of through holes at both ends of each recess passage, the through holes being connected to the respective ends of the recess passage. In an embodiment of the present invention, the corrosion operation and the extraction operation can be simultaneously performed on the plurality of sealed passage segments by performing the corrosion operation and the extraction operation on each sealed passage segment, respectively.

[0044] Compared with the prior art, the present invention has the following advantages: 1. Since etching and extraction are performed within one cavity, contamination problems caused by transferring semiconductor wafers from one cavity to another can be avoided. 2. The microcavities are formed in a helical structure, which can greatly improve the utilization rate of the reaction gas. 3. By corroding the semiconductor wafer with the corrosive gas flowing in the sealed passage, the amount of chemicals used can be greatly reduced, and the chemical reaction can be stopped quickly by controlling the supply of the corrosive gas. In addition, excessive corrosion caused by the residual chemical liquid when using the conventional chemical etching method can be avoided. 4. When carrying out the process of the present invention, no waste water or liquid is produced, so that the amount of pollutants discharged and the cost of dealing with the pollutants can be greatly reduced. 5. The corrosion depth can be precisely controlled. 6. By changing the gas pressure, the gas concentration, proportion and flow rate can be controlled, and the reaction rate can be controlled. 7. The amount of extraction liquid is very small, so the amount of chemicals used can be greatly reduced. In addition, since the present invention uses a small amount of extraction liquid, the concentration of metal contaminants in the extraction liquid of the present invention can be greatly improved compared to the conventional technology that uses a large amount of extraction liquid, even if the contamination concentration is the same. As a result, the detection rate of metals can be greatly improved. By using the method of the present invention, the area of ​​corrosion, the depth of corrosion, the roughness and uniformity of the etched surface can be precisely controlled.

[0045] The above is a full description of the specific implementation of the present invention. It should be noted that those skilled in the art can freely modify the specific embodiments of the present invention without departing from the scope of the claims of the present invention. That is, the scope of the claims of the present invention is not limited to the specific embodiments described above.

Claims

1. 1. A semiconductor processing apparatus comprising: a first cavity and a second cavity movable between an on position and an off position relative to the first cavity; When the second cavity is moved to the off position relative to the first cavity, a microcavity is formed between the first cavity and the second cavity, and a semiconductor wafer to be processed is stored in the microcavity, and when the second cavity is moved to the on position relative to the first cavity, the semiconductor wafer to be processed can be removed or stored; the first cavity and / or the second cavity includes a recess passage formed by recessing an inner wall surface facing the microcavity, and when the second cavity is moved to the off position relative to the first cavity and the unprocessed semiconductor wafer is accommodated in the microcavity, at least one surface of the unprocessed semiconductor wafer abuts against the inner wall surface constituting the recess passage, and the recess passage abuts tightly against the surface of the unprocessed semiconductor wafer to form a sealed passage; When performing a corrosion operation, a corrosive mixed gas is injected into the sealed passage, and the corrosive mixed gas flows in the sealed passage to corrode the surface of the semiconductor wafer exposed in the sealed passage, and then a gas or liquid is injected into the sealed passage to exhaust the reaction gas and reaction product gas remaining in the sealed passage; a predetermined amount of extraction liquid is injected into said sealed passage when an extraction operation is performed, the extraction liquid in said sealed passage flows within said sealed passage due to pressure and chemically reacts with metal contaminants remaining on the surface of said semiconductor wafer, thereby dissolving the metal contaminants into the extraction liquid, and the extraction liquid is discharged to the outside of said sealed passage, and said extraction liquid extracts the metal contaminants on the surface of said semiconductor wafer exposed within said sealed passage.

2. The corrosive mixed gas includes a corrosive gas, and the corrosive gas is at least one of hydrofluoric acid gas and nitric acid gas; The corrosive mixed gas further includes ozone or a carrier gas, and the carrier gas is at least one of nitrogen and an inert gas; 2. The semiconductor processing apparatus according to claim 1, wherein the extraction liquid is moved by a driving gas, and the driving gas is at least one of nitrogen and an inert gas.

3. 3. The semiconductor processing apparatus according to claim 2, wherein the corrosive mixed gas is a mixed gas containing a corrosive gas and ozone formed by adding ozone or a carrier gas to a corrosive liquid, or a mixed gas containing a corrosive gas and a carrier gas.

4. 3. The semiconductor processing apparatus according to claim 2, wherein the etching operation includes a first etching step and a second etching step which are alternately performed, in which in the first etching step, a first corrosive mixed gas containing the corrosive gas and ozone is injected into the sealed passage and the state is maintained for a first preset time, and in the second etching step, a second corrosive mixed gas containing the corrosive gas and a carrier gas is injected into the sealed passage and the state is maintained for a second preset time.

5. 5. The semiconductor processing apparatus of claim 4, wherein in the second etching step, the first corrosive mixed gas is still left in the sealed passage, and the corrosive gas in the second corrosive mixed gas enters the sealed passage by diffusion.

6. 2. The semiconductor processing apparatus according to claim 1, wherein the direction in which the corrosive mixed gas flows within the sealed passage is constantly changed during the etching operation.

7. The semiconductor processing apparatus of claim 1, characterized in that the first cavity and / or the second cavity further includes a first through hole that penetrates the first cavity and / or the second cavity from the outside and communicates with a first position of the recess passage, and a second through hole that penetrates the first cavity and / or the second cavity from the outside and communicates with a second position of the recess passage, the sealed passage communicates with the outside through the first through hole and the second through hole, and one of the first through hole and the second through hole is used as an inlet and the other is used as an outlet.

8. 8. The semiconductor processing apparatus according to claim 7, wherein the recess passage is formed in an annular spiral shape.

9. 2. The semiconductor processing apparatus according to claim 1, wherein a number of recess passages are formed by recessing from the first cavity into the inner wall surface side of the microcavity, and a number of sealed passages are formed by forming one first through hole and one second through hole in each recess passage, and a corrosion operation is performed for each sealed passage.

10. A semiconductor processing method for a semiconductor processing apparatus, the semiconductor processing apparatus including a first cavity and a second cavity that can move between an on position and an off position relative to the first cavity, a microcavity is formed between the first cavity and the second cavity when the second cavity moves to the off position relative to the first cavity, a semiconductor wafer to be processed is stored in the microcavity, the semiconductor wafer to be processed can be removed or stored when the second cavity moves to the on position relative to the first cavity, the first cavity and or a semiconductor processing method for a semiconductor processing apparatus, the semiconductor processing method comprising: a second cavity including a recess passage formed by recessing an inner wall surface facing the microcavity; when the second cavity is moved to the off position relative to the first cavity and the unprocessed semiconductor wafer is accommodated in the microcavity, at least one surface of the unprocessed semiconductor wafer abuts against the inner wall surface constituting the recess passage, and the recess passage abuts tightly against the surface of the unprocessed semiconductor wafer to form a sealed passage; moving the second cavity relative to the first cavity to an on position; loading a semiconductor wafer to be processed between the first cavity and the second cavity; moving the second cavity relative to the first cavity to an off position; a corrosion operation including injecting a corrosive mixed gas into the sealed passage, causing the corrosive mixed gas to flow within the sealed passage to corrode the surface of the semiconductor wafer exposed within the sealed passage, and then discharging waste gas from within the sealed passage; and an extraction operation, comprising the steps of injecting a predetermined amount of extraction liquid into the sealed passage, causing the extraction liquid in the sealed passage to flow within the sealed passage by pressure and then being discharged to the outside of the sealed passage, and the extraction liquid extracting metal contaminants on the surface of the semiconductor wafer exposed within the sealed passage.

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