Suppression of phototransistor gain in optical modulators.

Abstract

The optical modulator (50) includes an emitter layer (32) with a first bandgap energy and having N-type doping, a base layer (34) with a second bandgap energy and having P-type doping, and a sub-emitter layer (54) disposed between the emitter layer (32) and the base layer (34), the sub-emitter layer (54) having a third bandgap energy less than both the first bandgap energy and the second bandgap energy. The optical modulator (50) may further include a collector layer (16) with N-type doping and an undoped layer (12) between the collector layer (16) and the base layer (34). The sub-emitter layer (54) provides a barrier to electrons flowing from the emitter layer (32) while allowing photo-generated holes to recombine in the sub-emitter layer (54), thereby mitigating current amplification.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor, i.e. optical modulators, and more particularly to systems and methods for suppressing phototransistor gain in optical modulators fabricated from III-V semiconductors. [Background technology]

[0002] NPIN and NIPN modulators are known to have exceptional advantages for high bandwidth. As known in the art, N represents an N-type doped region, P represents a P-type doped region, and I represents an undoped intrinsic region. See, for example, "N-type doped regions," "P-type doped regions," and "I-type undoped intrinsic regions," all of which are incorporated by reference in their entirety. However, these disclosures do not mention that NPIN and NIPN structures form two-terminal heterojunction phototransistors with photocurrent gains (beta) of up to 100. Such devices amplify DC photocurrents to levels that are entirely impractical in real systems. Power dependence of performance, modulation pattern dependence (low optical signal-to-noise ratio (OSNR)), poor reliability, and high power dissipation are some of the problems that can result. The only mention in the literature is a reference to "beware of current leakage" [NPL 1 cited above]. This was related to sidewall damage during dry etching, not to a phototransistor effect.

[0003] NPIN and NIPN modulators have been shown to be beneficial for high bandwidth, but phototransistor effects have not been identified. For such modulators to be of practical use, these effects must be suppressed. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Y.Ogiso et al., “80-GHz Bandwidth and 1.5-V Vπ InP-Based IQ Modulator”, Journal of Lightwave Technology, vol.38, no.2, pp.249-255,15 Jan.15,2020 [Non-Patent Document 2] Ogiso, Y., et al. “

[0011] waveguide stripe direction nipn heterostructure InP optical modulator”, Electronics Letters 50.9 (2014): 688-690 [Non-Patent Document 3] Kikuchi, Nobuhiro, et al. “80-Gb / s low-driving-voltage InP DQPSK modulator with an npin structure”, IEEE Photonics Technology Letters 21.12 (2009): 787-789 Summary of the Invention

[0005] The present disclosure relates to a system and method for suppression of phototransistor gain in an optical modulator fabricated from III-V semiconductors having either an NPIN structure or an NIPN structure. The present disclosure can utilize an NPIN structure as described in Kikuchi, Nobuhiro, et al. (2009) or Y. Ogiso et al. (2014). The modulator core is in an intrinsic region or an undoped region. For the NPIN structure, the present disclosure includes a first upper cladding (emitter) with a first bandgap energy and with N-type doping, a second upper cladding (base) with a second bandgap energy and with P-type doping, and a third upper cladding (sub-emitter) with a third bandgap energy and with N-type doping, disposed between the first and second upper claddings. The third bandgap energy is less than both the first and second bandgap energies. The present disclosure includes an additional layer called a sub-emitter layer. The use of narrow bandgap n-type material between the P and N layers is novel. Alternatively, the present disclosure can utilize the NIPN structure of Y. Ogiso et al. (2020). The approach described herein is a key sector for high bandwidth optical modulators (100G and beyond).

[0006] In one embodiment, the optical modulator includes an emitter layer with a first bandgap energy and N-type doping, a base layer with a second bandgap energy and P-type doping, and a sub-emitter layer disposed between the emitter layer and the base layer, the sub-emitter layer having a third bandgap energy that is smaller than both the first bandgap energy and the second bandgap energy. The optical modulator may further include a collector layer with N-type doping and an undoped layer between the collector layer and the base layer. The optical modulator may include an NPIN junction or an NIPN junction. The sub-emitter layer provides a barrier for electrons flowing from the emitter layer while allowing photo-generated holes to recombine in the sub-emitter layer, thereby mitigating current amplification. The optical modulator may further include a first contact disposed on the emitter layer and a second contact disposed on the collector layer. The third bandgap energy may be about 1.1-1.2Q, where Q is the bandgap measured in μm. The third bandgap energy may be about 1.2Q, where Q is the bandgap measured in μm. The optical modulator is fabricated from III-V semiconductors. The sub-emitter layer may include a quaternary alloy that is P-based (InGaAsP) or Al-based (InGaAlAs) lattice-matched to InP.

[0007] In another embodiment, a method of forming an optical modulator includes forming an emitter layer with a first bandgap energy and having N-type doping, forming a base layer with a second bandgap energy and having P-type doping, and forming a sub-emitter layer disposed between the emitter layer and the base layer, the sub-emitter layer having a third bandgap energy less than both the first bandgap energy and the second bandgap energy. The method may further include forming a collector layer with N-type doping and forming an undoped layer between the collector layer and the base layer. The optical modulator may include an NPIN junction or an NIPN junction. The sub-emitter layer provides a barrier for electrons flowing from the emitter layer while allowing photo-generated holes to recombine in the sub-emitter layer, thereby mitigating current amplification. The method may further include forming a first contact disposed on the emitter layer and a second contact disposed on the collector layer. The third bandgap energy may be about 1.1-1.2Q, where Q is the bandgap measured in μm. The third bandgap energy may be about 1.2Q, where Q is the bandgap measured in μm. The optical modulator is fabricated from III-V semiconductors. The sub-emitter layer may include a quaternary alloy that is P-based (InGaAsP) or Al-based (InGaAlAs) lattice-matched to InP. [Brief description of the drawings]

[0008] The present disclosure is illustrated and described herein with reference to various drawing figures, in which, where appropriate, reference numerals are used to designate like system components / method steps.

[0009] [Figure 1] FIG. 1 is a diagram of a conventional indium phosphide (InP) PIN modulator. [Diagram 2] FIG. 1 is a cross-sectional view of a PIN modulator. [Diagram 3]FIG. 1 is a cross-sectional view of an NPIN modulator that provides an improvement over a PIN modulator. [Figure 4] FIG. 1 is a diagram of an NPIN modulator to explain the problem of the phototransistor effect. [Diagram 5] FIG. 5 is a diagram of an NPIN modulator according to the present disclosure having a heterostructure for reducing the problem of the phototransistor effect with the NPIN modulators of FIGS. 3 and 4. [Figure 6] 1 is a graph of transistor current amplification versus bandgap. [Figure 7] 5 is a diagram of reverse biased InP NPIN bands with and without light for the NPIN modulators of FIGS. 3 and 4. FIG. [Figure 8] 6 is a diagram of reverse biased InP NPIN bands with and without light for the NPIN modulator of FIG. 5 with a blocking sub-emitter. [Figure 9] 1 is a graph of phototransistor current gain versus sub-emitter bandgap in an NPIN modulator. [Figure 10] FIG. 1 is a circuit diagram of an NPIN modulator. [Figure 11] 6 is a graph of the doping profile of the NPIN modulator of FIG. 5. [Figure 12] 6 is a graph of the electric field in the NPIN modulator of FIG. 5. [Figure 13] 6 is a graph of the electric field in the conduction band of the NPIN modulator of FIG. 5. [Figure 14] A graph of current versus voltage when a BJT is turned on. Note that the current (I) and voltage (V) are shown for the base (b), emitter (e), and collector (c). [Figure 15] A graph of current versus voltage when a BJT is turned on. Note that the current (I) and voltage (V) are shown for the base (b), emitter (e), and collector (c). [Figure 16]A graph of current versus voltage when a BJT is turned on. Note that the current (I) and voltage (V) are shown for the base (b), emitter (e), and collector (c). [Figure 17] 1 is a graph of DC current gain (β) for a BJT. [Figure 18] 1 is a graph of the current transfer ratio (α) for a BJT. [Figure 19] FIG. 29 is a diagram of the physical layout of a PIN modulator in the y and x dimensions for use with reference to FIGS. 20-28. [Figure 20] 20 to 23 are graphs of the PIN photoresponse when short-circuited / reverse biased. Fig. 20 is a graph of the conduction band. [Figure 21] 1 is a graph of an electric field. [Figure 22] 1 is a graph of current-light characteristics. [Diagram 23] 24 to 27 are graphs of PIN photoresponse versus open circuit voltage. [Figure 24] 1 is a graph of the conduction band. [Diagram 25] 1 is a graph of an electric field. [Figure 26] 1 is a graph of electron concentration. [Figure 27] 1 is a graph of hole concentration. [Figure 28] FIG. 1 is a schematic diagram of the open circuit voltage of the PIN photoresponse. [Figure 29] FIG. 41 is a diagram of the physical layout of an NPIN modulator in the y and x dimensions for use with reference to FIGS. 30-39. [Diagram 30] 30-32 are graphs of the baseline optical response for the NPIN modulator 30. Fig. 30 is a graph of the DC IV characteristics. [Diagram 31] This is a graph of the electric field. [Diagram 32] 1 is a graph of the conduction band. [Diagram 33] 1 is a graph of DC IV characteristics. [Diagram 34]1 is a graph of an electric field. [Diagram 35] 1 is a graph of the conduction band. [Diagram 36] 36 to 38 are graphs showing the effect of widening the base. Fig. 36 is a graph of DC IV characteristics. [Figure 37] 1 is a graph of an electric field. [Figure 38] 1 is a graph of the conduction band. [Figure 39] 1 is a graph of the change in β versus emitter doping and base width. [Diagram 40] 1A-1C are various graphs of InGaAs (narrow bandgap), InP, and InAlAs (wide bandgap) showing the conduction and valence bands. [Diagram 41] FIG. 59 is a diagram of the physical layout of the NPIN modulator 50 in the y and x dimensions for use with reference to FIGS. [Diagram 42] 42 to 44 are graphs of InGaAs-NPIN photoresponse (narrow BG emitter). Fig. 42 is a graph of DC IV characteristics. [Diagram 43] 1 is a graph of an electric field. [Diagram 44] 1 is a graph of the conduction band. [Diagram 45] 45 to 47 are graphs of InAlAs-NPIN photoresponse (wide BG emitter), and Fig. 45 is a graph of DC IV characteristics. [Figure 46] 1 is a graph of an electric field. [Figure 47] 1 is a graph of the conduction band. [Figure 48] 1 is a graph of heterostructure NPIN photoresponse as a function of sub-emitter bandgap energy. [Figure 49] Figures 49-51 are graphs of gain versus blocking layer thickness and composition. Figure 49 is a graph of bandgap. [Figure 50] 1 is a graph of β versus blocker position. [Figure 51] 1 is a graph of β versus blocking layer thickness. [Figure 52] 1 is a graph of gain versus blocking layer position. [Figure 53] 1 is a graph of β versus band gap energy. [Figure 54] 1 is a graph of Q for InGaAlAs versus InGaAsP as a blocking layer. [Figure 55] 55 to 57 are graphs of InAlAs-NPIN optical response (wide BG base). Fig. 55 is a graph of DC IV characteristics. [Figure 56] 1 is a graph of an electric field. [Figure 57] 1 is a graph of the conduction band. [Figure 58] Optical amplification versus sub-emitter bandgap for three different temperatures [Eg = bandgap energy]. [Figure 59] 1 is a graph of Q for different temperatures. [Figure 60] FIG. 1 is a perspective view of an edge region of a fabricated NPIN structure. [Figure 61] 1 is a cross-sectional view of an edge region of a fabricated NPIN structure. [Figure 62] 1 is a graph of a simulation of a conventional 2D PIN edge. [Figure 63] 1 is a graph of NPIN at 1.2Q with perfect sidewalls. [Figure 64] 1 is a graph of NPIN at 1.2Q with sidewalls removed. [Figure 65] 1. A graph of NPIN current when the sidewall of 2Q is pulled back. [Figure 66] 1 is a sensitivity graph showing current increase with temperature for a variable pullback. [Figure 67] 13 is a sensitivity graph showing current vs. affinity offset with a variable pullback of 320K. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Again, the present disclosure relates to a system and method for suppression of phototransistor gain in optical modulators fabricated from III-V semiconductors, having either an NPIN or NIPN structure. The present disclosure can utilize an NPIN structure as described in Kikuchi, Nobuhiro, et al. (2009) or Y. Ogiso et al. (2014). The modulator core is in an intrinsic region or an undoped region. With respect to the NPIN structure, the present disclosure includes a first upper cladding (emitter) with a first bandgap energy and with N-type doping, a second upper cladding (base) with a second bandgap energy and with P-type doping, and a third upper cladding (sub-emitter) with a third bandgap energy and with N-type doping, disposed between the first and second upper claddings. The third bandgap energy is less than both the first and second bandgap energies. The present disclosure includes an additional layer called a sub-emitter layer. The use of narrow bandgap n-type material between the P and N layers is novel. Alternatively, the present disclosure can utilize the NIPN structure of Y. Ogiso et al. (2020). The approach described herein is a key sector for high bandwidth optical modulators (100G and beyond).

[0011] Conventional PIN / NPIN Modulators Figure 1 is a diagram of a conventional indium phosphide (InP) PIN modulator 10. The InP PIN modulator 10 includes a multi-quantum well (MQW) region 12 with doped top / bottom (P-InP, N-InP) cladding, layers 14, 16. This is an optical ridge waveguide in which light is phase modulated. A DC voltage 18 is applied across the p-layer 14 and n-layer 16 to keep the PIN stackup in reverse bias. An AC voltage 20 dynamically modulates the phase of the optical signal.

[0012] 2 is a cross-sectional view of PIN modulator 10. PIN modulator 10 includes top and bottom contacts 22 that connect to voltages 18, 20. Included are layers 14, 16 and MQW region 12. Light propagates from left to right in MQW region 12. Bandwidth is limited by the p-cladding contact / series resistance.

[0013] FIG. 3 is a cross-sectional view of an NPIN modulator 30 that provides an improvement over the PIN modulator 10. The NPIN modulator 30 includes the contact 22, layer 16, and MQW region 12, and further includes layer 14 having an emitter n-InP layer 32 and a base p-InP layer 34. Here, the p-doping in layer 16 has been replaced with a more conductive n-doped material. The n-doped structure in the emitter n-InP layer 32 has a reduced contact resistivity. The p-doped layer 34 is a current blocking layer. Such a structure has the highest bandwidth reported in the literature.

[0014] Replacing the PIN stack-up of the PIN modulator 10 with the NPIN of the NPIN modulator 30 improves device performance. However, the NPIN stack-up resembles a typical NPN bipolar junction transistor (BJT) and may amplify the photo-generated current in the MQW region 12. This phototransistor effect is detrimental to device operation and needs to be suppressed / eliminated.

[0015] Figure 4 is a diagram of an NPIN modulator 30 to illustrate the problem of the phototransistor effect. With light "on", the NPIN structure acts as a photocurrent amplifier. Such devices have been commercialized as photodetectors in other industries where amplification is desirable. With regard to modulator design, large photocurrents cause excessive power dissipation and loss of modulator efficiency, and this phenomenon needs to be suppressed. Notably, there is no discussion in the academic journals on high performance modulators of how to address this problem.

[0016] NPIN Modulator with Heterostructure for Reducing the Phototransistor Effect 5 is a diagram of an NPIN modulator 50 according to the present disclosure having a heterostructure for reducing the problem of the phototransistor effect with the NPIN modulator 30. FIG. 5 is a cross-sectional view of the epitaxy layer structure of the NPIN modulator 50. The NPIN modulator 50 includes the contact 22, the collector n-InP layer 16, the MQW region 12 (intrinsic region), the base p-InP layer 34, the new blocking sub-emitter narrow n-type layer 52, and the emitter n-InP layer 32.

[0017] It should be noted that the discussion herein focuses on the NPIN modulator 50. Those skilled in the art will recognize that the blocking sub-emitter narrow n-type layer 52 can also be used in an NIPN modulator.

[0018] The emitter n-InP layer 32 has a first bandgap energy, the base p-InP layer 34 has a second bandgap energy, and the sub-emitter narrow n-type layer 52 has a third bandgap energy that is less than both the first bandgap energy and the second bandgap energy.

[0019] The blocking sub-emitter narrow n-type layer 52 is a narrow band structure to suppress amplification. Note that due to optical losses, it is not possible to make the bandgap too narrow, and the sweet spot for the blocking sub-emitter narrow n-type layer 52 is about 1.1-1.2Q for C-band operation, where Q is the bandgap measured in μm. Figure 6 is a graph of transistor current amplification vs. bandgap. Curves B, R relate to InGaAsP and InGaAlAs sub-emitter systems, respectively. This further demonstrates that only the bandgap of the sub-emitter is essential, not the particular alloy (P-based vs. Al-based).

[0020] Figure 7 is a reverse bias InP NPIN band diagram with and without light for the NPIN modulator 30. Figure 8 is a reverse bias InP NPIN band diagram with and without light for the NPIN modulator 50 with a blocking sub-emitter.

[0021] FIG. 9 is a graph of phototransistor current gain versus sub-emitter bandgap for an NPIN modulator 50. The intersections 60, labeled "w / o blocking sub-emitter" and "InP bandgap," respectively, are the gain (100) of the modulator 30 without any measures to suppress phototransistor action. The line 62, labeled "w / wide bandgap base," is the effect of the prior art of incorporating an InAlAs "blocking layer" into the base. The current gain is 3. Below line 64 at any energy gap <1.05 eV is the beneficial effect of the present disclosure. The gain drops to a theoretical lower limit of 1. Physically, the sub-emitter provides a barrier to electrons flowing from the emitter while allowing photogenerated holes to recombine in the sub-emitter layer, thereby mitigating current amplification. See FIG. 8.

[0022] NPIN design as BJT transistor This section contains a series of electrical simulations that show that the NPN structure allows for transistor operation (current amplification). The simulations are a first exercise to understand the extent of the problem and serve as a concise review of transistor operation in vertical NPN BJTs.

[0023] FIG 10 is a circuit diagram of the NPIN modulator 50. The NPIN modulator 50 is a BJT. FIG 11 is a graph of the doping profile of the NPIN modulator 50. FIG 12 is a graph of the electric field in the NPIN modulator 50. FIG 13 is a graph of the conduction band energy as a function of applied external bias for the NPIN modulator 50.

[0024] Figures 14-16 are graphs of current versus voltage when the BJT is turned on. Of note, the current (I) and voltage (V) are shown for the base (b), emitter (e), and collector (c).

[0025] Figure 17 is a graph of the DC current gain (β) for the BJT. Figure 18 is a graph of the current transfer ratio (α) for the BJT.

[0026] [Table 1]

[0027] PIN diode photoresponse This section simulates the baseline performance of a conventional PIN diode structure under optical stimulation, i.e., the PIN modulator 10. This establishes the baseline photocurrent levels for these models and sets expectations for what needs to be achieved from any new NPIN design.

[0028] FIG. 19 is a diagram of the physical layout of PIN modulator 10 in the y and x dimensions, for use with reference to FIGS. 20-28.

[0029] Figures 20 to 23 are graphs of the PIN photoresponse when short-circuited / reverse biased. Figure 20 is a graph of the conduction band, Figure 21 is a graph of the electric field, Figure 22 is a graph of the current-light characteristics, and Figure 23 is a graph of the DC IV characteristics. The photocurrent varies linearly with the input optical power. With no bias applied, i.e., with a short-circuit current, a photocurrent of about 6.7 μA flows. The photocurrent does not depend on the applied voltage.

[0030] Figures 24-27 are graphs of the PIN photoresponse with open circuit voltage. Figure 24 is a graph of the conduction band, Figure 25 is a graph of the electric field, Figure 26 is a graph of the electron concentration, and Figure 27 is a graph of the hole concentration. When excess electrons (holes) accumulate on the left (right) side of the intrinsic layer, a dipole is formed whose electric field opposes and cancels the built-in field of the PIN structure. Thus, in the center of the intrinsic region, the drift component (E=0) or diffusion component (n, p are uniform) of the current vanishes for both types of carriers. The open circuit voltage of this structure is equal to 1.102V.

[0031] 28 is a schematic diagram of the open circuit voltage for the PIN photoresponse. The open circuit voltage is essentially equivalent to the optically induced bias.

[0032] [Table 2]

[0033] NPIN photoresponse This section examines the performance of an NPIN modulator 30 that does not use the proposed heterostructure. Note that the nominal photocurrent levels are nearly 100 times greater than those achieved for a conventional PIN structure. A series of simulations then demonstrates that the current amplification cannot be easily suppressed by modifying the geometry of the structure. Although not described here, the considered design modifications would impose a large penalty on the bandwidth of the device and are therefore not practical.

[0034] FIG. 29 is a diagram of the physical layout of NPIN modulator 30 in the y and x dimensions, for use with reference to FIGS. 30-39.

[0035] 30-32 are graphs of the baseline photoresponse for NPIN modulator 30. FIG. 30 is a graph of the DC IV characteristics, FIG. 31 is a graph of the electric field, and FIG. 32 is a graph of the conduction band. It takes only about 10 meV to forward bias the BE diode. At about 300 meV, the photocurrent is β max = saturates at 97.

[0036] 33-35 are graphs of the effect of reducing the emitter doping. FIG. 33 is a graph of DC IV characteristics, FIG. 34 is a graph of the electric field, and FIG. 35 is a graph of the conduction band. By reducing the emitter doping to 1E17, the β max is reduced to about 10. Moreover, the electric field distribution in the intrinsic region approaches that of an ideal PIN.

[0037] 36 to 38 are graphs showing the effect of widening the base. Fig. 36 is a graph of DC IV characteristics, Fig. 37 is a graph of the electric field, and Fig. 38 is a graph of the conduction band. β max may be reduced to about 13 by broadening the base (1000 nm).

[0038] FIG. 39 is a graph of the change in β versus emitter doping and base width.

[0039] Heterojunction NPIN photoresponse This section demonstrates the relationship between the band gap of the proposed emitter layer and the photocurrent amplification. The main conclusions include: Narrow bandgap emitters significantly suppress unwanted amplification Large bandgap emitters increase unwanted amplification The choice of specific materials represents a trade-off between electrical and optical performance.

[0040] FIG. 40 is various graphs for InGaAs (narrow bandgap), InP, and InAlAs (wide bandgap) showing the conduction and valence bands.

[0041] FIG. 41 is a diagram of the physical layout of NPIN modulator 50 in the y and x dimensions, for use with reference to FIGS.

[0042] 42 to 44 are graphs of InGaAs-NPIN photoresponse (narrow BG emitter). FIG. 42 is a graph of DC IV characteristics, FIG. 43 is a graph of the electric field, and FIG. 44 is a graph of the conduction band. β max is suppressed by 1. The E-field profile is not compromised in the MQW region. The narrower bandgap in the emitter (with respect to the base) suppresses β.

[0043] 45 to 47 are graphs of InAlAs-NPIN photoresponse (wide BG emitter). FIG. 45 is a graph of DC IV characteristics, FIG. 46 is a graph of the electric field, and FIG. 47 is a graph of the conduction band. β max is improved to 376. The E-field profile in the MQW region is significantly compromised. A wider bandgap in the emitter (with respect to the base) improves β.

[0044] Figure 48 is a graph of the heterostructure NPIN photoresponse. For x=0.47-y, InGaAlAs is lattice matched to InP.

[0045] Figures 49-51 are graphs of gain vs. blocking layer thickness and composition. Figure 49 is a graph of bandgap, Figure 50 is a graph of β vs. blocker position, and Figure 51 is a graph of β vs. blocking layer thickness. Figure 52 is a graph of gain vs. blocking position.

[0046] Figure 53 is a graph of the electric field for InGaAlAs vs. InGaAsP as a blocking layer. Figure 54 is a graph of Q for InGaAlAs vs. InGaAsP as a blocking layer.

[0047] In photocurrent calibration, a narrow bandgap (BG) at the base provides β enhancement, a narrow BG at the emitter provides β suppression, and a wide BG at the base provides β suppression to a lesser extent. Due to manufacturing and material constraints, this latter approach is not as effective at suppressing unwanted currents as the solution described herein.

[0048] 55 to 57 are graphs of InAlAs-NPIN photoresponse (wide BG base). FIG. 55 is a graph of DC IV characteristics, FIG. 56 is a graph of the electric field, and FIG. 57 is a graph of the conduction band. β max drops to 3. The E-field profile is slightly weaker in the MQW region. The narrower bandgap in the emitter (with respect to the base) suppresses β.

[0049] Dependence of band offsets on temperature in simple heterojunctions. Simulations to evaluate the device sensitivity to temperature; most simulations were performed at 300K, but the product is operated at 320K. This represents the photocurrent amplification as a function of emitter bandgap at three temperatures. For materials with bandgaps in the 1.1-1.2μm range, the suppression mechanism is robust up to 350K.

[0050] Figure 58 is a graph of current amplification versus sub-emitter bandgap for three different temperatures. Figure 59 shows the same as Figure 58, but with the bandgap measured in terms of wavelength (Q) instead of eV.

[0051] Non-idealities in fabricated devices The previous section focused on the vertical current flow in the NPIN structure. The fabricated device is finite and needs to be terminated. This section presents expectations for the edges of the fabricated device and considers whether non-idealities would degrade or negate the benefits of the proposed approach. The model predicts that performance will not be affected by the expected issues. This conclusion is derived from simulations of a conventional PIN structure as a baseline for subsequent results, and of the proposed NPIN structure while varying the shape of the proposed narrow bandgap layer.

[0052] Figure 60 is a perspective view of the edge region of a fabricated NPIN structure. Figure 61 is a cross-sectional view of the edge region of a fabricated NPIN structure. There are two NPIN devices: (i) the main vertical structure and (ii) the parasitic structure at the edge of the device. The narrow bandgap material may not cover the entire sidewall, raising the question of whether leakage will increase.

[0053] Figure 62 is a graph of a simulation of a conventional 2D PIN edge. Figure 63 is a graph of NPIN in 1.2Q with full sidewalls. Figure 64 is a graph of NPIN in 1.2Q with sidewalls removed. Figure 65 is a graph of NPIN current when the sidewalls of 1.2Q are pulled back.

[0054] Figure 66 is a sensitivity graph showing current increase with temperature for a variable pullback. Figure 67 is a sensitivity graph showing current vs. affinity offset for a variable pullback at 320K.

[0055] conclusion Although the present disclosure has been illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those skilled in the art that other embodiments and examples may perform similar functions and / or achieve similar results. All such equivalent embodiments and examples are within the spirit and scope of the present disclosure, are contemplated thereby, and are intended to be encompassed by the following claims. Furthermore, it should be noted that the various elements, operations, steps, methods, processes, algorithms, functions, techniques, etc. described herein can be used in any and all combinations with one another.

Claims

1. an emitter layer (32) with a first bandgap energy and having an N-type doping; a base layer (34) with a second bandgap energy and having P-type doping; a sub-emitter layer (54) disposed between the emitter layer (32) and the base layer (34), the sub-emitter layer (54) having a third bandgap energy less than both the first bandgap energy and the second bandgap energy; An optical modulator (50).

2. a collector layer (16) having an N-type doping; an undoped layer (12) between the collector layer (16) and the base layer (34); The optical modulator of claim 1 further comprising:

3. The optical modulator (50) of claim 1 or 2, wherein the optical modulator (50) comprises an NPIN junction.

4. The optical modulator (50) of claim 1 or 2, wherein the optical modulator (50) comprises a NIPN junction.

5. 5. The optical modulator (50) of claim 1, wherein the sub-emitter layer (54) provides a barrier to electrons flowing from the emitter layer (32) while allowing photo-generated holes to recombine in the sub-emitter layer (54), thereby reducing current amplification.

6. a first contact (22) disposed on the emitter layer (32); a second contact (22) disposed on the collector layer (16); The optical modulator (50) of any one of claims 1 to 5, further comprising:

7. The optical modulator (50) of any one of claims 1 to 6, wherein the third bandgap energy is about 1.1 to 1.2Q, where Q is the bandgap measured in μm.

8. The optical modulator (50) of any one of claims 1 to 5, wherein the third bandgap energy is about 1.2Q, where Q is the bandgap measured in μm.

9. The optical modulator (50) of any one of claims 1 to 8, wherein the optical modulator (50) is fabricated from III-V semiconductors.

10. The optical modulator (50) of any one of claims 1 to 9, wherein the sub-emitter layer (52) comprises a quaternary alloy.

11. The optical modulator (50) of claim 10, wherein the quaternary alloy is either P-based or Al-based.

12. A method of forming an optical modulator (50), comprising the steps of: forming an emitter layer (32) with a first bandgap energy and having N-type doping; forming a base layer (34) with a second bandgap energy and having P-type doping; forming a sub-emitter layer (54) disposed between the emitter layer (32) and the base layer (34), the sub-emitter layer (54) having a third bandgap energy less than both the first bandgap energy and the second bandgap energy; A method comprising:

13. forming a collector layer (16) having an N-type doping; forming an undoped layer (12) between the collector layer (16) and the base layer (34); The method of claim 12 further comprising:

14. 14. The method of claim 12 or 13, wherein the sub-emitter layer (54) provides a barrier to electrons flowing from the emitter layer (34) while allowing photo-generated holes to recombine in the sub-emitter layer (54), thereby mitigating current amplification.

15. forming a first contact (22) disposed on the emitter layer (32); forming a second contact (22) disposed on the collector layer (16); 15. The method of claim 13 or 14, further comprising:

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