Wafer grounding method using wafer edge backside coating exclusion area

Abstract

A system and method are provided for grounding a wafer (604, 904) in a charged particle beam device. The system and method includes providing an exclusion area (613, 911) on a backside film 608, 908 on the wafer of a size sufficient to allow electrical connection between the wafer and an electrical contact (612, 912) of the charged particle beam device. The system and method may include contacting a pin body to a surface of the wafer, the wafer having a coating thereon, the pin body comprising a first tip and a second tip each extending from the pin body, the contacting being performed in a first exclusion area of ​​the coating by either the first tip, the second tip, or any combination thereof. Also provided is a method for forming a coating on a wafer surface, the method including masking the first exclusion area on the wafer surface with a first exclusion mask.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [1] This application claims priority to U.S. Patent Application No. 63 / 323,728, filed March 25, 2022, U.S. Patent Application No. 63 / 341,334, filed May 12, 2022, and U.S. Patent Application No. 63 / 489,643, filed March 10, 2023, which are hereby incorporated by reference in their entireties.

[0002] [2] The description herein relates to the field of semiconductor manufacturing, and more particularly to wafer grounding and biasing that may be useful in semiconductor wafer processing using charged particle beam devices. [Background technology]

[0003] [3] Charged particle beam devices can generate two-dimensional images of a wafer substrate by detecting secondary, backscattered, mirror, or other types of electrons coming from the surface of the wafer substrate when the surface is bombarded with a charged particle beam generated by the charged particle beam device. In the semiconductor industry, various charged particle beam devices are used on semiconductor wafers for various purposes, such as wafer processing (e.g., electron beam direct write lithography systems), process monitoring (e.g., critical dimension scanning electron microscopes (CD-SEMs)), wafer inspection (e.g., electron beam inspection systems), and defect analysis (e.g., defect review SEMs, DR-SEMs, and focused ion beam systems, FIBs). When such devices function, the potential of the wafer substrate can be held or biased at a predetermined value for better imaging. This can be achieved by electrically connecting, more specifically, resistively connecting, the wafer substrate of interest to a programmable DC voltage source (e.g., a wafer bias supply). The electrical connection is made when the wafer substrate interacts with the charged particle beam, during which an excess charge may be provided to the wafer substrate, a process that may be referred to as wafer biasing.

[0004] [4] For wafer biasing, electrical contact from a wafer bias source to the wafer substrate is traditionally made at the backside of the wafer substrate by using one or more electrical contacts pressed against the backside of the wafer substrate. Typically, the front side of the wafer is unsuitable for placing electrical contacts because the features are formed on the front side. In some cases, a wafer may have an electrically insulating film disposed on its backside (e.g., a backside film). The backside film may make it difficult to establish a reliable electrical connection between the electrical contacts and the conductive surface of the wafer. Summary of the Invention

[0005] [5] Embodiments of the present disclosure include systems and methods for wafer grounding using an exclusion area on the wafer backside membrane. In some embodiments, the exclusion area is an area on the backside where there is no backside membrane material. Embodiments of the present disclosure provide clean contact between electrical contacts (such as ground pins) and the conductive surface of the wafer.

[0006] [6] Embodiments of the present disclosure include wafers having backside film exclusion areas for grounding the wafer. The exclusion areas can be located, for example, at the periphery, the central region, or an intermediate region between the center and periphery of the wafer backside.

[0007] [7] Embodiments of the present disclosure include a wafer grounding system having ground pins for contacting an exclusion area of ​​the backside film. The ground pins and exclusion area may be located, for example, at the periphery, the central region, or an intermediate region between the center and the periphery of the wafer backside.

[0008] [8] Embodiments of the present disclosure include a charged particle beam inspection method for inspecting a wafer having an exclusion area on a backside film. The method may include inspecting the wafer in two different inspection steps with the wafer supported at two different angular orientations in the wafer plane. The one or more exclusion areas are configured such that the wafer can be grounded in the exclusion areas during both inspection steps.

[0009] [9] Embodiments of the present disclosure include systems and methods for manufacturing wafers with backside film exclusion areas. Various exemplary systems and methods are disclosed for masking or otherwise preventing film formation in selected areas during a process for forming a thick backside film in a processing chamber.

[0010]

[10] Embodiments of the present disclosure include systems and methods for electrically connecting to a wafer. The systems and methods may include contacting a pin body to a surface of a wafer, the wafer having a coating on the surface, the pin body having a first tip and a second tip each extending from the pin body, the contacting being at a first exclusion area of ​​the coating by either one of the first tip, the second tip, or any combination thereof.

[0011]

[11] Additional objects and advantages of the disclosed embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments. Certain objects and advantages of the disclosed embodiments may be realized and attained by means of the elements and combinations recited in the appended claims. However, it is not necessary for an embodiment of the present disclosure to achieve such illustrative object or advantage, and some embodiments may not achieve any of the described objects or advantages.

[0012]

[12] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments, as may be claimed. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system, according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a schematic diagram illustrating an example electron beam tool that may be part of the example electron beam inspection system of FIG. 1, in accordance with an embodiment of the present disclosure. [Diagram 3] FIG. 1 is a diagram of an exemplary system for wafer grounding, according to an embodiment of the present disclosure. [Figure 4A]

[16] shows operational stages of an exemplary system for wafer grounding in a comparative embodiment. [Figure 4B]

[16] shows operational stages of an exemplary system for wafer grounding in a comparative embodiment. [Figure 4C]

[16] shows operational stages of an exemplary system for wafer grounding in a comparative embodiment. [Figure 4D]

[16] shows operational stages of an exemplary system for wafer grounding in a comparative embodiment. [Diagram 5]

[17] Diagram of potential problems caused by holes in the wafer backside membrane. [Figure 6A] FIG. 18 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 6B] FIG. 18 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 6C] FIG. 18 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 6D]

[19] illustrates an example relationship between radial position, size, and rotational positioning accuracy of the exclusion area, according to an embodiment of the present disclosure. [Figure 7A] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, according to an embodiment of the present disclosure. [Figure 7B] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, according to an embodiment of the present disclosure. [Figure 8A] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 8B] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 9A] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 9B] FIG. 2 is a diagram of an exemplary subsystem for wafer grounding, in accordance with an embodiment of the present disclosure. [Figure 10]

[23] FIG. 1 illustrates an exemplary wafer having a backside film exclusion area, according to an embodiment of the present disclosure. [Figure 11A] FIG. 1 illustrates an exemplary backside film formation chamber in a comparative embodiment of the present disclosure. [Figure 11B]

[25] FIG. 11B is a diagram of an exemplary wafer backside film that may be formed in the chamber of FIG. 11A in a comparative embodiment of the present disclosure. [Figure 12A]

[26] FIG. 1 illustrates an exemplary backside film formation chamber, according to an embodiment of the present disclosure. [Figure 12B]

[27] FIG. 12B illustrates an exemplary wafer backside film that may be formed in the chamber of FIG. 12A according to an embodiment of the present disclosure. [Figure 12C]

[28] FIG. 1 illustrates an exemplary backside film formation chamber, according to an embodiment of the present disclosure. [Figure 13A] FIG. 13 is a diagram of an exemplary backside film formation chamber in a comparative embodiment of the present disclosure. [Figure 13B]

[30] FIG. 13B is a diagram of an exemplary wafer backside film that may be formed in the chamber of FIG. 13A in a comparative embodiment of the present disclosure. [Figure 14A]

[31] FIG. 1 illustrates an exemplary backside film formation chamber, according to an embodiment of the present disclosure. [Figure 14B]

[32] FIG. 14B illustrates an exemplary wafer backside film that may be formed in the chamber of FIG. 14A according to an embodiment of the present disclosure. [Figure 15]

[33] FIG. 3 is a flowchart illustrating an exemplary method for forming a wafer backside film, according to an embodiment of the present disclosure. [Figure 16]

[34] FIG. 3 is a flow chart illustrating an exemplary method for grounding a wafer having a backside film, according to an embodiment of the present disclosure. [Figure 17]

[35] An exemplary exclusion area of ​​a wafer is shown along with the location of a single-tip ground pin. [Figure 18]

[36] Figure 1 illustrates an exemplary exclusion area of ​​a wafer along with the location of a dual-tip ground pin according to an embodiment of the present disclosure. [Figure 19]

[37] Figure 1 illustrates an exemplary exclusion area of ​​a wafer along with the location of a dual-tip ground pin according to an embodiment of the present disclosure. [Figure 20]

[38] Figure 1 illustrates an exemplary wafer with the backside membrane in contact with a dual-tip ground pin, according to an embodiment of the present disclosure. [Figure 21]

[39] FIG. 1 illustrates a cross-sectional view of an exemplary dual-tip ground pin, in accordance with an embodiment of the present disclosure. [Figure 22]

[40] FIG. 1 illustrates an exemplary wafer holder having a ground pin, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[41] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which the same numbers in different drawings represent the same or similar elements unless otherwise stated. The implementations described in the following description of the exemplary embodiments do not represent all implementations according to the present disclosure. Instead, these implementations are merely examples of apparatus and methods according to aspects related to the subject matter recited in the appended claims. Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detection systems and methods in systems utilizing electron beams ("e-beams"). However, the present disclosure is not so limited. Other types of charged particle beams (including, for example, protons, ions, muons, or any other particles carrying an electric charge) may be applied as well. Additionally, the systems and methods for detection may also be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, and the like.

[0015]

[42] Electronic devices consist of circuits formed on a piece of semiconductor material called a substrate. Semiconductor materials can include, for example, silicon, gallium arsenide, indium phosphide, and silicon germanium. Many circuits can be formed together on the same piece of silicon and are called integrated circuits, or ICs. The size of these circuits is shrinking dramatically to allow more circuits to fit on a substrate. For example, an IC chip in a smartphone can be the size of a thumbnail yet contain over 2 billion transistors, each of which can be less than one thousandth the size of a human hair.

[0016]

[43] The fabrication of these ICs, which contain extremely small structures or components, is a complex, time-consuming, and expensive process that often involves hundreds of individual steps. An error in even one step can introduce defects into the finished IC, rendering it unusable. Thus, one goal of the manufacturing process is to avoid such defects and maximize the number of working ICs produced by the process, thus increasing the overall yield of the process.

[0017]

[44] One element of improving yield is monitoring the chip manufacturing process to ensure that it produces a sufficient number of working integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages in their formation. Inspection can be done using a scanning charged-particle microscope (SCPM). For example, an SCPM can be a scanning electron microscope (SEM). A SEM can be used to image such tiny structures, in effect taking a "picture" of the structures on the wafer. The image can be used to determine whether the structures were formed properly in the proper locations. If the structures are defective, the process can be adjusted so that the defect is less likely to reoccur.

[0018]

[45] The working principle of an SEM is similar to that of a camera. A camera takes a picture by receiving and recording the intensity of light reflected or emitted from a person or object. An SEM takes a "picture" by receiving and recording the energy or quantity of electrons reflected or emitted from structures on a wafer. Before taking such a "picture," an electron beam may be projected onto the structure, and as electrons reflect or emit ("emit") from the structure (e.g., from the surface of the wafer, from structures beneath the surface of the wafer, or both), a detector in the SEM may receive and record the energy or quantity of those electrons to generate an inspection image. To take such a picture, the electron beam may scan (e.g., line-by-line or zigzag) across the wafer, and the detector may receive incoming and outgoing electrons from the area where the electron beam was projected (called the "beam spot"). The detector may receive and record the outgoing electrons from each beam spot one by one, and the recorded information for all beam spots may be combined to generate an inspection image. Some SEMs use a single electron beam to take a single "photo" to produce an inspection image (called "single-beam SEMs"), while other SEMs use multiple electron beams to take multiple "part photos" of the wafer in parallel and stitch them together to produce an inspection image (called "multi-beam SEMs"). By using multiple electron beams, the SEM can deliver more electron beams onto the structure to obtain these multiple "part photos", resulting in more electrons being emitted from the structure. Thus, the detector can receive more of the emitting electrons simultaneously and produce inspection images of the wafer's structures more efficiently and faster.

[0019]

[46] Typically, the structures are fabricated on a substrate (e.g., a silicon wafer) that is placed on a platform for imaging, called a stage. When the electron beam hits the structure, the substrate may become charged and no longer be electrically neutral. A charged substrate may acquire a voltage that affects the outgoing electrons, which may affect image quality. Therefore, to improve imaging, it may be advantageous to ground the substrate.

[0020]

[47] For grounding purposes, the substrate may be electrically connected to a power source. The electrical connection between the power source and the substrate may be made by pressing one or more conductive ground pins or probes against the back surface of the substrate (i.e., the surface without the IC structures). The back surface of the substrate may be covered by a thin film of material (the "back surface film").

[0021]

[48] ​​However, the backside membrane is not conductive. Various types of methods can be used to make an electrical connection across such a non-conductive backside membrane. Examples include: (1) electrical zapping, (2) penetration, and (3) pin impingement.

[0022]

[49] In the electrical zapping method, a ground pin is driven into the backside membrane, which may be partially but not completely penetrated. A power source may generate a high voltage (e.g., tens of kilovolts) electrical signal (the "zapping signal") between the ground pins with the purpose of disrupting the backside membrane to establish an electrical connection between the ground pins and the wafer. The zapping signal creates an electrical zap between the ground pins and the wafer, which may result in the backside membrane being disrupted.

[0023]

[50] In the piercing method, a ground pin is driven into the substrate, penetrating the backside membrane and making direct contact with the substrate. However, the piercing method results in damage to the backside membrane, which can lead to damage to the substrate during manufacturing. It can also generate excessive particles, which can lead to contamination of the SEM vacuum chamber. Furthermore, as discussed below, neither the piercing nor the zapping method can overcome all types of backside membranes.

[0024]

[51] Some wafers require thicker backside films than others. For example, some complex IC structures may have many layers. Such multi-layer structures may create higher tensions on the surface of the wafer than in other cases. High tensions may cause the wafer to warp or bow, which may result in errors (e.g., blurring) in the inspection image. To avoid wafer warping or bowing due to such complex structures, the wafer may be coated with a thickened backside film to increase its mechanical strength. However, making the backside film thick enough to prevent wafer warping or bowing may be too thick to achieve acceptable wafer grounding for either electrical zapping or conventional penetration methods.

[0025]

[52] To overcome the thick wafer problem, a "pin impact" method has been proposed. Instead of simply pushing a pin into the backside membrane as in the piercing method, the wafer grounding system can actuate the ground pin to deliver a strong impact to "punch" the thickened backside membrane. After penetrating the thickened backside membrane by impact, an electrical connection can be established between the ground pin and the conductive surface of the wafer for wafer grounding. However, some backside membranes are so thick that the force required for the pin impact method can damage the wafer. The deformation resulting from the impact can cause overlay errors and generate contaminant particles in the wafer environment. Furthermore, even if the punch is successful, it can be difficult to maintain continuity in the ground connection.

[0026]

[53] Embodiments of the present disclosure include systems and methods for wafer grounding using exclusion areas of the backside film. The exclusion areas can be areas on the backside where the backside film is absent or is thinned or otherwise modified (e.g., using a material of different electrical conductivity). Embodiments of the present disclosure provide clean contact between the ground pins and the conductive surface of the wafer while reducing the risk of overlay errors based on particle contamination and deformation. Additionally, the duration and stability of the electrical connection may also be improved.

[0027]

[54] Embodiments of the present disclosure allow for significant flexibility in the design of wafer ground systems. For example, an exclusion area may be placed around the periphery of the wafer, and advantageously, at least some of the wafer ground pins may be spaced away from the central region of the wafer. In some embodiments, the wafer may include multiple exclusion areas around the periphery to allow SEM inspection of the wafer at multiple angular orientations. In some embodiments, the wafer may include a single annular shaped exclusion area around the wafer periphery. This allows SEM inspection to have a continuously variable set of angular orientation options.

[0028]

[55] Further embodiments of the present disclosure include wafers having backside film exclusion areas, and systems and methods for manufacturing wafers having backside film exclusion areas. Various exemplary systems and methods are disclosed for masking, modifying, or preventing film formation in selected regions during formation of a thick backside film.

[0029]

[56] In some embodiments, the backside film is formed over the entire surface of the wafer, and portions of the film in the exclusion area are removed in a subsequent processing step. In some embodiments, the exclusion area comprises a conductive film having the same or similar thickness as the non-conductive backside film to achieve good electrical contact with high flatness on the backside of the wafer.

[0030]

[57] The ground pins may have a single tip that contacts the exclusion area of ​​the wafer. Because the exclusion area of ​​the wafer may be small, the positional accuracy of the single-tip ground pins that contact the exclusion area of ​​the wafer may be low. In some embodiments, to improve the positional accuracy of the ground pins that contact the exclusion area of ​​the wafer, each ground pin may include a pin body with two tips extending from the pin body (a "dual-tip" ground pin). The distance between the first and second tips of the ground pin may be substantially equal to the width of the exclusion area of ​​the wafer to improve the positional accuracy of the ground pins that contact the exclusion area of ​​the wafer. The dual-tip ground pins may be flexibly adjusted to increase the chances that the ground pins contact the exclusion area of ​​the wafer (i.e., the dual-tip ground pins may increase the positional accuracy).

[0031]

[58] In some embodiments, the ground pin may include a spring structure in the wafer holder, which may be configured to inhibit wafer warping or wafer bowing by reducing the force exerted on the wafer.

[0032]

[59] The relative dimensions of components in the drawings may be exaggerated for clarity. In the following description of the drawings, the same or similar reference numbers refer to the same or similar components or entities and only the differences with respect to individual embodiments are described.

[0033]

[60] As used herein, unless specifically stated otherwise, the term "or" includes all possible combinations, unless impracticable. For example, if a component is stated to include A or B, the component may include A, or B, or A and B, unless specifically stated otherwise or impracticable. As another example, if a component is stated to include A, B, or C, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C, unless specifically stated otherwise or impracticable. A phrase such as "at least one of" does not necessarily modify the entire list that follows, but rather each element of the list, such that "at least one of A, B, and C" should be understood to include only one of A, only one of B, only one of C, or any combination of A, B, and C. The phrases "one of A and B" or "any one of A and B" shall be interpreted in the broadest sense to include one of A or one of B.

[0034]

[61] FIG. 1 illustrates an exemplary electron beam inspection (EBI) system 100 in accordance with an embodiment of the present disclosure. The EBI system 100 may be used to image or otherwise process a wafer. The wafer may be grounded. As shown in FIG. 1, the EBI system 100 includes a main chamber 101, a load lock chamber 102, a beam tool 104, and an equipment front-end module (EFEM) 106. The beam tool 104 is disposed within the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include additional loading port(s). The first loading port 106a and the second loading port 106b accept wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). A "lot" is a number of wafers that may be loaded for processing as a batch.

[0035]

[62] One or more robot arms (not shown) of the EFEM 106 may transfer the wafer to the load lock chamber 102. The load lock chamber 102 may be connected to a load lock vacuum pumping system (not shown) that removes gas molecules in the load lock chamber 102 to reach a first pressure that is lower than atmospheric pressure. After the first pressure is reached, one or more robot arms (not shown) may transfer the wafer from the load lock chamber 102 to the main chamber 101. The main chamber 101 may be connected to a main chamber vacuum pumping system (not shown) that removes gas molecules in the main chamber 101 to reach a second pressure that is lower than the first pressure. After the second pressure is reached, the wafer is subjected to inspection by the beam tool 104. The beam tool 104 may be a single beam system or a multi-beam system.

[0036]

[63] A controller 109 is electronically connected to the beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. In Figure 1, the controller 109 is shown as being external to the structure that includes the main chamber 101, the load lock chamber 102, and the EFEM 106, but it should be understood that the controller 109 may be part of the structure.

[0037]

[64] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or special-purpose electronic device capable of manipulating or processing information. For example, a processor may include a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a system on a chip (SoC), an application specific integrated circuit (ASIC), and any number or combination of any type of circuitry capable of processing data. A processor may also be a virtual processor, including one or more processors distributed across multiple machines or devices coupled via a network.

[0038]

[65] In some embodiments, the controller 109 may further comprise one or more memories (not shown). The memories may be general-purpose or special-purpose electronic devices capable of storing code and data that are accessible by the processor (e.g., via a bus). For example, the memories may include any number or combination of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. The code may include an operating system (OS) and one or more application programs (or "apps") for specific tasks. The memories may also be virtual memories, including one or more memories distributed across multiple machines or devices coupled via a network.

[0039]

[66] Figure 2 illustrates an exemplary imaging system 200 according to an embodiment of the present disclosure. The electron beam tool 104 of Figure 2 may be configured for use in the EBI system 100 discussed above with reference to Figure 1. The electron beam tool 104 may be a single beam or a multi-beam device. As shown in Figure 2, the electron beam tool 104 includes a motorized sample stage 201 and a wafer holder 202 supported by the motorized sample stage 201 to hold a wafer 203 to be inspected. The electron beam tool 104 further includes an objective lens assembly 204, an electron detector 206, an objective aperture 208, a condenser lens 210, a beam limiting aperture 212, a gun aperture 214, an anode 216, and a cathode 218. The objective lens assembly 204 may, in some embodiments, include a swing objective retarding immersion lens (SORIL) comprising a pole piece 204a, a control electrode 204b, a deflector 204c, and an excitation coil 204d. Additionally, the electron beam tool 104 may include an Energy Dispersive X-ray Spectrometer (EDS) detector (not shown) for characterizing materials on the wafer 203.

[0040]

[67] A primary electron beam 220 is emitted from the cathode 218 by applying an accelerating voltage between the anode 216 and the cathode 218. The primary electron beam 220 passes through the gun aperture 214 and the beam limiting aperture 212. Both the gun aperture 214 and the beam limiting aperture 212 may determine the size of the electron beam incident on the condenser lens 210 below the beam limiting aperture 212. After the condenser lens 210 focuses the primary electron beam 220, the beam enters the objective aperture 208 to set the size of the electron beam before entering the objective lens assembly 204. The deflector 204c deflects the primary electron beam 220 to facilitate beam scanning on the wafer. For example, in the scanning process, the deflector 204c may be controlled to sequentially deflect the primary electron beam 220 onto different positions on the top surface of the wafer 203 at different times to provide data for image reconstruction for different portions of the wafer 203. Additionally, the deflector 204c may also be controlled to deflect the primary electron beam 220 at different times onto different sides of the wafer 203 at a particular location to provide data for volumetric image reconstruction of the wafer structures at the particular location. Additionally, in some embodiments, the anode 216 and cathode 218 may generate multiple primary electron beams 220, and the electron beam tool 104 may include multiple deflectors 204c to simultaneously project the multiple primary electron beams 220 onto different portions / sides of the wafer 203 to provide data for image reconstruction of different portions of the wafer 203.

[0041]

[68] The excitation coil 204d and pole piece 204a generate a magnetic field that starts at one end of the pole piece 204a and ends at the other end of the pole piece 204a. The portion of the wafer 203 scanned by the primary electron beam 220 may be immersed in this magnetic field and may become charged, generating an electric field. The electric field reduces the energy of the incident primary electron beam 220 near the surface of the wafer before it impacts the wafer 203. A control electrode 204b, electrically isolated from the pole piece 204a, controls the electric field on the wafer 203 to prevent micro-arcing of the wafer 203 and ensure proper beam focus.

[0042]

[69] Upon receiving the primary electron beam 220, a secondary electron beam 222 may be emitted from a portion of the wafer 203. The secondary electron beam 222 may form a beam spot on a sensor surface of the electron detector 206. The electron detector 206 may generate a signal (e.g., voltage, current, etc.) representative of the intensity of the beam spot and provide this signal to the image processing system 250. The intensity of the secondary electron beam 222 and the resulting beam spot may vary depending on the external or internal structure of the wafer 203. Furthermore, as discussed above, the primary electron beam 220 may be projected onto different locations on the top surface of the wafer, or on different sides of the wafer at a particular location, to generate secondary electron beams 222 (and resulting beam spots) of different intensities. Thus, by mapping the intensity of the beam spot with respect to the position of the wafer 203, the processing system may reconstruct an image reflecting the internal or external structure of the wafer 203.

[0043]

[70] The imaging system 200 may be used to inspect the wafer 203 on the motorized sample stage 201 and may include the electron beam tool 104 discussed above. The imaging system 200 may also include an image processing system 250 including an image acquisition device 260, a storage 270, and a controller 109. The image acquisition device 260 may include one or more processors. For example, the image acquisition device 260 may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, or the like, or a combination thereof. The image acquisition device 260 may be connected to the detector 206 of the electron beam tool 104 via a medium such as electrical conductors, fiber optic cables, portable storage media, IR, Bluetooth, the Internet, a wireless network, a radio, or a combination thereof. The image acquisition device 260 may receive signals from the detector 206 and construct an image. Thus, the image acquisition device 260 may acquire an image of the wafer 203. The image capture device 260 may also perform various post-processing functions such as generating contours, superimposing indices on the captured image, etc. The image capture device 260 may perform adjustments such as brightness and contrast of the captured image. The storage 270 may be a storage medium such as a hard disk, cloud storage, random access memory (RAM), or other type of computer readable memory. The storage 270 may be coupled with the image capture device 260 and may be used to store raw scanned image data as original images or to store post-processed images. The image capture device 260 and the storage 270 may be connected to the controller 109. In some embodiments, the image capture device 260, the storage 270, and the controller 109 may be integrated together as one control unit.

[0044]

[71] In some embodiments, the image acquisition device 260 may acquire one or more images of the sample based on an imaging signal received from the detector 206. The imaging signal may correspond to a scanning motion to perform charged particle imaging. The acquired image may be a single image including multiple imaging regions. The single image may be stored in the storage 270. The single image may be an original image that may be divided into multiple regions. Each of the regions may include one imaging region that includes a feature of the wafer 203.

[0045]

[72] Wafer grounding may be accomplished by conducting charge from the wafer 203 to the wafer holder 202 so that the wafer 203 is electrically neutral. In comparative grounding systems, a piercing or electrical zapping method may be used to achieve wafer grounding. In these methods, the wafer may be placed on a wafer stage with its backside supported by the wafer stage. The backside surface of the wafer substrate may have a coating (e.g., a backside membrane applied to the backside of the wafer). The backside membrane may be non-conductive. Two or more ground pins made of a conductive material (e.g., metal) may be pressed against the backside membrane without completely piercing the backside membrane.

[0046]

[73] In the electrical zapping method, current may enter the wafer from the first ground pin through the backside membrane via a first breakdown and exit the wafer through the backside membrane via a second breakdown to the second ground pin. The breakdown may create a stable electrical path (e.g., a direct current (DC) path) through the backside membrane, which may be referred to as a "bias path." The bias path may have an effective resistance. For example, the resistance of the backside membrane may contribute to an effective resistance that represents the resistance of the bias path from the first ground pin through the wafer to the second ground pin.

[0047]

[74] Figure 3 is a diagram of an example of a wafer grounding system 300 in a comparative embodiment. The system 300 includes a subsystem 302 for holding a wafer, an electrical signal generator 314, a sensor 316, a controller 322, and a control parameter optimizer 324.

[0048]

[75] The subsystem 302 includes an electrostatic holder 306 and a wafer 304. In some embodiments, the wafer 304 may be similar or the same as the wafer 203 of FIG. 2, and the electrostatic holder 306 may be similar or the same as the wafer holder 202 of FIG. 2. The wafer 304 includes a backside membrane 308. The backside membrane 308 may be non-conductive. The electrostatic holder 306 may include at least one electrode 310. The electrode 310 may be electrically conductive to attract and secure the wafer 304 to the electrostatic holder 306 via an electrostatic field. The subsystem 302 further includes at least one ground pin (or "probe") 312. The ground pin 312 may be electrically connected between an electrical signal generator 314 and the wafer 304. In some embodiments, the ground pin 312 may be pressed against the backside membrane 308 without penetrating completely through the backside membrane 308. The ground pin 312 may be electrically connected to an electrical signal generator 314 and a sensor 316 .

[0049]

[76] The electrical signal generator 314 may generate a zapping signal to ground the wafer 304. In some embodiments, the electrical signal generator 314 is a driver. The zapping signal may have a high voltage to cause a breakdown through the backside film 308 between the ground pin 312 and the wafer 304. The sensor 316 may be used to detect or measure an electrical characteristic 320 associated with the breakdown. For example, the electrical characteristic 320 may include at least one of impedance, resistance, capacitive reactance, admittance, emissivity, conductance, capacitive susceptance, or any parameter indicative of a characteristic of the wafer. In some embodiments, the electrical characteristic 320 may be associated with an electrical path including the ground pin and the wafer. For example, the subsystem 302 may be a single pin system with a single ground pin 312. In a single pin system, the sensor 316 may be electrically connected to the wafer 304 and may measure an electrical characteristic 320 indicative of a breakdown through the backside film 308 between the ground pin 312 and the wafer 304. Further details of the system of FIG. 3 can be found in International Publication No. 2021 / 037827, the entirety of which is incorporated herein by reference.

[0050]

[77] In some embodiments, highly complex structures are fabricated on the wafer. Such complex structures may comprise multiple layers. For example, complex structures include three-dimensional circuits comprising one or more NOT-AND ("NAND") gates, such as NAND flash memory circuits. Compared to other structures, multi-layered composite structures may induce high tensions on the surface of the wafer, which may cause the wafer to warp or bow. Bowed wafers may cause problems in the inspection process, such as portions of the wafer being out of the focal plane of the primary electron beam (e.g., primary electron beam 220 in FIG. 2). These problems may cause degradation of the quality of the inspection image (e.g., defocus, blurring, distortion, etc.).

[0051]

[78] To avoid warping or bowing of the wafer due to such complex structures, in some embodiments, the wafer may be coated with a thickened backside film to increase mechanical strength. The backside film may be thickened by 2x, 5x, or 10x or more. For example, in some comparative cases, the backside film may be 0.1-0.3 μm thick. To avoid warping or bowing of the wafer, the backside film may be thickened (e.g., 1.4-2.2 μm or more). However, the thickened backside film may be so thick that neither the electrical zapping method nor the penetration method is effective for wafer grounding. For example, the thickened backside film may be thick enough that the electrical zapping method cannot break through the dielectric breakdown. In another example, the thickened backside film may be thick enough that the penetration method cannot force a ground pin through it.

[0052]

[79] To ground wafers with thickened backside films, a "pin impact method" has been proposed. Figures 4A-4D show the operational stages of a comparative system 400 for pin impact wafer grounding. System 400 can be a subsystem of any system for wafer grounding (e.g., system 300 of Figure 3). It should be noted that although only one ground pin is shown in Figures 4A-4D, any single-pin system (e.g., subsystem 302 of Figure 3) or multi-pin system may be configured to compatibly implement the pin impact method. For example, in a multi-pin system, the pin impact method may be compatibly implemented on one or more of its multiple ground pins.

[0053]

[80] In Figures 4A-4D, the system 400 includes a wafer 404, a backside membrane 408, a ground pin 412, and an actuator (not shown). The backside membrane 408 can be the same as or similar to the backside membrane 308 of Figure 3. In some embodiments, the backside membrane 408 can be thickened. For example, the thickness of the backside membrane 408 can be greater than 0.3 μm (e.g., 1.4-2.2 μm). In some embodiments, the actuator can include one of an electric actuator (e.g., an electromechanical actuator such as an electric motor, or an electrohydraulic actuator including a hydraulic accumulator), a magnetic actuator (e.g., an electric motor), a spring (e.g., a coiled spring or a coiled polymer), a pneumatic actuator, or a hydraulic actuator.

[0054]

[81] FIG. 4A shows an initial stage of using the system 400, in which the ground pin 412 can be controlled (e.g., by the controller 322 in FIG. 3) to contact the backside film 408. For example, the actuator of the initial stage can be made inoperative. In other words, the ground pin 412 can be in a default position in the initial stage. In the initial stage, the default position causes the ground pin 412 to contact the backside film 408. Such an initial stage configuration can ensure the compatibility of the system 400 for grounding a wafer that does not have a thickened backside film. For example, when a wafer that does not have a thickened backside film is placed in the system 400, by setting the initial stage as shown in FIG. 4A, the system 400 can execute other methods for wafer grounding (e.g., electric zapping method or piercing method) without invoking the pin impact method.

[0055]

[82] FIG. 4B illustrates a first stage of the system 400 performing the pin impact method, in which the ground pin 412 is moved a distance away from the back membrane 408 (as indicated by the arrow). In some embodiments, an actuator may move the ground pin 412 away from the back membrane 408. In some embodiments, the ground pin 412 may be moved away from the back membrane 408 such that the distance between the ground pin 412 (e.g., measured from the tip of the ground pin 412) and the back membrane 408 may be greater than 100 microns. For example, the distance may be greater than 1 millimeter. In some embodiments, by moving the ground pin 412 away from the back membrane 408, the ground pin 412 may have sufficient space for acceleration, as described below.

[0056]

[83] FIG. 4C illustrates a second stage of the system 400 implementing the pin impact method, in which an actuator (not shown) may actuate (e.g., accelerate) the ground pin 412 toward the back membrane 408 (as indicated by the arrow). In some embodiments, the acceleration may end before the ground pin 412 impacts the back membrane 408. In some embodiments, the actuator may actuate the ground pin 412 such that the kinetic energy of the ground pin 412 before impacting the back membrane 408 may exceed, for example, 0.0002 Joules (e.g., when the maximum travel distance of the ground pin 412 is 3 millimeters). It should be noted that the kinetic energy of the ground pin before impacting the back membrane 408 may depend on its travel distance under actuation by the actuator and is not limited to the above example.

[0057]

[84] FIG. 4D illustrates the final stage of the system 400 performing the pin impingement method, in which the ground pin 412 penetrates the backside membrane 408 by impact due to the kinetic energy obtained in the second stage as described in FIG. 4C. In some embodiments, the ground pin 412 may penetrate the backside membrane 408 completely and directly contact the wafer 404 without drilling a hole. In such a case, an electrical connection between the ground pin 412 and the wafer 404 may be established to ground the wafer 404 using the penetration method of wafer grounding. In some embodiments, the ground pin 412 may not penetrate the backside membrane 408 completely, such that the distance between the tip of the ground pin 412 and the surface (e.g., conductive surface) of the wafer 404 may be 0.3 microns or less. In such a case, an electrical connection between the ground pin 412 and the wafer 404 may be established to ground the wafer 404 using the electrical zapping method of wafer grounding. Further details regarding the pin impingement method can be found in WO 2021 / 037827.

[0058]

[85] The pin impact method cannot overcome all the shortcomings of the prior art. For example, the destructive action of piercing the thick backside membrane can lead to particle contamination in the wafer environment. The force of the impact can degrade the ground pin and shorten its life. Even in the case of a successful impact, it can be difficult to maintain continuity between the wafer and the ground pin. The force of the impact can additionally cause deformation of the wafer, which can affect the overlay performance. The risk of deformation increases with increasing membrane thickness, since a large impact energy is required to pierce the membrane. Furthermore, as described below, if the location of the impact hole is not properly selected, further overlay errors can be introduced in subsequent processes.

[0059]

[86] Figure 5 illustrates overlay problems in subsequent processes that may result from poor placement of pin impingement holes. In Figure 5, the wafer that has undergone an inspection process is placed on a different wafer support during a subsequent processing step. For example, the wafer support may be a wafer table WT and the processing step may be a lithographic exposure of a further device layer in a microlithography exposure apparatus. The wafer 504 is supported on a backside membrane 508 on a number of burls B, which are a series of protrusions forming a flat support surface SS. In a previous inspection step, holes H have been formed in the backside membrane 508 to ground the wafer 504. If the wafer 504 is mounted on the wafer table WT such that the hole H is placed over one of the burls B, the wafer may not be properly supported. This creates a sag that may cause an overlay error in the exposure process.

[0060]

[87] The embodiments of the present disclosure reflect an improved method for grounding wafers, including wafers with thick backside membranes. Rather than punching large holes in the backside membrane during setup of the inspection process, an exclusion area is formed in the backside membrane during membrane formation. The ground pin can easily make stable electrical contact with the conductive surface of the wafer because there is no membrane to impede contact at the ground location. Alternatively, there may be an altered membrane in the exclusion area where it is easier for the ground pin to make electrical contact with the wafer than in other parts of the backside membrane. Advantages of the present disclosure are described in part with reference to the embodiments discussed herein.

[0061]

[88] FIG. 6A illustrates a subsystem 600 and a wafer 604 according to some embodiments of the present disclosure. The subsystem 600 can be a subsystem of any system for wafer grounding (e.g., system 300 of FIG. 3). In FIG. 6A, an exclusion area 613 is formed in the backside membrane 608 and aligned with the ground pin 612. The exclusion area 613 can be formed as multiple spaced apart areas, as a single continuous area, or in any geometric configuration. Alternatively or additionally, any of the ground pin 612, the wafer 604, the holder 606 or a subcomponent of the holder 606, a stage, or other support components can be movable by an actuator to align the ground pin 612 with the exclusion area 613. The backside membrane 608 can include a non-conductive material or a material having a lower electrical conductivity than the material of the wafer 604. For example, the backside membrane can include silicon dioxide and the wafer can include silicon. The membrane may be, for example, silicon nitride, other oxides, nitrides, carbides, or other suitable membrane material to provide structural support (e.g., support to prevent bowing or warping of the wafer). The exclusion area 613 may be a portion of the layer of backside membrane 608 where membrane material is missing or altered. The missing portion exposes the conductive surface of the wafer 604 to the ground pins 612. However, in some embodiments, the backside membrane material may not be completely missing from some or all of the exclusion area 613. In some embodiments, the backside membrane 608 is simply made thinner than the surrounding portions to allow grounding by any wafer grounding method, such as piercing, zapping, or pin impact.

[0062]

[89] It should be noted that while two ground pins are shown in FIG. 6A, single-pin systems (e.g., subsystem 302 in FIG. 3) or multi-pin systems may be configured that interchangeably perform the exclusion area method. For example, in a multi-pin system as seen in FIG. 6B, an exclusion area may be formed for each location of the multiple ground pins, or for a subset of the locations of the multiple ground pins. The exclusion area may be more or less than the ground pins. It should be understood that other variations are not inconsistent with some embodiments of the invention. For example, there may be a single ground pin 612 or multiple ground pins 612. There may be a single exclusion area 613 or multiple exclusion areas 613. The number of pins 612 may be less than, more than, or equal to the number of exclusion areas 613. One or more of the ground pins 612 may be configured to perform either the exclusion ground method, the piercing method, the zapping method, the pin impact method, or any other suitable wafer grounding method, or a combination of wafer grounding methods. The ground pins 612 and holder 606 can be adapted to a variety of wafers, including thin and thick backside film wafers, wafers with exclusion areas, and wafers without exclusion areas.

[0063]

[90] FIG. 6C is a diagram of an exemplary system 600 for wafer landing location adjustment, according to an embodiment of the present disclosure. It should be noted that while FIG. 6C discloses an arrangement in the beam tool 104 of the main chamber 101, the present disclosure is not limited to this arrangement and not all depicted components are present in all possible embodiments. In some embodiments, the system 600 may be located in the main chamber 101, such as the load lock chamber 102 or the beam tool 104. However, in general, the system 600 may be applied to any system or module in which a wafer 604 is supported during a process step. The system 600 may include a subsystem 602 configured on the wafer 604, a controller 615, a sensor 616, and a target adjustment value 614. Subsystem 602 may be similar to subsystem 302 of FIG. 3 or subsystem 602 of FIGS. 6A-6B and may include a wafer 604, a holder 606, a backside film 608, an electrode 610, a ground pin 612, an upper wafer stage 607, a lower wafer stage 609, and an actuator including a lifter 608.

[0064]

[91] The sensor 616 may measure the position or orientation of the wafer 604. Alternatively or additionally, the sensor 616 may measure the position or orientation of the exclusion area 613. The position or orientation may be relative to the ground pin 612, the holder 606, the stage top 607, the stage bottom 609, or another reference position or orientation. The sensor 616 may be located above, below, or adjacent to the wafer 604. The sensor 616 may be embedded within or mounted on the holder 606, the stage top 607, the stage bottom 609, or any other structural component that allows the sensor to determine the desired parameter. The sensor 616 may be configured to access the backside of the wafer 604 by a hole or other opening in an intervening component. For example, the sensor 616 may be located on the stage top 607 and configured to view the wafer 604 through an opening in the holder 606. The sensor 616 may be configured to detect reference features such as alignment notches or flats, wafer edges, fiducial marks, etc. For example, the sensor 616 may comprise a laser or other radiation source disposed above or below the wafer and a camera such as a CCD, CMOS, or other detection device configured to detect radiation. The sensor 616 may comprise, for example, an alignment measurement unit or a pre-alignment measurement unit configured to detect alignment features. The sensor 616 may be configured as a z-height sensor or other profilometer to identify the exclusion area 613 by the wafer backside topography due to a change in the thickness of the backside film. In general, the sensor 616 may be optical, capacitive, ultrasonic, or any other configuration to achieve the desired detection. For example, the sensor 616 may use imaging, time-of-flight, interferometry, ellipsometry, capacitance, ultrasonic, or any other suitable detection system to determine the exclusion area or reference location.

[0065]

[92] In some embodiments, the target adjustment 614 may include a value of a parameter used by the controller 615 to control an actuator of the subsystem 602 to align the location of the ground pin 612 to a target location. For example, the target location may include the location of the exclusion area 613. In some embodiments, data regarding the target adjustment 614 may be stored in a database (e.g., a database in one or more memories of the system 100 of FIG. 1). The actuator may include an electric actuator, a magnetic actuator, an electromagnetic actuator, a hydraulic actuator, a mechanical actuator, or any suitable type of actuator. In some embodiments, the wafer stage (including the upper portion 607 and the lower portion 609) may be the motorized sample stage 201 of FIG. 2.

[0066]

[93] The controller 615 may be electrically connected to the actuators, including actuators (not shown) electrically connected to the sensors 616 and mechanically connected to the lifter 608 and the top 607. The controller 615 may control the actuators to move various parts of the subsystem 602, such as the lifter 608, the top 607, the ground pins 612, or other mechanical components (e.g., a robotic arm) for moving the wafer 604. For example, a dashed arrow between the controller 615 and the top 607 may indicate that the controller 615 may control the actuators (not shown) to move the top 607 in a horizontal direction, a vertical direction, or both. A dashed arrow between the controller 615 and the lifter 608 may indicate that the controller 615 may control the lifter 608 to move the wafer 604 in a vertical direction. In some embodiments, the controller 615 may further connect to a database to read parameters for controlling the actuators or to store data received from the sensors 616. For example, controller 615 may access a database that stores target adjustment values ​​614. In some embodiments, controller 615 may be implemented as part of controller 109 of Figures 1-2. In some embodiments, controller 615 may be implemented as a controller separate from controller 109, such as a software module or a hardware module.

[0067]

[94] In some embodiments, the lower portion 609 may be fixed and the upper portion 607 may be movable. For example, the upper portion 607 may be movable (e.g., movable along a vertical direction, a horizontal direction, or both), or may be horizontally rotatable, or both. In some embodiments, the holder 606 may be fixed to the upper portion 607 and may be movable with the upper portion 607. In some embodiments, the upper portion 607 may support the wafer 604 via the holder 606 and may have a ground pin 612 fixed thereto. For example, an end of the ground pin may be fixed to the upper portion 607 and may be movable with the upper portion 607. When the wafer 604 rests on the upper portion 607 (e.g., on the holder 606), the ground pin 612 may contact the bottom surface of the wafer 604 (e.g., the backside film 608).

[0068]

[95] In some embodiments, the actuator may move the top portion. For example, the actuator may include a rotation mechanism (not shown) that rotates the top portion 607 horizontally, for example, through an azimuth angle. In some embodiments, the actuator may include a lifter 608. A first end of the lifter may be fixed to the bottom portion 609, and a second end of the lifter may be movable vertically. For example, the first end of the lifter may be fixed to the bottom portion 609 horizontally (e.g., by penetrating a hole in the bottom portion 609) and movable vertically. The second end of the lifter may be raised or lowered by a movement mechanism, such as an electromagnetic actuator or a hydraulic actuator. The second end of the lifter may penetrate the top portion 607, the holder 606, and the electrode 610, such as by penetrating a hole or groove therein. The second end of the lifter may move beyond the top surface of the holder 606 and contact the bottom surface of the wafer 604. In subsystem 602 , by raising the lifter to a certain height (eg, a few millimeters), the wafer 604 can be lifted off the top surface of the holder 606 and away from the ground pins 612 .

[0069]

[96] In some embodiments, the lifter 608 may be fixed vertically and horizontally and the top portion 607 may be movable vertically. When the top portion 607 is lowered, the ground pins 612 and holder 606 may also be lowered. However, the lifter 608 may support the wafer 604 and the wafer 604 may be fixed vertically. By lowering the top portion 607, the holder 606 may be lowered off the bottom surface of the wafer 604 and the ground pins 612 may be pulled away from the bottom surface.

[0070]

[97] In some embodiments of wafer ground location adjustment, the wafer may be loaded in a predefined position or orientation based on the determined location of the exclusion area. For example, visual inspection, pre-alignment detection, or other sensing operations may be used to determine a reference feature, such as an alignment notch or flat. The location of the exclusion area may then be determined by a known relationship between the reference feature and the exclusion area. Alternatively or additionally, a sensor may be used to directly determine the location of the exclusion area. In some embodiments, a sensor 616 as described above may be used to determine the location of the exclusion area or the reference feature. Based on the determined location of the exclusion area, the wafer may then be loaded in the appropriate position or orientation such that the ground pin 612 is aligned with the desired exclusion area 613.

[0071]

[98] In some embodiments, the controller 615 may adjust the relative displacement between the ground pin 612 and the exclusion area 613 based on the determined position error between the ground pin 612 and the exclusion area 613. For example, the controller 615 may control the sensor 616 to measure a parameter indicative of the relative position or orientation of the ground pin 612 and the exclusion area 613. The controller 615 may further retrieve a target adjustment value 614 (e.g., a target position or rotation angle value). The controller 615 may compare between the target position or angle and the current position or angle, such as by determining an angle difference between the target position or angle and the current position or angle. The controller 615 may then control the various actuators discussed above to adjust the ground location. In some embodiments, the controller 615 may store computer-readable instructions in an accessible memory, such as a software module, and execute such instructions to perform the operations described above. Further operational details can be found in International Publication No. WO 2021 / 037827, which is incorporated herein in its entirety.

[0072]

[99] The exclusion areas 613 may be sized to facilitate and stabilize electrical contact between the ground pins 612 and the wafer 604. The exclusion areas 613 may have a size expressed as a percentage of the total area of ​​the wafer 604, or relative to the ground pins 612 or other elements. For example, each of the exclusion areas 613 may have a size at least as large as a cross-sectional contact area of ​​each of the ground pins 612. The exclusion areas 613 may have a size large enough to account for alignment errors between the ground pins and the centroid of the exclusion area. In some embodiments, each of the exclusion areas 613 may have an area at least 1, 1.5, 2, 3, 5, 10, or 20 times the cross-sectional contact area of ​​the corresponding ground pin 612. The exclusion areas may have an area of, for example, 0.04 to 0.06 mm. 2 In some embodiments, each of the exclusion areas 613 is at least 0.01, 0.1, 0.5, 1, 1.5, 2, 3, or 5 mm 2The area may be greater than or equal to 100 mm.

[0073]

[0100] In some embodiments, the dimensions of the exclusion area may be designed according to a given positioning accuracy of the ground pin relative to the exclusion area. For example, if the positioning accuracy of the center of the ground pin relative to the center of the exclusion area is ±90 μm, the dimensions of the exclusion area may be equal to the width of the ground pin plus 180 μm. Alternatively, a larger tolerance may be added to account for unexpected errors or other issues. For example, the dimensions of the exclusion area having the same conditions as above may be designed with a positioning tolerance of, for example, ±250 μm. In this case, the dimensions of the exclusion area may be equal to the width of the ground pin plus 500 μm.

[0074]

[0101] The size of the exclusion area may also depend on the radial position on the wafer due to the limits of rotational positioning accuracy. As seen in FIG. 6D, the underside of the wafer 604 has two circular exclusion areas: an inner exclusion area 613i located near the center of the wafer 604, and an outer exclusion area 613o located near the periphery. For a given exclusion area size, the angular range θ1 of the inner exclusion area 613i is larger than the angular range θ2 of the outer exclusion area 613o. Thus, as the location of the exclusion area approaches the wafer edge, the positioning tolerances may become tighter in the circumferential direction (as seen in the middle row of FIG. 6D) or the size may become larger (as seen in the dashed lines in the lower row). However, because the exclusion area may be formed during the film formation process, there is a great deal of design flexibility that beneficially allows the use of peripheral exclusion areas.

[0075]

[0102] In some embodiments, the exclusion area may have a size in a first direction that is different from the size in a second direction. For example, the first direction may be a radial direction on the wafer surface and the second direction may be a circumferential direction on the wafer surface. The size in the first direction may be at least 0.1, 0.5, 1, 1.5, 2, 3, or 5 mm or more. The size in the second direction may be larger than the size in the first direction. In some embodiments, the size in the second direction may be 2, 5, 10, or 50 times the size in the first direction. The size in the second direction may surround the entire wafer. Alternatively, the size in the second direction may be the same as or smaller than the size in the first direction.

[0076]

[0103] In some embodiments, the ground pins may have pointed, elongated, or domed geometries, among others. In some embodiments, the additional freedom afforded by the custom exclusion area may allow for different pin sizes or geometries than currently used. For example, the exclusion area may be made large enough to accommodate larger ground pins to increase the contact area or to increase stability or durability. Additionally, the ground pins may have different shapes, such as blunt or flattened pillar shapes, to increase the contact surface area between the pins and the wafer while still providing a mechanically stable connection.

[0077]

[0104] 7A-7B show a subsystem 700 and a wafer 704 according to some embodiments of the present disclosure. The subsystem 700 can be a subsystem of any system for wafer grounding (e.g., system 300 of FIG. 3). FIG. 7A illustrates the backside of the wafer 704 in the subsystem 700. A holder 706 supports the wafer 704 and contacts a backside membrane 708 of the wafer 704. The holder 706 can be an electrostatic holder with at least one electrode 710. The ground pins 712 are located in a peripheral region. The peripheral region can be the periphery of the wafer 704. The exclusion area 713 is annular and surrounds the wafer 704 peripherally. In this configuration, the exclusion area 713 can avoid overlay issues, for example, if the exclusion area 713 is located outside the burl region of the wafer table or holder 706. For example, as discussed above with respect to Figure 5, there may be a number of burls B protruding from the wafer table WT forming a flat support surface, and if no exclusion area is provided, holes H may also be formed in the backside membrane to ground the wafer in the region of the burls. Alternatively, even if an annular exclusion area is placed over the burls, the resulting sag of the wafer may be more symmetrical and therefore easier to compensate. In some embodiments, placing the ground pins 712 at the periphery of the wafer 704 may also allow for greater flexibility or simplicity in the design of the holder 706 and electrodes 710.

[0078]

[0105] FIG. 7B illustrates a cross-sectional view of the subsystem 700 taken along line AA in FIG. 7A. The ground pin 712 may be in direct electrical contact with the conductive surface of the wafer 704 at any portion of the annular exclusion area 713 over which it is placed. In this manner, the annular shaped exclusion area 713 allows for greater flexibility. The wafer 704 may be rotated as needed, for example for alignment purposes, after which the wafer 704 may be grounded by deploying the ground pin 712. For example, in some embodiments, it may be desirable to scan the electron beam in a particular direction relative to device features of the wafer during inspection or lithography. It may be desirable to mount the wafer at a chosen angular orientation within the plane of the page in FIG. 7A. In some embodiments, it may be desirable to scan the wafer multiple times using multiple different angular orientations. In FIGS. 7A-7B, the ground pin 712 may contact the conductive surface at the exclusion area 713 regardless of the angular orientation at which the wafer 704 is mounted.

[0079]

[0106] 7A-7B show a single ground pin 712 and a continuous exclusion area 713, it should be understood that other variations are consistent with certain embodiments of the present disclosure. For example, there may be multiple ground pins 712 or multiple discrete exclusion areas 713. The number of ground pins 712 may be less than, more than, or equal to the number of exclusion areas 713. The ground pins 712 may be configured to perform any of the exclusion grounding methods of the present disclosure, piercing method, zapping method, pin impact method, or any other suitable wafer grounding method or combination of wafer grounding methods. The ground pins 712 and holder 706 may accommodate a variety of wafers, including thin and thick backside film wafers, wafers with exclusion areas, and wafers without exclusion areas.

[0080]

[0107] 8A-8B show a subsystem 800 and a wafer 804 according to some embodiments of the present disclosure. The subsystem 800 can be a subsystem of any system for wafer grounding (e.g., system 300 of FIG. 3). FIG. 8A illustrates a backside of a wafer 804 in the subsystem 800. A holder 806 supports the wafer 804 and contacts a backside membrane 808 of the wafer 804. The subsystem 800 includes a plurality of (e.g., three) ground pins 812 spaced apart with equal angular offsets (e.g., offset of 120°) and positioned to contact the periphery of the wafer 804. The wafer 804 includes a plurality of (e.g., six) exclusion areas 813 spaced apart with equal angular offsets (e.g., offset of 60°) corresponding to the offset of the ground pins 812 or a factor thereof (e.g., 2) around the periphery of the wafer 804. Alternatively or additionally, the ground pins 812 may be movable by an actuator to be positioned under the exclusion areas 813. The wafer 804 may be mounted such that the ground pins 812 are positioned under the first set of exclusion areas 813a or the second set of exclusion areas 813b. The exclusion areas may have a circumferential size large enough to accommodate angular adjustment of the wafer 804.

[0081]

[0108] Figure 8B illustrates a cross-sectional view of the subsystem 800 along line BB in Figure 8A. The ground pins 812 can be in direct electrical contact with the conductive surface of the wafer 804 at any exclusion areas 813 located thereon. In this manner, multiple exclusion areas 813 allow for greater flexibility, as discussed above with respect to Figures 7A-7B.

[0082]

[0109] For example, the method may include supporting a wafer on a holder at a first angular orientation, grounding the wafer by contacting a ground pin to the first exclusion area, performing a first charged particle beam process (such as a first SEM inspection) with the wafer in the first angular orientation, supporting the wafer on the holder at a second angular orientation different from the first angular orientation, grounding the wafer by contacting a ground pin to the second exclusion area, and performing a second charged particle beam process (such as a second SEM inspection) with the wafer in the second angular orientation. The first and second exclusion areas may be, for example, first and second portions of a continuous exclusion area (such as 713 as seen in FIG. 7A) or may be discrete first and second exclusion areas (such as 813a and 813b as seen in FIG. 8A).

[0083]

[0110] 9A-9B show further embodiments of a subsystem 900 and a wafer 904 according to some embodiments of the present disclosure. A holder 906 supports the wafer 904 and contacts the backside membrane 908 of the wafer 904. In FIGS. 9A-9B, the exclusion area includes a second material 911 having a higher electrical conductivity than the first material 909 of the backside membrane 908. The second material may include a conductive material such as aluminum, tungsten, gold, copper, or any other metal or conductive material. The second material 911 may partially or completely fill voids in the backside membrane 908. The second material 911 may be substantially flush with the backside membrane 908. The second material 911 may serve to add additional support against bow or warp of the wafer. The second material 911 may increase the flatness of the backside of the wafer 904 compared to other embodiments while still providing a stable electrical connection between the ground pin 912 and the wafer 904.

[0084]

[0111] The first material 909 and the second material 911 of the back membrane can differ in properties other than electrical conductivity. For example, the second material 911 can have a lower hardness than the first material 909 of the back membrane 908. The back membrane 908 can be configured such that the ground pin 912 can penetrate the second material 911 more easily than the first material 909.

[0085]

[0112] The configuration of the exclusion areas is not limited to those shown in Figures 7-9. Figure 10 shows, by way of example and not by way of limitation, a number of possible exclusion areas on wafers (a)-(f). In general, the exclusion areas may vary in number, size, shape, area, or any similar parameter, as desired. The exclusion areas may have at least one of annular, arcuate, rectangular, and circular shapes. The exclusion areas may be located in a central region, a peripheral region, or an intermediate region, or a combination of such regions. The exclusion areas may include voids entirely devoid of backside film material, regions where the backside film is relatively thinner than the remainder of the backside film layer, or regions including a second material having a higher electrical conductivity (or some other property) than the first backside film material. Although the configuration of Figure 10 is symmetrical, the exclusion areas need not be configured with rotational or mirror symmetry. In some embodiments, a single exclusion area may be located, for example, on the periphery of the wafer.

[0086]

[0113] FIG. 11A shows a processing chamber 1100 for forming a backside film on a wafer 1104 in a comparative embodiment. The processing chamber may include a suspension unit 1150 for suspending the wafer 1104 above a processing unit 1160 to expose the backside of the wafer 1104 in a processing region to a processing material 1170. The processing material 1170 may include, for example, a process gas, a target material, a chemical precursor, a plasma, or a combination of such processing materials, depending on the nature of the film formation process. The suspension unit 1150 includes one or more support members 1152 for supporting the backside of the wafer 1104 at one or more points. The comparative embodiment is not designed to form an exclusion area for grounding the wafer 1104 in a subsequent SEM inspection process or other semiconductor manufacturing process. The support members 1152 have narrow contacts with the backside of the wafer 1104 to suspend the wafer 1104 while allowing the backside film 1308 to be formed on substantially the entire backside.

[0087]

[0114] The processing chamber 1100 may be configured to perform any film formation process known in semiconductor manufacturing. By way of example and not limitation, the film formation process may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (ALD), sputtering, passivation, or any process for depositing, coating, or growing a backside film on the wafer 1104. In some embodiments, the processing chamber 1100 is a PECVD chamber. The processing unit 1160 may include a showerhead electrode electrically connected to a radio frequency power source (not shown) and configured to introduce a process gas 1170 including a precursor of the backside film material. The wafer 1104 is connected to a grounded electrode (not shown). The electrodes and radio frequency power source ionize precursors in the process gas 1170 to form a plasma, and some reactants of the plasma deposit as a backside film 1108 .

[0088]

[0115] FIG. 11B shows a view of the backside of the wafer 1104 processed in the processing chamber of FIG. 11A. As shown in FIG. 11B, the wafer backside film 1108 formed in the processing chamber 1100 includes a plurality of film reduction points 1114. The film reduction points are locations where the formation of the backside film 1108 is prevented to some extent by the support members 1152. The film reduction points 1114 may be considered partial exclusion areas that are smaller than ideal size or do not fully expose the conductive surface. For example, the film reduction points may have a size of, for example, 0.1 to 1.5 mm in the radial direction.

[0089]

[0116] Comparative embodiments may be designed with the goal of preventing as many film reduction points 1114 as possible, which may not fully expose the conductive surface of the wafer 1104, or may not expose a sufficient area of ​​the conductive surface for optimal grounding by the exclusion area method. Nevertheless, in some embodiments, the grounding method may include contacting the film reduction points 1114 with a ground pin (such as the peripheral ground pins 712-912 of FIGS. 7A-9B). The grounding method may include grounding the wafer 1104 using a piercing method, a zapping method, a pin impact method, or any other suitable wafer grounding method, or a combination of wafer grounding methods.

[0090]

[0117] In comparison with the comparative embodiment, the exclusion grounding method may be designed for the purpose of forming an exclusion area to be used in the grounding process. The exclusion grounding method may include determining the location of the exclusion area. The determination of the location of the exclusion area may be based on information obtained in the determination process or may be based on known information.

[0091]

[0118] The information obtained in the determination process may include, for example, optical inspection information or visual inspection information. For example, a dedicated inspection may be performed to find the exclusion area on the backside of the wafer. The inspection may be a visual inspection performed by an operator. The inspection may be an optical inspection. The optical inspection may distinguish the exclusion area from its surroundings by detecting differences in the optical properties (e.g., reflective, refractive, absorbing, filtering, or other properties) of the backside of the wafer relative to the ambient or projected light. The inspection may be an optical inspection to distinguish the exclusion area from its surroundings by detecting differences in the optical properties (e.g., reflective, refractive, or filtering properties) of the ambient or projected light passing through the wafer. Alternatively, data from another inspection may be utilized to determine the location of the exclusion area. The inspection may determine the location, shape, size, or type (e.g., voids, thin film areas, alternative materials, etc.) of the exclusion area. The information obtained in the determination process may include, for example, an electrical inspection. For example, the electrical inspection may utilize a sensor 316 to detect or measure an electrical property 320, as discussed above with respect to Figure 3. The results of measuring the electrical property at different points on the wafer surface may be used to determine the location, shape, size, or type of the exclusion area.

[0092]

[0119] The known information may include the location, shape, size, or type of the exclusion area provided by the wafer manufacturer or supplier. For example, the location of the center of the exclusion area may be provided in polar coordinates relative to a fiducial mark such as a pre-alignment notch. The location may be given with respect to an overlapping feature of the location, for example, a band surrounding the pre-alignment notch with a thickness (e.g., 0.01, 0.1, 0.5, 1, 1.5, 2, 3, or 5 mm), or an annular ring extending radially inward from the edge by a distance (e.g., 0.01, 0.1, 0.5, 1, 1.5, 2, 3, or 5 mm). The known information may include information obtained as discussed above, where the obtained information is obtained from different wafers.

[0093]

[0120] FIG. 12A illustrates a processing chamber 1200 according to some embodiments of the present disclosure. The processing chamber 1200 may be similar to the processing chamber 1100, except as described herein. The suspension unit 1250 includes one or more support members 1253 configured to cover one or more exclusion areas 1213 (see FIG. 12B). The support members 1253 may be configured to support the wafer 1204 during a film formation process. At the same time, the support members 1253 may be configured as an exclusion mask having a size and shape configured to prevent film formation in the exclusion areas 1213. The support members 1253 may have a size, shape, and configuration corresponding to any of the exclusion areas disclosed or contemplated herein, including the exclusion areas 613, 713, 813, 913, and 1013. For example, the support members 1253 may take the form of an arc or annular shape around the backside of the wafer 1204, or any other shape necessary to create the desired exclusion area.

[0094]

[0121] 12B illustrates a wafer 1204 formed with exclusion areas according to some embodiments of the present disclosure. The wafer 1204 has a backside film 1208 formed in a process chamber 1200. The support members 1253 contacted the backside of the wafer 1204 at the exclusion areas 1213 during formation of the backside film 1208, thereby inhibiting or eliminating film formation at the exclusion areas 1213. Thus, a thick backside film can be formed providing any desired number, size, shape, location, and orientation of the exclusion areas 1213. For example, the exclusion areas 1213 can take the form disclosed with respect to FIG. 10, or any other desired form.

[0095]

[0122] FIG. 12C illustrates a processing chamber 1201 according to some embodiments of the present disclosure. The processing chamber 1201 may be similar to, for example, the processing chamber 1200 of FIG. 12A or the processing chamber 1100 of FIG. 11A, except as described below. The suspension unit 1250 includes a proximity-type exclusion mask 1254 near the backside of the wafer 1204. In some embodiments, the exclusion mask 1254 does not contact the wafer 1204. In some embodiments, the exclusion mask 1254 touches the wafer 1204 but does not substantially support the weight of the wafer 1204. Support is provided by another mechanism, such as one or more support members (not shown). The support members may be the same as or similar to the support members 1152 of FIG. 11A or the support members 1253 of FIG. 12A. Alternatively, the wafer 1204 may be held by a gripping or chucking device at its top surface. In non-contact embodiments such as seen in FIG. 12C, the gap 1255 may be small enough that the exclusion mask 1254 inhibits or eliminates film formation in the exclusion area. The required or optimal gap distance may vary depending on the particular film formation method selected. By way of example and not limitation, in some embodiments, the gap 1255 distance may be 1-10 μm, 5-50 μm, 10-100 μm, 50 μm-1 mm, or 500 μm-10 mm. Although the exclusion mask 1254 is depicted as a rigid object, it may alternatively take any form that inhibits or prevents film formation in the exclusion area 1213. For example, the exclusion mask 1254 may be a removable film or treatment applied to the wafer 1204 prior to the backside film formation process in the processing chamber 1200 or 1201. Alternatively or additionally, the exclusion area 1213 may be formed by a post-deposition process such as an etching process. The exclusion area formed by the chamber in FIG. 12C may have the same or similar design as discussed above with respect to FIGS. 10 and 12B, or may take any other desired form.

[0096]

[0123] In addition to the various exclusion areas enabled by the present disclosure, the backside membrane may also be advantageously thickened. In comparative embodiments, the membrane thickness may be limited by the need to ground the wafer by piercing, zapping, or pin impact. The difficulty of grounding the wafer through a thick insulating layer may be overcome, so the thickness of the backside membrane may be increased. In some embodiments of the present disclosure, the wafer may have a backside membrane having a thickness of, for example, 1-2.2 μm, 2-5 μm, 5-10 μm, or 10-50 μm. The increased thickness may provide additional structural rigidity to prevent bowing or warping of the wafer while maintaining stable electrical contact with the conductive surface of the wafer during the wafer grounding process. The increased thickness may also serve to compensate for any loss of rigidity caused by the lack of material in the exclusion area. Thus, a thicker backside membrane may allow more design flexibility with respect to the exclusion area, for example, allowing a wider range of size and location options.

[0097]

[0124] FIG. 13A shows a processing chamber 1300 for forming a backside film on a wafer 1304 in a comparative embodiment. The processing chamber 1300 may include a table 1350 for holding the wafer 1304 under a processing unit 1360 to expose the upward facing backside of the wafer 1304 to a processing material 1370. The table 1450 may be, for example, a susceptor, a burl plate, or other device for supporting the wafer from below. The table 1350 includes a support surface for holding the wafer 1304 with its backside facing up. The comparative embodiment is not designed to form an exclusion area for grounding the wafer 1304 during a subsequent SEM inspection process or other semiconductor manufacturing process. The table 1350 does not substantially block a portion of the upward facing backside of the wafer 1304. Thus, substantially the entire backside can be coated with the backside film 1308. The membrane can be, for example, silicon dioxide, silicon nitride, other oxides, nitrides, carbides, or other suitable membrane materials to provide structural support (e.g., support to prevent bowing or warping of the wafer).

[0098]

[0125] The processing chamber 1300 may be configured to perform any film formation process known in the semiconductor manufacturing industry. By way of example and not limitation, the film formation process may include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma chemical vapor deposition (HDPCVD), physical vapor deposition (PVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (ALD), sputtering, passivation, or any process for depositing, coating, or growing a backside film on the wafer 1304. In some embodiments, the processing chamber 1300 is a PECVD chamber. The processing unit 1360 may include a showerhead electrode electrically connected to a radio frequency power source (not shown) and configured to introduce a process gas 1370 including a precursor of the backside film material. The wafer 1304 is connected to a grounded electrode (not shown). The electrodes and radio frequency power source ionize precursors in the process gas 1370 to form a plasma, and some reactants of the plasma deposit as a backside film 1308 .

[0099]

[0126] Figure 13B shows a view of the backside of a wafer 1304 that has been processed in the processing chamber of Figure 13A. As can be seen in Figure 13B, the wafer backside film 1308 formed in the processing chamber 1300 covers substantially the entire backside of the wafer 1304. There are no film reduction points or exclusion areas.

[0100]

[0127] FIG. 14A illustrates a processing chamber 1400 according to some embodiments of the present disclosure. The processing chamber 1400 may be similar to the processing chamber 1300, except as described herein. The table 1450 includes one or more exclusion masks 1454 configured to cover one or more exclusion areas 1413 (see FIG. 14B). The exclusion masks 1454 may have a size, shape, and configuration corresponding to any of the exclusion areas disclosed or contemplated herein, including exclusion areas 613, 713, 813, 913, and 1013. For example, the exclusion masks 1454 may have an arc or annular shape disposed around the backside of the wafer 1404, or any other shape necessary to create the desired exclusion area. The exclusion masks 1454 may be mounted on the table 1450 or placed directly on the wafer 1404. The latter is particularly advantageous when forming the exclusion area 1413 in the central region of the wafer 1404. The exclusion mask 1454 may be in contact with the upward facing backside of the wafer 1404 or may be a proximity type exclusion mask separated from the front side by a gap 1455. In a non-contact embodiment as seen in FIG. 14A, the gap 1455 may be small enough that the exclusion mask 1454 inhibits or eliminates film formation in the exclusion area 1413. The required or optimal gap distance may vary depending on the particular film formation method selected. By way of example and not by way of limitation, in some embodiments, the gap 1455 distance may be 1-10 μm, 5-50 μm, 10-100 μm, 50 μm-1 mm, or 500 μm-10 mm. Although the exclusion mask 1454 is depicted as a rigid object, it may alternatively take any form that inhibits or prevents film formation in the exclusion area 1413. For example, the exclusion mask 1454 may be a removable film or other treatment applied to the wafer 1404 prior to the backside film formation process in the processing chamber 1400. Alternatively or additionally, the exclusion areas 1413 may be formed by a post-deposition process, such as an etching process.

[0101]

[0128] 14B illustrates a wafer 1404 formed with exclusion areas according to some embodiments of the present disclosure. The wafer 1404 has a backside film 1408 formed in a process chamber 1400. An exclusion mask 1454 contacts or is in intimate contact with the backside of the wafer 1404 during formation of the backside film 1408, thereby inhibiting or eliminating film formation in the exclusion areas 1413. Thus, a thick backside film may be formed providing any desired number, size, shape, location, and orientation of the exclusion areas 1413.

[0102]

[0129] FIG. 15 illustrates a method 1500 for forming a backside film having an exclusion area according to an embodiment of the present disclosure. In step 1502, a wafer is loaded into a processing chamber. The processing chamber may be any suitable processing chamber, such as processing chambers 1200, 1201, and 1400 of FIG. 12A, FIG. 12C, or FIG. 14A. In step 1504, an area of ​​the wafer is masked with an exclusion mask according to the desired exclusion area, as discussed above. The exclusion mask may be any of elements 1253, 1254, or 1454 of FIG. 12A, FIG. 12C, or FIG. 14A. The exclusion mask may be a removable film or other treatment applied to the wafer, as discussed above. In some embodiments, the step of masking the wafer is performed simultaneously with, before, or after loading the wafer into the processing chamber. Step 1504 may include selecting a location for forming the exclusion area. The location for forming the exclusion area may be predetermined. In some embodiments, a location where an already formed exclusion area is located may be determined. The selection of the location of the exclusion area may be based on the alignment of the wafer, the scan pattern, or characteristics related to IC features to be formed on the other side of the wafer. In step 1506, a backside film is formed on the wafer according to a film formation process. In step 1508, the wafer is unloaded. In step 1510, the exclusion mask is removed from the wafer to expose the exclusion areas in the backside film. In some embodiments, the step of unloading the wafer occurs simultaneously with, before, or after the step of removing the exclusion mask.

[0103]

[0130] 16 illustrates a method 1600 for grounding a wafer held in a wafer holder according to some embodiments of the present disclosure. The wafer may have a coating on a surface of the wafer. The wafer holder may be part of an e-beam tool, such as shown in FIG. 2, a wafer grounding system, such as shown in FIG. 3, or a wafer grounding subsystem, such as shown in FIGS. 6A-9B.

[0104]

[0131] In step 1602, the location of the exclusion area of ​​the coating is determined. Determining the location of the exclusion area may be based on information obtained in a determination process or based on known information. Information obtained in the determination process may include, for example, optical inspection information or visual inspection information, as discussed above. Information obtained in the determination process may include hardness testing, thickness measurement, or any measurement process that determines a characteristic associated with the wafer or the exclusion area. In some embodiments, information obtained in the determination process may be based on electrical inspection. For example, electrical inspection may utilize sensor 316 to detect or measure electrical characteristic 320, as discussed above with respect to FIG. 3. Known information includes the location, shape, size, or type of the exclusion area provided by a wafer manufacturer or supplier. Known information includes a wafer map. Known information may include information obtained as discussed above, where the information obtained is obtained from a different wafer.

[0105]

[0132] In some embodiments, step 1602 may include, for example, detecting a reference feature and determining a location of the exclusion area based on a predetermined relationship between the reference feature and the exclusion area. For example, in step 1602, a pre-alignment detection system may be used to determine the location or orientation of an alignment notch or flat, a wafer edge, a fiducial, or a reference feature. Alternatively or additionally, the reference feature may be determined by manual inspection by an operator.

[0106]

[0133] In some embodiments, step 1602 may include, for example, directly detecting the location of the exclusion area. For example, the location of the exclusion area may be determined by optical inspection, a z-height sensor, or other profilometer to identify the exclusion area 613 by the backside topography of the wafer. Detection may be optical, capacitive, ultrasonic, or any other configuration to achieve the desired detection, as discussed above.

[0107]

[0134] In step 1604, a position or orientation of the wafer or the first electrical contact is adjusted so that the exclusion area is aligned with the first electrical contact. The first electrical contact may be a ground pin. The adjustment may be made before, during, or after loading the wafer onto the support. The adjustment of the position or orientation may be based on the determined location of the exclusion area relative to the electrical contact. For example, the wafer may be rotated or translated so that the exclusion area is positioned above the first electrical contact. Alternatively, the first electrical contact may be actuated so that it is positioned below the exclusion area. The adjustment may include a combination of movement of both the wafer and the first electrical contact.

[0108]

[0135] In some embodiments, to improve the positional accuracy of the ground pin contacting the exclusion area of ​​the wafer, the ground pin may include a pin body with two tips extending from the pin body (a "dual-tip" ground pin). The position of the dual-tip ground pin (e.g., dual-tip ground pin 2012 in FIG. 20, dual-tip ground pin 2112 in FIG. 21) may be flexibly adjusted to increase the chance of the ground pin contacting the exclusion area of ​​the wafer.

[0109]

[0136] In step 1606, a first electrical contact is contacted to the surface of the wafer. The first electrical contact may be actuated in a height direction such that the first electrical contact establishes sufficient electrical contact with the wafer to achieve a bias or ground operation. Contact may include any of the exclusion grounding methods of the present disclosure, piercing, zapping, pin impact, or any other suitable wafer grounding method or combination of wafer grounding methods.

[0110]

[0137] In step 1608, a charged particle beam process is performed while the wafer is biased or grounded. Charged particle beams can include wafer processing (e.g., electron beam direct write lithography systems), process monitoring (e.g., critical dimension scanning electron microscopes (CD-SEMs)), wafer inspection (e.g., electron beam inspection systems), defect analysis (e.g., defect review SEMs (DR-SEMs) and focused ion beam systems (FIBs)), or any other wafer processing operation in which it is advantageous to control the electrical properties of the wafer.

[0111]

[0138] 17 shows an example exclusion area 1713 of a wafer along with the location of a single-tip ground pin. The exclusion area 1713 may be an area of ​​the wafer that is free of backside film, thereby providing an area that facilitates the ground pin making stable electrical contact with the conductive surface of the wafer. The exclusion area 1713 may have a width 1713w.

[0112]

[0139] A typical ground pin has a single tip that contacts the wafer or the backside film of the wafer. Because the exclusion area of ​​the wafer may be small, the position accuracy of the single-tip ground pin that contacts the exclusion area may be low. For example, the position 1712a of the single-tip ground pin can only be adjusted by half the width 1713w of the exclusion area 1713. That is, if the single-tip ground pin is at the position 1712a, the single-tip ground pin (or the wafer) can be adjusted by the width 1713bw so that the ground pin is at the position 1712b, or the width 1713cw so that the ground pin is at the position 1712c. The widths 1713bw and 1713cw can each be half the width 1713w. However, the position of the single-tip ground pin can only be adjusted to one of the positions 1712b or 1712c, but not both positions. That is, the location error tolerance of the single-tip ground pin can only be half the width 1713w.

[0113]

[0140] Thus, if a single-tip ground pin is placed over a coated area (e.g., an area of ​​a wafer with a backside film), the single-tip ground pin may not be able to adjust itself to contact the exclusion area 1713. Thus, the single-tip ground pin may not be able to ground the wafer.

[0114]

[0141] Although FIG. 17 depicts locations 1712a, 1712b, and 1712c and widths 1713w, 1713bw, and 1713c, it should be understood that these elements may not actually be included on the wafer.

[0115]

[0142] FIG. 18 illustrates a wafer (e.g., wafer 203 of FIG. 2, wafer 304 of FIG. 3, wafer 404 of FIGS. 4A-4D, wafer 604 of FIGS. 6A-6D, wafer 704 of FIGS. 7A-7B, wafer 804 of FIGS. 8A-8B, wafer 904 of FIGS. 9A-9B, wafers (a)-(f) of FIG. 10, wafer 1204 of FIGS. 12A and 12C, wafer 1204 of FIGS. 14A-14C, wafer 1204 of FIGS. 15A-15C, wafer 1204 of FIGS. 16A-16C, wafer 1204 of FIGS. 17A-17C, wafer 1204 of FIGS. 18A-18C, wafer 1204 of FIGS. 19A-19C, wafer 1304 of FIGS. 20A-20C, wafer 1404 of FIGS. 21A-21C, wafer 1404 of FIGS. 22A-22C, wafer 1404 of FIGS. 23A-23C, wafer 1404 of FIGS. 24A-24C, wafer 1504 of FIGS. 25A-25C, wafer 1604 of FIGS. 26A-26C, wafer 1704 of FIGS. 27A-27C, wafer 1804 of FIGS. 28A-28C, wafer 1904 of FIGS. 29A-29C, wafer 1904 of FIGS. 30A-30C, wafer 1904 of FIGS. 31A-31C, wafer 1904 of FIGS. 32A-32C, wafer 1904 of FIGS. 33A-33C, wafer 190 20) (e.g., exclusion area 613 of FIGS. 6A-6C, inner exclusion area 613i of FIG. 6D, outer exclusion area 613o of FIG. 6D, exclusion area 713 of FIG. 7A, exclusion areas 813a-813b of FIG. 8A, exclusion area 1013 of FIG. 10, exclusion area 1213 of FIG. 12B, exclusion area 1413 of FIG. 14B, exclusion area 2013 of FIG. 20). Exclusion area 1813 may have a width 1813w.

[0116]

[0143] In some embodiments, to improve the positional accuracy of the ground pins contacting the exclusion area of ​​the wafer, each ground pin may include a pin body with two tips extending from the pin body (a "dual-tipped" ground pin). The distance between the first and second tips of the ground pin may be substantially equal to the width 1813w of the exclusion area 1813 (e.g., 0.01, 0.1, 0.5, 1, 1.5, 2, 3, or 5 mm or more) to improve the positional accuracy of the ground pins contacting the exclusion area 1813 of the wafer. The position 1812a of the dual-tipped ground pin may be flexibly adjusted to increase the chances that the ground pins contact the exclusion area of ​​the wafer (i.e., the dual-tipped ground pin may increase the positional accuracy).

[0117]

[0144] For example, a dual-tip ground pin may have a first tip at location 1802a and a second tip at location 1802b. The location 1812a of the dual-tip ground pin may be adjusted (e.g., linearly in the X or Y direction) by the width 1813a of the exclusion area 1813 (e.g., by adjusting the dual-tip ground pin, the wafer, or any combination thereof). In some embodiments, the location 1812a of the dual-tip ground pin or the wafer may be adjusted by rotating the dual-tip ground pin (e.g., in an angular direction parallel or perpendicular to the surface of the wafer). Thus, if the dual-tip ground pin is at location 1812a, it may be adjusted by width 1813w to be at location 1812b or by width 1813w to be at location 1812c. That is, the location error tolerance of the dual-tip ground pin may be twice the width 1813.

[0118]

[0145] Thus, when the dual-tip ground pin is placed over a coated area (e.g., an area of ​​a wafer with a backside film), the dual-tip ground pin or the wafer can be adjusted so that at least one pin of the dual-tip ground pin contacts the exclusion area 1813 and grounds the wafer.

[0119]

[0146] In some embodiments, the width of the exclusion area can be along the perimeter / periphery of the wafer (i.e., the width can extend in the same direction as the perimeter / periphery of the wafer). In some embodiments, the width of the exclusion area can extend toward the center of the wafer or toward any direction of the wafer. That is, the direction and orientation of the width of the exclusion area is not limited.

[0120]

[0147] Although locations 1812a, 1812b, 1812c, 1802a, and 1802b and width 1813w are depicted in FIG. 18, it should be understood that these elements may not actually be included on the wafer.

[0121]

[0148] FIG. 19 illustrates a wafer (e.g., wafer 203 of FIG. 2, wafer 304 of FIG. 3, wafer 404 of FIGS. 4A-4D, wafer 604 of FIGS. 6A-6D, wafer 704 of FIGS. 7A-7B, wafer 804 of FIGS. 8A-8B, wafer 904 of FIGS. 9A-9B, wafers (a)-(f) of FIG. 10, wafers (b)-(c) of FIGS. 12A and 12C) along with the location of dual tipped ground pins, according to some embodiments of the present disclosure. 12B, and 14B) of the wafer 1404 (e.g., the exclusion area 613 in FIGS. 6A-6C, the inner exclusion area 613i in FIG. 6D, the outer exclusion area 613o in FIG. 6D, the exclusion area 713 in FIG. 7A, the exclusion areas 813a-813b in FIG. 8A, the exclusion area 1013 in FIG. 10, the exclusion area 1213 in FIG. 12B, and the exclusion area 1413 in FIG. 14B).

[0122]

[0149] In some embodiments, as described above, the distance between the first and second tips of the dual-tip ground pin may be substantially equal to the width of the exclusion area (e.g., exclusion areas 1913 and 1915) to improve the positional accuracy of the ground pin contacting the wafer exclusion areas 1913 and 1915. The position 1912 of the dual-tip ground pin may be flexibly adjusted to increase the chance of the ground pin contacting the wafer exclusion area (i.e., the dual-tip ground pin may increase the positional accuracy).

[0123]

[0150] For example, the position 1912 of the dual-tip ground pin may be adjusted (e.g., linearly in the X or Y direction) by the width of the exclusion area 1913 (e.g., by adjusting the dual-tip ground pin, the wafer, or any combination thereof). In some embodiments, the position 1912 of the dual-tip ground pin or the wafer may be adjusted by rotating the dual-tip ground pin (e.g., in an angular direction parallel or perpendicular to the surface of the wafer). Thus, when the dual-tip ground pin is at the position 1912, the dual-tip ground pin may be adjusted by the width of the exclusion area 1913 to cover the tolerance area 1912t, or may be adjusted by the width of the exclusion area 1913 to cover the exclusion area 1913. That is, the location error tolerance of the dual-tip ground pin may be width 1913w2, which is twice the width of the exclusion area 1913.

[0124]

[0151] Similarly, the position 1914 of the second dual-tip ground pin may be adjusted (e.g., linearly in the X or Y direction) by the width of the exclusion area 1915 (e.g., by adjusting the dual-tip ground pin, the wafer, or any combination thereof). In some embodiments, the position 1914 of the dual-tip ground pin or the wafer may be adjusted by rotating the dual-tip ground pin (e.g., in an angular direction parallel or perpendicular to the surface of the wafer). Thus, when the dual-tip ground pin is at position 1914, the dual-tip ground pin may be adjusted by the width of the exclusion area 1915 to cover the tolerance area 1914t, or may be adjusted by the width of the exclusion area 1915 to cover the exclusion area 1915. That is, the location error tolerance of the dual-tip ground pin may be width 1915w2, which is twice the width of the exclusion area 1915.

[0125]

[0152] In some embodiments, the width of the exclusion area can be along the perimeter / periphery of the wafer (i.e., the width can extend in the same direction as the perimeter / periphery of the wafer). In some embodiments, the width of the exclusion area can extend toward the center of the wafer or toward any direction of the wafer. That is, the direction and orientation of the width of the exclusion area is not limited.

[0126]

[0153] Although FIG. 19 depicts locations 1912 and 1914, tolerance areas 1912t and 1914t, and widths 1913w2 and 1915w2, it should be understood that these elements may not actually be included on the wafer.

[0127]

[0154] FIG. 20 illustrates an exemplary wafer 200 having a backside membrane 2008 (backside membrane 308 of FIG. 3, backside membrane 408 of FIGS. 4A-4D, backside membrane 608 of FIGS. 6A-6C, backside membrane 708 of FIG. 7B, backside membrane 808 of FIG. 8B, backside membrane 908 of FIGS. 9A-9B, backside membrane 1208 of FIG. 12B, backside membrane 1408 of FIG. 14B) in contact with a dual-tip ground pin 2012, in accordance with some embodiments of the present disclosure. 4 (e.g., wafer 203 of FIG. 2, wafer 304 of FIG. 3, wafer 404 of FIGS. 4A-4D, wafer 604 of FIGS. 6A-6D, wafer 704 of FIGS. 7A-7B, wafer 804 of FIGS. 8A-8B, wafer 904 of FIGS. 9A-9B, wafers (a)-(f) of FIG. 10, wafer 1204 of FIGS. 12A and 12C, and wafer 1404 of FIG. 14A). Dual tipped ground pin 2012 can include a first tip 2012a and a second tip 2012b each extending from a body of dual tipped ground pin 2012.

[0128]

[0155] In some embodiments, the wafer 2004 may include an exclusion area 2013 (e.g., exclusion area 613 in Figures 6A-6C, inner exclusion area 613i in Figure 6D, outer exclusion area 613o in Figure 6D, exclusion area 713 in Figure 7A, exclusion areas 813a-813b in Figure 8A, exclusion area 1013 in Figure 10, exclusion area 1213 in Figure 12B, exclusion area 1413 in Figure 14B).

[0129]

[0156] In some embodiments, as described above, the distance between the first tip 2012a and the second tip 2012b may be substantially equal to the width of the exclusion area 2013 (e.g., 1813w in FIG. 18) to improve the positional accuracy of the dual tipped ground pin 2012 contacting the exclusion area 2013 of the wafer 2004. The position of the dual tipped ground pin 2012 (e.g., position 1812a in FIG. 18, position 1912 in FIG. 19, position 1914 in FIG. 19) may be flexibly adjusted to increase the chance of the dual tipped ground pin 2012 contacting the exclusion area 2013 of the wafer 2004 (i.e., the dual tipped ground pin may have increased positional accuracy).

[0130]

[0157] For example, as shown in Fig. 20(a), the second tip 2012b of the dual tip ground pin 2012 may contact the backside film 2008. However, as shown in Fig. 20(b), the dual tip ground pin 2012 may be flexibly tilted such that the first tip 2012a of the dual tip ground pin 2012 contacts the exclusion area 2013, thereby grounding the wafer 2004.

[0131]

[0158] Although a single dual-tip ground pin 2012 is shown in FIG. 20, it should be understood that multiple dual-tip ground pins may be included, with each dual-tip ground pin corresponding to an exclusion area 2013 of the wafer 2004.

[0132]

[0159] In some embodiments, the width of the exclusion area can be along the perimeter / periphery of the wafer (i.e., the width can extend in the same direction as the perimeter / periphery of the wafer). In some embodiments, the width of the exclusion area can extend toward the center of the wafer or toward any direction of the wafer. That is, the direction and orientation of the width of the exclusion area is not limited.

[0133]

[0160] 21 illustrates a cross-sectional view of an exemplary dual-tip ground pin 2112 (e.g., dual-tip ground pin 2012 of FIG. 20), according to some embodiments of the present disclosure. The dual-tip ground pin 2112 can have a first tip 2112a (e.g., first tip 2012a of FIG. 20) and a second tip 2112b (e.g., second tip 2012b of FIG. 20), each extending from a body of the dual-tip ground pin 2112.

[0134]

[0161] Figure 22 illustrates an exemplary wafer holder 2206 (e.g., wafer holder 202 of Figure 2, electrostatic holder 306 of Figure 3, holder 706 of Figures 7A-7B, holder 806 of Figures 8A-8B, holder 906 of Figures 9A-9B) having a ground pin 2212 according to some embodiments of the present disclosure. As shown in Figures 22(a) and (b), wafer holder 2206 may include ground pin 2212, which may include a spring structure. The spring structure of the ground pin 2212 is connected to a wafer 2204 (e.g., wafer 203 in FIG. 2, wafer 304 in FIG. 3, wafer 304 in FIG. 3, wafer 2004 in FIG. 20) having a back surface film 2008 (back surface film 308 in FIG. 3, back surface film 408 in FIG. 4A-FIG. 4D, back surface film 608 in FIG. 6A-FIG. 6C, back surface film 708 in FIG. 7B, back surface film 808 in FIG. 8B, back surface film 908 in FIG. 9A-FIG. 9B, back surface film 1208 in FIG. 12B, back surface film 1408 in FIG. 14B, wafer 2004 in FIG. 20). The wafer may be configured to suppress wafer warping or wafer bowing by reducing the force applied to wafer 404 of Figures 4A-4D, wafer 604 of Figures 6A-6D, wafer 704 of Figures 7A-7B, wafer 804 of Figures 8A-8B, wafer 904 of Figures 9A-9B, wafers (a)-(f) of Figure 10, wafer 1204 of Figures 12A and 12C, and wafer 1404 of Figure 14A). As shown in diagram (b) of FIG. 22, the ground pin 2212 may contact the wafer 2204 in an exclusion area of ​​the wafer 2204 (e.g., exclusion area 613 in FIGS. 6A-6C, inner exclusion area 613i in FIG. 6D, outer exclusion area 613o in FIG. 6D, exclusion area 713 in FIG. 7A, exclusion areas 813a-813b in FIG. 8A, exclusion area 1013 in FIG. 10, exclusion area 1213 in FIG. 12B, exclusion area 1413 in FIG. 14B, and exclusion area 2013 in FIG. 20) to ground the wafer 2204.

[0135]

[0162] Although a single ground pin 2212 is shown in FIG. 22, it should be understood that the wafer holder 2206 may include multiple ground pins, each ground pin corresponding to an exclusion area of ​​the wafer 2204 .

[0136]

[0163] A non-transitory computer readable medium may be provided that stores instructions for a processor (e.g., the processor of controller 109 of FIG. 1) to perform image processing, data processing, database management, graphic display, operation of a charged particle beam apparatus or other imaging device, control of wafer grounding, control of wafer grounding position adjustment, or pin impingement method, implementation of the exemplary method of FIGS. 15-16, etc. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid state drives, magnetic tape or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a pattern of holes, RAM, PROMs, and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, cache, registers, any other memory chips or cartridges, and networked versions thereof.

[0137]

[0164] The block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code, including one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the functions shown in the blocks may be performed in a different order than described in the figures. For example, two blocks shown in succession may be executed or performed substantially simultaneously, or the two blocks may be executed in reverse order depending on the related functions, if necessary. Also, some blocks may be omitted. It should also be understood that each block and combination of blocks in the block diagrams may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0138]

[0165] The embodiments may be further described using the following clauses. Article 1. 1. A method for electrically connecting to a wafer, comprising: contacting a first electrical contact with a surface of a wafer, the wafer having a coating thereon; A method comprising: The method wherein the contacting occurs at a first exclusion area of ​​the coating. Article 2. Determining a location of a first exclusion area; adjusting a position of the wafer or the first electrical contact such that the first exclusion area is aligned with the first electrical contact; 2. The method of claim 1, further comprising: Article 3. Adjusting the position of the wafer A wafer holder that holds a wafer is translated. 3. The method according to claim 2, comprising: Article 4. Adjusting the position of the wafer Rotating the wafer holder that holds the wafer 3. The method according to claim 2, comprising: Article 5. Adjusting the position of the wafer unloading the wafer from the first holding position of the wafer holder; reloading the wafer on the wafer holder at a second holding position different from the first holding position; 3. The method according to claim 2, comprising: Article 6. Adjusting the position of the wafer Unloading the wafer from the first holding orientation in the wafer holder; reloading the wafer on the wafer holder into a second holding orientation different from the first holding orientation; 3. The method according to claim 2, comprising: Article 7. Adjusting a position of the first electrical contact Actuating the first electrical contact 3. The method according to claim 2, comprising: Article 8. 2. The method of claim 1, wherein the coating is a backside film configured to inhibit wafer warp or wafer bow. Article 9. 2. The method of claim 1, wherein the exclusion area has a size of at least 1.5 mm in the radial direction of the surface. Article 10. 2. The method of claim 1, wherein the exclusion area has a size that is at least twice the size of a cross-sectional contact area between the first electrical contact and the wafer. Article 11. 2. The method of claim 1, wherein the wafer has a first electrical conductivity and the coating has a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 12. 2. The method of claim 1, wherein the first exclusion area comprises a void in the coating exposing an area on the surface of the wafer. Article 13. 2. The method of claim 1, wherein the coating has a first thickness in the first excluded area and a second thickness in an area adjacent the first excluded area, the second thickness being greater than the first thickness. Article 14. 2. The method of claim 1, wherein the coating has a thickness of at least 1 μm. Article 15. 2. The method of claim 1, wherein the first exclusion area comprises a first material having a first electrical conductivity and the coating comprises a second material having a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 16. 16. The method of claim 15, wherein the first material is substantially coplanar with the second material. Article 17. contacting the second electrical contact with the surface of the wafer; Further comprising: 2. The method of claim 1, wherein the first electrical contact and the second electrical contact contact the wafer simultaneously. Article 18. 18. The method of clause 17, wherein the second electrical contact contacts the wafer in a second exclusion area that is different from the first exclusion area. Article 19. The first exclusion area comprises a first portion and a second portion, and the method further comprises: contacting a first electrical contact with the surface at a first portion; contacting a second electrical contact with the surface at the second portion; 18. The method of claim 17, further comprising: Article 20. 20. The method of claim 19, wherein the first exclusion area has an annular shape. Article 21. 2. The method of claim 1, wherein the first exclusion area has at least one of an annular shape, an arcuate shape, a rectangular shape, or a circular shape. Article 22. 2. The method of claim 1, wherein the surface of the wafer includes a second exclusion area different from the first exclusion area. Article 23. 2. The method of claim 1, wherein the first exclusion area is located on the periphery of the surface. Article 24. moving the first electrical contact away from the first exclusion area; contacting the first exclusion area with a second electrical contact, the second electrical contact being different from the first electrical contact; 2. The method of claim 1, further comprising: Article 25. Performing a charged particle beam process on a wafer Further comprising: 2. The method of claim 1, wherein the first electrical contact contacts the surface of the wafer during a charged particle beam process. Article 26. 26. The method of claim 25, wherein the charged particle beam process is scanning electron microscopy of the wafer. Article 27. Electrically connecting the wafer to a bias supply via the first electrical contact. 2. The method of claim 1, further comprising: Article 28. 13. The method of claim 1, further comprising applying a DC voltage to the wafer through the first electrical contact. Article 29. 13. The method of claim 1, further comprising removing charge from the wafer by the first electrical contact. Article 30. 30. The method of claim 29, wherein removing charge from the wafer renders the wafer electrically neutral. Article 31. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method, the method comprising: contacting a first electrical contact with a surface of a wafer, the wafer having a coating thereon; Including, A non-transitory computer readable medium, wherein the contacting occurs at a first exclusion area of ​​the coating. Article 32. A set of instructions is executable by at least one processor of the device to cause the device to perform a method, the method comprising: Determining a location of a first exclusion area; adjusting a position of the wafer or the first electrical contact such that the first exclusion area is aligned with the first electrical contact; 32. The non-transitory computer-readable medium of claim 31, further comprising: Article 33. Adjusting the position of the wafer A wafer holder that holds a wafer is translated. 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 34. Adjusting the position of the wafer Rotating the wafer holder that holds the wafer 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 35. Adjusting the position of the wafer unloading the wafer from the first holding position of the wafer holder; reloading the wafer on the wafer holder at a second holding position different from the first holding position; 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 36. Adjusting the position of the wafer Unloading the wafer from the first holding orientation in the wafer holder; reloading the wafer on the wafer holder into a second holding orientation different from the first holding orientation; 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 37. Adjusting a position of the first electrical contact Actuating the first electrical contact 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 38. 32. The non-transitory computer readable medium of claim 31, wherein the coating is a backside film configured to inhibit wafer warping or wafer bowing. Article 39. 32. The non-transitory computer-readable medium of claim 31, wherein the exclusion area has a size of at least 1.5 mm in a radial direction of the surface. Article 40. 32. The non-transitory computer readable medium of clause 31, wherein the exclusion area has a size that is at least twice the size of a cross-sectional contact area between the first electrical contact and the wafer. Article 41. 32. The non-transitory computer readable medium of clause 31, wherein the wafer has a first electrical conductivity and the coating has a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 42. 32. The non-transitory computer readable medium of clause 31, wherein the first exclusion area comprises a void in the coating that exposes an area on the surface of the wafer. Article 43. 32. The non-transitory computer-readable medium of clause 31, wherein the coating has a first thickness in the first exclusion area and a second thickness in an area adjacent to the first exclusion area, the second thickness being greater than the first thickness. Article 44. 32. The non-transitory computer-readable medium of claim 31, wherein the coating has a thickness of at least 1 μm. Article 45. 32. The non-transitory computer-readable medium of claim 31, wherein the first exclusion area comprises a first material having a first electrical conductivity and the coating comprises a second material having a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 46. 46. ​​The non-transitory computer-readable medium of clause 45, wherein the first material is substantially coplanar with the second material. Article 47. a set of instructions executable by at least one processor of the device, contacting the second electrical contact with the surface of the wafer; and causing the device to further 32. The non-transitory computer readable medium of clause 31, wherein the first electrical contact and the second electrical contact contact the wafer simultaneously. Article 48. 48. The non-transitory computer readable medium of clause 47, wherein the second electrical contact contacts the wafer in a second exclusion area different from the first exclusion area. Article 49. The first exclusion area comprises a first portion and a second portion, and the method further comprises: contacting a first electrical contact with the surface at a first portion; contacting a second electrical contact with the surface at the second portion; 48. The non-transitory computer readable medium of claim 47, further comprising: Article 50. 50. The non-transitory computer-readable medium of clause 49, wherein the first exclusion area has an annular shape. Article 51. 32. The non-transitory computer-readable medium of claim 31, wherein the first exclusion area has at least one of an annular shape, an arcuate shape, a rectangular shape, or a circular shape. Article 52. 32. The non-transitory computer-readable medium of claim 31, wherein the surface of the wafer includes a second exclusion area that is different from the first exclusion area. Article 53. 32. The non-transitory computer-readable medium of clause 31, wherein the first exclusion area is disposed on a periphery of the surface. Article 54. a set of instructions executable by at least one processor of the device, moving the first electrical contact away from the first exclusion area; contacting the first exclusion area with a second electrical contact, the second electrical contact being different from the first electrical contact; 32. The non-transitory computer-readable medium of claim 31, further causing the device to: Article 55. a set of instructions executable by at least one processor of the device, Performing a charged particle beam process on a wafer and causing the device to further 32. The non-transitory computer readable medium of claim 31, wherein the first electrical contact contacts the surface of the wafer during a charged particle beam process. Article 56. 56. The non-transitory computer readable medium of clause 55, wherein the charged particle beam process is scanning electron microscopy of the wafer. Article 57. a set of instructions executable by at least one processor of the device, Electrically connecting the wafer to a bias supply via the first electrical contact. The non-transitory computer-readable medium of claim 31, further causing the device to perform the following: Article 58. a set of instructions executable by at least one processor of the device, applying a DC voltage to the wafer via the first electrical contact; 32. The non-transitory computer-readable medium of claim 31, further causing the device to: Article 59. a set of instructions executable by at least one processor of the device, Removing charge from the wafer by the first electrical contact 32. The non-transitory computer-readable medium of claim 31, further causing the device to: Article 60. 60. The non-transitory computer readable medium of claim 59, wherein removing charge from the wafer renders the wafer electrically neutral. Article 61. a wafer holder configured to hold a wafer having a coating on a surface of the wafer; A first electrical contact; a charged particle beam source configured to irradiate the wafer with a charged particle beam; a controller configured to contact a first electrical contact with a surface of the wafer at a first exclusion area of ​​the coating; A charged particle beam device comprising: Article 62. The controller determining the location of the first exclusion area; Adjusting the position of the wafer or the first electrical contact so that the first exclusion area is aligned with the first electrical contact. 62. The charged particle beam device of claim 61 further configured. Article 63. Adjusting the position of the wafer Translating the wafer holder 63. A charged particle beam device according to claim 62, comprising: Article 64. Adjusting the position of the wafer Rotating the wafer holder 63. A charged particle beam device according to claim 62, comprising: Article 65. Adjusting the position of the wafer unloading the wafer from the first holding position of the wafer holder; reloading the wafer on the wafer holder at a second holding position different from the first holding position; 63. A charged particle beam device according to claim 62, comprising: Article 66. Adjusting the position of the wafer Unloading the wafer from the first holding orientation of the wafer holder; reloading the wafer on the wafer holder into a second holding orientation different from the first holding orientation; 63. A charged particle beam device according to claim 62, comprising: Article 67. Adjusting a position of the first electrical contact Actuating the first electrical contact 63. A charged particle beam device according to claim 62, comprising: Article 68. 62. The charged particle beam device of claim 61, wherein the coating is a backside film configured to suppress wafer warp or wafer bow. Article 69. Charged particle beam device as described in clause 61, wherein the exclusion area has a size of at least 1.5 mm in the radial direction of the surface. Article 70. 62. The charged particle beam device of claim 61, wherein the exclusion area has a size that is at least twice the size of a cross-sectional contact area between the first electrical contact and the wafer. Article 71. 62. The charged particle beam device of clause 61, wherein the wafer has a first electrical conductivity and the coating has a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 72. 62. The charged particle beam device of claim 61, wherein the first exclusion area comprises a gap in the coating exposing an area on the surface of the wafer. Article 73. 62. The charged particle beam device of clause 61, wherein the coating has a first thickness in the first exclusion area and a second thickness in an area adjacent the first exclusion area, the second thickness being greater than the first thickness. Article 74. 62. The charged particle beam device of claim 61, wherein the coating has a thickness of at least 1 μm. Article 75. 62. A charged particle beam device as described in clause 61, wherein the first exclusion area comprises a first material having a first electrical conductivity and the coating comprises a second material having a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 76. 76. The charged particle beam device of claim 75, wherein the first material is substantially coplanar with the second material. Article 77. the controller is further configured to bring the second electrical contact into contact with the surface of the wafer; 62. The charged particle beam device of clause 61, wherein the first electrical contact and the second electrical contact are configured to contact the wafer simultaneously. Article 78. 78. The charged particle beam device of clause 77, wherein the second electrical contact is configured to contact the wafer in a second exclusion area different from the first exclusion area. Article 79. the first exclusion area includes a first portion and a second portion; The controller contacting a first electrical contact with the surface at a first portion; contacting a second electrical contact with the surface at the second portion; 78. The charged particle beam device of claim 77, further configured Article 80. Charged particle beam device as described in clause 79, wherein the first exclusion area has an annular shape. Article 81. Charged particle beam device according to clause 61, wherein the first exclusion area has at least one of an annular shape, an arcuate shape, a rectangular shape, or a circular shape. Article 82. 62. The charged particle beam device of clause 61, wherein the surface of the wafer includes a second exclusion area different from the first exclusion area. Article 83. 62. The charged particle beam device of claim 61, wherein the first exclusion area is arranged on the periphery of the surface. Article 84. The controller Moving the first electrical contact away from the first exclusion area; A second electrical contact is contacted with the first exclusion area, and the second electrical contact is different from the first electrical contact. 62. The charged particle beam device of claim 61 further configured. Article 85. The controller Performing a charged particle beam process on the wafer The method further comprises: 62. The charged particle beam device of claim 61, wherein the first electrical contact contacts a surface of the wafer during charged particle beam processing. Article 86. 86. The charged particle beam apparatus of claim 85, wherein the charged particle beam process is scanning electron microscopy of a wafer. Article 87. Wafer Bias Supply Source Further comprising: 62. The charged particle beam device of claim 61, wherein the controller is further configured to electrically connect the wafer to a bias supply via the first electrical contact. Article 88. 62. The charged particle beam device of claim 61, wherein the controller is further configured to supply a DC voltage to the wafer via the first electrical contact. Article 89. 62. The charged particle beam device of claim 61, wherein the first electrical contact is configured to remove charge from the wafer. Article 90. 89. The charged particle beam device of claim 89, wherein removing charge from the wafer renders the wafer electrically neutral. Article 91. a wafer holder configured to hold a wafer in a processing chamber, the processing chamber configured to form a coating on the wafer; a first exclusion mask configured to cover a first exclusion area of ​​the wafer, the first exclusion mask configured to inhibit or prevent film formation in the first exclusion area during a film formation process in the processing chamber; A wafer holding mechanism for a wafer processing system comprising: Article 92. 92. The wafer holding mechanism of clause 91, wherein the first exclusion mask is a support member of a wafer holder, the support member configured to support the wafer in the first exclusion area. Article 93. 93. The wafer holding mechanism of clause 92, further comprising a second exclusion mask configured to cover a second exclusion area of ​​the wafer. Article 94. 94. The wafer retention mechanism of clause 93, wherein the second exclusion mask does not substantially support the wafer. Article 95. 95. The wafer holding mechanism of clause 94, wherein the second exclusion mask is configured to contact the wafer in the second exclusion area without substantially supporting the wafer. Article 96. 95. The wafer holding mechanism of clause 94, wherein the second exclusion mask is configured to inhibit or prevent film formation in the second exclusion area without contacting the wafer. Article 97. 95. The wafer retention mechanism of clause 94, wherein the second exclusion mask comprises a removable membrane. Article 98. 92. The wafer holding mechanism of clause 91, wherein the first exclusion mask is configured to contact the wafer in the first exclusion area without substantially supporting the wafer. Article 99. 92. The wafer holding mechanism of clause 91, wherein the first exclusion mask is configured to inhibit or prevent film formation in the first exclusion area without contacting the wafer. Article 100. 100. The wafer holding mechanism of clause 99, wherein the wafer holder comprises a support member configured to support the wafer in an area other than the first exclusion area. Article 101. 92. The wafer holding mechanism of clause 91, wherein the first exclusion mask has a shape corresponding to a shape of the first exclusion area. Article 102. 92. The wafer holding mechanism of clause 91, wherein the wafer holder comprises a table configured to support the wafer from below. Article 103. 13. The wafer holding mechanism of claim 102, wherein the first exclusion mask is configured to cover the first exclusion area from above the wafer. Article 104. 92. The wafer retention mechanism of clause 91, wherein the first exclusion mask includes a removable membrane. Article 105. 92. The wafer holding mechanism of clause 91, wherein the processing chamber is one of a chemical vapor deposition chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, and a passivation chamber. Article 106. a coating on the surface of the wafer; a first exclusion area of ​​the coating, the first exclusion area configured to facilitate a connection between an electrical contact of the charged particle beam inspection device and the wafer; A semiconductor wafer comprising: Article 107. 107. The semiconductor wafer of claim 106, wherein the coating is a backside film configured to inhibit wafer warp or wafer bow. Article 108. 107. The semiconductor wafer of claim 106, wherein the first exclusion area has a size of at least 1.5 mm in a radial direction of the surface. Article 109. 107. The semiconductor wafer of claim 106, wherein the first exclusion area has a size that is at least twice the size of a cross-sectional contact area between the electrical contact and the wafer. Article 110. 107. The semiconductor wafer of clause 106, wherein the wafer has a first electrical conductivity and the coating has a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 111. 107. The semiconductor wafer of claim 106, wherein the first exclusion area comprises a void in the coating exposing an area on the surface of the wafer. Article 112. 107. The semiconductor wafer of clause 106, wherein the coating has a first thickness in the first exclusion area and a second thickness in an area adjacent the first exclusion area, the second thickness being greater than the first thickness. Article 113. 107. The method of claim 106, wherein the coating has a thickness of at least 1 μm. Article 114. 107. The semiconductor wafer of claim 106, wherein the first exclusion area comprises a first material having a first electrical conductivity and the coating comprises a second material having a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity. Article 115. 15. The semiconductor wafer of claim 114, wherein the first material is substantially coplanar with the second material. Article 116. 107. The semiconductor wafer of claim 106, wherein the first exclusion area has at least one of an annular shape, an arcuate shape, a rectangular shape, or a circular shape. Article 117. 107. The semiconductor wafer of claim 106, wherein the surface of the wafer includes a second exclusion area different from the first exclusion area. Article 118. 107. The semiconductor wafer of claim 106, wherein the first exclusion area is located on the periphery of the surface. Article 119. 1. A method for forming a coating on a wafer surface, comprising: loading a wafer into a processing chamber; masking a first exclusion area on the wafer surface with a first exclusion mask; performing a film formation process in the processing chamber; A method comprising: The method, wherein a first exclusion mask inhibits or eliminates film formation in the first exclusion areas. Article 120. Holding the wafer by a wafer holder in a processing chamber 120. The method of claim 119, further comprising: Article 121. Clause 121. The method of clause 120, wherein the first exclusion mask is a support member of a wafer holder, the support member configured to support the wafer in the exclusion area. Article 122. masking a second exclusion area on the surface of the wafer with a second exclusion mask; 122. The method of claim 121, further comprising: Article 123. Clause 123. The method of clause 122, wherein the second exclusion mask does not substantially support the wafer. Article 124. Clause 123. The method of clause 122, wherein the second exclusion mask contacts the wafer in the second exclusion area without substantially supporting the wafer. Article 125. Clause 123. The method of clause 122, wherein the second exclusion mask inhibits or prevents film formation in the second exclusion areas without contacting the wafer. Article 126. 130. The method of claim 122, wherein the second exclusion mask comprises a removable membrane. Article 127. Clause 121. The method of clause 120, wherein the wafer holder comprises a support member configured to support the wafer in an area other than the first exclusion area. Article 128. 121. The method of clause 120, wherein the wafer holder comprises a table configured to support the wafer from below. Article 129. Clause 119. The method of clause 119, wherein the first exclusion mask is configured to contact the wafer in the first exclusion area without substantially supporting the wafer. Article 130. supporting the wafer with a support member; Clause 119. The method of clause 119, wherein the support member is configured to support the wafer in an area other than the first exclusion area. Article 131. Clause 119. The method of clause 119, wherein the first exclusion mask is configured to inhibit or prevent film formation in the first exclusion area without contacting the wafer. Article 132. supporting the wafer with a support member; Clause 132. The method of clause 131, wherein the support member is configured to support the wafer in an area other than the first exclusion area. Article 133. Clause 119. The method of clause 119, wherein the first exclusion mask has a shape corresponding to a shape of the first exclusion area. Article 134. Clause 119. The method of clause 119, wherein a first exclusion mask is configured to cover a first exclusion area from above the wafer. Article 135. 120. The method of clause 119, wherein the first exclusion mask comprises a removable membrane. Article 136. 120. The method of claim 119, wherein the film formation process includes one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and passivation. Article 137. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method, the method comprising: loading a wafer into a processing chamber; masking a first exclusion area on the wafer surface with a first exclusion mask; performing a film formation process in the processing chamber; A non-transitory computer readable medium comprising: A non-transitory computer readable medium, wherein a first exclusion mask inhibits or eliminates film formation in a first exclusion area. Article 138. a set of instructions executable by at least one processor of the device, Holding the wafer by a wafer holder in a processing chamber The non-transitory computer-readable medium of claim 137, further causing the device to perform the following: Article 139. The non-transitory computer readable medium of clause 138, wherein the first exclusion mask is a support member of a wafer holder, the support member configured to support the wafer in the first exclusion area. Article 140. a set of instructions executable by at least one processor of the device, masking a second exclusion area on the wafer surface with a second exclusion mask; The non-transitory computer-readable medium of clause 139, further causing the device to perform the following: Article 141. The non-transitory computer readable medium of clause 140, wherein the second exclusion mask does not substantially support the wafer. Article 142. The non-transitory computer readable medium of clause 140, wherein the second exclusion mask contacts the wafer in the second exclusion area without substantially supporting the wafer. Article 143. The non-transitory computer readable medium of clause 140, wherein the second exclusion mask inhibits or prevents film formation in the second exclusion area without contacting the wafer. Article 144. The non-transitory computer readable medium of clause 140, wherein the second exclusion mask comprises a removable membrane. Article 145. The non-transitory computer readable medium of clause 138, wherein the wafer holder comprises a support member configured to support the wafer in an area other than the first exclusion area. Article 146. 19. The non-transitory computer readable medium of claim 138, wherein the wafer holder comprises a table configured to support the wafer from below. Article 147. The non-transitory computer readable medium of clause 137, wherein the first exclusion mask is configured to contact the wafer in the first exclusion area without substantially supporting the wafer. Article 148. a set of instructions executable by at least one processor of the device, Supporting the wafer with the support member A non-transitory computer-readable medium further causing a device to: 148. The non-transitory computer readable medium of claim 147, wherein the support member is configured to support the wafer in an area other than the first exclusion area. Article 149. The non-transitory computer readable medium of clause 137, wherein the first exclusion mask is configured to inhibit or prevent film formation in the first exclusion area without contacting the wafer. Article 150. a set of instructions executable by at least one processor of the device, Supporting the wafer by the support member A non-transitory computer-readable medium further causing a device to: Clause 149. The non-transitory computer-readable medium of clause 149, wherein the support member is configured to support the wafer in an area other than the first exclusion area. Article 151. The non-transitory computer-readable medium of claim 137, wherein the first exclusion mask has a shape corresponding to a shape of the first exclusion area. Article 152. The non-transitory computer readable medium of clause 137, wherein the first exclusion mask is configured to cover a first exclusion area from above the wafer. Article 153. 138. The non-transitory computer readable medium of claim 137, wherein the first exclusion mask comprises a removable membrane. Article 154. 138. The non-transitory computer-readable medium of claim 137, wherein the film formation process includes one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, and passivation. Article 155. actuating the first electrical contact in a height direction to contact the first electrical contact with the surface of the wafer; 2. The method of claim 1, further comprising: Article 156. Performing a wafer grounding process by one of pressing, zapping, or pin impact methods. 2. The method of claim 1, further comprising: Article 157. Determining the location of the first exclusion area; Detecting locations of reference features on the wafer; determining a location of the first exclusion area based on the detected location of the reference feature; 3. The method according to claim 2, comprising: Article 158. Clause 158. The method of clause 157, wherein the reference feature is one of an alignment notch, a flat portion of the wafer edge, or a fiducial mark. Article 159. Determining the location of the first exclusion area; Using sensors to detect the location of the exclusion area 3. The method according to claim 2, comprising: Article 160. Detecting the location Detecting an optical property of a surface of the wafer; detecting a capacitive characteristic of a surface of the wafer; Detecting an acoustic characteristic of a surface of the wafer; or Detecting the topography of the surface of a wafer 159. The method of claim 159, comprising any one of the following: Article 161. 3. The method of claim 2, wherein adjusting the position of the wafer or the first electrical contact includes actuating one of a wafer holder, a wafer stage, or a wafer lifter. Article 162. 2. The method of claim 1, wherein the exclusion area has a first size in a first direction that is no more than 750 μm greater than a dimension of the first electrical contact in the first direction when the first electrical contact is in contact with the exclusion area. Article 163. Clause 163. The method of clause 162, wherein the exclusion area has a second size in a second direction that is greater than the first size, the second direction being substantially perpendicular to the first direction. Article 164. a set of instructions executable by at least one processor of the device, actuating the first electrical contact in a height direction to contact the first electrical contact with the surface of the wafer; 32. The non-transitory computer-readable medium of claim 31, further causing the device to: Article 165. The non-transitory computer-readable medium of clause 31, wherein a set of instructions executable by at least one processor of the device further causes the device to perform a wafer grounding process by one of a pressing method, a zapping method, or a pin impact method. Article 166. Determining the location of the first exclusion area; Detecting locations of reference features on the wafer; determining a location of the first exclusion area based on the detected location of the reference feature; 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 167. The non-transitory computer-readable medium of clause 166, wherein the reference feature is one of an alignment notch, a flat portion of a wafer edge, or a fiducial mark. Article 168. Determining the location of the first exclusion area; Using sensors to detect the location of the exclusion area 33. A non-transitory computer readable medium as set forth in clause 32, comprising: Article 169. Detecting the location Detecting an optical property of a surface of the wafer; detecting a capacitive characteristic of a surface of the wafer; Detecting an acoustic characteristic of a surface of the wafer; or Detecting the topography of the surface of a wafer A non-transitory computer readable medium as described in clause 168, comprising any one of the following: Article 170. 33. The non-transitory computer readable medium of clause 32, wherein adjusting the position of the wafer or the first electrical contact includes actuating one of a wafer holder, a wafer stage, or a wafer lifter. Article 171. 32. The non-transitory computer-readable medium of clause 31, wherein the exclusion area has a first size in a first direction that is no more than 750 μm greater than a dimension of the first electrical contact in the first direction when the first electrical contact is in contact with the exclusion area. Article 172. The non-transitory computer-readable medium of clause 171, wherein the exclusion area has a second size in a second direction that is greater than the first size, and the second direction is substantially perpendicular to the first direction. Article 173. 62. The charged particle beam device of claim 61, wherein the controller is further configured to actuate the first electrical contact in a height direction to bring the first electrical contact into contact with the surface of the wafer. Article 174. 62. The charged particle beam device of claim 61, wherein the controller is further configured to perform a wafer grounding process by one of a pressing method, a zapping method, or a pin impact method. Article 175. Determining the location of the first exclusion area; Detecting locations of reference features on the wafer; determining a location of the first exclusion area based on the detected location of the reference feature; 63. A charged particle beam device according to claim 62, comprising: Article 176. 176. The charged particle beam device of claim 175, wherein the reference feature is one of an alignment notch, a flat portion of the wafer edge, or a fiducial mark. Article 177. Determining the location of the first exclusion area; Using sensors to detect the location of the exclusion area 63. A charged particle beam device according to claim 62, comprising: Article 178. Detecting the location Detecting an optical property of a surface of the wafer; detecting a capacitive characteristic of a surface of the wafer; Detecting an acoustic characteristic of a surface of the wafer; or Detecting the topography of the surface of a wafer 178. A charged particle beam device as described in clause 177, comprising any of the following: Article 179. 63. The charged particle beam device of clause 62, wherein adjusting the position of the wafer or the first electrical contact comprises actuating one of a wafer holder, a wafer stage, or a wafer lifter. Article 180. 62. The charged particle beam device of claim 61, wherein the exclusion area has a first size in a first direction that is no more than 750 μm greater than a dimension of the first electrical contact in the first direction when the first electrical contact is in contact with the exclusion area. Article 181. Charged particle beam device according to clause 180, wherein the exclusion area has a second size in a second direction that is larger than the first size, the second direction being substantially perpendicular to the first direction. Article 182. The method of any one of clauses 1-30 or 155-163, wherein the first electrical contact comprises a pin body, a first tip, and a second tip, the first tip and the second tip each extending from the pin body. Article 183. Clause 183. The method of clause 182, wherein the distance between the first tip and the second tip is substantially equal to a width of the first exclusion area of ​​the coating. Article 184. Clause 184. The method of clause 183, further comprising adjusting the pin body to contact the surface of the wafer within a width of the first exclusion area of ​​the coating. Article 185. Clause 185. The method of clause 184, wherein adjusting the pin body includes any one of linearly adjusting the pin body, angularly adjusting the pin body, or a combination thereof. Article 186. The method of any one of clauses 1-30 or 155-163, wherein the first electrical contact comprises a spring in the wafer holder. Article 187. Clause 187. The method of clause 186, wherein the spring is configured to inhibit wafer warp or wafer bow. Article 188. The method of any one of clauses 1-30, 155-163, or 182-187, wherein the first electrical contacts include a plurality of first electrical contacts and the first exclusion area includes a plurality of first exclusion areas, each first electrical contact corresponding to a first exclusion area. Article 189. The non-transitory computer-readable medium of any one of clauses 31-60 or 164-172, wherein the first electrical contact comprises a pin body, a first tip, and a second tip, the first tip and the second tip each extending from the pin body. Article 190. The non-transitory computer-readable medium of claim 189, wherein a distance between the first tip and the second tip is substantially equal to a width of the first exclusion area of ​​the coating. Article 191. The non-transitory computer readable medium of clause 190, wherein a set of instructions executable by at least one processor of the device further causes the device to adjust the pin body to contact the surface of the wafer within a width of a first exclusion area of ​​the coating. Article 192. The non-transitory computer readable medium of clause 191, wherein adjusting the pin body includes any one of adjusting the pin body in a linear direction, adjusting the pin body in an angular direction, or a combination thereof. Article 193. The non-transitory computer readable medium of any one of clauses 31-60 or 164-172, wherein the first electrical contact comprises a spring in the wafer holder. Article 194. 194. The non-transitory computer readable medium of claim 193, wherein the spring is configured to suppress wafer warping or wafer bowing. Article 195. The non-transitory computer-readable medium of any one of clauses 31-60, 164-172, or 189-194, wherein the first electrical contacts include a plurality of first electrical contacts and the first exclusion area includes a plurality of first exclusion areas, each first electrical contact corresponding to a first exclusion area. Article 196. A charged particle beam device as described in any one of clauses 61-90 or 173-181, wherein the first electrical contact comprises a pin body, a first tip, and a second tip, the first tip and the second tip each extending from the pin body. Article 197. Charged particle beam device according to clause 196, wherein the distance between the first tip and the second tip is substantially equal to a width of the first exclusion area of ​​the coating. Article 198. The charged particle beam device of claim 197, wherein the controller is further configured to adjust the pin body to contact the surface of the wafer within a width of the first exclusion area of ​​the coating. Article 199. The charged particle beam device of claim 198, wherein adjusting the pin body includes any one of adjusting the pin body in a linear direction, adjusting the pin body in an angular direction, or a combination thereof. Article 200. The charged particle beam device of any one of clauses 61-90 or 173-181, wherein the first electrical contact comprises a spring in the wafer holder. Article 201. The charged particle beam device of claim 200, wherein the spring is configured to suppress wafer warp or wafer bow. Article 202. A charged particle beam device as described in any one of clauses 61-90, 173-181, or 196-201, wherein the first electrical contact includes a plurality of first electrical contacts and the first exclusion area includes a plurality of first exclusion areas, each first electrical contact corresponding to a first exclusion area. Article 203. Clause 106. The wafer holding mechanism of any one of clauses 91-105, wherein the wafer holder further comprises a spring configured to contact the first exclusion area of ​​the wafer. Article 204. 204. The wafer retention mechanism of claim 203, wherein the spring is configured to inhibit wafer warping or wafer bowing. Article 205. 119. The semiconductor wafer of any one of clauses 106-118, wherein the electrical contact comprises a pin body, a first tip, and a second tip, the first tip and the second tip each extending from the pin body. Article 206. 206. The semiconductor wafer of claim 205, wherein a distance between the first tip and the second tip is substantially equal to a width of the first exclusion area of ​​the coating. Article 207. 207. The semiconductor wafer of claim 206, wherein the controller is further configured to adjust the pin bodies to contact the surface of the wafer within a width of the first exclusion area of ​​the coating. Article 208. The semiconductor wafer of clause 207, wherein adjusting the pin body includes any one of adjusting the pin body in a linear direction, adjusting the pin body in an angular direction, or a combination thereof. Article 209. 119. The semiconductor wafer of any one of clauses 106-118, wherein the electrical contacts include springs in the wafer holder. Article 210. 209. The semiconductor wafer of claim 209, wherein the spring is configured to inhibit wafer warp or wafer bow. Article 211. The semiconductor wafer of any one of clauses 106-118 or 205-210, wherein the electrical contacts include a plurality of electrical contacts and the first exclusion area includes a plurality of first exclusion areas, each electrical contact corresponding to a first exclusion area. Article 212. 1. A method for electrically connecting to a wafer, comprising: contacting a pin body with a surface of the wafer, the wafer having a coating on a surface thereof; the pin body having a first tip and a second tip each extending from the pin body; A method comprising: The method, wherein the contacting is performed at a first exclusion area of ​​the coating by either a first tip, a second tip, or any combination thereof. Article 213. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method, the method comprising: contacting a pin body with a surface of the wafer, the wafer having a coating on a surface thereof; the pin body having a first tip and a second tip each extending from the pin body; A non-transitory computer readable medium comprising: A non-transitory computer readable medium, wherein the contacting occurs at a first exclusion area of ​​the coating by either a first tip, a second tip, or any combination thereof. Article 214. a wafer holder configured to hold a wafer having a coating on a surface of the wafer; a pin body, the pin body including a first tip and a second tip each extending from the pin body; a charged particle beam source configured to irradiate the wafer with a charged particle beam; a controller configured to contact either one of the first tip, the second tip, or any combination thereof, with a surface of the wafer at a first exclusion area of ​​the coating; A charged particle beam device comprising: Article 215. a coating on the surface of the wafer; a first exclusion area of ​​the coating, the first exclusion area configured to facilitate a connection between a first tip extending from the pin body of a charged particle beam inspection device, a second tip extending from the pin body, or a combination thereof, and a wafer; A semiconductor wafer comprising:

[0139]

[0166] It will be understood that the embodiments of the present disclosure are not limited to the exact structures described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope of the present disclosure.

Claims

1. a wafer holder configured to hold a wafer having a coating on a surface of the wafer; A first electrical contact; a charged particle beam source configured to irradiate the wafer with a charged particle beam; a controller configured to contact the first electrical contact with the surface of the wafer at a first exclusion area of ​​the coating; A charged particle beam device comprising:

2. The controller: determining a location of the first exclusion area; adjusting a position of the wafer or the first electrical contact such that the first exclusion area is aligned with the first electrical contact; The charged particle beam device of claim 1 , further configured to:

3. determining a location of the first exclusion area; Detecting locations of reference features on the wafer; determining a location of the first exclusion area based on the detected location of the reference feature; The charged particle beam device of claim 2 , comprising:

4. Charged particle beam device according to claim 1 , wherein the exclusion area has a size of at least 1.5 mm in a radial direction of the surface.

5. 2. The charged particle beam device of claim 1, wherein the wafer has a first electrical conductivity and the coating has a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity.

6. The charged particle beam device of claim 1 , wherein the first exclusion area comprises a gap in the coating that exposes an area on the surface of the wafer.

7. 2. The charged particle beam device of claim 1, wherein the coating has a first thickness in the first exclusion area and a second thickness in an area adjacent the first exclusion area, the second thickness being greater than the first thickness.

8. Charged particle beam device according to claim 1 , wherein the coating has a thickness of at least 1 μm.

9. 2. The charged particle beam device of claim 1, wherein the first exclusion area comprises a first material having a first electrical conductivity and the coating comprises a second material having a second electrical conductivity, the first electrical conductivity being greater than the second electrical conductivity.

10. the controller is further configured to bring a second electrical contact into contact with the surface of the wafer; The charged particle beam device of claim 1 , wherein the first electrical contact and the second electrical contact are configured to contact the wafer simultaneously.

11. The charged particle beam device of claim 1 , wherein the first exclusion area has at least one of an annular shape, an arcuate shape, a rectangular shape, or a circular shape.

12. The controller: A charged particle beam process is performed on the wafer. The method further comprises: The charged particle beam device of claim 1 , wherein the first electrical contact contacts the surface of the wafer during the charged particle beam process.

13. Wafer Bias Supply Source Further comprising: The charged particle beam device of claim 1 , wherein the controller is further configured to electrically connect the wafer to a bias supply through the first electrical contact.

14. A non-transitory computer readable medium storing a set of instructions executable by at least one processor of a device to cause the device to perform a method, the method comprising: contacting a first electrical contact with a surface of a wafer, the wafer having a coating on the surface; Including, The non-transitory computer readable medium, wherein the contacting occurs at a first exclusion area of ​​the coating.

15. 1. A method for forming a coating on a wafer surface, comprising: loading a wafer into a processing chamber; masking a first exclusion area on the wafer surface with a first exclusion mask; performing a film formation process in the processing chamber; A method comprising: The method, wherein the first exclusion mask inhibits or eliminates film formation in the first exclusion areas.

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