Wafer holder for reducing electric field distortion near the wafer edge

Abstract

An improved system 700 for inspection of outer wafer portions in a charged particle beam system such as a scanning electron microscope (SEM) is disclosed. The system compensates for electric field distortions occurring at the outer wafer portions using multiple conductive electrodes (e.g., rings 710, 711) around the wafer 703. Different complementary voltages VS1, VS2 are applied to the rings to achieve precise compensation of the electric field distortions.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Application No. 63 / 330,249, filed April 12, 2022, which is incorporated by reference in its entirety into this specification.

[0002] The present disclosure relates to the field of charged particle beam devices, and more particularly to wafer edge inspection for charged particle inspection systems. [Background technology]

[0003]

[0003] Charged particle beam devices can generate two-dimensional images of a wafer substrate by detecting secondary, backscattered, mirror, or other types of electrons that arise from the surface of the wafer substrate when the charged particle beam generated by the charged particle beam device strikes the wafer substrate. In the semiconductor industry, various charged particle beam devices are used on semiconductor wafers for various purposes, such as wafer processing (e.g., electron beam direct write lithography systems), process monitoring (e.g., critical dimension scanning electron microscopes (CD-SEMs)), wafer inspection (e.g., electron beam inspection systems), defect analysis (e.g., defect review SEMs (so-called DR-SEMs), focused ion beam systems (so-called FIBs)), etc.).

[0004]

[0004] During wafer inspection, potential defects in the wafer are found and removed, allowing for defect-free structures to be formed in the wafer at a later stage. During this wafer inspection process, the wafer may be placed inside a conductive ring (also called a high voltage (HV) ring structure) on the wafer holder (stage). The conductive ring may also be called a compensation ring. A compensation voltage is usually applied to this conductive ring to further reduce distortion of the electric field near the outer part of the wafer, thereby reducing misalignment and resolution loss of the scanned image in this area. However, such compensation does not sufficiently reduce the misalignment and resolution loss. Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide a system and method for inspecting an edge of a sample in a charged particle beam system.

[0006]

[0006] Some embodiments provide a system for reducing electric field distortion near an outer portion of a wafer, the system including a wafer holder including a holding portion configured to hold a wafer having a first outer diameter, a first conductive electrode configured to surround the wafer, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter, a second conductive ring configured to surround the first conductive electrode, the second conductive ring having a fourth inner diameter greater than the second inner diameter, and a first, second and a third voltage source, a first voltage source connected to the first conductive electrode, a second voltage source connected to the second conductive electrode, and a third voltage source connected to the wafer; and a controller configured to control each of the first, second, and third voltage sources to operate at a first voltage, a second voltage, and a third voltage, respectively, wherein the first voltage, the second voltage, and the third voltage are selected to reduce distortion of the electric field at an outer portion of the wafer, and the first voltage, the second voltage, and the third voltage are different from one another.

[0007]

[0007] Some embodiments provide a non-transitory computer readable medium storing a set of instructions executable by at least one processor of the device, the instructions causing the device to perform a method including loading a wafer having a first outer diameter into a wafer holder including a holding portion; applying a first voltage to a first conductive electrode surrounding the holding portion, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being larger than the first outer diameter; applying a second voltage to a second conductive electrode surrounding the first conductive electrode, the second conductive electrode having a fourth inner diameter larger than the second inner diameter; and applying a third voltage to the wafer, wherein the first voltage, the second voltage, and the third voltage are selected to reduce distortion of the electric field at an outer portion of the wafer, and the first voltage, the second voltage, and the third voltage are different from one another.

[0008]

[0008] Additional objects and advantages of the disclosed embodiments will be set forth in part in the description that follows, and in part will be apparent from the description that follows, or may be learned by practice of the embodiments. Some objects and advantages of the disclosed embodiments may be realized and obtained by means of the elements and combinations recited in the claims. However, it is not necessary for an embodiment of the present disclosure to achieve such exemplary objects or advantages, and in some embodiments, none of the described objects or advantages may be achieved.

[0009]

[0009] It is to be understood that both the foregoing general description and the following detailed description are intended to be exemplary and explanatory only and are not intended to restrict the disclosed embodiments as may be recited in the claims. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an example electron beam inspection (EBI) system consistent with certain embodiments of the present disclosure. [Diagram 2]

[0011] 2 is a schematic diagram illustrating an example electron beam tool consistent with certain embodiments of the present disclosure that may be part of the example electron beam inspection system of FIG. 1. [Diagram 3]

[0012] 1 illustrates a top view of an exemplary system according to a comparative embodiment. [Figure 4]

[0013] 4 illustrates a cross-sectional view of the exemplary system of FIG. 3 according to a comparative embodiment. [Diagram 5]

[0014] 1 shows a cross-sectional view of an exemplary system according to a comparative embodiment. [Figure 6]

[0015] 6 illustrates a cross-sectional view of the exemplary system of FIG. 5 according to a comparative embodiment. [Figure 7A]

[0016] 1 illustrates a top view of an example multi-ring system consistent with certain embodiments of the present disclosure. [Figure 7B]

[0017] 1 illustrates a cross-sectional view of an example multi-ring system consistent with certain embodiments of the present disclosure. [Figure 8A]

[0018] 1 illustrates an example configuration for applying various voltages to a multi-ring system consistent with certain embodiments of the present disclosure. [Figure 8B]

[0018] An example configuration for applying various voltages to a multi-ring system consistent with some embodiments of the present disclosure is shown. [Figure 8C]

[0018] An example configuration for applying various voltages to a multi-ring system consistent with some embodiments of the present disclosure is shown. [Figure 8D]

[0018] An example configuration for applying various voltages to a multi-ring system consistent with some embodiments of the present disclosure is shown. [Figure 9A]

[0019] 1 illustrates an example configuration using a coating on an insulating block of a ring system consistent with some embodiments of the present disclosure. [Figure 9B]

[0019] An example configuration using a coating on an insulating block of a ring system consistent with some embodiments of the present disclosure is shown. [Figure 9C]

[0019] An example configuration using a coating on an insulating block of a ring system consistent with some embodiments of the present disclosure is shown. [Figure 10A]

[0020] 1 illustrates a top view of an example system during wafer loading, consistent with certain embodiments of the present disclosure. [Figure 10B]

[0021] FIG. 10B illustrates a top view of the example system of FIG. 10A after wafer loading, consistent with certain embodiments of the present disclosure. [Figure 11]

[0022] 13 shows an example comparison between a single conductive ring of a comparative example and a multi-ring system according to an embodiment of the present disclosure. [Figure 12]

[0023] 1 shows a flowchart of an example method for compensating for edge field distortion in a charged particle beam process, consistent with certain embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0024] Reference will now be made in detail to exemplary embodiments illustrated in the accompanying drawings. The following description refers to the accompanying drawings, in which the same numbers in different drawings represent the same or similar elements unless otherwise stated. The implementations described in the following description of exemplary embodiments do not represent all implementations consistent with the present disclosure. Rather, they are merely illustrative of apparatus and methods consistent with aspects related to the claimed subject matter. Without limiting the scope of the present disclosure, some embodiments may be described in the context of providing detection systems and methods in systems utilizing electron beams ("e-beams"). However, the present disclosure is not so limited. Other types of charged particle beams (including, for example, protons, ions, muons, or other particles that carry an electric charge) may be applied as well. The systems and methods for detection may also be used in other imaging systems, such as optical imaging, photon detection, x-ray detection, ion detection, and the like.

[0012]

[0025] Electronic devices are built with circuits formed on a piece of semiconductor material called a substrate. Examples of semiconductor materials include silicon, gallium arsenide, indium phosphide, and silicon germanium. Many circuits can be formed on the same piece of silicon, which is called an integrated circuit, or IC. These circuits have been dramatically miniaturized, allowing more and more to fit on the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail, yet contain over 2 billion transistors, each smaller than 1 / 1000th the size of a human hair.

[0013]

[0026] The manufacture of these ICs, which have extremely small structures or components, is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. An error in even one step can cause the finished IC to be defective and unusable. Therefore, one of the goals of the manufacturing process is to avoid such defects and maximize the number of functional ICs created by the process, i.e., to increase the overall process yield.

[0014]

[0027] One element of improving yield is monitoring the chip manufacturing process to ensure that a sufficient number of functional integrated circuits are being produced. One way to monitor the process is to inspect the chip's circuit structures at various stages in their formation. Inspection can be done with a scanning charged particle microscope ("SCPM"). For example, an SCPM can be a scanning electron microscope (SEM). Using an SCPM, it is possible to image these extremely small structures, essentially taking a "picture" of the structures on the wafer. This image can be used to determine whether the structures were properly formed in the correct location. If the structures are defective, the process can be adjusted, thus reducing the likelihood that such defects will reoccur.

[0015]

[0028] The working principle of an SEM is similar to that of a camera. A camera takes pictures by receiving and recording the intensity of light reflected or emitted from a person or object. An SEM takes "pictures" by receiving and recording the energy or quantity of electrons reflected or emitted from structures on a wafer. Before taking such a "picture," an electron beam may be projected onto the structure, and as electrons are reflected or emitted ("ejected") from the structure (e.g., from the wafer surface, from structures below the wafer surface, or both), a detector in the SEM may receive and record the energy or quantity of those electrons to generate an inspection image. To take such a "picture," the electron beam may be scanned (e.g., line-by-line or zig-zag) across the wafer, and a detector may receive the ejected electrons that emerge from the area where the electron beam is projected (called the "beam spot"). The detector may receive and record the ejected electrons from each beam spot, one at a time, and the recorded information for all beam spots may be combined to generate an inspection image. Some SEMs use a single electron beam (called "single-beam SEM") to generate an inspection image by taking a single "photo", while others use multiple electron beams (called "multi-beam SEM") to take multiple "sub-photos" of the wafer in parallel and stitch them together to generate the inspection image. By using multiple electron beams, the SEM can apply more electron beams to the structure to obtain these multiple "sub-photos", resulting in more electrons being ejected from the structure. Thus, the detector can receive more of the ejected electrons simultaneously, allowing for more efficient and faster production of the inspection image of the wafer's structures.

[0016]

[0029] Typically, structures are created for imaging on a substrate (e.g., a silicon substrate) that is placed on a platform called a stage or electric chuck (e-chuck). The platform may include a wafer holder that surrounds the wafer. In a conventional wafer platform system, when the wafer is placed on the wafer holder, a gap is created between the edge of the wafer and the inner circle of the wafer holder. This gap causes discontinuities or distortions in the electric field at the outer portion of the wafer, including the wafer edge, which affects the performance of the SEM. In particular, the distortions in the electric field may cause defocusing, deflection, or distortion of the electron beam, which may affect the corresponding image of the wafer. In some cases, additional voltages are provided using a high voltage (HV) ring structure placed near the gap to make the electric potential at the outer portion of the wafer more uniform. The outer portion of the wafer can be considered as the peripheral area of ​​the wafer within a predetermined distance from the wafer edge. In some embodiments of the present disclosure, the outer portion may be a peripheral region of the wafer that is within 1 mm, 2 mm, 3 mm, 5 mm, 10 mm, or 20 mm of the wafer edge. However, the conductive ring may be fixed and the gap between the wafer edge and the ring may not be adjustable. Problems may arise if the wafer is not fully placed within the ring structure, for example, if the wafer is off-center. In such a situation, the conductive ring may need to provide different compensation voltages at different locations. Furthermore, in at least some conventional systems, the conductive ring may be below the wafer surface, which requires very high compensation voltages (several kV) to achieve the desired compensation performance.

[0017]

[0030] To overcome the above problems, the ring can be positioned so that it is flush with the top surface of the wafer and touches or is as close as possible to the wafer edge. This can result in a more uniform potential distribution near the outer portion of the wafer. However, depending on the contour of the wafer edge, the segments may not be able to fully abut the wafer. For example, chamfered edges, alignment notches, or manufacturing defects may result in a residual gap between the ring and the wafer.

[0018]

[0031] Generally, current conventional systems are unable to fully compensate for the distorted electric field or may require additional compensation elements in the electron-optical system to be adjusted to reduce the impact on image quality to an acceptable level. Thus, current wafer inspection systems and processes can experience many errors due to non-uniform electric fields near the outer portions of the wafer.

[0019]

[0032] To improve the wafer inspection process, it may be beneficial to eliminate or minimize electric field distortions at the outer portion of the wafer. According to at least some embodiments of the present disclosure, a multi-ring system is proposed. This configuration may include a first ring surrounding the wafer and a second ring surrounding the first ring. The first and second rings may therefore also be referred to as the inner and outer rings, respectively. The system may include first and second voltage sources configured to provide first and second different voltages to the inner and outer rings. The system may also include a third voltage source configured to provide a third voltage to the wafer, different from the first and second voltages. The combination of these voltages may generate a more uniform electric field at the outer portion of the wafer. The inner or outer ring may be an adjustable, segmented conductive ring. The inner or outer ring may also be implemented as a conductive film on a mirror block piece on the wafer holder.

[0020]

[0033] In this specification, unless otherwise stated, the term "or" includes all possible combinations, except where impracticable. For example, if a component is described as being able to include A or B, the component may include A, or may include B, or may include A and B, unless otherwise stated or impracticable. As a second example, if a component is described as being able to include A, B, or C, the component may include A, or may include B, or may include C, or may include A and B, or may include A and C, or may include B and C, or may include A, B, and C.

[0021]

[0034] 1 illustrates an exemplary electron beam inspection (EBI) system 100 consistent with some embodiments of the present disclosure. The EBI system 100 may be used for imaging. As shown in FIG. 1, the EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. The beam tool 104 is disposed within the main chamber 101.

[0022]

[0035] The EFEM 106 includes a first load port 106a and a second load port 106b. The EFEM 106 may include additional load port(s). The first load port 106a and the second load port 106b receive wafer front-opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other materials) to be inspected or samples (wafers and samples may be used interchangeably). A "lot" refers to multiple wafers that may be loaded for processing as a batch.

[0023]

[0036] The wafer can be transferred to the load / lock chamber 102 by one or more robot arms (not shown) in the EFEM 106. The load / lock chamber 102 is connected to a load / lock vacuum pumping system (not shown) that removes gas molecules in the load / lock chamber 102 to reach a first pressure lower than atmospheric pressure. After the first pressure is reached, the wafer can be transferred from the load / lock chamber 102 to the main chamber 101 by one or more robot arms (not shown). The main chamber 101 is connected to a main chamber vacuum pumping system (not shown) that removes gas molecules in the main chamber 101 to reach a second pressure lower than the first pressure. After the second pressure is reached, the wafer is subjected to inspection by the beam tool 104. The beam tool 104 can be a single beam system or a multi-beam system.

[0024]

[0037] The controller 109 is electronically connected to the beam tool 104. The controller 109 may be a computer configured to perform various controls of the EBI system 100. Although the controller 109 is depicted in FIG. 1 as being external to the structure including the main chamber 101, the load / lock chamber 102, and the EFEM 106, it will be understood that the controller 109 may be part of such a structure.

[0025]

[0038] In some embodiments, the controller 109 may include one or more processors (not shown). A processor may be a general-purpose or specific electronic device capable of manipulating or processing information. For example, such processors may include a central processing unit (or "CPU"), a graphics processing unit (or "GPU"), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a programmable logic array (PLA), a programmable array logic (PAL), a general purpose array logic (GAL), a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a system on a chip (SoC), an application specific integrated circuit (ASIC), and any number or combination of any type of circuitry capable of processing data. A processor may be a virtual processor, including one or more processors distributed across multiple machines or devices coupled via a network.

[0026]

[0039] In some embodiments, the controller 109 may further include one or more memories (not shown). A memory may be a general-purpose or specific electronic device capable of storing code and data accessible by a processor (e.g., via a bus). For example, such memory may include any combination of any number of random access memory (RAM), read-only memory (ROM), optical disks, magnetic disks, hard drives, solid-state drives, flash drives, security digital (SD) cards, memory sticks, compact flash (CF) cards, or any type of storage device. The code may include an operating system (OS) and one or more application programs (or "apps") for specific tasks. The memory may be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled over a network.

[0027]

[0040] FIG. 2 illustrates an exemplary imaging system 200 according to an embodiment of the present disclosure. The electron beam tool 104 of FIG. 2 can be configured for use in the EBI system 100 of FIG. 1. The electron beam tool 104 can be a single beam or a multi-beam device. As illustrated in FIG. 2, the electron beam tool 104 includes a motorized sample stage 201 and a wafer holder 202 supported by the motorized sample stage 201 and holding a wafer 203 to be inspected. The wafer holder includes a holding portion configured to hold the wafer, for example, by electrostatic attraction. The electron beam tool 104 further includes an objective lens assembly 204, an electron detector 206 (including electron sensor surfaces 206a and 206b), an objective aperture 208, a condenser lens 210, a beam limiting aperture 212, a gun aperture 214, an anode 216, and a cathode 218. The objective aperture 208 or the beam limiting aperture 212 may be, for example, an array of apertures. It is understood that the electron detector 206 may also be a single piece, for example, annular. In some embodiments, the objective lens assembly 204 may include a swing objective retarding immersion lens (SORIL) that includes a pole piece 204a, a control electrode 204b, a deflector 204c, and an excitation coil 204d. The electron beam tool 104 may further include an energy dispersive x-ray spectrometer (EDS) detector (not shown) for characterizing materials on the wafer 203.

[0028]

[0041] A primary electron beam 220 is emitted from the cathode 218 by applying an accelerating voltage between the anode 216 and the cathode 218. The primary electron beam 220 passes through a gun aperture 214 and a beam limiting aperture 212, which together determine the size of the electron beam incident on a condenser lens 210 located below the beam limiting aperture 212. The condenser lens 210 focuses the primary electron beam 220 before it enters the objective aperture 208, thereby setting the size of the electron beam before it enters the objective lens assembly 204. The deflector 204c deflects the primary electron beam 220 to facilitate beam scanning over the wafer. For example, the deflector 204c can be controlled to sequentially deflect the primary electron beam 220 to different positions on the top surface of the wafer 203 at different times during the scanning process to provide data for image reconstruction for different portions of the wafer 203. The deflector 204c can also be controlled to deflect the primary electron beam 220 at different times and at different angles of incidence to different sides of a feature at a particular location on the wafer 203. This can be used to provide data for volumetric image reconstruction of the wafer structure at that location.

[0029]

[0042] Additionally, in some embodiments, the anode 216 and cathode 218 may generate multiple primary electron beams 220, for example using a source conversion unit (not shown). The source conversion unit can change a single electron source into a virtual multi-source array. The electron beam tool 104 may further include multiple deflectors 204c to simultaneously scan the multiple primary electron beams 220 over the wafer to provide data for image reconstruction of different portions of the wafer 203. Further details of the source conversion unit are described in U.S. Pat. No. 9,691,588, which is incorporated herein by reference in its entirety.

[0030]

[0043] The excitation coil 204d and the pole piece 204a generate a magnetic field that starts at one end of the pole piece 204a and ends at the other end of the pole piece 204a. The portion of the wafer 203 scanned by the primary electron beam 220 may be immersed in this magnetic field and become electrically charged, which creates an electric field. This electric field reduces the energy of the primary electron beam 220 impinging near the surface of the wafer 203 before it hits the wafer 203. The control electrode 204b is electrically isolated from the pole piece 204a and controls the electric field on the wafer 203 to prevent micro-arcing of the wafer 203 and ensure proper beam focus.

[0031]

[0044] Upon receiving the primary electron beam 220, a portion of the wafer 203 may emit a secondary electron beam 222. The secondary electron beam 222 may form a beam spot on the sensor surfaces 206a and 206b of the electron detector 206. The electron detector 206 may generate a signal (e.g., voltage, current, etc.) representative of the intensity of the beam spot and provide this signal to the image processing system 250. The intensity of the secondary electron beam 222, and the resulting beam spot, may vary depending on the external or internal structure of the wafer 203. Furthermore, as described above, the primary electron beam 220 may be projected onto different locations on the top surface of the wafer or at different angles of incidence relative to a particular location on the wafer, thereby generating secondary electron beams 222 (and resulting beam spots) of different intensities. Thus, by mapping the intensity of the beam spot to a location on the wafer 203, the processing system may reconstruct an image reflecting the internal or surface structure of the wafer 203.

[0032]

[0045] As described above, the imaging system 200 can be used to inspect the wafer 203 on the motorized sample stage 201 and includes the electron beam tool 104. The imaging system 200 can also include an image processing system 250 including an image acquisition unit 260, a storage 270, and a controller 109. The image acquisition unit 260 can include one or more processors. For example, the image acquisition unit 260 can include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, or the like, or a combination thereof. The image acquisition unit 260 can be connected to the detector 206 of the electron beam tool 104 via a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, a wireless radio, or a combination thereof. The image acquisition unit 260 can receive signals from the detector 206 to construct an image. The image acquisition unit 260 can thus acquire an image of the wafer 203. The image acquisition unit 260 may also perform various post-processing functions such as generating contours, overlaying indicators on the acquired image, etc. The image acquisition unit 260 may also adjust the brightness and contrast of the acquired image, etc. The storage 270 may be a storage medium such as a hard disk, cloud storage, random access memory (RAM), or other type of computer readable memory. The storage 270 may be coupled with the image acquisition unit 260 and used to store the raw scanned image data as original images and to store post-processed images. The image acquisition unit 260 and the storage 270 may be connected to the controller 109. In some embodiments, the image acquisition unit 260, the storage 270, and the controller 109 may be integrated into one control unit.

[0033]

[0046] In some embodiments, the image acquisition unit 260 can acquire one or more images of the sample based on the imaging signal received from the detector 206. The imaging signal can correspond to a scanning process for performing charged particle imaging. The acquired image can be a single image including multiple imaging areas. Such a single image can be stored in the storage 270. The single image can be an original image that can be divided into multiple regions. Each region can include one imaging area that includes a feature of the wafer 203.

[0034]

[0047] In some embodiments, information from the image capture can be used to characterize the electric field distortion. For example, the image may include a characteristic type of image distortion that corresponds to the type of electric field distortion expected at the outer portion of the wafer. The image may also be compared to a reference feature layout at the outer portion of the wafer to identify the distortion.

[0035]

[0048] 3 shows a top view of an exemplary wafer system according to a comparative embodiment. The system for compensating for distortions at the outer portion of a wafer 303 includes a compensation electrode 302 between the wafer 303 and an inner side 305 of a wafer holder 301. The compensation electrode 302 is separated from the wafer 303 by a gap g. A voltage is applied to the compensation electrode to offset distortions in the potential distribution at the outer portion of the wafer 303.

[0036]

[0049] Figure 4 shows a cross-sectional view of the system of Figure 3. Here, the compensation electrode 402 is located completely below the level of the wafer 403. This arrangement requires a very high compensation voltage, for example several kV. And even with a high voltage, because there is only one electrode, the potential distribution is not ideally shaped to compensate for the distortions in the outer parts of the wafer 403. As a result, the potential distribution 409 in the region above the wafer 403 exhibits a distortion 409a in the outer parts of the wafer 403. This distortion extends beyond the wafer edge 407.

[0037]

[0050] Some comparative embodiments may include an additional electrode 412 positioned inside the wafer edge 407 and below the underside of the wafer 403. This type of additional electrode 412 is not configured to affect distortions at the outer portions of the wafer, but is configured as a shielding electrode to block the electric field 404 of the chuck electrode 413. The shielding electrode 412 cannot cooperate with the compensating electrode 402 to sufficiently reduce the electric field distortion 409a at the outer portions of the wafer 403 because its location and the voltage applied to it are selected for a different purpose.

[0038]

[0051] In some comparative examples, the top surface of the electrode 402 is located above the wafer 403, but the field compensation is still suboptimal for the reasons mentioned above. With only one electrode, there is a large shape mismatch between the field at the outer portion of the wafer and the compensation field. Therefore, the single ring system of Figures 3-4 requires SEM column adjustments at each location on the outer portion of the wafer to bring the beam shift and spot size within specifications. This process is very time consuming and negatively impacts inspection throughput.

[0039]

[0052] 5 shows a top view of a wafer system according to another comparative embodiment, where a compensation ring 502 is designed to abut the edge of and be substantially flush with the top surface of a wafer 503. According to this comparative embodiment, the voltage applied to the compensation ring 502 and the voltage applied to the wafer 503 are ideally substantially equal.

[0040]

[0053] FIG. 6 shows a cross-sectional view of the system of FIG. 5. The conductive ring 602 can be driven horizontally and vertically as indicated by the arrows to minimize the gap g and make the ring 602 flush with the top surface of the wafer 403. The potential distribution is more uniform than in the comparative embodiment of FIGS. 3-4. By closing the gap, most of the distortion 609b is shifted away from the outer portion of the wafer 603. However, the gap g cannot be completely eliminated if the inner contour of the conductive ring 602 does not perfectly match the edge of the wafer 403. For example, the wafer 603 is shown as having a chamfered edge, which prevents the ring 602 from completely abutting the wafer. This results in a residual distortion 609a in the potential distribution 609, which cannot be corrected by the system of FIGS. 5-6. Besides the chamfered wafer edge, other physical conditions can cause such distortion. For example, a registration notch or flat may cause a residual gap between the conductive ring 602 and the wafer 603. Residual gaps may also occur due to misalignment, damage, warping, or manufacturing defects in the conductive ring 602 or wafer 603.

[0041]

[0054] FIG. 7A illustrates a multi-ring system 700 according to some embodiments of the present disclosure. The multi-ring system includes a plurality of substantially concentric conductive rings. In some embodiments, the multi-ring system includes a first conductive ring 710 ("inner ring") surrounding a wafer 703 and a second conductive ring 711 ("outer ring") surrounding the inner ring 710. The wafer 703 is held on a holding portion 702 (not shown in FIG. 7A) of a wafer holder 701. An inner diameter of a portion of the inner ring 710 may be larger than an outer diameter of the wafer 703, as indicated by gap g1. An inner diameter of a portion of the outer ring 711 may be larger than an outer diameter of the inner ring 710, as indicated by gap g2. In some embodiments, more than two conductive rings are provided. For example, there may be an intermediate ring located between the inner ring 710 and the outer ring 711. The inner ring 710 or the outer ring 711 may include multiple conductive ring segments, as described further below in connection with Figures 10A-10B. The conductive ring may be formed of a conductive material, such as a metal. For example, the material may be a non-magnetic metallic material, such as titanium, aluminum, etc. Alternatively, the conductive ring may be formed by a conductive coating of such a material disposed on a non-conductive structure.

[0042]

[0055] FIG. 7B illustrates a cross-sectional view of the system of FIG. 7A according to some embodiments of the present disclosure. First and second voltage sources VS1 / VS2 may be connected to the conductive materials of the inner ring 710 and the outer ring 711, respectively. A third voltage source VS3 may be connected to the wafer 703. The first, second, and third voltage sources VS1-VS3 may each provide independent voltages to the inner ring 710, the outer ring 711, and the wafer 703, respectively, under the control of a voltage controller 720. The voltage controller 720 may be coupled to a charged particle beam device (e.g., the EBI system 100). For example, the voltage controller 720 may be the controller 109 of FIG. 2. The first voltage, the second voltage, and the third voltage, when applied to the inner ring 710, the outer ring 711, and the wafer 703, respectively, result in an associated first potential distribution, a second potential distribution, and a third potential distribution. For example, the third voltage source VS3 may be controlled to provide a third potential distribution on the surface of the wafer 703. The third potential distribution may be substantially uniform and distortion-free across a majority of the wafer surface. However, as discussed above, the third potential distribution may exhibit distortions at the outer portion of the wafer, resulting in a distorted electric field. In some embodiments of the present disclosure, the first and second voltages from the voltage sources VS1 and VS2 may be selected such that the superposition of the first and second potential distributions compensates for the third potential distribution. In this way, the superposition of all three potential distributions results in a composite potential distribution that extends uniformly across the outer portion and outward beyond the wafer edge. To achieve this result, several parameters may be optimized, including the magnitude and sign of the first and second voltages, the relative gap spacing and height of the first and second conductive rings 710 / 711 with respect to the wafer 703, etc.

[0043]

[0056] The inner ring 710 or the outer ring 711 may be fixed in position. Alternatively, the inner ring 710 or the outer ring 720 may be movable horizontally or vertically by an actuator 708 under the control of an actuation controller 750. The actuation controller 750 may be coupled to a charged particle beam device (e.g., EBI system 100). For example, the actuation controller 750 may be the controller 109 of FIG. 2. The actuation controller 750 may be a voltage controller 720 or may be coupled to a voltage controller 720 as shown in FIG. 7B. Configuring the conductive ring as a fixed element allows for a more robust and simple design, while configuring the conductive ring as a movable element allows for a more versatile system. For example, the movable ring allows for more freedom to quickly adjust for different SEM settings. Additionally, the movable ring segments may help avoid damage during wafer swapping, as discussed above. In some embodiments, both the inner ring 710 and the outer ring 711 are in fixed positions and are not segmented. Also, in some embodiments, the outer ring 711 is fixed and not segmented, while the inner ring 710 is segmented and moveable to allow for loading and unloading of the wafer 703. Also, in some embodiments, both the inner ring 710 and the outer ring 711 are moveable or have moveable segments. As will be explained further below, in a multi-ring system, the conductive rings need not be in contact with the edge of the wafer 703, but may be separated by a gap. This provides additional design freedom and allows for numerous variations.

[0044]

[0057] As shown in FIG. 7B, the positions of the inner ring 710 and the outer ring 711 may be optimized in both radial and height dimensions to achieve the appropriate relative height and gap distance. In some embodiments, the height and gap separation may range from, for example, 0.1 to 3 mm. In FIG. 7B, there is a first gap g1 between the inner ring 710 and the wafer 703, and a second gap g2 between the outer ring 711 and the inner ring 710. Also, in a multi-ring system, the top surfaces of each ring do not need to be coplanar with the wafer 703 or with each other, so optimizations may include height differences between elements. For example, there may be a first height difference h1 between the top surface of the wafer 703 and the top surface of the inner ring 710. There may also be a second height difference h2 between the top surface of the outer ring 711 and the top surface of the inner ring 710. The first height difference h1 may be greater or less than the second height difference h2. The first and second height differences hl / h2 may be positive or negative radially outward. For example, a height change that increases radially outward from the wafer can be considered a positive height difference, and a height change that decreases radially outward from the wafer can be considered a negative height difference. Because the magnitudes of the first and second potentials vary with distance from the first and second conductive rings 710 and 711, optimizing the height and gap distance can achieve very effective compensation at the outer portions of the wafer 703 without affecting the more radially inward regions of the third potential distribution. Here, "optimizing" the ring position can mean, for example, active adjustment by an actuator, proper design of a fixed arrangement, or manual adjustment offline.

[0045]

[0058] The conductive rings may be arranged in other ways than those depicted in FIG. 7B. For example, the top surfaces of the inner ring 710 and the outer ring 711 are both shown to be higher than the top surface of the wafer 703, but this need not be the case. In some embodiments, the top surface of the inner ring 710 or the outer ring 711 may be substantially at or above the bottom surface of the wafer 703, or may be substantially at or above the top surface of the holding portion 702. Furthermore, in FIG. 7B, a portion of the inner ring 710 is located below the wafer 703. However, this need not be the case. In some embodiments of the present disclosure, the innermost portion of the inner ring 710 is located radially outward of the edge of the wafer 703. In some embodiments, the inner ring 710 may include a horizontally extending portion and a vertically extending portion, with a portion of the vertically extending portion located radially inward of the edge of the wafer 703, as shown in FIG. 7B. In some embodiments, the inner ring 710 may only include a substantially vertically extending portion that is located radially inward of the edge of the wafer 703. In some embodiments, the conductive ring has other cross-sectional shapes, such as a square, a circle, an oval, or a more complex cross-sectional shape.

[0046]

[0059] In embodiments that include a movable conductive ring (or ring segment), the range of movement may include all of the possible ranges disclosed above, or only a portion of the disclosed ranges. For example, some embodiments may include a movable ring that has a vertical range of movement from, e.g., a few mm above the top surface of the wafer, to, e.g., approximately halfway between the top and bottom surfaces of the wafer.

[0047]

[0060] In addition to optimizing the spatial arrangement of the inner and outer rings 710 / 711, the magnitude and sign of the first and second voltages may be selected to compensate for the electric field at the outer portion of the wafer.

[0048]

[0061] 8A-8D illustrate possible voltage source configurations according to some embodiments of the present disclosure. In FIG. 8A, a third voltage V is applied to the wafer 803 by a third voltage source VS3 (not shown). Furthermore, the same third voltage V is applied to the inner ring 810 and the outer ring 811 by first and second voltage sources VS1-VS2 (not shown), respectively. The resultant potential distribution 809 does not exhibit an ideal flat shape at the outer portion of the wafer 803.

[0049]

[0062] In the comparative example of FIG. 8B, the wafer 803 and the outer ring 811 are still maintained at the same voltage V. However, between the wafer 803 and the outer ring 811, the inner ring 810 is maintained at a first voltage (V-V1) that is lower than V because the first voltage (V-V1) includes a first compensation voltage component (-V1). In other words, the first voltage (V-V1) is equal to the third voltage V plus the first compensation delta value (-V1). In this configuration, a distortion 809a in the resultant potential distribution 809 is seen at the outer portion of the wafer 803.

[0050]

[0063] FIG. 8C shows another possible configuration according to a comparative embodiment, where the inner ring 810 is maintained at the same voltage V as the wafer 803. The outer ring 811 is maintained at a second voltage (V+V2) higher than V because the second voltage (V+V2) includes a second compensation voltage component V2. In other words, the second voltage (V+V2) is equal to the third voltage V plus the second compensation delta value V2. In this case, the distortion 809a at the outer portion of the wafer 803 is similar to that of FIGS. 8A-8B, but opposite.

[0051]

[0064] 8D shows another possible configuration 800 consistent with embodiments of the present disclosure, where both the inner ring 810 and the outer ring 811 are held at different voltage values, both different from each other and different from the value V applied to the wafer 803. For example, a lower first compensation voltage (V-V1) may be applied to the inner ring 810, and a higher second compensation voltage (V+V2) may be applied to the outer ring 811. The delta values ​​applied to the inner and outer rings 810 / 811 may be of opposite signs. The superposition of the first and second potential distributions produced by the inner and outer rings 810 / 811 very effectively compensates for the distortion of the outer portion of the third potential distribution, producing a composite potential distribution 809 with high uniformity across the outer portion of the wafer.

[0052]

[0065] The embodiments of Figures 8A-8C disclose configurations in which one conductive ring is maintained at the same voltage as the wafer, and illustrate the distortions that may occur in association with such configurations. However, it should be understood that these distortion examples are intended to aid in the explanation of other embodiments of the present disclosure (e.g., the embodiment of Figure 8D). These examples are not intended to suggest that a voltage value equal to that of the wafer cannot be used to compensate for the potential distribution. As discussed above, the state of the resultant potential distribution at the outer portion of the wafer is a function of many factors. For example, the gap spacing or height can be selected in addition to the voltage value of the conductive ring to provide a desired potential at a desired point. In some embodiments of the present disclosure, the height, gap, and voltage configurations can be such that a uniform resultant potential distribution is achieved while maintaining the inner ring, outer ring, or other conductive ring at the same voltage as the wafer.

[0053]

[0066] 9A-9C show a multi-ring system according to some embodiments of the present disclosure. Conductive rings 910 and 911 are formed as a conductive coating on a non-conductive surface. For example, the coating can be a non-magnetic metallic material (e.g., titanium, aluminum, etc.) formed on the mirror blocks of wafer holder 901. Coatings 910 and 911 act as electrodes in a manner similar to rings 710 and 711 of FIGS. 7A-7B or rings 810 and 811 of FIGS. 8A-8D.

[0054]

[0067] Similar to the embodiment of Figure 7B, coatings 910 and 911 may be connected to independently controlled voltage sources VS1 / VS2 (not shown), which may apply voltages as described with respect to Figures 7A-7B or 8A-8D. For example, the voltage applied to coating 910 by voltage source VS1 may be greater than, less than, or equal to the voltage applied to coating 911 by voltage source VS2.

[0055]

[0068] The coatings 910 and 911 may be formed with various heights and gap distances as necessary to generate the desired compensation at the outer portion of the wafer 903. The surface on which the coatings are formed (e.g., the mirror block of the wafer holder) may similarly have a surface profile corresponding to the desired height and gap distance. For example, in FIG. 9A, the height difference h2 (not shown) between the inner ring 910 and the outer ring 911 is zero. In FIG. 9B, the height difference h2 is positive while the gap g2 (not shown) is zero. In FIG. 9C, the height difference h2 is negative while the gap g2 is zero. It will be understood that other configurations are possible as long as the coatings are arranged to enable the desired compensation at the outer portion of the wafer. For example, if the height h2 is not zero, the gap g2 may be negative. That is, there may be a radial overlap between the inner ring 910 and the outer ring 911.

[0056]

[0069] Also, the coating may not be located on the mirror blocks of the wafer holder. A single conductive ring may comprise a non-conductive ring structure onto which both the inner ring 910 and the outer ring 911 are deposited as conductive films. The non-conductive ring structure may be fixed or movable, and segmented or continuous, as described above with respect to previous embodiments.

[0057]

[0070] In general, ideal values ​​for voltage, height, gap spacing, and other parameters depend on the particular equipment settings, imaging conditions, sample (or other process) being inspected, and these values ​​also depend on each other. Appropriate values ​​may be determined through modeling or experimentation, and such values ​​may be stored, for example, in software look-up tables, for use during charged particle beam processes, such as SEM inspection of wafers. The embodiments of the present disclosure allow for rapid adjustment of spatial or electrical parameters to account for changes in process conditions based on prior information. In addition, process data may be fed back into the system to make corrections in real time during a current or subsequent process. For example, information from an image acquisition portion of an SEM inspection system may be used to characterize the field distortions at the outer portion of the wafer. Such information may include, for example, characteristic types of image distortions that correspond to expected types of field distortions at the outer portion of the wafer. Images may be compared to reference feature layouts at the outer portion of the wafer to identify the distortions. Corrections may be fed back based on the process data.

[0058]

[0071] 10A and 10B show a segmented multi-ring system according to some embodiments of the present disclosure. Providing segmented conductive rings allows for easier loading and unloading of wafers with less risk of collision. Although the following description refers to an embodiment in which only the inner ring 1010 is segmented or movable, it should be understood that the outer ring 1011 may be segmented or movable as well. Alternatively or additionally, the segmented or movable configuration may be applied to an embodiment in which both conductive rings are formed on a single structure, such as the embodiment of FIGS. 9A-9C.

[0059]

[0072] FIG. 10A shows a top view of an example system during wafer loading according to some embodiments of the present disclosure. Shown in FIG. 10A are a wafer holder 1001, a wafer 1003, a conductive outer ring 1011, and four segments (labeled 1010a-1010d) that make up a conductive inner ring 1010. The wafer 1003 is held by a holding portion (not shown) of the wafer holder. There is a gap g2 between the inside of the outer ring 1011 and the outside of the conductive ring segments 1010a-1010d. Similarly, there is a gap g1 between the inside of the conductive ring segments 1010a-1010d and the edge of the wafer 1003.

[0060]

[0073] In some embodiments, the wafer holder 1001 is kept stationary while the wafer 1003 is loaded. The four segments 1010a-1010d of the conductive ring 1010 then move radially outward towards the outer ring 1011, increasing the size of the gap g1. This helps to avoid collisions with the edge of the wafer 1003. The segments do not move outward enough to cause a collision with the outer ring 1011. The outer ring 1011 may also be segmented and movable, so that the segments of the outer ring move radially outward towards the inside 1005 of the wafer holder 1001 during or before the movement of the inner ring segments 1010a-1010d. In this way, the gap g2 is maintained at a safe size during the radial outward movement. The conductive ring segments may move individually or all at once, or in any combination. Once the wafer 1003 is loaded, the four segments 1010a-1010d of the conductive ring can be moved radially inward toward the wafer 1003 to return the gap g1 to its working size.

[0061]

[0074] In the disclosed system, a top view of the system after a wafer 1003 has been loaded is shown in Figure 10B. The conductive ring segments are brought close to the wafer 1003, and the gap g1 is again optimized for electric field compensation.

[0062]

[0075] In some embodiments, the conductive ring segments 1010a-1010d are designed to have an inner radius of curvature that is the same as the radius of the wafer 1003, resulting in a uniform gap g1 around the circumference of the wafer when the radially oriented surfaces of the segments 1010a-1010d are substantially in contact with one another to complete the conductive ring 1010. Also, the gap g2 between the outer ring 1011 and the inner ring 1010 is larger in FIG. 10B than in FIG. 10A.

[0063]

[0076] Additionally, the outer ring 1011 and the inner ring 1010 may be energized as described above, thereby causing the wafer electric field to extend continuously across the outer portion of the wafer, including the wafer edge.

[0064]

[0077] 10A and 10B show a conductive ring having four segments, it is understood that any number of segments can be used. For example, the number of segments can be as small as two. It is further understood that some of the segments can have fixed positions. For example, it is understood that segment 1010d can have a fixed radial position while other segments (i.e., segments 1010a, 1010b, and 1010c) can move radially inward and outward.

[0065]

[0078] The process of moving the conductive ring 1010 as described above can also be referred to as a conductive ring conditioning process. In some embodiments, to reduce the time required for the conductive ring conditioning process, there can be two sets of wafer holders, a first wafer holder for performing the electron beam inspection and a second wafer holder for performing the wafer loading and conductive ring conditioning process in parallel. That is, the wafer in the first wafer holder can undergo electron beam inspection, while the wafer in the second wafer holder can undergo wafer loading and conductive ring conditioning process. It is understood that once the wafer in the first wafer holder finishes the electron beam inspection, the wafer can be removed by conditioning the conductive ring and the first wafer holder can be moved to a wafer loading position to load the next wafer. During the same period, the second wafer holder can be placed in position for inspection after finishing the conductive ring conditioning process. Details of the system of Figures 10A-10B are described in U.S. Application No. 63 / 274,918, which is incorporated herein by reference in its entirety.

[0066]

[0079] FIG. 11 shows an example of experimental results comparing a single conductive ring (single mirror block electrode coating) of a comparative example with a multi-ring system (two mirror block electrode coating) according to an embodiment of the present disclosure. In addition to image misregistration from beam shift, the resolution due to spot size change is also considered. For the single mirror block coating, the resolution is reduced by 53% and the image misregistration is 100 as a normalized value in arbitrary length units. With the two mirror block coating according to an embodiment of the present disclosure, the edge field distortion can be precisely compensated by applying opposite bias voltages. The image misregistration due to beam deflection due to edge field distortion is reduced to 0.79 and the resolution is nearly identical between the wafer edge and the wafer center.

[0067]

[0080] 12 illustrates a flowchart of an example method 1200 for compensating for edge field distortion in a charged particle beam process according to an embodiment of the present disclosure. The method 1200 may be performed by a charged particle beam system (e.g., the EBI system 100 of FIG. 1). The charged particle beam system may include an edge field compensation system according to an embodiment of the present disclosure. For example, the process may utilize the systems of FIGS. 7A-7B, 8A-8D, or 9A-9C.

[0068]

[0081] In step 1210, a sample is loaded into a holder of a charged particle beam system. For example, the sample may be a wafer (e.g., wafer 703 / 803 / 903 / 1003, etc.).

[0069]

[0082] In step 1220, compensation settings for the process are obtained. The compensation settings may include specific values ​​or ranges for any of the parameters related to the edge field compensation process. The compensation settings may include voltage values ​​applied to the inner conductive ring, the outer conductive ring, the additional conductive ring, or the wafer. The compensation settings may include position settings, such as height or gap distance of a conductive ring relative to another conductive ring or the sample. The values ​​or ranges of these compensation settings may be based on, for example, instrument settings, imaging conditions, sample conditions, detection data, experiments, computer modeling, information about current or previous charged particle processes. This information may be stored in a software lookup table or other information database.

[0070]

[0083] In step 1230, a voltage is applied to the sample. This voltage may be responsible for creating a substantially uniform potential distribution across the top surface of the sample. This potential distribution may include distortions in the outer portions of the sample, which are compensated for by the first and second voltages described below.

[0071]

[0084] In step 1240, first and second compensation voltages are applied to the first and second electrodes. The first and second electrodes may be, for example, conductive rings 710 / 711, 810 / 811, or coatings 910 / 911 or 1010 / 1011. The first electrode may be an inner electrode that substantially surrounds the sample. The second electrode may be an outer ring that substantially surrounds the inner ring. The method may include applying an additional voltage to an additional electrode. The first or second electrode may be continuous or segmented. The first or second electrode may be fixed or movable. The first or second electrode may comprise a metal or other conductive material. The first or second electrode may be a conductive coating formed on a non-conductive surface.

[0072]

[0085] The first compensation voltage may be different from the t voltage or the second compensation voltage. The second compensation voltage may be different from the first compensation voltage or the voltage. For example, the first compensation voltage may be lower than the voltage, which may be lower than the second compensation voltage. In other words, the first or second compensation voltage may be equal to the voltage plus a first or second compensation delta value. The compensation delta value may be positive or negative.

[0073]

[0086] In step 1250, the charged particle beam system performs a charged particle process at the edge of the sample. For example, the charged particle beam system may be the EBI system 100 of FIG. 1. The charged particle beam process may be an SEM inspection at the outer portion of the wafer. The compensation effect of the first and second voltages on the first and second conductive rings results in a substantially uniform spread of the resultant potential distribution across the outer portion and beyond the wafer edge. As a result, the electric field at the outer portion has little or no distortion. Using the above method, a charged particle beam process with high resolution and low beam deflection due to edge effects can be performed at the outer portion of the sample.

[0074]

[0087] It will be apparent that not all steps of the method 1200 need to be performed in the order presented, and some steps may be performed simultaneously. For example, the step 1220 of obtaining compensation settings may be performed before the step 1210 of loading the sample into the charged particle beam system. The step 1240 of applying the first and second voltages may be performed before, after, or simultaneously with the step 1230 of applying the third voltage. For example, it may be beneficial to apply said voltages simultaneously with the first and second compensation voltages to reduce the risk of arcing.

[0075]

[0088] It should also be noted that the devices and systems described in connection with Figures 1-12 are not limited to use in wafer inspection. Rather, these devices and systems can be used in any system or device that includes high voltage components and adjustable mechanical assemblies and requires uniform voltage distribution or elimination of distortion near the wafer edge. For example, such systems or devices can include, but are not limited to, a SEM, a transmission electron microscope (TEM), an electron beam lithography tool, or an X-ray device.

[0076]

[0089] A non-transitory computer readable medium may be provided that stores instructions that cause a processor (e.g., a processor of the controller 109 of FIG. 1 ) to perform image processing, data processing, database management, graphic display, operate a charged particle beam instrument or another imaging device, inspect a wafer, move the conductive ring radially outward to make space for placing the wafer on the stage, place the wafer on the stage, move the conductive ring radially inward until the conductive ring is within a predetermined distance from the edge of the wafer, sense the voltage of the conductive ring and the wafer, sense the position of the conductive ring and the wafer, adjust the voltage of the conductive ring to be equal to the voltage of the wafer to create a substantially uniform electric field, adjust the position of the conductive ring to be equal to the position of the wafer so that their top surfaces are coplanar, and the like. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid state drives, magnetic tape or any other magnetic data storage medium, CD-ROMs, any other optical data storage medium, any physical medium with a pattern of holes, RAM, PROM, EPROM, FLASH-EPROM or any other flash memory, NVRAM, cache, registers, any other memory chip or cartridge, and networked versions thereof.

[0077]

[0090] The embodiments can be further described using the following clauses. 1. A system for reducing electric field distortion near an outer portion of a wafer, comprising: a wafer holder including a holding portion configured to hold a wafer having a first outer diameter; a first conductive electrode configured to surround the wafer, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; a second conductive ring having a fourth inner diameter greater than the second inner diameter configured to surround the first conductive electrode; first, second and third voltage sources, the first voltage source connected to the first conductive electrode, the second voltage source connected to the second conductive electrode, and the third voltage source connected to the wafer; a controller configured to control each of the first, second and third voltage sources to operate at a first voltage, a second voltage and a third voltage, respectively; the first voltage, the second voltage, and the third voltage are selected to reduce distortion of the electric field at an outer portion of the wafer; The system wherein the first voltage, the second voltage, and the third voltage are different from one another. 2. The system of claim 1, wherein the second voltage is lower than the first voltage. 3. The system of claim 1, wherein the second voltage is higher than the first voltage. 4. The system of claim 1, wherein the third voltage is higher than the first voltage. 5. The system of claim 1, wherein the third voltage is lower than the first voltage. 6. The system of clause 1, wherein the first conductive electrode or the second conductive electrode has a fixed position. 7. The system of claim 1, wherein the first conductive electrode and the second conductive electrode have fixed positions. 8. The system described in clause 1, wherein the first conductive electrode or the second conductive electrode is movable in a first direction. 9. The system of claim 8, wherein the first direction is a radial direction or an elevation direction. 10. The system described in clause 1, further comprising a third conductive electrode positioned between the first conductive electrode and the second conductive electrode. 11. The system of claim 1, further comprising a first gap between the second inner diameter and the first outer diameter. 12. The system of claim 1, further comprising a second gap between the third outer diameter and the fourth inner diameter. 13. A first conductive electrode comprising a first upper surface; a second conductive electrode including a second upper surface; 2. The system of claim 1, wherein the first top surface or the second top surface is configured not to be coplanar with a top surface of the wafer. 14. The system of clause 13, wherein the first top surface or the second top surface is configured to be substantially at the same height as or higher than the top surface of the wafer. 15. The system of clause 13, wherein the first upper surface or the second upper surface is configured to be substantially at the same height as or higher than the lower surface of the wafer. 16. The system of claim 13, further comprising a first height difference between the first top surface and the top surface of the wafer. 17. The system of claim 16, wherein the first height difference is a positive height difference. 18. The system of claim 16, wherein the first height difference is a negative height difference. 19. The system of clause 13, further comprising a second height difference between the first upper surface and the second upper surface. 20. The system of claim 19, wherein the second height difference is a positive height difference. 21. The system of claim 19, wherein the second height difference is a negative height difference. 22. The system described in clause 1, wherein the first conductive electrode or the second conductive electrode is a conductive ring. 23. The system of claim 22, wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material. 24. The system of claim 23, wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion. 25. The system described in clause 1, wherein the first conductive electrode or the second conductive electrode is divided into segments including a first segment and a second segment. 26. The system of claim 25, wherein the first segment is movable relative to the second segment. 27. A system for reducing electric field distortion near an outer portion of a wafer, comprising: a wafer holder including a holding portion configured to hold a wafer having a first outer diameter; a first conductive electrode configured to surround the wafer, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; a second conductive ring having a fourth inner diameter greater than the second inner diameter configured to surround the first conductive electrode; first, second and third voltage sources, the first voltage source connected to the first conductive electrode, the second voltage source connected to the second conductive electrode, and the third voltage source connected to the wafer; a controller configured to control each of the first, second and third voltage sources to operate at a first voltage, a second voltage and a third voltage, respectively; The system, wherein the first voltage, the second voltage, and the third voltage are selected to reduce distortion of the electric field at an outer portion of the wafer. 28. The system of clause 27, wherein the controller is configured to control each of the first, second and third voltage sources such that each of the first voltage, second voltage and third voltage are different from each other. 29. The system of claim 27, wherein the second voltage is lower than the first voltage. 30. The system of claim 27, wherein the second voltage is higher than the first voltage. 31. The system of claim 27, wherein the third voltage is higher than the first voltage. 32. The system of claim 27, wherein the third voltage is lower than the first voltage. 33. The system of clause 27, wherein the first conductive electrode or the second conductive electrode has a fixed position. 34. The system of claim 27, wherein the first conductive electrode and the second conductive electrode have fixed positions. 35. The system of claim 27, wherein the first conductive electrode or the second conductive electrode is movable in a first direction. 36. The system of claim 35, wherein the first direction is a radial direction or an elevation direction. 37. The system of clause 27, further comprising a third conductive electrode positioned between the first conductive electrode and the second conductive electrode. 38. The system of clause 27, further comprising a first gap between the second inner diameter and the first outer diameter. 39. The system of clause 27, further comprising a second gap between the third outer diameter and the fourth inner diameter. 40. A first conductive electrode including a first upper surface; a second conductive electrode including a second upper surface; 28. The system of claim 27, wherein the first top surface or the second top surface is configured not to be coplanar with a top surface of the wafer. 41. The system of clause 40, wherein the first top surface or the second top surface is configured to be substantially at the same height as or higher than the top surface of the wafer. 42. The system of clause 40, wherein the first upper surface or the second upper surface is configured to be substantially at the same height as or higher than the lower surface of the wafer. 43. The system of clause 40, further comprising a first height difference between the first top surface and the top surface of the wafer. 44. The system of claim 43, wherein the first height difference is a positive height difference. 45. The system of claim 43, wherein the first height difference is a negative height difference. 46. ​​The system of clause 40, further comprising a second height difference between the first upper surface and the second upper surface. 47. The system of claim 46, wherein the second height difference is a positive height difference. 48. The system of claim 46, wherein the second height difference is a negative height difference. 49. The system of claim 27, wherein the first conductive electrode or the second conductive electrode is a conductive ring. 50. The system of claim 49, wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material. 51. The system of claim 50, wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion. 52. The system of clause 27, wherein the first conductive electrode or the second conductive electrode is divided into segments including a first segment and a second segment. 53. The system of claim 52, wherein the first segment is movable relative to the second segment. 54. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device, the instructions comprising: loading a wafer having a first outer diameter into a wafer holder including a retaining portion; applying a first voltage to a first conductive electrode surrounding the retention portion, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; applying a second voltage to a second conductive electrode surrounding the first conductive electrode, the second conductive electrode having a fourth inner diameter greater than the second inner diameter; and applying a third voltage to the wafer, the first voltage, the second voltage, and the third voltage are selected to reduce distortion of the electric field at an outer portion of the wafer; A non-transitory computer-readable medium that causes a device to perform a method, wherein the first voltage, the second voltage, and the third voltage are different from one another. 55. The non-transitory computer-readable medium of clause 54, wherein the second voltage is lower than the first voltage. 56. The non-transitory computer-readable medium of clause 54, wherein the second voltage is higher than the first voltage. 57. The non-transitory computer-readable medium of clause 54, wherein the third voltage is higher than the first voltage. 58. The non-transitory computer-readable medium of clause 54, wherein the third voltage is less than the first voltage. 59. The non-transitory computer-readable medium of clause 54, wherein the first conductive electrode or the second conductive electrode has a fixed position. 60. The non-transitory computer-readable medium of clause 54, wherein the first conductive electrode and the second conductive electrode have fixed positions. 61. The non-transitory computer-readable medium of clause 54, wherein a set of instructions executable by at least one processor of the device further causes the device to move the first conductive electrode or the second conductive electrode in a first direction. 62. The non-transitory computer-readable medium of clause 61, wherein the first direction is a radial direction or a height direction. 63. The non-transitory computer-readable medium of clause 54, wherein the set of instructions executable by at least one processor of the device further causes the device to apply a fourth voltage to a third conductive electrode positioned between the first conductive electrode and the second conductive electrode. 64. The non-transitory computer-readable medium of clause 54, wherein a first gap exists between the second inner diameter and the first outer diameter. 65. The non-transitory computer-readable medium of clause 54, wherein a second gap exists between the third outer diameter and the fourth inner diameter. 66. A first conductive electrode includes a first upper surface; a second conductive electrode including a second upper surface; 55. The non-transitory computer-readable medium of clause 54, wherein the first top surface or the second top surface is not coplanar with the top surface of the wafer. 67. The non-transitory computer-readable medium of clause 66, wherein the first top surface or the second top surface is substantially at the same height as the top surface of the wafer or is higher than the top surface of the wafer. 68. The non-transitory computer-readable medium of clause 66, wherein the first upper surface or the second upper surface is configured to be substantially at the same height as the lower surface of the wafer or higher than the lower surface of the wafer. 69. The non-transitory computer-readable medium of clause 66, wherein a first height difference exists between the first top surface and the top surface of the wafer. 70. The non-transitory computer-readable medium of clause 69, wherein the first height difference is a positive height difference. 71. The non-transitory computer-readable medium of clause 69, wherein the first height difference is a negative height difference. 72. The non-transitory computer-readable medium of clause 66, wherein a second height difference exists between the first upper surface and the second upper surface. 73. The non-transitory computer-readable medium of clause 72, wherein the second height difference is a positive height difference. 74. The non-transitory computer-readable medium of clause 72, wherein the second height difference is a negative height difference. 75. The non-transitory computer-readable medium of clause 54, wherein the first conductive electrode or the second conductive electrode is a conductive ring. 76. The non-transitory computer-readable medium of clause 54, wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material. 77. The non-transitory computer-readable medium of clause 76, wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion. 78. The non-transitory computer-readable medium of clause 54, wherein the first conductive electrode or the second conductive electrode is divided into segments including a first segment and a second segment. 79. The non-transitory computer-readable medium of clause 78, wherein the set of instructions executable by at least one processor of the device further causes the device to move the first segment relative to the second segment. 80. Loading a wafer having a first outer diameter into a wafer holder including a retaining portion; applying a first voltage to a first conductive electrode surrounding the retention portion, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; applying a second voltage to a second conductive electrode surrounding the first conductive electrode, the second conductive electrode having a fourth inner diameter greater than the second inner diameter; applying a third voltage to the wafer; The method, wherein the first voltage, the second voltage, and the third voltage are different from one another. 81. The method of clause 80, further comprising selecting the first voltage, the second voltage, and the third voltage to reduce distortion of the electric field at an outer portion of the wafer. 82. The method of clause 80, wherein the second voltage is lower than the first voltage. 83. The method of clause 80, wherein the second voltage is higher than the first voltage. 84. The method of claim 80, wherein the third voltage is higher than the first voltage. 85. The method of clause 80, wherein the third voltage is lower than the first voltage. 86. The method of clause 80, wherein the first conductive electrode or the second conductive electrode has a fixed position. 87. The method of clause 80, wherein the first conductive electrode and the second conductive electrode have fixed positions. 88. The method of clause 80, further comprising moving the first conductive electrode or the second conductive electrode in a first direction. 89. The method of claim 88, wherein the first direction is a radial direction or a height direction. 90. The method of clause 80, further comprising applying a fourth voltage to a third conductive electrode positioned between the first conductive electrode and the second conductive electrode. 91. The method of clause 80, wherein a first gap exists between the second inner diameter and the first outer diameter. 92. The method of clause 80, wherein a second gap exists between the third outer diameter and the fourth inner diameter. 93. A first conductive electrode including a first upper surface; a second conductive electrode including a second upper surface; The method of claim 80, wherein the first top surface or the second top surface is not coplanar with a top surface of the wafer. 94. The method of clause 93, wherein the first top surface or the second top surface is substantially at the same height as or higher than the top surface of the wafer. 95. The method of clause 93, wherein the first upper surface or the second upper surface is configured to be substantially flush with or higher than the lower surface of the wafer. 96. The method of claim 93, wherein a first height difference exists between the first top surface and the top surface of the wafer. 97. The method of claim 96, wherein the first height difference is a positive height difference. 98. The method of claim 96, wherein the first height difference is a negative height difference. 99. The method of claim 93, wherein a second height difference exists between the first upper surface and the second upper surface. 100. The method of claim 99, wherein the second height difference is a positive height difference. 101. The method of claim 99, wherein the second height difference is a negative height difference. 102. The method of clause 80, wherein the first conductive electrode or the second conductive electrode is a conductive ring. 103. The method of claim 80, wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material. 104. The method of clause 103, wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion. 105. The method of claim 80, wherein the first conductive electrode or the second conductive electrode is divided into segments, including a first segment and a second segment. 106. The method of clause 105, wherein the set of instructions executable by at least one processor of the device further causes the device to move the first segment relative to the second segment. 107. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device, the instructions comprising: loading a wafer having a first outer diameter into a wafer holder including a retaining portion; applying a first voltage to a first conductive electrode surrounding the retention portion, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; applying a second voltage to a second conductive electrode surrounding the first conductive electrode, the second conductive electrode having a fourth inner diameter greater than the second inner diameter; and applying a third voltage to the wafer, A non-transitory computer-readable medium that causes a device to perform a method, wherein the first voltage, the second voltage, and the third voltage are different from one another. 108. The non-transitory computer-readable medium of clause 107, wherein the set of executable instructions further causes the device to select the first voltage, the second voltage, and the third voltage to reduce distortion of the electric field at an outer portion of the wafer. 109. The non-transitory computer-readable medium of clause 107, wherein the second voltage is less than the first voltage. 110. The non-transitory computer-readable medium of clause 107, wherein the second voltage is higher than the first voltage. 111. The non-transitory computer-readable medium of clause 107, wherein the third voltage is higher than the first voltage. 112. The non-transitory computer-readable medium of clause 107, wherein the third voltage is less than the first voltage. 113. The non-transitory computer-readable medium of clause 107, wherein the first conductive electrode or the second conductive electrode has a fixed position. 114. The non-transitory computer-readable medium of clause 107, wherein the first conductive electrode and the second conductive electrode have fixed positions. 115. The non-transitory computer-readable medium of clause 107, wherein the set of instructions executable by at least one processor of the device further causes the device to move the first conductive electrode or the second conductive electrode in a first direction. 116. The non-transitory computer-readable medium of clause 115, wherein the first direction is a radial direction or a height direction. 117. The non-transitory computer-readable medium of clause 107, wherein the set of instructions executable by at least one processor of the device further causes the device to apply a fourth voltage to a third conductive electrode positioned between the first conductive electrode and the second conductive electrode. 118. The non-transitory computer-readable medium of clause 107, wherein a first gap exists between the second inner diameter and the first outer diameter. 119. The non-transitory computer-readable medium of clause 107, wherein a second gap exists between the third outer diameter and the fourth inner diameter. 120. A first conductive electrode including a first upper surface; a second conductive electrode including a second upper surface; The non-transitory computer-readable medium of clause 107, wherein the first top surface or the second top surface is not coplanar with the top surface of the wafer. 121. The non-transitory computer-readable medium of clause 120, wherein the first top surface or the second top surface is substantially at the same height as the top surface of the wafer or is higher than the top surface of the wafer. 122. The non-transitory computer-readable medium of clause 120, wherein the first top surface or the second top surface is configured to be substantially flush with the bottom surface of the wafer or higher than the top surface of the wafer. 123. The non-transitory computer-readable medium of clause 120, wherein a first height difference exists between the first top surface and the top surface of the wafer. 124. The non-transitory computer-readable medium of clause 123, wherein the first height difference is a positive height difference. 125. The non-transitory computer-readable medium of clause 123, wherein the first height difference is a negative height difference. 126. The non-transitory computer-readable medium of clause 120, wherein a second height difference exists between the first upper surface and the second upper surface. 127. The non-transitory computer-readable medium of clause 126, wherein the second height difference is a positive height difference. 128. The non-transitory computer-readable medium of clause 126, wherein the second height difference is a negative height difference. 129. The non-transitory computer-readable medium of clause 107, wherein the first conductive electrode or the second conductive electrode is a conductive ring. 130. The non-transitory computer-readable medium of clause 107, wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material. 131. The non-transitory computer-readable medium of clause 130, wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion. 132. The non-transitory computer-readable medium of clause 107, wherein the first conductive electrode or the second conductive electrode is divided into segments, including a first segment and a second segment. 133. The non-transitory computer-readable medium of clause 133, wherein the set of instructions executable by at least one processor of the device further causes the device to move the first segment relative to the second segment.

[0078]

[0091] The block diagrams included in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or part of code that includes one or more executable instructions for implementing a certain logical function. It should be understood that in some alternative implementations, the functions shown in the blocks may occur in a different order than the order described in the figures. For example, two blocks shown in succession may be executed or performed substantially simultaneously, or the two blocks may be executed in the reverse order depending on the related functionality. Also, some blocks may be omitted. It should be further understood that each block of the block diagram, and combinations of blocks, may be implemented by a dedicated hardware-based system that performs a certain function or operation, or by a combination of dedicated hardware and computer instructions.

[0079]

[0092] It will be understood that the embodiments of the present disclosure are not limited to the precise configurations described above and illustrated in the accompanying drawings, and that various modifications and variations are possible without departing from the scope thereof.

Claims

1. 1. A system for reducing electric field distortion near an outer portion of a wafer, comprising: a wafer holder including a holding portion configured to hold a wafer having a first outer diameter; a first conductive electrode configured to surround the wafer, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; a second conductive ring having a fourth inner diameter larger than the second inner diameter configured to surround the first conductive electrode; first, second and third voltage sources, a first voltage source connected to the first conductive electrode, a second voltage source connected to the second conductive electrode, and a third voltage source connected to the wafer; a controller configured to control each of the first, second, and third voltage sources to operate at a first voltage, a second voltage, and a third voltage, respectively; the first voltage, the second voltage, and the third voltage are selected to reduce distortion of an electric field at the outer portion of the wafer; The system wherein the first voltage, the second voltage, and the third voltage are different from one another.

2. The system of claim 1 , wherein the second voltage is higher than the first voltage.

3. The system of claim 1 , wherein the third voltage is greater than the first voltage.

4. The system of claim 1 , wherein the first conductive electrode or the second conductive electrode has a fixed position.

5. The system of claim 1 , wherein the first conductive electrode or the second conductive electrode is movable in a first direction.

6. The system of claim 5 , wherein the first direction is a radial direction or an elevation direction.

7. the first conductive electrode includes a first upper surface; the second conductive electrode includes a second upper surface; The system of claim 1 , wherein the first top surface or the second top surface is configured not to be coplanar with a top surface of the wafer.

8. The system of claim 7 , wherein the first top surface or the second top surface is configured to be substantially flush with or higher than a top surface of the wafer.

9. The system of claim 7 further comprising a first height difference between the first top surface and a top surface of the wafer.

10. The system of claim 1 , wherein the first conductive electrode or the second conductive electrode is a conductive ring.

11. The system of claim 10 , wherein the first conductive electrode or the second conductive electrode is a conductive coating on a non-conductive material.

12. The system of claim 11 , wherein the non-conductive material is a portion of the wafer holder that surrounds the holding portion.

13. The system of claim 1 , wherein the first conductive electrode or the second conductive electrode is divided into segments, including a first segment and a second segment.

14. The system of claim 13 , wherein the first segment is movable relative to the second segment.

15. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a device, comprising: The instruction: loading a wafer having a first outer diameter into a wafer holder including a retaining portion; applying a first voltage to a first conductive electrode surrounding the retention portion, the first conductive electrode having a second inner diameter and a third outer diameter, the second inner diameter being greater than the first outer diameter; applying a second voltage to a second conductive electrode surrounding the first conductive electrode, the second conductive electrode having a fourth inner diameter greater than the second inner diameter; and applying a third voltage to the wafer, the first voltage, the second voltage, and the third voltage are selected to reduce distortion of an electric field at the outer portion of the wafer; 11. A non-transitory computer-readable medium that causes the device to perform a method, wherein the first voltage, the second voltage, and the third voltage are different from one another.

Images