Optical Multi-Die Interconnect Bridge (OMIB)

Abstract

The package includes a bridge element (OMIB) and first and second photonic pathways forming a bidirectional photonic pathway. The OMIB has first and second interconnect regions that connect with one or more dies. Third and fourth unidirectional photonic pathways may couple between the first interconnect region and an optical interface (OI). The photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes a computational element around a central region in close proximity to the second portion. The OMIB may include germanium, silicon, an alloy of germanium, an alloy of silicon, an indium phosphide (InP)-based III-V material, or a gallium arsenide (GaAs)-based III-V material. The OMIB may include temperature compensation for the modulator.

Description

[Technical field]

[0001] This application is a continuation of U.S. provisional patent application entitled “Optical, Multi-Die Interconnect Bridge (OMIB),” filed on February 27, 2023. No. 63 / 448,585 This application claims priority to U.S. Provisional Patent Application No. 63 / 420,330, entitled “Thermally Stable Optical Modulation Elements Coupled to Electronic Elements,” filed October 28, 2022, and U.S. Provisional Patent Application No. 63 / 321,453, entitled “Photonic Memory Fabric for System Memory Interconnection,” filed March 18, 2022. These priority applications are incorporated by reference herein as if fully set forth herein.

[0002] Each publication, patent, and / or patent application mentioned in this specification is herein incorporated by reference in its entirety to the same extent as if each individual publication and / or patent application was specifically and individually indicated by reference.

[0003] The disclosed implementations relate generally to devices and methods used for interconnecting semiconductor dies, and more particularly, to devices and methods for optical interconnection with integrated circuits and / or external chiplets. [Background technology]

[0004] The subject matter discussed in this section should not be assumed to be prior art merely as a result of its reference in this section. Similarly, it should not be assumed that problems related to the subject matter mentioned in this section or provided as background have been previously recognized in the prior art. The subject matter in this section is merely representative of various approaches, which may themselves correspond to the implementation of the claimed technology.

[0005] Integrated circuits (ICs) having processors, especially those for performing artificial intelligence and machine learning functions, move large amounts of data between one or more processor ICs and one or more memory ICs. Chiplets can help interconnect processor dies, memory dies, and other circuits to increase bandwidth and reduce latency and power consumed in the process. Summary of the Invention

[0006] Processing AI workloads often involves dedicated hardware. Typical hardware bridges two chips with an electrical interconnect that consumes high power, has pin-count limitations, and can only bring data to the edge of the chip. If the memory is in the central region of the chip, it requires signals to travel an extra distance every time the processor accesses the memory by sending a request from outside the chip to the edge of the chip. This is highly inefficient and makes it difficult for AI computing hardware to keep up with the demands required by AI applications.

[0007] In a first aspect, an implementation provides a package including a bridge element, a first unidirectional photonic path, and a second unidirectional photonic path. The bridge element includes a first interconnect region and a second interconnect region, both configured to electrically connect with one or more dies. The unidirectional photonic path couples in opposite directions between the two interconnect regions. The third and fourth unidirectional photonic paths may bidirectionally couple between the first interconnect region and an optical interface (OI). A first portion of a photonic transceiver may be coupled to the first interconnect region to transmit a first optical signal via the first unidirectional photonic path and receive a second optical signal via the second unidirectional photonic path. The first portion of the photonic transceiver may be further configured to transmit a third optical signal via the third unidirectional photonic path and receive a fourth optical signal via the fourth unidirectional photonic path. The first portion of the photonic transceiver may reside in a photonic integrated circuit (PIC) and the second portion of the photonic transceiver may reside in an electrical integrated circuit (EIC). The first and second portions may be coupled via an electrical interconnect less than 2 mm in length. The modulator may be an electroabsorption modulator fabricated in germanium, silicon, alloys of germanium, alloys of silicon, indium phosphide (InP)-based III-V materials, or gallium arsenide (GaAs)-based III-V materials. The EIC may include two or more computational elements around a central region. The second portion is proximate to one of the computational elements.

[0008] A further understanding of the nature and advantages of specific implementations disclosed herein may be realized by reference to the remaining portions of the specification and the attached drawings.

[0009] The present invention will now be described with reference to the drawings. [Brief description of the drawings]

[0010] [Figure 1]FIG. 2 is a top view of a wafer and die that includes, or may be included in, one or more microelectronic packages with OMIBs according to various implementations. [Diagram 2] 1 illustrates an exemplary OMIB with two bridging dies. [Diagram 3] 1 illustrates an exemplary package in which two dies can be coupled via electrical interconnects. [Figure 4] 1 illustrates an exemplary package in which two dies can be coupled via electrical interconnects. [Figure 5A-5E] 1 illustrates an exemplary package that employs an optical engine to provide an optical signal for use by a photonic network. [Figure 6] 1 illustrates a perspective view of an exemplary OMIB bridging two dies and mated with a light engine. [Figure 7A] 1 illustrates a perspective view of an exemplary OMIB that bridges two dies and receives unmodulated light from a chiplet light engine (CLE). [Figure 7B] 1 illustrates an exemplary package in which CLE can be used. [Figure 8A] FIG. 2 illustrates an example OMIB with a photonic link capable of connecting two dies in a package in accordance with some implementations. [Figure 8B] 1 illustrates one implementation having two OMIBs coupled between a first die and a second die. [Figure 9] FIG. 2 illustrates an example system of a link using WDM for communication from a die to an external device in accordance with some implementations. [Figure 10] 10 illustrates an example reverse channel for the WDM system of FIG. 9 in accordance with some implementations. [Figure 11] 1 illustrates an exemplary unidirectional logical channel comprising multiple photonic links. [Figure 12] 12 illustrates the transfer of an exemplary 8-word message on the unidirectional logical channel of FIG. 11 . [Figure 13]1 illustrates an exemplary AMS block in detail. [Figure 14A] Illustrates the placement of three OMIBs that bridge portions of two dies. [Figure 14B] 1 shows an example arrangement of five dies bridged by an OMIB. [Figure 14C] 1 shows an example arrangement of dies bridged by both OMIB and electrical bridges. [Figure 14D] 1 illustrates an exemplary offset checkerboard for OMIB bridging die in two dimensions. [Figure 15] 1 is a flowchart illustrating an example method of manufacturing an OMIB in accordance with various implementations. [Figure 16] 1 illustrates components of an exemplary system in which one or more OMIBs may be used. [Figures 17A-17D] An example of an EIC / OMIB combination that uses temperature compensation to extend the temperature range of the modulator in the OMIB is shown. [Figure 18] 18 illustrates an exemplary method 1800 for manufacturing a system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the drawings, like reference numbers may indicate functionally similar elements. The systems and methods illustrated in the drawings and described in the following detailed description could be arranged and designed in a wide variety of different implementations. Neither the drawings nor the detailed description are intended to limit the scope of the claimed subject matter. Rather, they are merely representative of various implementations of the present invention.

[0012] Processing AI workloads often involves dedicated hardware. Typical hardware bridges two chips with an electrical interconnect that consumes high power, has pin-count limitations, and can only bring data to the edge of the chip. If the memory is in the central region of the chip, it requires signals to travel an extra distance every time the processor accesses the memory by sending a request from outside the chip to the edge of the chip. This is highly inefficient and makes it difficult for AI computing hardware to keep up with the demands required by AI applications.

[0013] This document discloses an optical multi-die interconnect bridge element (OMIB). The OMIB may be used as a bridge between semiconductor dies, e.g., electrical integrated circuits (EICs). The bridge may include an OMIB alone or in combination with a substrate coupled to or having an OMIB embedded therein. Using an OMIB for a multi-die processing system solves many of the problems associated with processing AI workloads, including latency, power, and bandwidth. A photonic receiver may include two parts, e.g., a first part in the OMIB that includes a modulator and / or photodetector, and a second part in the EIC that includes an AMS block as described later in this specification.

[0014] In various configurations, the OMIB can transmit or receive photonic signals to carry data. Memory, such as a cache, may be located in a central region of the EIC die within two millimeters (2 mm) of the AMS block, and a photonic transmitter in the OMIB is proximate to an edge of the memory directly above or below the portion of the die where the edge of the memory is located. The central region may intersect the center of the EIC die. Computational elements, such as a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), etc., may also be advantageously located in the central region of the die within two millimeters (2 mm) of where the photonic transmitter is located, or in spatial conjunction with the memory. Photonic ICs are avoided from reaching the center of the die of the connecting chip due to heat generated by the connecting chip. The photonic chip may have a limited temperature range within which the modulator functions within specifications. One of the reasons the OMIB in the disclosed technology is able to reach the center of the die is due to the use of thermally stabilized modulators such as those described in U.S. Provisional Patent Application No. 63 / 420,330, entitled "Thermally Stable Optical Modulation Elements Coupled to Electronic Elements."

[0015] As a result, OMIB is faster and uses less power compared to conventional systems. Latency is improved by transporting data photonically to the computation point instead of to the edge of the die. This allows the die to save electrical pipeline stages and use fewer electrical connections to transport data from the edge of the chip to the interior where the memory is located. Moving data electrically from the edge of the die to the interior requires a slower, more power-hungry path for the data. When a typical system is used to train AI models, the benefits of moving data photonically to the computation point are continually replicated, resulting in substantial savings and / or feasibility of these types of complex AI systems. term

[0016] This specification may use perspective-based descriptions, such as top / bottom, inside / outside, above / below, etc. Such descriptions are used merely for ease of discussion and are not intended to limit application of the implementations described herein to any particular orientation.

[0017] As used herein, the phrase "one of" should be construed to mean only one of the listed items. For example, the phrase "one of A, B, and C" should be construed to mean either A only, B only, or C only.

[0018] As used herein, the phrase "at least one of" should be interpreted to mean one or more items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" should be interpreted to mean any combination of A, B, and / or C.

[0019] Unless otherwise specified, the use of ordinal adjectives such as "first," "second," "third," etc. to describe objects refers merely to different instances or classes of the object and does not indicate a rank or order.

[0020] The term "coupled" is used in the operational sense and is not limited to direct or indirect coupling. "Coupled to" is generally used to mean directly coupled, while "coupled with" is generally used to mean directly or indirectly coupled. "Coupling" in electronic systems may refer to a configuration that allows the flow of information, signals, data, or physical quantities, such as electrons, between two elements that are coupled to or connected to each other. In some cases, this flow may be unidirectional, while in other cases, the flow may be bidirectional or multidirectional. Coupling may be galvanic (meaning in this context that there is a direct electrical connection), capacitive, inductive, electromagnetic, optical, or via any other process allowed by physics.

[0021] The term "connected" is used to indicate a direct connection between the things that are connected, for example an electrical, optical, electromagnetic, or mechanical connection, without an intermediary or device.

[0022] The term "configured to" perform one or more tasks is a broad description of a structure generally meaning "having circuitry" to perform one or more tasks in operation. In this manner, the described items may be configured to perform a task even when the unit / circuit / component is not currently on or active. In general, the circuitry forming the structure corresponding to "configured" may include hardware circuits and may further be controlled by switches, fuses, bond wires, metal masks, firmware, and / or software. Similarly, for convenience herein, various items may be described as performing one or more tasks. Such descriptions should be construed as including the expression "configured to."

[0023] As used herein, the term "based on" is used to describe one or more factors that influence the decision. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based only on the specified factors, or on the specified factors as well as other factors that are not specified. Consider the phrase "determining A based on B." This phrase specifies that B is a factor that is used to determine A or that influences the decision of A. This phrase does not exclude that the decision of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations in which A is determined only based on B. Thus, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0024] A "processor" includes any suitable hardware system, mechanism, or component that processes data, signals, or other information. A processor may include a general-purpose central processing unit, multiple processing units, dedicated circuitry for implementing functions, or other systems. Examples of processing systems may include servers, clients, end-user devices, routers, switches, network storage, etc. A "computer" may be any processor in communication with a memory. The memory may be any suitable processor-readable storage medium, such as, for example, a random access memory (RAM), a read-only memory (ROM), a magnetic or optical disk, or other tangible medium suitable for storing instructions for execution by a processor.

[0025] The terms "substantially," "nearly," "approximately," "near," and "about" refer to within plus or minus 10% of the indicated value, unless expressly specified.

[0026] The following terms or acronyms are defined, at least in part, as follows:

[0027] AI-Artificial Intelligence

[0028] AMS - Analog / Mixed Signal

[0029] BGA - Ball Grid Array

[0030] A channel is one or more lanes that can be joined together.

[0031] Chiplet - An integrated circuit with a simple or specialized function used in combination with other ICs or chiplets in a multi-chip assembly.

[0032] CLE - Chiplet Light Engine

[0033] CPU - Central Processing Unit

[0034] CW - Continuous Wave

[0035] DDR Memory - Double Data Rate Memory

[0036] DFB - Distributed Fiber Bragg

[0037] DIMM - Dual In-line Memory Module

[0038] DRV-Driver

[0039] DSP - Digital Signal Processor

[0040] EAM - Electroabsorption Modulator

[0041] EIC - Electronic Integrated Circuit

[0042] EW- Evanescent Wave

[0043] FAU - Fiber Array Unit

[0044] FBG - Fiber Bragg Grating

[0045] FPGA - Field Programmable Gate Array

[0046] GC-Grating Coupler - A Coupler between Optical Fiber and On-Chip Photonic Waveguide

[0047] GPU - Graphics Processing Unit

[0048] GRIN Lens - Graded Index Lens

[0049] HBM - High Bandwidth Memory

[0050] IC - Integrated Circuit - Monolithic integrated circuit, i.e., a single semiconductor die that may be supplied as a bare die or a packaged circuit. For purposes of this specification, the term integrated circuit also includes packaged circuits that include multiple semiconductor dies, stacked dies, or multiple die substrates. Such structures are now commonplace within the industry, are produced by the same supply chain, and are often indistinguishable to the average user from monolithic circuits.

[0051] The lane includes a serializer, a link, and a deserializer.

[0052] LED - Light Emitting Diode

[0053] LDSU - Load / Store Unit

[0054] A link in this patent is the combination of a modulator, a photonic path (in an optical transmission medium), and a photodetector.

[0055] LGA - Land Grid Array

[0056] ML - Machine Learning

[0057] MLA - Microlens Array

[0058] MOD - Modulator

[0059] MZI - Mach-Zehnder Interferometer

[0060] OI - Optical Interface - An interface that uses any means for optical interfacing between a fiber and a photonic IC.

[0061] OMIB - Optical Multi-Die Interconnect Bridge

[0062] PCB - Printed Circuit Board

[0063] PCIe - PCI Express - High Speed ​​Serial Computer Expansion Bus.

[0064] PCM - Phase Change Memory

[0065] PD - light detector, e.g. photodiode.

[0066] PGA - Pin Grid Array

[0067] PIC - Photonic Integrated Circuit

[0068] QR - Quick Response

[0069] A processing device, processor, computing device, or computing element may refer to any device or part of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0070] RAM - Random Access Memory. Some varieties include Static RAM (SRAM), Dynamic RAM (DRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Conductive Bridge RAM (CBRAM).

[0071] RDL - Redistribution Layer - An extra metal layer on an IC to make bond pads available at other locations on the die.

[0072] SCM - Storage Class Memory

[0073] SLD - Superluminescent Diode

[0074] SSD - Solid State Drive

[0075] SOA - Semiconductor Optical Amplifier

[0076] TPU - Tensor Processing Unit

[0077] UCIe - Universal Chiplet Interconnect Express - An open specification for die-to-die interconnects and serial buses between chiplets.

[0078] VCSEL - Vertical Cavity Surface Emitting Laser

[0079] A waveguide is an implementation of a unidirectional photonic pathway in an optical transmission medium.

[0080] WDM - Wavelength Division Multiplexing. Implementation

[0081] Implementations herein relate to addressing power, latency, or pin count concerns by providing various OMIB configurations and various packages that include at least one OMIB. FIG. 1 is a top view of a wafer 100 and a die 102 that may include or be included in one or more microelectronic packages with an OMIB according to various implementations. The wafer 100 may be constructed of a semiconductor material and may include one or more die 102 with IC structures formed on the surface of the wafer 100. Each of the die 102 may be a unit of a semiconductor product that includes an appropriate IC. After fabrication of the semiconductor product is completed, the wafer 100 may undergo a singulation process in which the die are separated from one another to provide individual "chips" of the semiconductor product. The die 102 and at least one other die may be included in a microelectronic package with an OMIB.

[0082] The OMIB may be formed in a second process using a second wafer (not shown) in a manner similar to the fabrication of the die 102. The OMIB is a photonic integrated circuit (PIC) with optical components fabricated therein, as opposed to the die 102, which is an electronic integrated circuit (EIC) and generally has electronic elements fabricated therein. The OMIB may be embedded in a package substrate. The package substrate may be considered to be a cored or coreless substrate. The package substrate may include one or more layers of dielectric material, which may be organic or inorganic. The package substrate may further include one or more conductive elements, such as vias, pads, traces, microstrips, striplines, and the like. The conductive elements may be in or on the surface of the package substrate. In general, the conductive elements may enable routing of signals through the package substrate or between elements coupled to the package substrate. In some implementations, the package substrate may be, for example, a printed circuit board (PCB), an interposer, a motherboard, or some other type of substrate.

[0083] FIG. 2 shows an example of an OMIB with two bridging dies. The OMIB 200 formed in the second stage of the manufacturing process may share a dimension (horizontal or vertical) with each die 102 formed in the first stage of the manufacturing process. The dies may be as large as possible within the size limitations of the reticle used in the manufacturing. In FIG. 2, the die 102 has a width corresponding to the maximum reticle width MRW1 of the EIC reticle and a height corresponding to the maximum reticle height MRH1 of the EIC reticle, and the OMIB 200 has a width corresponding to the maximum reticle width MRW2 of the PIC reticle. This may be for convenience and cost reduction during manufacturing and is not a limitation to the various implementations.

[0084] In some implementations, the wafer 100 or die 102 may include memory devices, computational devices, or both (e.g., random access memory (RAM) devices (e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, or conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, NOR, or EXOR gates), NAND flash memory, solid state device (SSD) memory, NOR flash memory, CMOS memory, thin film transistor-based memory, phase change memory (PCM), storage class memory (SCM), magnetoresistive memory (MRAM), resistive RAM, DRAM, high bandwidth memory (HBM), DDR-based DRAM, DIMM memory, CPU, GPU, MPU, tensor engine, load / store unit (LDSU), neural computation engine, dot product and / or convolution engine, field programmable gate array (FPGA), AI accelerator, or any other suitable circuit element). Multiple of these devices may be combined on a single die 102. For example, die 102 may include memory with multiple memory arrays, one or more processors, other logic, communication circuits, and power management functions, and may execute instructions stored in the memory arrays or otherwise interact with the memory arrays using the processors on die 102.

[0085] FIG. 3 illustrates an exemplary package 300 in which a die 310 and a die 320 may be coupled via electrical interconnects. The package 300 includes an OMIB 330 that serves as a bridge between the die 310 and the die 320. An optional substrate 340 is coupled to the OMIB 330 such that the OMIB 330 is embedded in the substrate 340. Although shown as being flush in FIG. 3, the OMIB 330 may not be flush with the surface of the substrate 340, but rather may protrude at least partially from the substrate 340 or may be embedded in an inner layer of the substrate 340. The various elements illustrated may be on or at least partially protrude from the surface of the OMIB 330 or the die 310 and / or 320. Also, the specific number of elements, interconnects, die, and other devices may vary in other implementations. In some implementations, the package may include an adhesive, a sealant, an underfill material, a molding material, an overmold material, or some other structural or dielectric material. In some implementations, certain elements may be located at different positions in the signal path relative to other elements. An optical interface (OI) 350 is included on the surface of OMIB 330. Optical interface 350 may couple to optical engine 370 to receive unmodulated light via fiber(s) 360 and / or to external device optical interfaces to exchange modulated and / or unmodulated light in either direction. In addition to optical interface 350, there may be one or more electrical interfaces on the surface of OMIB 330 for interfacing with external electrical devices.

[0086] Various implementations can use different types of light engines. The light engines can be external to the OMIB or integrated into the OMIB. Exemplary implementations can use the following light engines to bring signals to and from a package that includes the OMIB 330: Laser Diodes - These are highly coherent light sources that produce narrower beams of light and are widely used in photonic chips for data communication and sensing applications; Light Emitting Diodes (LEDs) - A type of diode that emits light when an electric current passes through it (widely used for photonic chips due to their low cost, small size, and long life); Superluminescent Diodes (SLDs) - SLDs are similar to LEDs but emit a wider broadband light spectrum (SLDs are used for applications such as light amplification, applications such as wavelength division multiplexing, and fiber optic sensing); Vertical Cavity Surface Emitting Lasers (VCSELs) - these are lasers that emit light perpendicular to the chip surface, making them ideal for applications in photonics (VCSELs are used widely in data communication and sensing applications, e.g., 3D sensing, LIDAR, and data center interconnect); and Silicon Photonics - devices that use the light propagation properties of silicon to create light sources on silicon chips (Silicon photonics has the potential to revolutionize photonics by reducing the size, cost, and power consumption of photonic components). These are some of the most commonly used light sources with packages including OMIB330. The choice of light engine depends on the specific requirements of the implementation, e.g., wavelength, power, modulation speed, etc.

[0087] The light engine may be located locally on the OMIB 330 or connected to the OMIB 330 via fiber 360. If integrated on the PIC, a distributed fiber Bragg (DFB) laser or quantum dot laser may be attached during processing or integrated into the native technology where possible. If remote, any packaged continuous wave (CW) laser with suitable power and spectrum for the modulation technology may be used. In one implementation, the light source is a set of DFB lasers attached to a silicon interposer and connected to the PIC via optical fiber.

[0088] Optical interface 350 is used to terminate optical fibers at the edge or top of OMIB 330 to provide optical input and / or output from an external processor or device communicatively coupled to package 300 via the fiber. The choice of OI depends on the specific requirements of the implementation, such as, for example, optical wavelength, coupling efficiency, and cost. Optical interface 350 and any other optical interfaces in OMIB 330 may include any means for optically interfacing between a fiber and a photonic IC, such as, for example, edge couplers, grating couplers (CG), graded index (GRIN) lens couplers, fiber Bragg grating (FBG) couplers, microlens array (MLA) couplers, evanescent wave (EW) couplers, adiabatic couplers, wavelength division multiplexing (WDM) couplers, prism couplers, butt couplers, end-fire couplers, and V-groove couplers.

[0089] In one implementation, the optical interface 350 includes a fiber array unit (FAU) to optically connect the OMIB to a light source and / or an optical I / O unit. An FAU is a device used in optical communication systems that combines or splits optical signals from multiple fibers into a single optical signal, respectively. FAUs can be used in a variety of applications, such as wavelength division multiplexing (WDM), parallel optical interconnects, and optical sensing. There are two main types of fiber array units that can be used: linear and circular. Linear FAUs combine or split optical signals along a straight line, while circular fiber array units combine or split optical signals in a circular configuration. Either type of fiber array unit is typically made of precision molded optical plastic or ceramic material and can have a few to hundreds of fibers arranged in a specific pattern. The choice of FAU depends on the specific requirements of the application, such as the number of fibers, fiber arrangement, wavelength of light used, and desired coupling efficiency. Each die may have an associated analog / mixed-signal (AMS) block associated with the portion of the OMIB to which it is coupled, and one or more transistors or support circuitry for routing electrical signals to the transistors, or some other IC component.

[0090] The OMIB 330 may further include one or more electrical interfaces (EIs). The OIs and EIs may be attached to the surface of the OMIB offset between the bridged dies 102 or in areas in the x or y directions that the dies 102 do not extend into. The EIs have similar functionality to the OIs, except that they give the OMIB the ability to transmit data to and from the dies via electrical connections rather than optical connections, e.g., an external I / O block may be connected to the OMIB via a wire from the EI to the external I / O block. Different types of electrical connections are possible, including wires, RDLs, etc. The electrical connections generally transmit and receive data electrically across the electrical interconnects between the EI and any of the dies bridged by the OMIB, or between the EI and the external I / O block, using a known standard or bus protocol. The electrical path between the EI and the die may be routed through the OMIB, through the substrate, or both (or in the case of an RDL, through one of the layers of the OMIB and / or substrate).

[0091] FIG. 4 illustrates an exemplary package 400 in which a die 410 and a die 420 may be coupled via electrical interconnects. Package 400 is similar to package 300 of FIG. 3 and has similar element numbers, but additionally illustrates a first photonic transceiver 432 and a second photonic transceiver 434. A portion of first transceiver 432 is within die 410 and a portion of second photonic transceiver 434 is within die 420. Another portion of first transceiver 432 is within OMIB 430 and another portion of second transceiver 434 is within OMIB 430. FIG. 4 illustrates bidirectional photonic pathways 481, 482, and 483. Bidirectional photonic pathway 483 connects first photonic transceiver 432 and second photonic transceiver 434. Bidirectional photonic pathway 483 may include two or more unidirectional photonic pathways in opposite directions to create a bidirectional pathway between two transceivers and enable optical communication and / or data movement through photonic channels in both directions between the two dies 410 and 420. Bidirectional photonic pathway 481 links photonic transceiver 432 to optical interface 450, and bidirectional photonic pathway 482 links photonic transceiver 434 to optical interface 450. Optical interface 450 is coupled to an optical engine via fiber(s) 460. Bidirectional photonic pathways 481-483 may form a photonic network within OMIB 430. Optical interface 450 may include any means for interfacing between a fiber and a photonic IC. Substrate 400 is optional.

[0092] The photonic pathway may be implemented in an optical transmission medium, which may include a waveguide on a PIC, an optical fiber or other optical transmission medium (e.g., free space optics or glass etched waveguides, etc.), or some combination of the above. Examples of optical modulators include, but are not limited to, electroabsorption modulators (EAMs), microring resonators, or any suitable optical component with sufficient thermal stability.

[0093] 5A-E show an example package that uses an optical engine to provide an optical signal for use by a photonic network. The optical engine may include a laser diode, optics, and / or control electronics. The laser diode is the laser source, and the optics are used to shape and control the output of the laser. The control electronics (not shown) provide the necessary power and modulation to the laser diode to generate the desired output. In the implementation of FIG. 5A-E, the optical engine provides the optical signal through an optical interface, such as a FAU and a GC, to a splitter, a modulator (MOD) adjacent to the AMS block of the first die, and finally a photodetector (PD) adjacent to the AMS block of the second die. If the laser is a chiplet optical engine (as described with reference to FIG. 7A), a FAU is not required and the light can be guided directly into the GC. The photonic network in the OMIB of FIG. 5A-E allows for multiple optical paths. Although FIG. 5A-E shows a GC and FAU jointly forming an optical interface, any means for interfacing between the fiber and the photonic IC may be used in the implementation.

[0094] FIG. 5A illustrates an example OMIB intra-connection 500 showing the optical path starting at the optical engine 570. FIG. 5A includes a first die 510 divided into a general purpose section 510B, which may include various processing, storage, and communication functions, and an AMS section 510A, which includes analog / mixed-signal circuitry for interfacing with the OMIB 530. FIG. 5A further includes an optional substrate 540 and optical engine 570. The AMS section 510A of the first die 510 may include a driver (DRV1) and a transimpedance amplifier (TIA1). The AMS section 520A of the second die 520 may include a driver (DRV2) and a transimpedance amplifier (TIA2).

[0095] The optical engine 570 transmits the light through a fiber array unit FAU and a grating coupler GC (or any other OI configured to receive light at an OI input and pass the received light at an OI output) into a splitter SP in the OMIB 530. The splitter SP distributes the light towards modulators MOD1 and MOD2 through two different photonic paths 531 and 532. In some implementations, a splitter or splitter tree distributes the light through more than two different photonic paths to feed additional modulators. The photonic paths may be implemented with any suitable optical transmission medium and may include a mix of waveguides and fibers.

[0096] The modulator MOD1 modulates the light received from the splitter SP with information from the driver DRV1 and transmits the modulated light to the photodetector PD2 via the photonic path 533. The photodetector PD2 converts the received light into an electrical signal for the second die 520. The modulator MOD2 modulates the light received from the splitter SP with information from the driver DRV2 and transmits the modulated light to the photodetector PD1 via the photonic path 534. The photodetector PD1 converts the received light into an electrical signal for the first die 510. In conjunction with a serializer (not shown) in the first die 510, the driver DRV1, the transimpedance amplifier TIA2, and a deserializer (not shown) in the second die 520, the modulator MOD1, the photonic path 533, and the photodetector PD1 form a data channel from the first die 510 to the second die 520.

[0097] The photonic IC OMIB 530 includes a first interconnect region, a second interconnect region, and an offset region. The first interconnect region includes a bond pad pattern located on MOD1 and PD1 that matches a bond pad pattern on the first die 510 that is located under DRV1 and TIA1, or is otherwise configured to form an electrical connection between the respective components. The second interconnect region includes a bond pad pattern located on PD2 and MOD2 that matches a bond pad pattern on the second die 520 that is located under TIA2 and DRV2, or is otherwise configured to form an electrical connection between the respective components. The offset region, detailed in FIG. 6, includes an optical interface, such as a GC / FAU. Two or more bond pads of the bond pad pattern on the first die 510 are physically and electrically coupled to two or more bond pads of the bond pad pattern in the first interconnect region, and two or more bond pads of the bond pad pattern on the second interconnect circuit are physically and electrically coupled to two or more bond pads of the bond pad pattern in the second interconnect region. One or more of the two or more bond pads on the first die 510 may be located more than one hundred microns (100 μm) from an edge of the first die 510. One or more of the two or more bond pads on the second die 520 may be located more than one hundred microns (100 μm) from an edge of the second die 520. The distance between the (bottom) surface of the first die 510 and the (top) surface of the OMIB 530 is less than 2 mm, and often less than 50 microns. The distance between the (bottom) surface of the second die 520 and the (top) surface of the OMIB 530 is less than 2 mm, and often less than 50 microns.

[0098] FIG. 5B shows the same example showing only the signal paths. The paths of non-modulated light are omitted. FIG. 5B shows one signal path in bold as follows: The interface I / F in the first die 510 sends a digital signal carrying the information to be transmitted from the general purpose part 510B of the first die 510 to the driver DRV1. The driver DRV1 converts the digital signal to an analog electrical signal suitable for driving a photonic modulator and sends the analog electrical signal to the modulator MOD1 in the OMIB 530. The modulator MOD1 sends the light modulated with the information to be transmitted to the photodetector PD2 via the photonic path 533. The photodetector PD2 converts the modulated light to a current signal and sends the current signal to the transimpedance amplifier TIA2, which amplifies the signal and converts it to a voltage signal suitable for the digital interface I / F2. The interface I / F2 converts the voltage to a digital signal suitable for processing in the general purpose part 520B of the second die 520. Similarly, information transmitted from the general purpose portion 520B of the second die 520 to the general purpose portion 510B of the first die 510 travels via I / F2, DRV2, MOD2, photonic path 534, photodetector PD1, transimpedance amplifier TIA1, and interface I / F1.

[0099] Photonic paths 533 and 534 include waveguides or other suitable optical transmission media to carry optical signals from the modulators to the photodetectors. The modulators in OMIB 530 are coupled to drivers in the AMS portion of the first or second die via copper pillars or other suitable electrical interconnects. The photodetectors in OMIB 530 are coupled to transimpedance amplifiers in the AMS portion of the first or second die via copper pillars or other suitable electrical interconnects. The photonic paths in OMIB 530 may be unidirectional, and pairs of opposing photonic paths may be included in a single bidirectional information channel.

[0100] The electrical interconnects are shown as providing a bond (or adjacent bond) between elements in the AMS section and corresponding elements in the OMIB 530. In one implementation, the interconnects are copper posts of lengths of 2 millimeters or less. In other implementations, the electrical interconnects may be solder bumps formed of materials such as tin, silver, or copper. When solder bumps are used for the interconnects, the solder bumps may be flip-chip bumps. In still other implementations, the interconnects may be ball grid array (BGA) elements, pin grid array (PGA), land grid array (LGA) elements, or some other type of interconnect. In general, the interconnects may physically and electrically couple the AMS block to the OMIB 530. For example, one or more of the interconnects may physically couple to pads of the die and pads of the substrate 540 and / or OMIB 530 and pass electrical signals therebetween. The interconnects 525 may not have a uniform size, shape, or pitch. Fine pitch interconnects may be desired to enable dense communication paths between elements coupled to the OMIB. In implementations, one or more sizes, shapes, pitches, or types of interconnects may differ from those shown in the figures or from other interconnects. The particular type, size, shape, or pitch of an interconnect may be based on one or more factors, such as, for example, the use case, the materials used, design considerations, and manufacturing considerations.

[0101] 5C shows an example of an OMIB-to-OMIB connection. The paths of unmodulated light are omitted. The first die 510 and the second die 520 can be in photonic communication with the external device optical interface 571 by way of the OMIB 580 and fiber 561. For example, the first die 510 can transmit to the external device optical interface 571 via I / F1, DRV1, MOD1, photonic path 581, optional multiplexer MUX (if wavelength division multiplexing is desired), GC, FAU, and fiber 561. Conversely, the first die 510 can receive from the external device optical interface 571 via fiber 561, FAU, GC, photonic path 583, optional demultiplexer DEMUX (if wavelength division multiplexing is desired), PD1, TIA1, and I / F1.

[0102] 5D shows an example of a stacked die configuration. The AMS circuitry (DRV1 and TIA1) is included in a first AMS die 511A, and the general purpose / digital circuitry is included in a first generic die 511B. The first AMS die 511A is stacked on top of an OMIB 580 via electrical interconnect 526A, and the first generic die 511B is stacked on top of the first AMS die 511A via electrical interconnect 526B. The OMIB 580 interfaces with an optical engine 570 and / or an external device optical interface 571 via fiber 560, which may further interface with the second die 520.

[0103] 5E illustrates a configuration in which the first generic die 512B and the first AMS die 512A are stacked separately and arranged side-by-side on the OMIB 590. An electrical interconnect, such as a bus, allows signaling (e.g., using UCIe, PCIe, or any suitable protocol) between the first generic die 512B and the first AMS die 512A. The electrical interconnect may include an electrical path 527A from TIA1 to I / F1 and an electrical path 527B from I / F1 to DRV1.

[0104] FIG. 6 shows a perspective view 600 of an exemplary OMIB 630 bridging two dies (first die 610 and second die 620) and coupled to an optical engine 670. The substrate 640 is optional. Each of the first die 610 and second die 620 has an AMS block (first AMS portion 610A and second AMS portion 620A) in an area overlapping the OMIB 630 such that the AMS block is adjacent to and / or stacked on the OMIB 630 in a configuration that couples the first die 610 to the OMIB 630 and couples the second die 630 to the OMID 630 via electrical connections. The interconnections may be made by copper posts or any other suitable electrical interconnects. The offset portion of the OMIB provides an offset area where the OI and / or external optical engine 670 may be located. The external optical engine 670 provides a light source for the photonic network via the OI. The external device optical interface 671 provides bidirectional communication with the die via a fiber between the OI and the external device optical interface 671. In FIG. 6, the top surface of the OMIB 630 and the substrate 640 are shown as being substantially coplanar, but as previously mentioned, the OMIB 630 need not be coplanar with the surface of the substrate 640. The bottom surface of the first die 610 or the second die 620 may be physically and electrically coupled to the top surface of the OMIB 630. When the first portion of the transceiver (the modulator and / or PD in the OMIB 630) is aligned with the second portion of the transceiver (the AMS section 610A or the AMS section 620A), the OMIB 630 and the first die 610 or the second die 620 form an adjacent coupling.

[0105] 7A shows a perspective view of an example OMIB 730 that bridges two dies and receives unmodulated light from a chiplet light engine (CLE). The substrate 740 is optional. Each of the first die 710 and the second die 720 includes an AMS block (710A, 720A) in a region that overlaps the OMIB 730 such that the AMS block is above and / or stacked on the OMIB 730 in a configuration that couples the two dies to the OMIB 730 via appropriate electrical interconnects (e.g., where the modulator is located directly above the driver and the TIA is located directly above the PD). The CLE is located in an offset region of the OMIB 730. The CLE includes a laser, which may be positioned parallel to the surface of the OMIB 730, a first optical component (e.g., a mirror 701 for reflecting the laser beam downward or to the side), and a second optical component (e.g., a lens 702 for focusing the laser beam to a small area), where the first optical component and the second optical component may be configured to rotate the light from the laser substantially 90 degrees so that it can be directed into the OMIB. Within the OMIB, the light may enter a GC that includes a 90 degree mirror, and thus a waveguide that runs parallel to the surface of the OMIB. An external device optical interface 771 communicates bidirectionally with the die via a fiber between the OI and the external device optical interface 771.

[0106] FIG. 7B illustrates an exemplary package 700 in which the CLE 775 can be used. The substrate 741 is optional. The optical signal is provided from the CLE 775 via the OMIB 731 to the grating coupler CG1 (or any other means of interfacing between a fiber and a photonic IC) and the splitter SP, from where it is directed to the first die 711 and the second die 721. The OMIB 731 also provides an optical path in both directions between the dies. The second grating coupler CG2 and other associated fiber connectors using the FAU, or any other means of interfacing between a fiber and a photonic IC, provide access to and from the external device optical interface 771. In some implementations, the CLE 775 can be included in a CLE array. In further implementations, the CLE 775 can include a semiconductor optical amplifier (SOA) or SOA array for amplifying the power of the unmodulated light.

[0107] FIG. 8A illustrates an example OMIB 830 with a photonic link capable of connecting two dies in a package according to some implementations. The OMIB 830 provides optical communication from each of the modulators (MOD1-4) in the first die 810 to each of the photodetectors (PD1-4) in the second die 820. A waveguide system in the OMIB may bridge and / or enable connection between a transmitting unit (not shown) in the first die 810 and a receiving unit (not shown) in the second die 820. An optical engine 870, which may be internal or external to the OMIB 830, outputs a carrier light of a single wavelength ·a1. A splitter tree SPT may split the light having wavelength ·a1 through multiple optical paths (four are shown) to the modulators MOD1-4. The modulators modulate the light having the single wavelength ·a1 and transmit the modulated light to the photodetectors PD1-4 through the respective waveguides. 8A shows four links, each including a modulator, a photonic path, and a photodetector. Each link may be part of a lane that further includes a serializer and a deserializer. Multiple lanes may be combined together into a single channel, which may be unidirectional or bidirectional.

[0108] 8B illustrates one implementation having two OMIBs 831 and 832 coupled between a first die 811 and a second die 821. An optical engine 870 outputs carrier light to a splitter tree SPT, which may split the light among multiple optical paths to modulators MOD1-4 associated with one or more photonic channels. For example, a first bidirectional photonic channel may include links MOD1 / PD1 and MOD2 / PD2, and a second bidirectional photonic channel may include links MOD3 / PD3 and MOD4 / PD4.

[0109] 9 is a diagram illustrating an example system of a link using WDM for communication from a die to an external device, according to some implementations. In this example, a first die 910 and an external device are coupled via grating couplers GC and FAUs in an OMIB 930 (or any other means for optically interfacing between a fiber and a photonic IC), an optical fiber 991, and an external device optical interface 971.

[0110] An optical engine 970, which may be internal or external, provides light at multiple wavelengths (e.g., 2-16 wavelengths), such as, for example, four wavelengths ·b1, ·b2, ·b3, ·b4, to the OMIB 930 as shown. A splitter tree SPT (e.g., similar to the splitter tree SPT of FIG. 8A) may split the light at multiple wavelengths among multiple different channels or different links (e.g., two links, only one fully shown here), which may be in different OMIBs or different PICs. The carrier light at wavelengths ·b1, ·b2, ·b3, ·b4 is provided to optical modulators MOD1-4, which may modulate the four light beams with different portions of the information to be transmitted, and a WDM multiplexer (MUX) combines the four light beams into a single beam containing the four different wavelengths. The single light beam is then transmitted to the external device optical interface 971 via the GC, the FAU, and the optical fiber 991.

[0111] 10 illustrates an example reverse channel for the WDM system of FIG. 9, according to some implementations. An external device optical interface 971 provides an optical signal via fiber 991, FAU, and GC to a WDM demultiplexer (DEMUX) in OMIB 930. The WDM demultiplexer separates the optical signal into four separate modulated signals having wavelengths ·b1, ·b2, ·b3, and ·b4. These four signals are provided via respective optical waveguides to photodetectors PD1-4 that electrically interface with the first die 910 to provide information from an external device to the first die 910.

[0112] Although the implementations described above are directed to photonic channels showing four optical links in one direction and a WDM multiplexer receiving four different wavelengths, in other implementations, two or more optical links and a WDM multiplexer receiving two or more different wavelengths may be used, and accordingly, the WDM demultiplexer outputs two or more different wavelengths corresponding to these alternative implementations.

[0113] For example, as described above, with intra-OMIB and inter-OMIB photonic channels, which typically include one or more links per direction, processors in an EIC(s) in a single package may be connected in an electrophotonic network. The resulting network topology generally depends on the choice of the pair of dies that are coupled via the associated photonic channels, and a variety of example topologies are known in the art. Note, however, that although this document generally refers to bidirectional photonic channels, which provide a more flexible network structure for implementing ML and other computational models compared to unidirectional photonic channels, electrophotonic networks may also be formed with unidirectional photonic channels, and such networks may retain any of the advantages discussed herein (e.g., power reduction due to photonic data transfer over long distances).

[0114] As previously mentioned, a photonic channel can include at least two unidirectional sets of one or more links to create a bidirectional channel. Examples of such channels include, but are not limited to, a photonic channel between two dies when bridged by an OMIB, and a photonic channel between an OI on an OMIB and an external device optical interface. The nature of the external device optical interface can be varied, so long as it has the optical capability to receive messages sent from the OMIB and / or transmit messages that can be received and used by the OMIB or any die using the OMIB as a bridge.

[0115] The messages may be in the form of packets of variable size. Figure 11 shows an exemplary unidirectional logical channel 1100 comprising multiple photonic links. The logical channel 1100 has an input link 1101, a transmit bonding engine 1102, photonic paths 1103A-D, a receive bonding engine 1104, and an output link 1105. The transmit bonding engine 1102 may split incoming data packets across active photonic links and add sequence information. The receive bonding engine 1104 reassembles the data packets using the sequence information. In the illustrated example, data arrives at the receive bonding engine on four links.

[0116] FIG. 12 illustrates the transfer of an exemplary eight-word message in the unidirectional logical channel 1100 of FIG. 11. The message comprises words W0 through W7. The transmit bonding engine 1102 splits the word across the four active photonic links. For example, a first link carries words W0 and W4. A second link carries words W1 and W5, and so on. The transmit bonding engine 1102 appends sequence information to each of the partial messages, and the receive bonding engine 1104 reassembles the entire message at its output. Bonding allows for the construction of a high-bandwidth, low-latency channel from multiple low-bandwidth links and may provide the ability to work around non-functioning links.

[0117] FIG. 13 shows an example AMS block in detail. FIG. 13 shows an AMS transmit block 1310A for a first die and an AMS receive block 1320A for a second die. The AMS receive block 1315 for the first die and the AMS transmit block 1328 for the second die are not detailed to simplify the figure. Each of the AMS blocks 1310A and 1320A may be connected to the OMIB 1330 via one or more electrical interconnects (only the interconnect 1314 for the AMS transmit block 1310A and the interconnect 1321 for the AMS receive block 1320A are shown here). 13, each link in the photonic channel comprises an optical transmitting unit Tx, an optical receiving unit Rx, and an optical transmission medium (e.g., optical waveguide or fiber) connecting the transmitting unit to the receiving unit, where AMS transmitting block 1310A is coupled to AMS receiving block 1320A, and AMS transmitting block 1335 is coupled to AMS receiving block 1336. The transmitting unit (e.g., transmitting unit 1331) includes an optical modulator (e.g., optical modulator 1333) that imparts a message to an optical signal by modulating the carrier light output by optical engine 1370, and an electrical serializer (e.g., serializer 1313) that converts an electronic message received in parallel data words into a signal suitable for driving the optical modulator. The receiving unit (e.g., receiving unit 1332) includes a photodetector (e.g., photodetector 1334) for converting the optical signal received over the transmission medium back into an electrical signal, and associated electronics including a transimpedance amplifier (e.g., TIA 1322) and a gain controller (e.g., gain controller 132) for normalizing the signal level, a slicer (e.g., slicer 1324) for extracting the bit stream, and a deserializer (e.g., deserializer 1325) for converting the received message back into parallel data.The AMS transmit block 1310A further includes a transmit bonding engine 1312 that can split messages from the first interface 1311 as described in more detail with reference to Figure 11, and the AMS receive block 1320A includes a receive bonding engine 1326 that reassembles messages for the second interface 1327 as described in more detail with reference to Figure 12. The OMIB 1330 includes a receive block 1336 that interfaces with the AMS receive block 1315, a transmit block 1335 that interfaces with the AMS transmit block 1328, and an optical engine 1370. Optical interface OI1, and an optical interface OI2.

[0118] In one implementation, information is modulated at 56 Gb / s with a non-return to zero (NRZ) code, although more spectrally efficient modulation schemes, such as PAM-4 or PAM-8 or higher order pulse amplitude modulation, may be used to enable higher bandwidth and lower latency links.

[0119] 14A illustrates a configuration of three OMIBs bridging portions of two dies. OMIB 1430A bridges two computational elements 1411 in a first die 1410, a first portion of a central region 1412 in the first die 1410, two computational elements 1421 in a second die 1420, and a first portion of a memory region 1422 in the second die 1420. OMIB 1430B bridges two computational elements 1421 in a second die 1420 and a second portion of a memory region 1422 in the second die 1420. OMIB 1430C bridges two computational elements 1411 in a first die 1410, a second portion of a central region 1412 in the first die 1410, two computational elements 1421 in a second die 1420, and a third portion of a memory region 1422 in the second die 1420. The central region 1412 is located centrally within the first die 1410 to equalize latency between the compute elements 1411 and the central region 1412. The central region 1412 may include memory, cache memory, other shared memory, a network-on-chip crossbar, a switch, a routing mechanism, and a memory controller. The memory region 1422 is located centrally within the second die 1420 to equalize latency between the compute elements 1421 and the memory region 1422. The memory region 1422 may include cache memory, other shared memory, and a memory controller. The portion of the die that the OMIB bridges has 10 compute elements and two memory regions. An additional OMIB (not shown) may be located on the opposite side of the first die 1410 and the second die 1420 to bridge the additional die, compute elements, and portions of the memory region. This configuration allows packets to be photonically routed from the external device optical interface 1471 to an AMS block that is close to the memory being used or accessed and close to where the computational element 1411 or 1421 may perform one or more computations on the data in the memory area.The ability of the OMIB to carry instructions from any computational element or external device, for example, using packets carried as photonic signals over the OMIB within one of the dies 1410 or 1420 to load or store data in memory regions 1412 or 1422, and / or process data in computational elements 1411 or 1421 proximate to the central region 1412 or 1422, addresses many of the issues of stranded memory and / or latency introduced when optical signals cannot extend beyond the edge of the die.

[0120] The AMS transmit and receive blocks can bring optical signals into the central region of either die (e.g., to a memory controller to access memory in the central region) from any external device optical interface connected to the OMIB by an OMIB-to-OMIB link, or from an AMS transmit and receive block with an OMIB-to-OMIB connection in a bridge. The OI of each OMIB may be connected by a fiber, but this is not required. A first side (e.g., right side) of the AMS transmit block 1413 or the AMS receive block 1414 is aligned with a first side (e.g., left side) of the central region (e.g., central region 1412). The first side of the central region is in close proximity to and / or in contact with a computational element 1411, such as a CPU, GPU, TPU, etc. A second side (e.g., left side) of the AMS transmit block 1413 or the AMS receive block 1414 is aligned with the left side of the OMIB. The lateral alignment is approximate and does not need to be exact, but typically the alignment is at least in two dimensions to allow for adjacency between the optical and electrical elements in the OMIB and AMS blocks, respectively.

[0121] FIG. 14B shows an example configuration of five dies 1410-1414 bridged by OMIBs. With this configuration of package 1440, bridges can be added infinitely in two dimensions as needed. In this configuration, each OMIB has two interconnect regions for attaching the die. L2 cache or other memory regions can be located and / or fabricated in the center of the die so that the memory regions can reach photonically inside (rather than at the edge) of the die, reducing latency. It is also possible to provide an optical channel between the OMIBs, for example by linking the two OMIBs via optical fibers. The OIs can be placed within offset regions of the OMIBs. The configuration of FIG. 14B can be extended infinitely in the x and y directions. The configuration of FIG. 14B can also be routed through multiple hops in the diagonal direction, further reducing routing latency significantly.

[0122] 14C shows an example configuration of dies 1413-1417 bridged by both an OMIB and an electrical bridge 1419. In some implementations, the OMIB and the electrical bridge are combined into a single die.

[0123] As shown below, one OMIB can bridge four dies. For example, an OMIB can be used to bridge the dies both vertically and horizontally, resulting in four interconnect areas on each OMIB to correspond to the four AMS blocks on each die. The OMIB in this configuration can provide channels in six directions, including two horizontal, two vertical, and two diagonal directions.

[0124] FIG. 14D shows an example offset checkerboard of OMIBs bridging dies (1410, 1418) in two dimensions. Each OMIB has four interconnect regions, and four dies can be bridged using six links (two vertical, two horizontal, and two diagonal links) representing six intra-die connections on each OMIB. Some dies, for example die 1418, may include memory regions. The AMS block may interface with the memory regions, as well as any processing elements and other logic. However, FIG. 14D may not be to scale. An OMIB with dimensions similar to those of the bridged die can reach the AMS block near the center of the die. The AMS blocks may also be relatively much smaller than those shown in this example, and each die and each OMIB may have more than four interconnect regions.

[0125] 15 is a flow chart illustrating an example method 1500 of manufacturing an OMIB according to various implementations. The method 1500 includes the following operations.

[0126] Operation 1510—fabricating a bridge including a photonic link from a first interconnect region to a second interconnect region, the photonic link including a first electrical interconnect, a modulator coupled to the first electrical interconnect, an optical transmission medium coupled to the modulator, a photodetector coupled to the optical transmission medium, and a second electrical interconnect. In some implementations, the modulator is configured to be thermally stabilized by applying a stabilizing voltage to the modulator, the stabilizing voltage related to a die temperature, and the stabilizing voltage induces a change in dielectric absorption in the modulator.

[0127] Action 1520 - Arrange interconnect regions to enable electrical interconnection and / or adjacent coupling with AMS blocks within the die.

[0128] Action 1530 - Fabricate intra-OMIB connections between interconnect regions.

[0129] Act 1540 - Fabricating an OMIB inter-connection between two interconnect regions and an optical interface.

[0130] FIG. 16 illustrates components of an example system 1600 in which one or more OMIBs may be used. Each of the components or groups of components may include an AMS block and an interface for coupling to one or more OMIBs. For example, the system 1600 may include a display device interface circuit, such as a connector, and a driver to which a display device 1606 may be coupled. In this case, the display device 1606 need not be integrated into or a component of the system 1600. Similarly, the system 1600 may not have an audio input device 1624 or an audio output device 1608, but may have audio input or output device interface circuitry, such as, for example, a connector and support circuitry, for coupling to an external audio input device or an external audio output device.

[0131] The system 1600 may include one or more processing devices 1602. The processing device 1602 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphic processing units (GPUs), tensor processing units (TPUs), AI accelerators, fixed gate programmable arrays (FPGAs), load / store units (LDSUs), neural computation engines (NCEs), dot product and / or convolution engines, server processors, or any other suitable processing devices. The system 1600 may include a memory 1604, which may itself include one or more memory devices, such as, for example, volatile memory, non-volatile memory, flash memory, solid-state memory, and / or hard drives, including, but not limited to, random access memory (RAM) devices (e.g., static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, or conductive bridge RAM (CBRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), NAND flash memory, solid-state drive (SSD) memory, NOR flash memory, CMOS memory, thin-film transistor-based memory, phase change memory (PCM), storage class memory (SCM), magnetoresistive memory (MRAM), resistive RAM, DRAM, high bandwidth memory (HBM), DDR-based DRAM, DIMM memory. In some implementations, the memory 1604 may include memory that shares a die with the processing device 1602. This memory may be used as a cache memory and may include embedded dynamic RAM or spin transfer torque magnetic RAM.

[0132] In some implementations, the system 1600 may include a communications chip 1612. For example, the communications chip 1612 may be configured to manage wireless communications for transferring data to and from the device.

[0133] The communications chip 1612 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16-compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. The communications chip 1612 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Next Generation HSPA (E-HSPA), or LTE network. The communications chip 1612 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Next Generation UTRAN (E-UTRAN). The communications chip 1612 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The communications chip 1612 may operate according to other wireless protocols in other implementations. The system 1600 may include an antenna 1622 for facilitating wireless communications and / or receiving other wireless communications (such as, for example, AM or FM radio transmissions).

[0134] In some implementations, the communication chip 1612 may manage wired communications, such as, for example, electrical, optical, or any other suitable communication protocol (e.g., Ethernet or USB). As described above, the communication chip 1612 may include multiple communication chips. For example, a first communication chip 1612 may be dedicated to short-range wireless communications, such as, for example, Wi-Fi or Bluetooth, and a second communication chip 1612 may be dedicated to long-range wireless communications, such as, for example, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some implementations, the first communication chip 1612 may be dedicated to wireless communications, and the second communication chip 1612 may be dedicated to wired communications.

[0135] The system 1600 may include a battery / power circuit 1614. The battery power circuit 164 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the system 1600 to an external energy source (e.g., AC line power). The system 1600 may include a display device 1606 (or corresponding interface circuitry as described above). The display device 1606 may include any visual indicator, such as, for example, a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, a flat panel display, a virtual reality headset, an augmented reality headset, etc. The system 1600 may include an audio output device 1608 (or corresponding interface circuitry as described above). The audio output device 1608 may include any device that generates an audible indicator, such as, for example, a speaker, a headset, an earphone, a vibrating element, a piezoelectric crystal, etc. The system 1600 may include an audio input device 1624 (or corresponding interface circuitry as described above). Audio input device(s) 1624 may include any device that generates a signal representing sound, such as, for example, a microphone, a microphone array, or a digital instrument (eg, an instrument with a pickup or Musical Instrument Digital Interface (MIDI) output).

[0136] The system 1600 may include a positioning device 1618 (or corresponding interface circuitry), such as, for example, in accordance with the Global Positioning System (GPS), Galileo, GLONASS, BeiDou, IRNSS, NavIC, and / or QZSS. The positioning device 1618 may communicate with a satellite-based system as known in the art and receive the position of the system 1600. The system 1600 may include another output device 1610 (or corresponding interface circuitry as described above). Examples of the another output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. The system 1600 may include another input device 1620 (or corresponding interface circuitry as described above). Examples of other input devices 1620 include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touch pad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0137] System 1600 may have any desired form factor, such as, for example, a handheld or mobile device (e.g., a mobile phone, a smartphone, a tablet computer, a laptop computer, an Internet of Things (IoT) device, a netbook computer, an ultrabook computer, a mobile Internet device, a music player, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electronic device, a server device or other network computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electronic device. In some implementations, system 1600 may be any other electronic device that processes data. Thermal behavior

[0138] The close spacing of the EIC and PIC chiplets (less than 2 millimeters, often within 50 microns) creates thermal challenges for the OMIB. Depending on the type of modulator used, the temperature range for operation within specification can be less than 30 degrees Celsius. However, the die temperature of the EIC can vary more significantly depending on the ambient temperature, load conditions, supply voltage, and other factors. Modulator types include Mach-Zehnder Interferometers (MZI), ring modulators, and electroabsorption modulators (EAM). Ring modulators have a very narrow temperature range (less than 1 degree Celsius), while MZIs and EAMs can have operating ranges of over 30 degrees Celsius. Both the modulator temperature and bias voltage can affect the frequency (wavelength) at the efficiency peak of the modulator. The wavelength of the laser may be unaffected or differently affected by these parameters. Thus, a change in temperature will cause a difference between the laser wavelength and the efficiency peak wavelength of the modulator, affecting the modulation depth.

[0139] Implementations may include an inherently optimal modulator over a desired temperature range. Alternatively, implementations may provide temperature compensation, including temperature sensing or predictive capabilities. Temperature compensation may be fully integrated into the OMIB, or partially integrated into the OMIB and partially integrated into the connection die.

[0140] 17A-D show examples of EIC / OMIB combinations that use temperature compensation to extend the temperature range of a modulator in the OMIB. FIG. 17A shows an EIC 1710 physically and electrically coupled to a PIC 1720 (e.g., an OMIB) via a metal interconnect, such as a bump or copper pillar. The EIC 1710 includes a driver DRV 1711 and a temperature element TE 1712. The TE 1712 may include a temperature sensor, a temperature predictor, or both (the temperature predictor predicts the die or PIC temperature based on the processor load conditions known in software or firmware). In some implementations, the temperature sensor is located less than two millimeters (2 mm) from the DRV 1711. In further implementations, the temperature sensor is located within fifty microns (50 μm) of the DRV 1711. The driver DRV 1711 delivers a high data rate modulated signal to a modulator 1721 in the PIC 1720. The TE 1712 delivers a low-frequency (compared to the data rate) temperature-dependent bias voltage to the MOD 1721. If the temperature dependence of the bias voltage is inversely proportional to the temperature dependence of the modulator over an extended temperature range, the effect of temperature on the modulator performance in the extended temperature range is cancelled. In a further implementation, the TE 1712 includes a look-up table to convert measured or predicted temperature to a temperature-compensated modulator bias voltage.

[0141] In Figure 17B, the EIC 1730 is physically and electrically coupled to the PIC 1740 (e.g., an OMIB). The EIC 1730 includes a driver DRV 1731, a temperature element TE 1732, and a summer 1733. The PIC 1740 includes a modulator MOD 1741. The summer 1733 adds a low frequency temperature dependent bias voltage from the TE 1732 to the high data rate modulated signal from the DRV 1731 and forwards it to the MOD 1741. In some implementations, the TE 1732 includes a look-up table to convert a measured or predicted temperature to a temperature compensated modulator bias voltage.

[0142] In Figure 17C, the EIC 1750 is physically and electrically coupled to a PIC 1760 (e.g., an OMIB). The EIC 1750 includes a driver 1751, and the PIC 1760 (e.g., an OMIB) includes a modulator MOD 1761 and a temperature sensor TS 1762. The TS 1762 is located near the MOD 1761 and delivers a temperature dependent bias voltage to the MOD 1761. The temperature dependence of the bias voltage is inversely proportional to the temperature dependence of the MOD 1761 over an extended temperature range, thereby extending its operating temperature range.

[0143] In FIG. 17D, the EIC1770 is physically and electrically coupled to the PIC1780 (e.g., OMIB). The PIC1780 includes a modulator MOD1781 and a temperature sensor TS1782. The TS has a temperature sensor output configured to be coupled to a circuit external to the PIC1780 (e.g., the EIC1770). The EIC1770 includes a driver DRV1771, a temperature controller TC1772, and a summer 1733. The TC1772 is configured to receive a first temperature-dependent signal from a circuit external to the EIC1770 (e.g., from the TS1782 in the PIC1780). The TC1772 converts the first temperature-dependent signal to a temperature-dependent bias voltage, whose temperature dependence is inversely proportional to the temperature dependence of the MOD1781 over an extended temperature range. The TC1772 may perform the conversion using temperature-linear and temperature-nonlinear analog circuits. Alternatively or additionally, the TC 1772 may perform the conversion using digital circuitry to access a memory 1774 that stores the temperature profile. The TC 1772 may be included in a temperature element TE, such as the TE 1732 of FIG. 17B. In some implementations, the TC 1772 includes a look-up table to convert a measured or predicted temperature to a temperature-compensated modulator bias voltage.

[0144] Some modulators, for example when integrated into an OMIB, can provide stable operation over a wide temperature range of the modulator for the optical components without additional temperature compensation. The modulator may use the Franz-Keldysh effect for electrically induced changes in optical absorption. A variety of materials may be used for the modulator, including germanium and its alloys, silicon and its alloys, III-V materials such as materials based on the indium phosphide (InP) or gallium arsenide (GaAs) material systems. For example, one or more implementations described herein include chip hardware that includes features and functions to provide thermally stable optical modulation element(s) coupled to electronic element(s) (e.g., a driver in an AMS transmit block). In one or more implementations, the hardware is a device that includes an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC). The PIC may be electrically interconnected in a combined or adjacent combined manner with the EIC. Each of the transmit units may include a thermally stable optical modulator in a portion that resides in the PIC. Data may travel optically within the PIC via an optical carrier between one of the thermally stable optical modulators in the first portion of the OMIB and one of the receiving units in or interconnected with the second portion of the OMIB. In one or more implementations, the thermally stable optical modulator operates in a temperature range of greater than 30 degrees Celsius. In this example, the thermally stable optical modulator may further include a material selected from the group including germanium, silicon, alloys of germanium, alloys of silicon, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementations, the optical modulator is an electroabsorption modulator (EAM) that uses the Franz-Keldysh effect for electrically induced changes in optical absorption.

[0145] In one or more implementations, the thermally stable optical modulator is an EAM that operates in a temperature range of less than 30 degrees Celsius. In this example, the thermally stable optical modulator may include (e.g., includes) germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementations, the thermally stable optical modulator uses the quantum confined Stark effect (QCSE) for electrically induced changes in optical absorption. In one or more implementations, the thermally stable optical modulator has an output with a high optical modulation amplitude. In this example, the thermally stable optical modulator may include a material selected from a group including germanium, silicon, germanium alloys, silicon alloys, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementations, the thermally stable optical modulator uses the quantum confined Stark effect (QCSE) for the electrically induced change in optical absorption. In one or more implementations, the thermally stable optical modulator is configured for stable operation over a wide temperature range. In this example, the thermally stable optical modulator may include a material selected from the group including germanium, silicon, alloys of germanium, alloys of silicon, indium phosphide (InP)-based III-V materials, and gallium arsenide (GaAs)-based III-V materials. In one or more implementations, the modulator uses the Franz-Keldysh effect for the electrically induced change in optical absorption. manufacturing

[0146] FIG. 18 illustrates an exemplary method 1800 of manufacturing a system. The method 1800 comprises a step 1810 including manufacturing a system including a first die (integrated circuit), a second die (integrated circuit), a photonic IC providing a bridge function, a light source, and a data channel. The photonic IC includes a first interconnect region, a second interconnect region, and an offset region. A bond pad pattern on the first integrated circuit matches a bond pad pattern in the first interconnect region, and a bond pad pattern on the second integrated circuit matches a bond pad pattern in the second interconnect region. Two or more bond pads on the first integrated circuit are physically and electrically coupled to two or more bond pads in the first interconnect region, and two or more bond pads on the second integrated circuit are physically and electrically coupled to two or more bond pads in the second interconnect region. A light source is optically coupled to a first optical interface (first OI) in the offset region. The data channel comprises a serializer and driver in the first integrated circuit, a modulator, a photonic path, and a photodetector in the photonic IC, and a transimpedance amplifier and a deserializer in the second integrated circuit. The distance between the surface of the first integrated circuit and the surface of the photonic IC is less than 2 mm, and the distance between the surface of the second integrated circuit and the surface of the photonic IC is less than 2 mm. In many cases, the distance is less than fifty microns (50 μm). At least one of the two or more bond pads on the first integrated circuit may be located within one hundred microns (100 μm) of an edge of the first integrated circuit. At least one of the two or more bond pads on the second integrated circuit may be located within one hundred microns (100 μm) of an edge of the second integrated circuit. The modulator may be an electroabsorption modulator (EAM). The modulator may be a Mach-Zehnder interferometer (MZI). The first die or the photonic IC may include a temperature sensor or temperature predictor capable of delivering a temperature dependent bias signal. Consideration

[0147] The present description has been described with respect to specific implementations, which are merely illustrative and not limiting. The present description may refer to specific structural implementations and methods, and is not intended to limit the present technology to the specifically disclosed implementations and methods. The present technology may be implemented using other features, elements, methods, and implementations. The implementations are described to explain the present technology, and do not limit its scope, which is defined by the claims. Those skilled in the art will recognize various equivalent variations to the above description.

[0148] For example, many of the examples herein use grating couplers to couple the fiber to the photonic IC. However, many of the implementations work well with other means for optically interfacing between the fiber and the photonic IC, such as those described with reference to FIG. 3. Many of the examples show only an OMIB bridging a first die and a second die, but the OMIB may bridge any number of dies. Many of the examples show the AMS functionality included in the first die and / or the second die, but the AMS functionality may be included partially or completely in a separately stacked IC, as shown, for example, in FIGS. 5D-E. All such implementations are within the scope and scope of the disclosed technology.

[0149] All features disclosed herein, including the claims, summary, and drawings, and all steps in any disclosed method or process, may be combined in any combination, except combinations in which at least some of such features and / or steps are mutually exclusive. Each feature disclosed herein, including the claims, summary, and drawings, may be replaced with an alternative feature serving the same, equivalent, or similar purpose, unless an exception is expressly stated.

[0150] Although the present description has been described with respect to specific implementations, these specific implementations are merely exemplary and not limiting. For example, many of the operations may be implemented on a printed circuit board (PCB) using off-the-shelf devices, in a system on a chip (SoC), an application specific integrated circuit (ASIC), a programmable processor, a coarse grain reconfigurable architecture (CGRA), or in a programmable logic device such as a field programmable gate array (FPGA), eliminating the need for at least some of any dedicated hardware. The implementation may be as a single chip or as a multi-chip module (MCM) that packages multiple semiconductor dies in a single package. All such variations and modifications are deemed to be within the scope of the disclosed technology, the nature of which is determined from the above description.

[0151] Any suitable technology for fabricating electronic devices may be used to implement the circuits of a particular implementation, including CMOS, FinFET, BiCMOS, bipolar, JFET, MOS, NMOS, PMOS, HBT, MESFET, etc. A variety of semiconductor materials may be used, such as silicon, germanium, SiGe, GaAs, InP, GaN, SiC, graphene, etc. The circuits may have single-ended or differential inputs and single-ended or differential outputs. The terminals of the circuits may function as inputs, outputs, or both, or may be in a high impedance state, or may function to receive a power supply, a ground reference, a reference voltage, a reference current, etc. Although the physical processing of signals may be presented in a particular order, this order may be changed in different particular implementations. In some particular implementations, multiple elements, devices, or circuits shown as sequential in this specification may operate in parallel.

[0152] Particular implementations may be implemented using programmed general-purpose digital computers, application specific integrated circuits, programmable logic devices, field programmable gate arrays, optical, chemical, biological, quantum, or nano-engineered systems, or the like. Other components and mechanisms may be used. In general, the functionality of particular implementations may be realized by any means known in the art. Distributed, networked systems, components, and / or circuits may be used. Communications, communication or transfer of data may be wired, wireless, or by any other means.

[0153] One or more of the elements shown in the drawings / figures may be implemented in a further divided or integrated manner, or may be excluded or rendered inoperative in particular instances, as may be useful according to a particular application.

[0154] Thus, while specific implementations have been described herein, it will be understood that modifications, variations, and freedom from substitution are contemplated in the above disclosure, and that in some cases some features of a specific implementation may be employed without the corresponding use of other features without departing from the scope and spirit of the described embodiment. Accordingly, many modifications may be made to adapt a particular situation or material to the essential scope and spirit.

Claims

1. a bridge element having first and second interconnect regions for electrical interconnection to one or more die; a first photonic pathway from the first interconnect region to the second interconnect region; a second photonic pathway from the second interconnect region to the first interconnect region; and A package comprising:

2. a third photonic path from the first interconnect region to an optical interface (OI); a fourth photonic path from the OI to the first interconnect region; and The package of claim 1 further comprising:

3. a first portion of a photonic transceiver coupled to the first interconnect region for transmitting a first optical signal via the first photonic path and receiving a second optical signal via the second photonic path; The package of claim 1 further comprising:

4. The package of claim 3 , wherein the first portion of the photonic transceiver includes a modulator and / or a photodetector.

5. 4. The package of claim 3, wherein the first portion of the photonic transceiver is further configured to transmit a third optical signal via the third photonic path and to receive a fourth optical signal via the fourth photonic path.

6. 4. The package of claim 3, wherein the first portion of the photonic transceiver resides in a photonic integrated circuit (PIC) and the second portion of the photonic transceiver resides in an electrical integrated circuit (EIC), and the first and second portions are coupled via an electrical interconnect less than two millimeters (2 mm) in length.

7. 4. The package of claim 3, wherein the first portion includes an optical modulator for modulating the first optical signal or a third optical signal in response to a modulation signal from the second portion via the electrical interconnect, and the third optical signal passes through a third optical path.

8. 8. The package of claim 7, wherein the modulator is an electro-absorption modulator fabricated from a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, indium phosphide (InP) based III-V materials, and gallium arsenide (GaAs) based III-V materials.

9. 8. The package of claim 7, wherein the EIC is a component of a first die coupled with the first interconnect region, the EIC includes a central region, and the second portion is within or within 2 millimeters of the central region.

10. The package of claim 9 , wherein the central region includes one or more of a memory, a cache, a network-on-chip crossbar, a switch, or a routing mechanism.

11. The package of claim 9 , wherein the central region intersects a center of the first die.

12. 10. The package of claim 9, wherein the EIC further comprises a plurality of computational elements disposed about the central region, the second portion being within or within 2 millimeters of the computational elements.

13. The package of claim 1 , further comprising a substrate coupled to the bridge element, the bridge element being embedded in the substrate such that a top surface of the bridge element is substantially coplanar with a top surface of the substrate.

14. The package of claim 12 , wherein an OI is offset at a top surface in at least one dimension from the first or second interconnect region.

15. The package of claim 12 , wherein the first interconnect region extends to a top surface to contiguously couple the first portion with the second portion on the bottom surface of the first die.

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