System and method for controlling a power limiter - Patents.com

Abstract

A method of controlling limits on power provided by a high frequency (HF) radio frequency (RF) generator is described. The method includes determining whether an average power reflected back to the HFRF generator is less than a maximum limit value, and if the average power is determined to be less than the maximum limit value, determining whether the power reflected back to the HFRF generator in a number of bins in a cycle is less than a predetermined threshold. The method further includes determining whether a number of misadjusted bins exceeds a predetermined number in response to determining that the power reflected back to the HFRF generator in a number of bins in a cycle is equal to or greater than the predetermined threshold. The method includes activating a power limiter filter in response to determining that the number of misadjusted bins is less than or equal to the predetermined number.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The embodiments described in this disclosure relate to systems and methods for controlling a power limiter. [Background technology]

[0002] The background art description provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within this background art section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0003] A radio frequency (RF) generator generates and supplies an RF signal. The RF generator is connected to an impedance matching circuit. The impedance matching circuit receives the RF signal, matches the impedance of a load to the impedance of a source, and outputs another RF signal. The other RF signal is supplied to a plasma chamber. A semiconductor wafer is placed in the plasma chamber for processing.

[0004] During semiconductor wafer processing, power of an RF signal generated by an RF generator is supplied to the semiconductor wafer, and it is difficult to control the supply of power in a desired manner for processing the semiconductor wafer.

[0005] It is out of this context that the embodiments described in this disclosure arise. Summary of the Invention

[0006]

[0010] Embodiments of the present disclosure provide a system and method for controlling a power limiter. It should be appreciated that the present embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Some embodiments are described below.

[0007] In one embodiment, a method for controlling limits on power supplied by a high frequency (HF) radio frequency (RF) generator is described. The method includes determining whether an average power reflected toward the HFRF generator is less than a maximum limit value, and, if the average power is determined to be less than the maximum limit value, determining whether the power reflected toward the HFRF generator for a plurality of bins in a cycle is less than a predetermined threshold. The method further includes, in response to determining that the power reflected toward the HFRF generator for a plurality of bins in a cycle is equal to or greater than the predetermined threshold, determining whether a number of misadjusted bins exceeds a predetermined number. The method includes activating a power limiter filter if the number of misadjusted bins is determined to be less than or equal to the predetermined number.

[0008] In one embodiment, a controller is described. The controller includes a processor that determines whether the average power reflected toward the HFRF generator is less than a maximum limit value, and if the average power is determined to be less than the maximum limit value, determines whether the power reflected toward the HFRF generator for a plurality of bins during a cycle is less than a predetermined threshold. In response to determining that the power reflected toward the HFRF generator for a plurality of bins during a cycle is equal to or greater than the predetermined threshold, the processor determines whether the number of misadjusted bins exceeds a predetermined number. The processor activates a power limiter filter if the number of misadjusted bins is determined to be less than or equal to the predetermined number. The controller includes a memory device coupled to the processor.

[0009] In one embodiment, a plasma system is described. The plasma system includes a low frequency (LF) RF generator. The LFRF generator generates an LFRF signal. The plasma system further includes an HFRF power supply that generates an HFRF signal. The plasma system includes a matcher coupled to the LFRF generator and the HFRF generator to receive the LFRF generator and HFRF signal and output a modified signal. The plasma system includes a plasma chamber coupled to the matcher to receive the modified signal. The plasma system also includes a controller coupled to the HFRF power supply. The controller determines whether an average power reflected toward the HFRF generator is less than a maximum limit value, and if the average power is determined to be less than the maximum limit value, determines whether the power reflected toward the HFRF generator for a plurality of bins in a cycle is less than a predetermined threshold. In response to determining that the power reflected toward the HFRF generator for a plurality of bins in a cycle is greater than or equal to the predetermined threshold, the controller determines whether the number of misadjusted bins exceeds a predetermined number. If the number of misadjusted bins is determined to be less than or equal to the predetermined number, the controller activates a power limiter filter.

[0010] Some advantages of the systems and methods for controlling a power limiter described herein include filtering, such as removing limits on the power delivered by an HFRF generator. For each bin, the power delivered by the HFRF generator is determined. And for each bin, if the power is increased, the power limiter limits the increase to protect the HFRF generator components. However, there are cases where a limit is not necessary. For example, some bins may have low power reflected back toward the HFRF generator, and therefore, less likely to damage components. Therefore, the limit can be ignored, and the power can be increased to process substrates at a higher processing rate.

[0011] Certain other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0012] The present embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0013] [Figure 1] FIG. 1 is a diagram of one embodiment of a plasma system illustrating the use of a low frequency (LF) radio frequency (RF) generator and a high frequency (HF) RF generator.

[0014] [Figure 2A] FIG. 2A is one embodiment of a graph illustrating a clock signal.

[0015] [Figure 2B] FIG. 2B is a graph plotting one embodiment of a voltage signal to illustrate binning.

[0016] [Figure 2C] FIG. 2C is an illustration of one embodiment of a graph illustrating the generation of HF offset values ​​at which an HFRF generator is operated during processing of a substrate.

[0017] [Figure 3A] FIG. 3A is a diagram of one embodiment of a system illustrating a power limiter filter.

[0018] [Figure 3B] FIG. 3B is a flow chart illustrating one embodiment of a method for determining whether to limit the power provided by an HFRF generator. DETAILED DESCRIPTION OF THE INVENTION

[0019] The following embodiments describe systems and methods for controlling a power limiter. It will be apparent that the embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments.

[0020] 1 is a diagram of one embodiment of a plasma system 100 illustrating the use of a low frequency (LF) RF generator 102 and an HFRF generator 104. System 100 includes LFRF generator 102, HFRF generator 104, a host computer 106, a matcher 107, and a plasma chamber 108. Plasma system 100 further includes a voltage (V) sensor 110 and a power (P) sensor 112.

[0021] For example, the LFRF generator 102 has an operating frequency of 400 kilohertz (kHz) or 2 megahertz (MHz). For example, the HFRF generator 104 has an operating frequency of 27 MHz or 60 MHz. Examples of the host computer 106 include a desktop, laptop, tablet, controller, and smartphone. Examples of the matcher 107 include an impedance matching circuit, an impedance matcher, a matching circuit, or an impedance matching network. For example, the matcher 107 includes a first branch circuit and a second branch circuit. Each branch circuit includes one or more matching network elements. Examples of matching network elements include a capacitor, an inductor, and a resistor. An example of the plasma chamber 108 is a capacitively coupled plasma (CCP) chamber.

[0022] The host computer 106 includes a processor 114 and a memory device 116. Examples of the processor 114 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 116 include read-only memory and random access memory.

[0023] The plasma chamber 108 includes a lower electrode LE and an upper electrode UE. A gap is formed between the lower electrode LE and the upper electrode UE, and a substrate S is placed in the gap on an upper surface of the lower electrode LE for processing. An example of the substrate S is a semiconductor wafer on which integrated circuits are fabricated.

[0024] The processor 114 is coupled to the memory device 116. The processor 114 is coupled to the LFRF generator 102 via a transfer cable 118 and to the HFRF generator 104 via a transfer cable 120. Examples of transfer cables include electrical cables that transfer data in a parallel or serial manner, or using the Universal Serial Bus (USB) protocol. The LFRF generator 102 has an output 122 that is coupled to an input 126 of a matcher 107 via an RF cable 124. Similarly, the HFRF generator 104 has an output 128 that is coupled to an input 132 of the matcher 107 via an RF cable 130. The matcher 107 has an output 134 that is coupled to the lower electrode LE via an RF transmission line 136. A first branch of the matcher 107 is coupled between the input 126 and the output 134, and a second branch of the matcher 107 is coupled between the input 132 and the output 134. The upper electrode UE is coupled to ground potential.

[0025] The V sensor 110 is coupled to the processor 114 via a transmission cable 138, and the P sensor 112 is coupled to the processor 114 via a transmission cable 140. The V sensor 110 is coupled to an output 134 of the matcher 134. The P sensor 112 is also coupled to an output 128 of the HFRF generator 104. The output of the P sensor 112 is coupled to the HFRF generator 104. For example, the output of the P sensor 112 is coupled to a processor, such as a digital signal processor (DSP), of the HFRF generator 104 via a transmission cable 143.

[0026] The processor 114 generates a recipe signal 142 including a low frequency and one or more power levels of the RF signal 150 generated by the LFRF generator 102. For example, the low frequency is equal to the operating frequency of the LFRF generator 102. For example, the one or more power levels include one or more power amounts or one or more power values. For example, the power level includes a single power amount. For another example, the power level includes multiple power amounts within a predetermined range. The processor 114 transmits the recipe signal 142 to the LFRF generator 102 via the transfer cable 118. The processor 114 also generates a recipe signal 144 including a high frequency and one or more power levels of the RF signal 152 generated by the HFRF generator 104. For example, the high frequency is equal to the operating frequency of the HFRF generator 104. The processor 114 transmits the recipe signal 144 to the HFRF generator 104 via the transfer cable 120.

[0027] Upon receiving recipe signal 142, LFRF generator 102 generates RF signal 150 having the low frequency and one or more power levels indicated in recipe signal 142. LFRF generator 102 transmits RF signal 150 to matcher 107 via output 122, RF cable 124, and input 126. Similarly, upon receiving recipe signal 144, HFRF generator 104 generates RF signal 152 having the high frequency and one or more power levels indicated in recipe signal 144. HFRF generator 104 transmits RF signal 152 to matcher 107 via output 128, RF cable 130, and input 132.

[0028] Upon receiving RF signal 150, the first branch of matcher 107 matches the impedance of a load coupled to output 134 with the impedance of a source coupled to input 126, modifying the impedance of RF signal 150 to provide a first modified RF signal. Examples of loads coupled to output 134 include RF transmission line 136 and plasma chamber 108. Examples of sources coupled to input 126 include RF cable 124 and LFRF generator 102. Similarly, upon receiving RF signal 152, the second branch of matcher 107 matches the impedance of a load coupled to output 134 of matcher 107 with the impedance of a source coupled to input 132 of matcher 107, modifying the impedance of RF signal 152 to provide a second modified RF signal.

[0029] The matcher 107 combines, such as by adding together, the first and second modified RF signals to output a modified RF signal 154 at an output 134. The modified RF signal 154 is transmitted from the output 134 to the lower electrode LE via an RF transmission line 136. When one or more process gases, such as a fluorine-containing gas, an oxygen-containing gas, or a nitrogen-containing gas, are supplied to the gap between the lower electrode LE and the upper electrode UE, in addition to the modified RF signal 154, a plasma is discharged or sustained in the gap. The plasma processes the substrate S. Examples of processing the substrate S include etching features in the substrate S, depositing material on the substrate S, and cleaning the substrate S.

[0030] While the substrate S is being processed, the V sensor 110 measures the voltage at the output 134, outputs a voltage signal 156, and transmits the voltage signal 156 to the processor 114 via the transfer cable 138. Similarly, while the substrate S is being processed, the P sensor 112 measures the power, such as the delivered power or the reflected power, at the output 134, outputs a power signal 158, and transmits the power signal 158 to the processor 114 via the transfer cable 140.

[0031] In one embodiment, the V sensor 110 is coupled at any point on the RF transmission line 136 .

[0032] In one embodiment, the P sensor 112 is coupled at any point on the RF cable 130 .

[0033] 2A is one embodiment of a graph 200 illustrating a clock signal 202. By way of example, the clock signal 202 is generated by the processor 114 (FIG. 1). The x-axis of the graph 200 plots time t, ranging from time t0 to time t40. The y-axis of the graph 200 plots the voltage of the clock signal 202. The clock signal 202 periodically transitions between a logic level 1 and a logic level 0. A logic level 1 corresponds to 5 volts, and a logic level 0 corresponds to 0 volts.

[0034] Clock signal 202 transitions from logic level 0 to logic level 1 at time t0 and remains at logic level 1 from time t0 to time t10. At time t10, clock signal 202 transitions from logic level 1 to logic level 0 and remains at logic level 0 from time t10 to time t20. The transitions between logic levels 1 and 0 are repeated from time t20 to time t40. Clock signal 202 has cycle n from time t0 to time t20 and has a consecutive cycle (n+1) from time t20 to time t40, where n is a positive integer. After clock cycle (n+1), clock signal 202 has an additional clock cycle, such as clock cycle (n+2).

[0035] 2B is a graph 210 that plots one embodiment of a voltage signal 156, such as a delivered voltage signal, to illustrate binning. As an example, graph 210 is generated by processor 114 (FIG. 1) upon receiving voltage signal 156 from V-sensor 110 (FIG. 1).

[0036] The graph 210 plots the voltage signal 156 against time t. For example, the y-axis of the graph 210 represents the voltage of the voltage signal 156, and the x-axis of the graph 210 represents time t. The y-axis, starting in the positive y-direction, plots multiple voltage values ​​from V0 to V6. Also, the y-axis, starting in the negative y-direction, plots multiple voltage values ​​from V0 to −V6. The voltage value V6 is greater than the voltage value V0, and the voltage value −V6 is less than the voltage value V0. For example, the voltage value V0 is zero. As another example, the voltage value V0 is negative. As one example, the x-axis of the graph 210 represents time t at which the voltage value of the voltage signal 156 is received by the processor 114 from the V sensor 110.

[0037] The voltage signal 156 represents the voltage of the first modified RF signal, or primarily represents the voltage of the RF signal 150 generated by the LFRF generator 102. For example, the voltage signal 156 represents the voltage of the RF signal 150. As another example, the voltage signal 156 primarily represents the voltage of the RF signal 150 and minimally represents the voltage of the RF signal 152 generated by the HFRF generator 104 (FIG. 1). For example, the voltage of the voltage signal 156 is the voltage of the RF signal 150. As another example, 90% of the voltage of the voltage signal 156 is the voltage of the RF signal 150, and the remaining 10% of the voltage of the voltage signal 156 is the voltage of the RF signal 152. The voltage signal 156 extends over multiple clock cycles of the clock signal 202 (FIG. 2A). For example, the voltage signal 156 extends from time t0 to time t20, and the time interval between time t0 and t20 represents cycle n of the clock signal 202. The voltage signal 156 extends from time t20 to time t40, the time interval between time t20 and time t40 representing cycle (n+1) of the clock signal 202.

[0038] The processor 114 divides the voltage signal 156 during each cycle of the clock signal 202 into multiple bins, such as 10 or 20 bins. For example, during cycle n, the voltage signal 156 is divided into bins 1 through 10 of a cycle of the voltage signal 156, and during cycle (n+1), the voltage signal 156 is divided into bins 1 through 10 of another cycle of the voltage signal 156, and so on. For example, the processor 114 divides the voltage signal 156 during each cycle of the clock signal 202. For example, the voltage signal 156 is divided into 10 equal time intervals during each cycle, with each time interval designated by the processor 114 as a bin.

[0039] The processor 114 extends each bin over the same time interval. For example, bin 1 extends from time t0 to time t2, bin 2 extends from time t2 to time t4, bin 3 extends from time t4 to time t6, bin 4 extends from time t6 to time t8, and bin 5 extends from time t8 to time t10. Bin 5 may be referred to herein as bin 0. Bin 6 also extends from time t10 to time t12, bin 7 extends from time t12 to time t14, bin 8 extends from time t14 to time t16, bin 9 extends from time t16 to time t18, and bin 10 extends from time t18 to time t20.

[0040] The processor 114 identifies bin 0 as the time interval that includes the point where the voltage signal 156 crosses the x-axis and determines that point to be a negative zero crossing 214. For example, the processor 114 determines that the point where the voltage of the voltage signal 156 is zero and the slope of the voltage signal 156 is negative is a negative zero crossing 214. The slope of the voltage signal 156 is negative during the time interval of bin 0. As another example, at the negative zero crossing 214, the voltage of the voltage signal 156 is non-zero.

[0041] The processor 114 identifies one of bins 1 through 10 that contains the negative zero crossing 214, such as by designating it as bin 0. For example, bin 5 is designated as bin 0. Bins 1 through 4 and a first portion of bin 0 form a positive cycle of the voltage signal 156, and a second portion of bin 0 and bins 6 through 10 form a negative cycle of the voltage signal 156. The sum of the positive and negative cycles of the voltage signal 156 forms a cycle of the voltage signal 156. The first portion of bin 0, which is part of the positive cycle of the voltage signal 156, extends over the time interval from time t8 to time t9, when the negative crossing 214 occurs. The second portion of bin 0, which is part of the negative cycle of the voltage signal 156, extends over the time interval from time t9 to time t10.

[0042] FIG. 2C is an illustration of one embodiment of a graph 220 illustrating the generation of HF offset values, which are frequency values, at which the HFRF generator 104 (FIG. 1) is operated during processing of a substrate S. When the HFRF generator 104 operates at an operating frequency, the HFRF generator 104 generates an RF signal 152 (FIG. 1) having multiple frequency offset values, which are also frequency values. The graph 220 is generated by the processor 114 (FIG. 1). The graph 220 plots the HF offset values, which are offsets of the RF signal 152 from a reference high frequency value HF0, on the y-axis versus time t. The reference high frequency value HF0 is the frequency of the RF signal 152 during bin 0. Time t is plotted on the x-axis of the graph 220. For example, the x-axis of the graph 210 (FIG. 2B) is used as the x-axis of the graph 220.

[0043] The y-axis of graph 220 plots HF offset values ​​from high frequency value HF0. HF offset values ​​range from HF0 to HF2 in the positive y-direction and from HF0 to HF(-4) in the negative y-direction. Note that HF ​​offset values ​​increase from HF0 to HF2 and decrease from HF0 to HF(-4). For example, HF offset value HF1 exceeds high frequency value HF0, HF offset value HF2 exceeds HF offset HF1, and so on. Similarly, HF offset value HF(-1) is less than high frequency value HF0, HF offset value HF(-2) is less than HF offset value HF(-1), and so on.

[0044] Note that the HF offset value, or frequency offset value, is an offset, such as an addition or subtraction, from a reference high frequency value HF0 of the RF signal 152. For example, an HF offset HF(-0.5) is -0.5 MHz lower than the reference high frequency value HF0, and an HF offset HF2 is 2 MHz higher than the reference high frequency value HF0. As another example, a first frequency offset value is -0.4 MHz lower than the reference high frequency value HF0, and a second frequency offset value is 1.4 MHz higher than the reference high frequency value HF0. In this manner, the HFRF generator 104, having an operating frequency of 60 MHz, operates within a range of frequency values, such as between 57 MHz and 63 MHz, during each cycle of the clock signal 202.

[0045] As shown in graph 220, processor 114 applies an HF offset and a reference high frequency value HF0 during each cycle of clock signal 202. For example, processor 114 controls HFRF generator 104 to operate with an HF offset value HF(−0.5) during bin 1, an HF offset value HF(−2) during bin 2, an HF offset value HF(−4) during bin 3, an HF offset value HF(−1) during bin 4, a reference high frequency value HF0 during bin 0, an HF offset value HF1 during bin 6, an HF offset value HF0.5 during bin 7, an HF offset value HF2 during bin 8, an HF offset value HF1.5 during bin 9, and an HF offset value HF1 during bin 10. For example, processor 114 transmits recipe signal 144 ( FIG. 1 ) indicating that HFRF generator 104 is to generate an RF signal 152 with an HF offset (−0.5) during bin 1, an RF signal 152 with an HF offset (−2) during bin 2, etc. For example, upon receiving the recipe signal 144, the HFRF generator 104 generates an RF signal 152 that has an HF offset of (-0.5) during bin 1, an HF offset of (-2) during bin 2, and so on. The application of the reference high frequency value HF0 may be referred to herein as a bin frequency tuning method (BFT), and the determination of the HF offset based on the reference high frequency value HF0 and the power parameters, or the application of the HF offset, or both the determination and application, may be referred to herein as a pyramidal tuning (PT) method.

[0046] During a frequency adjustment operation, each HF offset value in a bin is determined and applied by the processor 114 based on the frequency offset value and a power parameter, such as a corresponding voltage reflection coefficient (Gamma or Γ) or voltage standing wave ratio (VSWR), for that bin. For example, during bin M of cycle Y, such as cycle n or cycle (np), of the clock signal 202 processing the substrate S, the processor 114 controls the HFRF generator 104 to operate at a respective frequency offset value, such as a first frequency offset value, and receives multiple power values ​​of the power signal 158 ( FIG. 1 ) from the P sensor 112. Here, M is any integer from 1 to 4 and 5 to 10, p is an integer less than the integer n, and Z is an integer. In this example, each frequency offset value is stored in the memory device 116 for access by the processor 114. Furthermore, in this example, the processor 114 determines a power parameter from the power value in bin M of cycle Y when the HFRF generator 104 operates at the respective frequency offset value. Also in this example, processor 114 accesses from memory device 116 ( FIG. 1 ) a value of forward power, which is the power supplied by HFRF generator 104 during bin M of cycle Y. In this example, processor 114 calculates a first statistical delivered power value, such as an average or median, from power values ​​received from P sensor 112 during bin M of cycle Y when HFRF generator 104 operates at each frequency offset value. In this example, the first statistical delivered power value is the value of power delivered by HFRF generator 104 during bin M of cycle Y. Also in this example, processor 114 subtracts the first statistical delivered power value from the forward power value at bin M of cycle Y to determine a first value of reflected power for bin M of cycle Y. In this example, processor 114 calculates a ratio between the first value of reflected power for bin M of cycle Y and the forward power value at bin M of cycle Y to calculate a first power reflection coefficient for bin M. Also in this example, processor 114 calculates the square root of the first power reflection coefficient for bin M of cycle Y to calculate a first voltage reflection coefficient for bin M of cycle Y.

[0047] Continuing with the present example, during bin M of cycle Z, such as cycle (n) or cycle (n-p+q) or cycle n, of the clock signal 202 processing the substrate S, the processor 114 controls the HFRF generator 104 to correct the respective frequency offset value to a respective HF offset value, such as HF offset value HF(-0.5), and receives multiple power values ​​of the power signal 158 (FIG. 1) from the P sensor 112, where q is an integer and the integer (n-p+q) is greater than the integer (n) but less than the integer n. In this example, the respective HF offset values ​​are stored in the memory device 116 for access by the processor 114. Further, in this example, the processor 114 determines a power parameter from the power value for bin M of cycle Z when the HFRF generator 104 operates at the respective HF offset value. In this example, the processor 114 accesses from the memory device 116 (FIG. 1) the value of the forward power, which is the power supplied by the HFRF generator 104 during bin M of cycle Z. In this example, the processor 114 calculates a second statistical delivered power value, such as an average or median, from the power values ​​received from the P sensor 112 during bin M of cycle Z when the HFRF generator 104 operates at each HF offset value. In this example, the second statistical delivered power value is the value of power delivered by the HFRF generator 104 during bin M. In this example, the processor 114 also subtracts the second statistical delivered power value for bin M of cycle Z from the forward power value at bin M of cycle Z to determine a second value of reflected power for bin M of cycle Z. In this example, the processor 114 also calculates a ratio between the second value of reflected power for bin M of cycle Z and the forward power value at bin M of cycle Z to calculate a second power reflection coefficient for bin M of cycle Z. In this example, the processor 114 also calculates the square root of the second power reflection coefficient for bin M of cycle Z to calculate a second voltage reflection coefficient for bin M of cycle Z.

[0048] Continuing with the present example, processor 114 compares the second voltage reflection coefficient to the first voltage reflection coefficient and determines that the second voltage reflection coefficient is less than the first voltage reflection coefficient. In this example, processor 114 determines to operate HFRF generator 104 at the respective HF offset value during bin M of cycle n, (n+1), etc. if the second voltage reflection coefficient is determined to be less than the first voltage reflection coefficient. Conversely, in this example, processor 114 determines to operate HFRF generator 104 at the respective HF offset value during bin M of cycle n, (n+1), etc. if the first voltage reflection coefficient is determined to be less than the second voltage reflection coefficient.

[0049] As another example, instead of comparing the second voltage reflection coefficient to the first voltage reflection coefficient, processor 114 compares the first voltage reflection coefficient or the second voltage reflection coefficient to a predetermined value to determine whether to operate HFRF generator 104 at the respective frequency offset value or the respective HF offset value during bin M of cycle n, (n+1), etc. For example, if it is determined that the first voltage reflection coefficient exceeds the predetermined value and the second voltage reflection coefficient is less than the predetermined value, processor 114 determines to operate HFRF generator 104 at the respective HF offset value during bin M of cycle n, (n+1), etc. On the other hand, for example, if it is determined that the second voltage reflection coefficient exceeds the predetermined value and the first voltage reflection coefficient is less than the predetermined value, processor 114 determines to operate HFRF generator 104 at the respective frequency offset value during bin M of cycle n, (n+1), etc.

[0050] As another example, processor 114 determines the ratio of the first sum to the first difference to output a first VSWR. Continuing with this example, the first sum is the sum of 1 and the first voltage reflection coefficient. In this example, the first difference is the difference between 1 and the first voltage reflection coefficient. Furthermore, in this example, processor 114 determines the ratio of the second sum to the second difference to output a second VSWR. Continuing with this example, the second sum is the sum of 1 and the second voltage reflection coefficient. In this example, the second difference is the difference between 1 and the second voltage reflection coefficient. In this example, processor 114 compares the second VSWR to the first VSWR and determines that the second VSWR is less than the first VSWR. In this example, if processor 114 determines that the second VSWR is less than the first VSWR, processor 114 determines to operate HFRF generator 104 at the respective HF offset values ​​during bin M of cycle n, (n+1), etc. The processor 114 applies the respective HF offset values ​​to the HFRF generator 104 by operating the HFRF generator 104 at the respective HF offset values ​​during bin M of cycle n, (n+1), etc. Further, in this example, the processor 114 determines that if the first VSWR is determined to be less than the second VSWR, then the processor 114 determines that the processor 114 operates the HFRF generator 104 at the respective frequency offset values ​​during bin M of cycle n, (n+1), etc. The processor 114 applies the respective frequency offset values ​​to the HFRF generator 104 by operating the HFRF generator 104 at the respective frequency offset values ​​during bin M of cycle n, (n+1), etc.

[0051] As another example, instead of comparing the second VSWR to the first VSWR, processor 114 compares the first VSWR or the second VSWR to a predetermined value to determine whether to operate HFRF generator 104 at the respective frequency offset value or the respective HF offset value during bin M of cycle n, (n+1), etc. For example, if it is determined that the first VSWR exceeds the predetermined value and the second VSWR is less than the predetermined value, processor 114 determines to operate HFRF generator 104 at the respective HF offset value during bin M of cycle n, (n+1), etc. On the other hand, for example, if it is determined that the second VSWR exceeds the predetermined value and the first VSWR is less than the predetermined value, processor 114 determines to operate HFRF generator 104 at the respective frequency offset value during bin M of cycle n, (n+1), etc.

[0052] Note that, by way of example, reflected power is the power reflected from the plasma chamber 108, the RF transmission line 136, the matcher 107, and the RF cable 130 (FIG. 1) toward the HFRF generator 104. The power reflected toward the HFRF generator 104 may be referred to herein as high frequency reflected power.

[0053] In one embodiment, the frequency offset value may be referred to herein as the HF offset.

[0054] 3A is a diagram of one embodiment of a system 300 illustrating a power limiter filter 316. The system 300 includes a controller system 302, a driver and amplifier system 304, and a power supply 306. The driver and amplifier system 304 includes a driver and an amplifier. For example, the driver is coupled to the power limiter filter 316 on one end and to the amplifier on the opposite end. An example of the driver includes one or more transistors. An example of the power supply 306 is an electronic oscillator that generates an RF signal having a sinusoidal waveform.

[0055] Controller system 302 includes a BFT+PT applicator 308, referred to herein as applicator 308. Examples of applicator 308 are a processor or controller, such as processor 114 (FIG. 1). As described herein, examples of a controller are a DSP, a microcontroller, a combination of one or more processors and one or more memory devices, an ASIC, and a PLD. Controller system 302 further includes a supply power calculator 312, a power limiter 314, and a power limiter filter 316. By way of example, applicator 308 is part of or components of host computer 106 (FIG. 1). In this example, power limiter 314, power limiter filter 316, and supply power calculator 312 are part of or components of a controller of HFRFG 104. Also in this example, driver and amplifier system 304 and power supply 306 are components of HFRFG 104. For example, the functionality of applicator 308 described herein may be implemented by processor 114, and the functionality of power limiter 314, power limiter filter 316, and supplied power calculator 312 described herein may be implemented by a DSP in HFRF generator 104. Further, for example, processor 114 performs the functions described herein as being performed by applicator 308. An example of supplied power calculator 312 is a processor, such as a DSP in HFRF generator 104, or a controller in HFRF generator 104. Also, an example of power limiter 314 is a processor or controller, an example of power limiter filter 316 is a processor or controller, and an example of supplied power calculator 312 is a processor or controller.

[0056] Applicator 308 is coupled to power limiter 314 and power limiter filter 316. Power limiter filter 316 is coupled to power limiter 314. For example, applicator 308 is coupled to power limiter 314 and power limiter filter 316 via transmission cable 120 (FIG. 1). Power limiter 314 and power limiter filter 316 are coupled to supplied power calculator 312. Supply power calculator 312 is coupled to driver 304, which is coupled to power supply 306. The functionality of controller system 302 is described below with reference to FIG. 3B.

[0057] In one embodiment, one or more functions of the applicator 308, the supplied power calculator 312, the power limiter 314, and the power limiter filter 316 described herein are implemented or performed by one or more controllers. For example, one or more functions of the applicator 308, the supplied power calculator 312, the power limiter 314, and the power limiter filter 316 are implemented or performed by the processor 114. As another example, one or more functions of the applicator 308, the supplied power calculator 312, the power limiter 314, and the power limiter filter 316 are implemented or performed by a controller of the HFRF generator 104.

[0058] 3B is a flow chart illustrating one embodiment of a method 320 for determining whether to limit the power provided by the HFRFG 104 (FIG. 1). The method 320 is performed by the controller system 302 (FIG. 3A).

[0059] Method 320 includes operation 322, which is performed by applicator 308 (FIG. 3A). Operation 322 occurs during cycle Y. When HFRF generator 104 is operated at each frequency offset value from bins 1 through 10 during cycle Y, processor 114 receives high-frequency reflected power from P sensor 112 during each time interval from bins 1 through 10 and calculates an average reflected power from the high-frequency reflected power. For example, processor 114 receives high-frequency reflected power values ​​RP1 during bin 1, RP2 during bin 2, and so on, until it receives high-frequency reflected power value RP10 during bin 10. In this example, processor 114 calculates the average value of the high-frequency reflected power received during bins 1 through 10 to determine the average reflected power. For example, processor 114 calculates the average value of the values ​​RP1 through RP10 by dividing the sum of values ​​RP1 through RP10 by 10. In operation 322, the processor 114 compares the average reflected power to a maximum limit value to determine whether the average reflected power is less than the maximum limit value. The maximum limit value is a value stored in the memory device 116 (FIG. 1). The maximum limit value is received from a user via an input device for storage in the memory device 116. Examples of input devices include a keyboard, a mouse, a keypad, and a status. The input device is coupled to the processor 114 via an input / output interface. As another example, an average VSWR or an average voltage reflection coefficient is used instead of the average reflected power. It should be noted that the average VSWR or the average voltage reflection coefficient is representative of the average reflected power.

[0060] If the average reflected power is determined to be equal to or greater than the maximum limit, such as equal to or greater than the maximum limit, the processor 114 issues a misadjustment alarm in operation 324 of method 320. For example, the processor 114 controls a display device to generate a notification indicating that the radio frequency of the HFRF generator 104 is in a misadjusted state. The processor 114 is coupled to the display device. Examples of the display device include a liquid crystal display (LCD), a light emitting diode (LED) display, and a plasma display.

[0061] On the other hand, if the average reflected power is determined to be less than the maximum limit, then in operation 326 of method 320, applicator 308 determines whether the high frequency reflected power in a plurality of bins, such as all bins 1 through 10, during a cycle of voltage signal 156 is less than a predetermined threshold for one of the plurality of bins. Operation 326 occurs during cycle Y. The predetermined threshold for one of the plurality of bins is stored in memory device 116 and received from a user via an input device.

[0062] To determine whether the RF reflected power is less than a predetermined threshold, the applicator 308 compares the RF reflected power in each bin within a cycle of the voltage signal 156 with a predetermined threshold. For example, the applicator 308 compares the value of the RF reflected power RP1 with a predetermined threshold to determine whether the value is less than the predetermined threshold. In this example, the applicator 308 compares each of the values ​​RP2 through RP10 with a predetermined threshold to determine whether each of the values ​​RP2 through RP10 is less than the predetermined threshold. Furthermore, in this example, if each of the values ​​RP1 through RP10 is determined to be less than the predetermined threshold, the applicator 308 determines that the RF reflected power in the multiple bins is less than the predetermined threshold. On the other hand, in this example, if at least one of the values ​​RP1 through RP10 is determined to be equal to or greater than the predetermined threshold, such as equal to or greater than the predetermined threshold, the applicator 308 determines that the RF reflected power in the multiple bins is equal to or greater than the predetermined threshold.

[0063] If the RF reflected power in the plurality of bins is determined to be less than a predetermined threshold, the applicator 308 activates the power limiter 314 in operation 328 of method 320. If the power limiter 314 is activated, the applicator 308 also controls the HFRF generator 104 ( FIG. 1 ) to increase the forward power of the RF signal 152 ( FIG. 1 ) to meet a set value in operation 330 of method 320. For example, in operation 320, the processor 104 sends a signal to the power limiter 314 via the transmission cable 120 ( FIG. 1 ) to limit, e.g., cap, the increase in the amount of forward power of the RF signal 152. In this example, the applicator 308 also sends a command via the transmission cable 120 to the supplied power calculator 312 to increase the forward power supplied by the HFRF generator 104 until the set value is achieved or until the limit is reached, whichever occurs first. Additionally, in this example, a copy of the command sent to the power supply calculator 312 is sent to the power limiter 314 .

[0064] For example, upon receiving a signal to limit the increase in the amount of forward power of the RF signal 152 during cycle Z, the power limiter 314 is triggered, for example, to operate, and when triggered, the power limiter 314 determines to limit, for example, to set an upper limit, the increase in the amount of forward power of the RF signal 152. In this example, the increase in the amount of power is limited during cycle Z. For example, the power limiter 314 determines that an increase in the amount of forward power in the command to the supply power calculator 312 could lead to damage to components of the driver and amplifier system 304 (FIG. 3A) and determines to limit the increase in the amount of forward power to a pre-limited amount. In this example, the power limiter 314 accesses the pre-limited amount from a memory device of the HFRF generator 104 and reduces the increase in the amount of forward power to the pre-limited amount.

[0065] In this example, when it is determined that the supply of power by the HFRF generator 104 should be limited to the pre-limited amount of power, the power limiter 314 generates and sends a control signal to the supplied power calculator 312 during cycle Z. Furthermore, in this example, upon receiving the control signal, the supplied power calculator 312 sends a command signal to the driver and amplifier system 304 to limit, for example, by reducing the increase in the amount of forward power of the RF signal 152 to the pre-limited amount. Also, in this example, upon receiving the command signal to achieve the limit, the driver of the driver and amplifier system 304 generates a current signal based on the pre-limited amount and sends the current signal to the amplifier of the driver and amplifier system 304. In this example, upon receiving the current signal, the amplifier amplifies, for example, by increasing or decreasing the amplitude of the current signal to achieve limiting the amount of power of the RF signal 152 to the pre-limited amount, outputs the amplified signal, and sends the amplified signal to the RF power supply 306. Further, in the example, upon receiving the amplified signal, the RF power supply 306 generates the amount of power in the RF signal 152 to achieve the pre-limited amount during cycle Z.

[0066] On the other hand, if operation 332 of method 320 determines that the high frequency reflected power in multiple bins is greater than or equal to the predetermined threshold, then applicator 308 determines whether the number of misadjusted bins exceeds a predetermined number. Operation 332 is performed during cycle Y. For example, based on the comparison in operation 326, applicator 308 determines that the high frequency reflected power is greater than or equal to the predetermined threshold for each of bins 1, 2, and 4, and therefore determines that bins 1, 2, and 4 are misadjusted. For example, processor 114 controls HFRF generator 104 to operate at a respective frequency offset value for each of bins 1, 2, and 4, compares the high frequency reflected power received from P sensor 112 during each of bins 1, 2, and 4 with the predetermined threshold, and determines that the high frequency reflected power is greater than or equal to the predetermined threshold for each of bins 1, 2, and 4.

[0067] Further, in this example, applicator 308 counts the number of bins 1, 2, and 4 to generate a number of miscalibrated bins, such as three. Also, in this example, applicator 308 compares the number 3 with a predetermined number to determine whether the number 3 exceeds the predetermined number. In this example, if it is determined that the number 3 exceeds the predetermined number, applicator 308 determines that a plurality of bins exceeds the predetermined number. Further, in this example, on the other hand, if it is determined that the number 3 is equal to or less than the predetermined number, applicator 308 determines that the number of miscalibrated bins is less than the predetermined number.

[0068] If the number of misadjusted bins is determined to exceed the predetermined number, operation 324 is performed. On the other hand, if the number of misadjusted bins is determined to be less than or equal to the predetermined number, such as equal to or less than the predetermined number, applicator 308 sends a signal to power limiter filter 316 to activate power limiter filter 316.

[0069] In operation 334 of method 320, power limiter filter 316 is activated. By activating power limiter filter 316, the number of misadjusted bins in operation 332 is ignored by power limiter filter 316 and power limiter 314. Also, when power limiter filter 316 is activated, in operation 330 of method 320, applicator 308 controls HFRF generator 104 (FIG. 1) to increase the forward power of RF signal 152 (FIG. 1) to match the set value. For example, in operation 334, processor 104 sends a signal to power limiter 314 to activate it, and simultaneously sends a signal to power limiter filter 316 via transmission cable 120 (FIG. 1) to activate it. In this example, a signal is sent to the power limiter filter 316 to control, such as by reducing, removing, or not applying, the limit on the increase in the amount of forward power of the RF signal 152. Also in this example, the applicator 308 sends a command to the supplied power calculator 312 via the transmission cable 120 to increase the forward power supplied by the HFRF generator 104 until a set value is achieved. In this example, a copy of the command to increase the forward power is sent to the power limiter 314 and the power limiter filter 316.

[0070] For example, upon receiving a signal to increase the amount of forward power of RF signal 152 during cycle Z, power limiter 314 and power limiter filter 316 are triggered, for example, to operate. In the example, when triggered, power limiter 314 determines to limit, for example, by setting an upper limit, the increase in the amount of forward power of RF signal 152 to a pre-limited amount. In the example, the increase in the amount of power is limited during cycle Z. Also in the example, when power limiter filter 316 is triggered, power limiter filter 316 determines to control to limit the increase in the amount of forward power of RF signal 152. In the example, power limiter 314 accesses the pre-limited amount from a memory device of HFRF generator 104, reduces the increase in the amount of forward power to the pre-limited amount, and provides the pre-limited amount to power limiter filter 316.

[0071] In this example, when it is determined to control the limit on the power supply by the HFRF generator 104, the power limiter filter 316 generates a control signal to remove or reduce the pre-limited amount during cycle Z and sends it to the supplied power calculator 312. Furthermore, in this example, upon receiving the control signal, the supplied power calculator 312 sends a command signal to the driver and amplifier system 304 to control, for example, to reduce or remove the limit on the increase in the amount of forward power of the RF signal 152. Also, in this example, upon receiving the command signal to control the limit, the driver of the driver and amplifier system 304 generates a current signal based on the control signal and sends the current signal to the amplifier of the driver and amplifier system 304. In this example, upon receiving the current signal, the amplifier amplifies, for example, by increasing or decreasing the amplitude of the current signal to obtain a set value for the forward power of the RF signal 152, outputs an amplified signal, and sends the amplified signal to the RF power supply 306. Furthermore, in this example, upon receiving the amplified signal, the RF power supply 306 generates the amount of power of the RF signal 152 to obtain a set value during cycle Z.

[0072] Thus, in method 320, in operation 322, the pacing quality is represented by an average value, such as an average voltage reflection coefficient, or average VSWR, or average reflected power, and the power limiter 314 and power limiter filter 316 are operated based on the average power. Sometimes, the set point may be a low power setting. When the set point is a low power setting, the pacing quality is ignored, and the low power setting is provided by increasing the forward power. If the high frequency reflected power in multiple bins is below a predetermined threshold, it is safe for the HFRF generator 104 to increase the forward power because there is little risk.

[0073] It should be noted that in embodiments, some of the operations described above may be performed over multiple cycles of clock signal 202 .

[0074] The embodiments described herein may be practiced with various computer system configurations including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, etc. The embodiments described herein may also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0075] In some embodiments, the controller is part of a system, which may be part of the examples described above. The system includes semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). The system is integrated with electronics to control the operation of the electronics before, during, and after processing of the semiconductor wafer or substrate. The electronics may control various components or subcomponents of the system, referred to as a "controller." The controller may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or system type. Such processes may include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from the tool, and wafer transfer to and from other transport tools and / or load locks connected or interfaced to the system.

[0076] Broadly, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits include chips in the form of firmware that store program instructions, DSPs, chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various personalizations (or program files) that define operational parameters for performing processes on or for semiconductor wafers. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0077] The controller, in some embodiments, may be part of or coupled to a computer that is integrated into, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer system, thereby enabling remote access for wafer processing. By enabling remote access to the system, the controller can monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance metrics from multiple fabrication operations, modify parameters of a current process, set up processing steps following a current process, or initiate a new process.

[0078] In some embodiments, a remote computer (e.g., a server) provides the process recipe to the system over a computer network, including a local network or the Internet. The remote computer includes a user interface that allows for input or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of settings for processing wafers. It should be understood that the settings are specific to the type of process being performed and the type of tool the controller interfaces with or controls. Thus, as described above, the controller is distributed, such as by including one or more separate controllers that are networked together and work toward a common purpose, such as performing the processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on the chamber that are remotely located (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperatively control the process within the chamber.

[0079] In various embodiments, the plasma systems described herein include, but are not limited to, plasma etch chambers, deposition chambers, spin rinse chambers, metal plating chambers, cleaning chambers, bevel edge etch chambers, physical vapor deposition (PVD) chambers, chemical vapor deposition (CVD) chambers, atomic layer deposition (ALD) chambers, atomic layer etch (ALE) chambers, ion implantation chambers, track chambers, or any other semiconductor processing chambers associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0080] It is further noted that while the operations described above are described with reference to a parallel plate plasma chamber, e.g., a capacitively coupled plasma chamber, in some embodiments, the operations described above also apply to other types of plasma chambers, e.g., plasma chambers including inductively coupled plasma (ICP) reactors, transformer coupled plasma (TCP) reactors, plasma chambers including conductor tools, dielectric tools, electron cyclotron resonance (ECR) reactors, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor in an ICP plasma chamber.

[0081] As described above, depending on the process operations being performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from containers of wafers to tool locations and / or load ports within the semiconductor fabrication factory.

[0082] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are operations that physically manipulate physical quantities.

[0083] Some embodiments also relate to hardware units or apparatus for performing these operations, where the apparatus is specifically constructed for use as a special-purpose computer. When defined as a special-purpose computer, the computer performs other processes, program execution, or routines that are not part of its dedicated purpose, but remains operable for its dedicated purpose.

[0084] In some embodiments, the operations described herein are performed by a selectively activated computer, configured by one or more programs stored in computer memory, or obtained over a computer network. When data is obtained over a computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0085] Also, one or more embodiments described herein may be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROMs (CD-ROMs), CD recordables (CD-Rs), CD rewritables (CD-RWs), magnetic tape, and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium comprises computer-readable tangible media distributed over network-coupled computer systems so that the computer-readable code is stored and executed in a distributed fashion.

[0086] Although some of the method operations above have been presented in a particular order, it should be understood that in various embodiments, other housekeeping operations are performed between the method operations, or the method operations are adjusted to occur at slightly different times, or are distributed across the system so that the method operations can occur at various intervals, or are performed in an order other than that set forth above.

[0087] It is further noted that in one embodiment, one or more features of any of the above-described embodiments may be combined with one or more features of any other embodiment without departing from the scope described in the various embodiments described in this disclosure.

[0088] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. The present embodiments are therefore to be considered illustrative and not restrictive, and may be modified within the scope and equivalents of the appended claims.

Claims

1. 1. A method for controlling limits on power provided by a high frequency (HF) radio frequency (RF) generator, comprising: determining whether an average power reflected back toward the HFRF generator is less than a maximum limit; if the average power is determined to be less than the maximum limit, determining whether the power reflected back toward the HFRF generator for a number of bins during a cycle is less than a predetermined threshold; determining whether a number of misaligned bins exceeds a predetermined number in response to determining that the power reflected toward the HFRF generator in the plurality of bins during the cycle is equal to or greater than the predetermined threshold; activating a power limiter filter when the number of misadjusted bins is determined to be less than or equal to the predetermined number. A method comprising:

2. 2. The method of claim 1 , The method further comprising activating a power limiter if the power reflected back towards the HFRF generator in the plurality of bins during the cycle is determined to be less than the predetermined threshold.

3. 3. The method of claim 2, The method further comprising increasing the power provided by the HFRF generator when the power limiter is activated.

4. 2. The method of claim 1 , The method further comprising increasing the power supplied by the HFRF generator when the power limiter filter is activated.

5. 2. The method of claim 1 , The method further comprising issuing a misalignment alarm if the average power reflected back towards the HFRF generator is determined to be equal to or greater than the maximum limit.

6. 2. The method of claim 1 , The method further comprising issuing a misalignment alarm if the number of misaligned bins is determined to exceed the predetermined number.

7. 2. The method of claim 1 , The method, wherein the plurality of bins includes all of the bins in the cycle.

8. 2. The method of claim 1 , The method, wherein the cycles are cycles of a voltage signal at an output of an impedance matching circuit coupled to the HFRF generator.

9. 1. A controller for controlling limits on power provided by a high frequency (HF) radio frequency (RF) generator, comprising:

1. A processor comprising: determining whether the average power reflected back to the HFRF generator is less than a maximum limit; if the average power is determined to be less than the maximum limit, determining whether the power reflected back to the HFRF generator for a number of bins during a cycle is less than a predetermined threshold; determining whether a number of misaligned bins exceeds a predetermined number in response to determining that the power reflected toward the HFRF generator in the plurality of bins during the cycle is equal to or greater than the predetermined threshold; configured to activate a power limiter filter when the number of misadjusted bins is determined to be less than or equal to the predetermined number. A processor; a memory device coupled to the processor; A controller comprising:

10. 10. The controller of claim 9, The controller, wherein the processor is configured to activate a power limiter if the power reflected towards the HFRF generator in the plurality of bins during the cycle is determined to be less than the predetermined threshold.

11. 11. The controller of claim 10, The controller, wherein the processor is configured to increase the power supplied by the HFRF generator when the power limiter is activated.

12. 10. The controller of claim 9, The controller, wherein the processor is configured to increase the power supplied by the HFRF generator when the power limiter filter is activated.

13. 10. The controller of claim 9, The controller, wherein the processor is configured to issue a misalignment alarm if the average power reflected back towards the HFRF generator is determined to be equal to or greater than the maximum limit.

14. 10. The controller of claim 9, The controller, wherein the processor is configured to issue a misadjustment alarm if the number of misadjusted bins is determined to exceed the predetermined number.

15. 10. The controller of claim 9, The plurality of bins includes all of the bins in the cycle.

16. 10. The controller of claim 9, The cycles are cycles of a voltage signal at an output of an impedance matching circuit coupled to the HFRF generator.

17. 1. A plasma system for controlling limitations on power provided by a high frequency (HF) radio frequency (RF) generator, comprising: a low frequency (LF) RF generator configured to generate a LF RF signal; an HFRF power source configured to generate an HFRF signal; a matcher coupled to the LFRF generator and the HFRF generator to receive the LFRF signal and the HFRF signal and to output a modified signal; a plasma chamber coupled to the matcher to receive the modified signal; a controller coupled to the HFRF power source; Equipped with The controller: determining whether the average power reflected back to the HFRF generator is less than a maximum limit; if the average power is determined to be less than the maximum limit, determining if the power reflected back to the HFRF generator for a number of bins during a cycle is less than a predetermined threshold; determining whether a number of misaligned bins exceeds a predetermined number in response to determining that the power reflected back to the HFRF generator in the plurality of bins during the cycle is equal to or greater than the predetermined threshold; The plasma system configured to activate a power limiter filter when the number of misadjusted bins is determined to be less than or equal to the predetermined number.

18. 20. The plasma system of claim 17, The plasma system, wherein the controller is configured to activate a power limiter when the power reflected toward the HFRF generator in the plurality of bins during the cycle is determined to be less than the predetermined threshold.

19. 20. The plasma system of claim 18, The plasma system, wherein the controller is configured to increase the power supplied by the HFRF generator when the power limiter is activated.

20. 20. The plasma system of claim 17, The plasma system, wherein the controller is configured to increase the power supplied by the HFRF generator when the power limiter filter is activated.

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