SRAM Gate Spacer Structure

Abstract

Apparatus and techniques are disclosed for fabricating an apparatus including a semiconductor device, the semiconductor device including one or more static random access memory (SRAM) transistors each including a first gate spacer structure, one or more logic nominal transistors each including a second gate spacer structure, and one or more logic gate bias transistors each including a third gate spacer structure, the third gate spacer structure being thinner than the first gate spacer structure, and the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each having the same contact poly pitch (CPP).

Description

[Technical field]

[0001] Aspects of the present disclosure relate generally to apparatus including semiconductor devices, and more particularly, but not exclusively, to gate spacer structures and fabrication techniques for same in high density circuits. [Background technology]

[0002] Wireless communication systems have evolved through various generations, including first-generation analog wireless telephone service (1G), second-generation (2G) digital wireless telephone service (including interim 2.5G and 2.75G networks), third-generation (3G) high-speed data, Internet-enabled wireless service, and fourth-generation (4G) service (e.g., Long Term Evolution (LTE) or WiMax). Currently, many different types of wireless communication systems are in use, including cellular systems and personal communications service (PCS) systems. Examples of known cellular systems include the cellular analog advanced mobile phone system (AMPS) and digital cellular systems based on code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), etc.

[0003] The fifth generation (5G) wireless standard, called New Radio (NR), will enable higher data transfer speeds, more connections, and better coverage, among other improvements. The 5G standard from the Next Generation Mobile Network Alliance is designed to offer higher data rates, more accurate positioning, and other technological enhancements compared to previous standards.

[0004] Technologies and advancements in wireless communications are transforming the automotive industry. Modern vehicles can be fully cloud-connected, allowing passengers to connect with the car in a fully immersive experience. Modern vehicles that are connected to everything (e.g., wireless connectivity, sensors, etc.) can provide driver assistance that enables higher safety. This level of connectivity comes with extremely high processing requirements for the car to sense, process, and make decisions in real-time. The high processing demands are driving the adoption of cutting-edge technology nodes in the automotive industry to meet these capacity performance needs.

[0005] Integrated circuit technology has achieved great strides in advancing computing power through the miniaturization of active components, enabling practical implementation and commercialization of the aforementioned wireless communication systems and their components. However, miniaturization of circuits and devices can pose fabrication and design challenges. Technologies such as 5 nanometer (nm) and below suffer from high defect rates and yield loss due to very dense designs. For example, in high density static random access memory (SRAM) bitcell designs, gate-source / drain (S / D) contact shorts are a significant cause of defects during fabrication as well as qualification. Technology scaling pushes designers to shrink the gate-S / D space, which is further exacerbated in SRAM bitcells due to aggressive design between various nodes. These short defects represent a high defect per million (DPPM) risk for consumer and automotive products. Demanding applications such as advanced driver-assistance system (ADAS) products require high-density SRAM designs to support the computing needs of these types of applications.

[0006] Reliability requirements for demanding applications / products such as ADAS products can be on the order of 1 DPPM. However, conventional designs, including those using advanced technology nodes (e.g., 5 nm and beyond), have DPPM on the order of thousands. Accordingly, there is a need for systems, devices, and methods that overcome the shortcomings of conventional gate structures and high density circuit designs, including the methods, systems, and devices provided herein in the following disclosure. Summary of the Invention

[0007] The following presents a simplified summary of one or more aspects of the disclosed herein. As such, the following summary is not intended to be an extensive overview of all contemplated aspects, nor is it intended to identify key or critical elements of all contemplated aspects or to delineate the scope of any particular aspect. Accordingly, the sole purpose of the following summary is to present certain concepts of one or more aspects of the mechanisms disclosed herein in a simplified form prior to the detailed description presented below.

[0008] In accordance with various aspects disclosed herein, at least one aspect includes an apparatus comprising a semiconductor device including one or more static random access memory (SRAM) transistors, each including a first gate spacer structure, one or more logic nominal transistors, each including a second gate spacer structure, and one or more logic gate bias transistors, each including a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, and the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP).

[0009] In accordance with various aspects disclosed herein, at least one aspect includes a method for manufacturing a semiconductor device, comprising: forming one or more static random access memory (SRAM) transistors, each including a first gate spacer structure; forming one or more logic nominal transistors, each including a second gate spacer structure; and forming one or more logic gate bias transistors, each including a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, and wherein the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP).

[0010] Other objects, features and advantages associated with the apparatus and methods disclosed herein will become apparent to one skilled in the art based on the accompanying drawings and detailed description.

[0011] The accompanying drawings are presented to aid in the explanation of various aspects of the present disclosure and for a more complete understanding of the same, many of the attendant advantages of which will become better understood and readily obtained by reference to the following detailed description and by consideration of the accompanying drawings, which are presented merely to illustrate, and not to limit, the present disclosure. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 illustrates a semiconductor device including an SRAM bit cell, a logic standard cell having a nominal device, and a logic standard cell having a gate bias device, in accordance with one or more aspects of the present disclosure. [Figure 2A] 1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Figure 2B]1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Figure 2C] 1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Figure 2D] 1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Figure 2E] 1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Figure 2F] 1A-1D illustrate cross-sectional views of various aspects of a semiconductor device including an SRAM bit cell, a logic standard cell with a nominal device, and a logic standard cell with a gate bias device in accordance with one or more aspects of the present disclosure. [Diagram 3] 1 illustrates a simplified diagram of logic blocks within a SoC in accordance with one or more aspects of the present disclosure. [Figure 4A] 1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Figure 4B] 1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Figure 4C] 1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Figure 4D] 1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Figure 4E]1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Figure 4F] 1 illustrates portions of one or more processes for manufacturing a semiconductor device according to one or more aspects of the present disclosure. [Diagram 5] 1 illustrates a flowchart of a method for manufacturing a semiconductor device in accordance with one or more aspects of the present disclosure. [Figure 6] 1 illustrates components of an apparatus according to one or more aspects of the present disclosure. [Figure 7] 1 illustrates an exemplary user device, in accordance with one or more aspects of the present disclosure. [Figure 8] 1 illustrates various electronic devices that may be integrated with any of the aforementioned devices, in accordance with one or more aspects of the present disclosure.

[0013] According to common practice, features illustrated in the drawings may not be drawn to scale. Accordingly, dimensions of illustrated features may be arbitrarily expanded or reduced for clarity. According to common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not show all components of a particular apparatus or method. Moreover, like reference numerals refer to like features throughout the specification and figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The disclosed aspects of the present disclosure are illustrated in the following description and associated drawings that are directed to specific aspects of the present disclosure. Alternative aspects may be devised without departing from the scope of the teachings of the present disclosure. In addition, well-known elements of exemplary aspects of the present disclosure may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings of the present disclosure.

[0015] In certain described example implementations, instances are identified in which various component structures and operational portions are derived from known conventional techniques and configured in accordance with one or more exemplary aspects. In such instances, internal details of known conventional component structures and / or operational portions may be omitted to help avoid potential obscuration of the concepts illustrated in the exemplary aspects disclosed herein.

[0016] The terms used herein are merely for the purpose of describing particular aspects and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] As mentioned above, reliability requirements for demanding applications / products such as ADAS products can be on the order of 1 DPPM. However, conventional designs, including the use of advanced technology nodes (e.g., 5 nm and beyond), have DPPM on the order of 1000. Conventional designs have attempted to use conservative designs for reliability, limiting the use of blocks that use the minimum spacing that allows for the best technology scaling (density). For example, some conventional designs have included (1) increasing the distance between the gate and source / drain contacts (gate pitch) in SRAM HD cells (which increases the bit cell area in the X direction, thus increasing the chip area), (2) increasing the distance between nodes [cross-coupling] (which increases the bit cell area in the Y direction, thus increasing the chip area), (3) screening with high dynamic voltage stress and other screening methods (which proved insufficient for 5 nm node designs), and (4) expensive burn-in stress and system level testing (which proved insufficient for 5 nm node designs).

[0018] In designs of 5nm FinFET devices and beyond with very small dimensions, gate-S / D shorts are one of the major defects for yield and reliability. It has been very difficult to eliminate these defects using conventional designs and processes. Various products have suffered increased customer returns due to these defects. As the desire for high performance computing systems-on-chip continues to grow, demanding use cases from autonomous driving, augmented / mixed reality, gaming, and smart cities will benefit from adopting cutting edge technologies such as 5nm node and beyond to meet their computing needs, but this comes with high risks to reliability and yield.

[0019] These shorts are mostly seen in high density SRAMs due to the overlap / proximity of the gate edge and S / D contacts used to reach the maximum density offered by the technology (e.g., 5 nm). To design the highest density SRAM HD cells, the XY dimensions of the cell cannot be changed for a given technology.

[0020] The proximity of the gate cut to the S / D contact introduces a systematic process weakness to the replacement metal gate module (e.g., due to residual metal at the edge of the gate). Because the S / D contact is very close to this residual metal, a short potential is created between the gate (G) and the S / D. This GS / D short is more pronounced in SRAM high-density (HD) cells than in high current (HC) cells because there is less node-to-node space / separation.

[0021] According to various aspects of the disclosure, the apparatus and semiconductor devices including the SRAM transistor structures disclosed herein may be used to improve defectivity (DPPM, yield) while maintaining very high design density. At least some of the various aspects of the disclosure relate to developing alternative gate spacer structure schemes for SRAM designs while maintaining the maximum density offered in a given technology. In some aspects, the gate spacer structures in the SRAM transistors and logic nominal transistors have additional thickness relative to the logic gate bias transistors, which may be thinned or have one or more spacer layers removed during fabrication. The increased gate spacer structure thickness eliminates gate-S / D contact shorts in the bit cells without affecting the logic gate bias transistors in non-critical paths of the design (e.g., in logic blocks and memory periphery). Conventional solutions to solve gate-S / D short defects are as follows: prohibit the use of high density SRAMs, increase the outer spacer thickness in the entire area of ​​the chip, and prohibit the use of logic gate bias device designs (longer channel devices used in logic blocks to reduce leakage and important for reducing chip static power).

[0022] At least some of the various aspects of the disclosure include a thinner gate spacer structure in the logic gate bias transistor than in the SRAM transistor (or SRAM and logic nominal transistor) at the same gate pitch / contact poly pitch (CPP). In some aspects, the gate spacer structure is formed by multiple gate spacer layers, and the thickness can be increased by increasing the thickness of one or more gate spacer layers (or not decreasing the thickness of one or more gate spacer layers) for the logic gate bias device) or by increasing the number of layers only in the SRAM transistor (or SRAM and logic nominal device). For example, an additional outer spacer layer can be added, or the thickness of the existing outer spacer layer can be increased (or not decreased). In some aspects, the thickness or number of layers of only the gate spacer structure in the logic gate bias device can be reduced. According to at least some of the aspects of the disclosure, this eliminates (or substantially reduces) gate-S / D contact shorts in the bitcell without impacting the chip / SoC area.

[0023] As mentioned above, conventional solutions to solve gate-S / D short defects are: prohibiting the use of HD SRAM, increasing the thickness of the outer spacer in the whole area of ​​the chip, and prohibiting the use of logic gate bias devices (energy-efficient devices used in logic blocks to reduce leakage / static power). These solutions used by foundries bring great disruption to the design and increase the area and cost of semiconductor devices (e.g., integrated circuits (ICs), chips, dies, SoCs, etc.).

[0024] Various aspects of the disclosure allow for the use of building blocks of a given technology (e.g., high density SRAM, logic gate bias devices, etc.) while addressing gate-S / D shorts and maintaining desirable chip area / cost. Furthermore, various aspects of the disclosure require little or no additional design effort, and in some aspects, only one additional low-cost mask is used.

[0025] FIG. 1 illustrates a portion of a semiconductor device 100 according to at least one embodiment of the present disclosure. A top view of a portion of a standard cell design is shown. The standard cell design may include one or more transistors, and while only one transistor element may be referenced or illustrated in some of the drawings, it will be understood that this does not preclude the presence of additional transistors. Furthermore, references to a particular cell or transistor may be applied interchangeably to other similar cells and / or transistors within the cell. In particular, FIG. 1 illustrates an SRAM high density (HD) bit cell (SRAM cell 110), a nominal logic transistor cell (logic nominal cell 130), and a logic gate bias transistor cell (logic gate bias cell 150). The various transistor cells may include 3D transistor structures (e.g., FinFET, nanosheet, nanowire, vertical FET, etc.) with epitaxial source / drain regions. It will be understood that for a given technology (e.g., 5 nm), there are logic nominal (standard) devices for speed and logic gate bias devices for leakage management (longer gate length with the same CPP). Furthermore, it will be understood that the CPPs (e.g., 115, 135, and 155) of each standard design are the same for design simplification, design density improvement, and fabrication standardization. However, the gate-to-gate space in the logic gate bias cell 150 is smaller than that in the logic nominal cell 130 or the SRAM cell 110. It will be understood that the first gate length 117 of the SRAM cell 110 and the second gate length 137 of the logic nominal cell 150 are the same (a), but each is smaller than the third gate length 157 (a') of the logic gate bias cell 130. The SRAM cell 110 further includes a source / drain (S / D) contact 112, a gate 116, a gate contact 118, and shows a gate cut 111. As discussed above, portion 125 is a weak spot for potential gate-to-S / D shorts due to the gate cut / replacement metal gate process and the close proximity of S / D contacts 112. Logic nominal cell 130 further includes source / drain (S / D) contact 132, gate 136, gate contact 138, and exhibits gate cut 131.The logic gate bias cell 150 further includes a source / drain (S / D) contact 152 , a gate 156 , a gate contact 158 ​​, and exhibits a gate cut 151 .

[0026] It will be appreciated that the SRAM cell 110, the logic nominal cell 130, and the logic gate bias cell 150 have the same CPP. The first gate length 117 of the SRAM cell 110 and the second gate length 137 of the logic nominal cell 130 are the same and are on the order of three nanometers (3 nm) or less (e.g., 3 nm or less) shorter than the third gate length 157 of the logic gate bias cell 150. However, as mentioned above and further described below, the spacer of the logic gate bias cell 150 will be thinner than the spacer of the SRAM cell 110 or the logic nominal cell 130.

[0027] 2A-2F illustrate a portion of a semiconductor device 200 in accordance with at least one embodiment of the present disclosure. Specifically, cross-sectional views of the portion of the semiconductor device include transistors for an SRAM cell 210 in FIG. 2A, a logic nominal cell 230 in FIG. 2B, and a logic gate bias cell 250 in FIG. 2C.

[0028] 2A illustrates a cross-sectional view of a portion of an SRAM cell 210 including one or more SRAM transistors 211, in accordance with at least one embodiment of the present disclosure. The SRAM cell 210 includes a first gate length 217 (also labeled a) and has a CPP 215 between gates 216 and a gate spacer-to-gate spacer opening 213 (also labeled b) between gate spacer structures 218. An S / D contact 212 is disposed in the opening 213 between the gate spacer structures 218 and contacts an S / D epitaxy region 214 in the SRAM cell 210. It will be appreciated that the opening 213 is a function of the CPP 215, the gate-to-gate spacing 219, the first gate length 217, and the thickness of the gate spacer structure 218.

[0029] 2B illustrates a cross-sectional view of a portion of a logic nominal cell 230 including one or more logic nominal transistors 231, according to at least one embodiment of the present disclosure. The logic nominal cell 230 includes a second gate length 237 (also labeled a) and has a CPP 235 between gates 236 and a gate spacer-to-gate spacer opening 233 (also labeled b) between gate spacer structures 238. An S / D contact 232 is disposed in the opening 233 between the gate spacer structures 238 and contacts an S / D epitaxy region 234 in the logic nominal cell 230. It will be appreciated that the opening 233 is a function of the CPP 235, the gate-to-gate space 239, the second gate length 237, and a thickness of the gate spacer structure 238, which in this view is similar to the gate spacer structure 218 of the SRAM cell 210. It will be appreciated that the various aspects of the disclosure are not limited to the gate spacer structures (218, 238) of the SRAM cell 210 and the logic nominal cell 230 being the same.

[0030] 2C illustrates a cross-sectional view of a portion of a logic gate bias cell 250 including one or more gate bias transistors 251, in accordance with at least one embodiment of the present disclosure. The logic gate bias cell 250 includes a third gate length 257 (also labeled a′) and has a CPP 255 between gates 256 and a gate spacer-to-gate spacer opening 253 (also labeled b″) between gate spacer structures 258. An S / D contact 252 is disposed in the opening 253 between the gate spacer structures 258 and contacts an S / D epitaxy region 254 in the logic gate bias cell 250. It will be appreciated that the opening 253 is a function of the CPP 255, the gate-to-gate spacing 259, the third gate length 257, and the thickness of the gate spacer structure 258.

[0031] As described above, the SRAM cell 210, the logic nominal cell 230, and the logic gate bias cell 250 generally have the same CPP. Furthermore, the second gate length 237 of the logic nominal cell 230 is also the same as the first gate length 217 of the SRAM cell 210. However, the first gate length 217 of the SRAM cell 210 is shorter than the third gate length 257 of the logic gate bias cell 250. Each technology (e.g., 5 nm) has logic nominal device (minimum width) specifications (e.g., SRAM cell 210 and logic nominal cell 230) for high frequency operation and gate bias devices (e.g., logic gate bias cell 250) with larger gate lengths for leakage / energy management. As shown, the SRAM cell 210, the logic nominal cell 230, and the gate bias cell 250 have the same CPP (e.g., CPP 215, CPP 235, and CPP 255, respectively). However, unlike conventional designs, the reduced gate spacer structure thickness of logic gate bias cell 250 allows for an increased opening 253 between gate spacer structures 258 as described herein compared to conventional designs. In the illustrated example, the outer gate spacer layer of gate spacer structure 258 has a reduced thickness compared to the outer gate spacer layer of gate spacer structure 218 of FIG. 2A. However, it will be understood that the various aspects are not limited to this illustrated configuration, which is provided merely as an example to help explain various aspects of the disclosure.

[0032] 2C, in various aspects of the disclosure, the opening 253(b") from gate spacer structure 258 to gate spacer structure 258 in logic gate bias cell 250 is larger than the opening 273(b') from gate spacer structure 278 to gate spacer structure 278 (e.g., the space between gate spacer structures) in conventional logic gate bias cell 270. It will be understood that conventional logic gate bias cell 270 and gate spacer structure 278 are shown in part and are provided merely for comparison purposes. Controlling the thickness of gate spacer structure 258 of logic gate bias cell 250 to have a thinner dimension than SRAM cell 210 (or conventional logic gate bias design) helps ensure sufficient opening 253 into S / D epitaxy region 254 to allow for the formation and connection of S / D contact 252. The gate-to-gate spacer structure 273(b') of SRAM cell 210 is larger than the opening 273(b') of conventional logic gate bias cell 270 (e.g., the space between gate spacer structures). Since the gate spacing 219 is larger than the gate-to-gate spacing 259 of the logic gate bias cell 250, this would reduce the opening (e.g., 253) / space between the gate spacer structures 258 if the thickness of the gate spacer structures was not reduced relative to the gate spacer structures 218 of the SRAM cell 210. In contrast, conventional techniques may use a uniform increase in the outer spacers (e.g., the fourth spacer in this figure across the chip) to address, for example, gate-to-S / D shorts in the bit cells. However, as shown in conventional logic gate bias cell 270, this may result in an increase in the problem of "S / D contact non-opening" in the logic gate bias cell 270, where there is an opening 275 under the S / D contact 272 (i.e., the opening 273 is too narrow, preventing the S / D contact 272 from adequately connecting to the S / D epitaxy region).

[0033] In contrast, according to various aspects of the disclosure, in the logic gate bias cell 250, the gate spacer structure 258 is thinner relative to the gate spacer structure 218 of the SRAM cell 210 (or the SRAM cell 210 and the logic nominal cell 230) to prevent an overly narrow S / D contact opening 253. In some aspects, the semiconductor device 200 includes one or more static random access memory (SRAM) transistors 211, each including a first gate spacer structure 218, and one or more logic nominal transistors 231, each including a second gate spacer structure 238. In addition, the semiconductor device 200 includes one or more logic gate bias transistors 251, each including a third gate spacer structure 258. The third gate spacer structure 258 is thinner than the first gate spacer structure 218 or the first and second gate spacer structures (218 and 238). The first gate spacer structure 218 has a first thickness, the second gate spacer structure 238 has a second thickness, and the third gate spacer structure 258 has a third thickness. In some embodiments, the first thickness or the first and second thicknesses are 20% to 30% greater than the third thickness. In some embodiments, the first thickness is 8.5 nm to 9 nm. In some embodiments, the second and third thicknesses can be the same. In other embodiments, the second thickness can be less than the first thickness and greater than the third thickness.

[0034] In some embodiments, as shown in FIG. 2D, the first gate spacer structure 218 of the SRAM transistor 211 and the second gate spacer structure 238 of the logic nominal transistor 231 may have the same material, the same number of spacer layers (e.g., SP1, SP2, SP3, and SP4), and the same thickness. In some embodiments, as shown in FIG. 2E, the first gate spacer structure 218 of the SRAM transistor 211 and the second gate spacer structure 238 of the logic nominal transistor 231 may include one or more spacer layers (e.g., SP1, SP2, SP3, and SP4) that are different in material and have the same number of spacer layers and the same thickness. In some embodiments, as shown in FIG. 2F, the first gate spacer structure 218 of the SRAM transistor 211 and the second gate spacer structure 238 of the logic nominal transistor 231 may include different numbers of spacer layers. For example, the first gate spacer structure 218 may include spacer layers SP1, SP2, SP3, and SP4. In contrast, the second gate spacer structure 238 may include spacer layers SP1, SP2, and SP3. In some embodiments, one or more of the spacer layers may be formed of different materials. Furthermore, in some embodiments, the first gate spacer structure 218 of the SRAM transistor 211 and the second gate spacer structure 238 of the logic nominal transistor 231 may have different thicknesses, with the second gate spacer structure 238 being thinner than the first gate spacer structure 218.

[0035] From the illustrated exemplary configurations, it will be understood that various aspects of the disclosure are not limited to one configuration of gate spacer structures or the relationship between gate spacer structures of different transistors. For example, in some aspects, the first gate spacer structure 218 (or the first and second gate spacer structures 218 and 238) comprises a first material and a second material, and the third gate spacer structure 258 comprises a second material. In some aspects, the first gate spacer structure 218 (or the first and second gate spacer structures 218 and 238) and the third gate spacer structure 258 each comprise at least one of silicon nitride, silicon dioxide, silicon boride, silicon carbide, oxynitride, or combinations thereof. In some embodiments, the thickness of the first gate spacer structure 218 (or the first and second gate spacer structures 218 and 238) may be increased compared to the third gate spacer structure 258 by adding one or more additional spacer layers to the first gate spacer structure 218 (or the first and second gate spacer structures 218 and 238).

[0036] In some embodiments, each of the SRAM transistor 211, the logic nominal transistor 231, and the logic gate bias transistor 251 is a three-dimensional transistor (3D transistor), such as a FinFET, a nanosheet, a nanowire, and / or a vertical FET. In some embodiments, the SRAM transistor 211 / SRAM cell 210, the logic nominal transistor 231 / cell 230, and the logic gate bias transistor 251 / cell 250 each have the same contact poly pitch (CPP), which may be set to a minimum value for a given technology (e.g., 5 nm). In some embodiments, the SRAM transistor 211 and the logic nominal transistor 231 each have a first gate length 217 and a second gate length 237 (also labeled a), and the logic gate bias transistor 251 each have a third gate length 257 (also labeled a′), where the third gate length 257 is greater than the first gate length 217 and the second gate length 237 (i.e., a′>a). It will be understood that the various figures provided herein are merely provided to aid in explaining the various aspects, and are not drawn to any particular scale or relative sizes of components or layers. Accordingly, the various aspects of the disclosure are not limited to the illustrated examples provided in the accompanying figures.

[0037] FIG. 3 illustrates a semiconductor device 300 according to at least one embodiment of the present disclosure. In the illustrated plan view, the semiconductor device 300 includes a plurality of logic nominal transistor cells (logic nominal cells 330) and logic gate bias transistor cells (logic gate bias cells 350). The logic nominal cells 330 are placed on a critical path 305 (e.g., the path with the longest delay in the semiconductor device 300, the path that limits the operating frequency of the digital block 301, the processor, etc.). As described above, the logic nominal cells 330 support high frequencies, while the logic gate bias cells 350 have reduced leakage, but also reduced switching speed. It will be appreciated that by using the logic nominal cells 330 in the critical path and the logic gate bias cells 350 elsewhere, the design of the semiconductor device 300 can be optimized to provide a very high speed and very low leakage design for a given technology without impacting the area used.

[0038] In order to fully explain the design aspects of the present disclosure, a method of fabrication is presented. Other methods of fabrication are possible, and the described method of fabrication is presented only to aid in understanding the concepts disclosed herein.

[0039] 4A-4F illustrate a fabrication technique according to one or more aspects of the present disclosure. It will be understood that the following fabrication process is provided merely as a general illustration of some of the aspects of the present disclosure, and is not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of various aspects of the disclosure without detailed description of each detail and / or every possible process variation.

[0040] For example, the fabrication process may follow some initial steps such as source / drain (S / D) formation using a PMOS first process. However, an NMOS first process may also be used. In some embodiments, the process may include PMOS spacer deposition and SRAM PMOS (pull-up) patterning and etching (A mask). The process may continue with logic PMOS patterning and etching (B mask). The process may continue with SRAM and logic PMOS epitaxial growth. The process may continue with logic and SRAM NMOS spacer deposition, patterning, and NMOS epitaxial growth (C mask). At this stage, further details are provided below.

[0041] Referring to FIG. 4A, a portion of a fabrication process for a semiconductor device 400 is shown in accordance with at least one embodiment of the present disclosure. Cross-sectional views of a PMOS SRAM transistor 410, a PMOS logic gate bias transistor 450, an NMOS SRAM transistor 470, and an NMOS logic gate bias transistor 480 are shown. The logic nominal transistor is not explicitly shown. However, according to various embodiments of the disclosure, it will be understood that in some embodiments, the logic nominal transistor may be processed together with the SRAM transistor 410 and therefore will have approximately the same gate spacer structure as the SRAM transistor 410. In other embodiments, the logic nominal transistor may be processed together with the logic gate bias transistor 480 and therefore will have approximately the same gate spacer structure as the logic gate bias transistor 480. It will be understood that any of these options may be achieved by the use of one additional mask as described herein. However, in other alternative embodiments, the logic nominal transistor may be processed differently from both the SRAM transistor 410 and the logic gate bias transistor 480 using additional mask and process steps as described herein (e.g., FIGS. 2D-2F) such that the gate spacer structure of the logic nominal transistor includes a different design than the SRAM transistor 410. Accordingly, the various aspects disclosed herein are not limited to the alternative configurations of the logic nominal transistor having the same gate spacer structure as either the SRAM transistor 410 or the logic gate bias transistor 480 described below.

[0042] As described above, PMOS source / drain epitaxial regions 414 and 454 for PMOS transistors 410 and 450, and NMOS source / drain epitaxial regions 474 and 484 for NMOS transistors 470 and 480 are fabricated. Additionally, gates 416, 456, 476, and 486 for PMOS SRAM transistor 410, PMOS logic gate bias transistor 450, NMOS SRAM transistor 470, and NMOS logic gate bias transistor 480, respectively, are shown. Each gate 416, 456, 476, and 486 has a gate spacer structure 440, 460, 440, and 460, respectively, formed in part from multiple spacer layers 441, 442, and 443. It will be understood that the various aspects are not limited to a particular number of spacer layers. Additionally, each layer shown may be formed from the deposition of one or more layers of material. As described above, a first gate spacer structure 440 is formed for the gates 416 and 476 of the SRAM transistors 410 and 470, and a third gate spacer structure 460 is formed for the gates 456 and 486 of the logic gate bias transistors 450 and 480. In some embodiments where a logic nominal transistor is processed together with the SRAM transistor or the logic gate bias transistor, the second gate spacer structure of the logic nominal transistor will be as shown at 440 or 460. Accordingly, specific examples of second gate spacer structures are not provided herein.

[0043] Referring to FIG. 4B, a portion of a fabrication process of a semiconductor device 400 is shown according to at least one embodiment of the present disclosure. The process continues with a first option having a uniform (e.g., over all areas) outer layer deposition (e.g., in this figure, the fourth spacer layer 444). The spacer layer 444 increases the thickness of the first gate spacer structure 440 for the gates 416 and 476 of the SRAM transistors 410 and 470, and the third gate spacer structure 460 for the gates 456 and 486 of the logic gate bias transistors 450 and 480. The spacer layer 444 may be formed from one or more layers of the same material to build up the thickness of the first gate spacer structure 440 and the third gate spacer structure 460 at this stage of the process.

[0044] Referring to FIG. 4C, a portion of the fabrication process of the semiconductor device 400 is shown according to at least one embodiment of the present disclosure. The process continues with a second option having a uniform deposition (e.g., over all areas) of a fourth spacer layer 444 and a fifth spacer layer 445. It will be understood that the specific number of layers (e.g., fourth and fifth) is provided merely for illustration and should not be construed as limiting the various disclosed or claimed aspects to any specific number of layers. The deposition of the spacer layer 444 and the spacer layer 445 increases the thickness of the first gate spacer structure 440 for the gates 416 and 476 of the SRAM transistors 410 and 470 and the third gate spacer structure 460 for the gates 456 and 486 of the logic gate bias transistors 450 and 480. The spacer layer 445 may include a different material than the spacer layer 444. At this stage of the process, both the first gate spacer structure 440 and the third gate spacer structure 460 include spacer layer 444 and spacer layer 445 .

[0045] Referring to FIG. 4D, a portion of the fabrication process of the semiconductor device 400 according to at least one embodiment of the present disclosure is illustrated. The process continues with deposition and patterning of photoresist 492 such that the PMOS SRAM transistor 410 and the NMOS SRAM transistor 470 are blocked. The PMOS logic gate bias transistor 450 and the NMOS logic gate bias transistor 480 are open. For convenience of illustration, in this embodiment and the following illustrated embodiments, a first optional spacer configuration is used in which the spacer layer 444 is the outer layer of both the first gate spacer structure 440 and the third gate spacer structure 460. However, it will be understood that this process and the following process can also be applied to the second optional configuration of FIG. 4C. In addition, it will be understood that only one additional mask (D mask) can be used to perform the process described herein. The additional mask can be generated using existing markers. In addition, the material of the outer spacer layer (e.g., 444 or 445) can be different from the other spacer layers to better control the etching process.

[0046] Referring to FIG. 4E, a portion of the fabrication process of the semiconductor device 400 according to at least one embodiment of the present disclosure is illustrated. The process continues with an etching process. A photoresist 492 covers the PMOS SRAM transistor 410 and the NMOS SRAM transistor 470 during the etching process. The spacer layer 444a is an outer layer of the third gate spacer structure 460 of the PMOS logic gate bias transistor 450 and the NMOS logic gate bias transistor 480 and is exposed to the etching process. Accordingly, the spacer layer 444a is thinner than the spacer layer 444 of the first gate spacer structure 440 after the etching process, and the third gate spacer structure 460 is thinner than the first gate spacer structure 440.

[0047] Referring to FIG. 4F, a portion of the fabrication process of the semiconductor device 400 is shown according to at least one embodiment of the present disclosure. The process continues with the removal of the photoresist 492. A PMOS SRAM transistor 410, a PMOS logic gate bias transistor 450, an NMOS SRAM transistor 470, and an NMOS logic gate bias transistor 480 are shown for option 1 and option 2. In option 1, the spacer layer 444a is an outer layer of the third gate spacer structure 460 and is thinner than the spacer layer 444, which is the outer layer of the first gate spacer structure 440, as described above. In option 2, the spacer layer 444 is an outer layer of the third gate spacer structure 460 and the spacer layer 445 is an outer layer of the first gate spacer structure 440. Accordingly, the first gate spacer structure 440 has an additional spacer layer, and therefore the third gate spacer structure 460 is thinner than the first gate spacer structure 440.

[0048] In some aspects, the fabrication process can continue with a gate cut process, a replacement metal gate process, and further fabrication of the semiconductor device 400 from either option as known in the art, and therefore no further details are provided. It will be understood that various aspects are not limited to proceeding with the gate cut process and replacement metal gate process described, as additional and / or alternative conventional processing steps can be performed with respect to the fabrication of the semiconductor device 400. For example, in some aspects where the SRAM transistors are different from the logic nominal transistors, the mask definition (e.g., D' mask) is different. In this design, the SRAM transistors are blocked, but the logic nominal transistors and the logic gate bias transistors are open, resulting in the same gate spacer structure for the logic nominal transistors and the logic gate bias transistors. In further aspects, additional masks and processing steps can be used during fabrication to provide a design in which the SRAM transistors, the logic nominal transistors, and the logic gate bias transistors each have a different gate spacer structure. Accordingly, various aspects of the disclosure are not limited to the illustrated process steps, as additional and / or alternative processing steps can be performed with respect to the fabrication of the semiconductor devices disclosed herein.

[0049] From the above, it will be understood that there are various methods for fabricating the device disclosed herein. Figure 5 shows a simplified flowchart of a method 500 for fabricating a semiconductor device according to one or more embodiments of the disclosure. The method 500 may begin in block 502 with forming one or more static random access memory (SRAM) transistors, each including a first gate spacer structure. The method may continue in block 504 with forming one or more logic nominal transistors, each including a second gate spacer structure. The method may continue in block 506 with forming one or more logic gate bias transistors, each including a third gate spacer structure, the third gate spacer structure being thinner than the first gate spacer structure, and the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each having the same contact poly pitch (CPP).

[0050] It will be appreciated from the above disclosure to one of ordinary skill in the art that additional processes for fabricating various aspects of the disclosure will be apparent, and that literal representations of the processes described herein have not been provided or shown in the accompanying drawings. Furthermore, it will be appreciated that the sequence of fabrication processes is not necessarily in any order, and may be performed simultaneously and / or later processes may be described earlier for convenience in describing various aspects of the disclosure.

[0051] 6 illustrates components of an apparatus 600 according to one or more aspects of the present disclosure. Regardless of the various configurations of the semiconductor devices 610 (e.g., die, SOC, etc.), each includes one or more of the transistors having the first, second, and third gate spacer structures described above. In the illustrated embodiment, a package 620 may be configured to couple the semiconductor device 610 to a PCB 690. It will be appreciated that in some aspects, the semiconductor device 610 may be directly coupled to the PCB 690. The PCB 690 is also coupled to a power source 680 (e.g., a power management integrated circuit (PMIC)), which allows the package 620 and the semiconductor device 610 to be electrically coupled to the PMIC 680. Specifically, one or more power (VDD) lines 691 and one or more ground (GND) lines 692 may be coupled to the PMIC 680 and distribute power to the PCB 690, the package 620, and to the semiconductor device 610 via a VDD BGA pin 625 and a GND BGA pin 627. Each of the VDD and GND lines 691 and 692 may be formed from traces, shapes, or patterns in one or more metal layers (e.g., layers 1-6) of the PCB 690 coupled through one or more vias that penetrate an insulating layer that separates the metal layers 1-6 in the PCB 690. The PCB 690 may include one or more PCB capacitors (PCB caps) 695, which may be used to condition the power signal, as known to those skilled in the art. Additional connections and devices may be coupled to package 620 via one or more additional BGA pins (not shown) on package 620 and / or may reach package 620 via additional BGA pins through PCB 690. It will be understood that the illustrated configurations and descriptions are provided merely to aid in explaining various aspects disclosed herein. For example, PCB 690 may have a greater or lesser number of metal and insulating layers, there may be multiple lines supplying power to various components, etc.Accordingly, the above illustrative examples and associated figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0052] According to various aspects disclosed herein, at least one aspect includes an apparatus, the apparatus including a semiconductor device (e.g., 100, 200, 300, and 400) having one or more static random access memory (SRAM) transistors (e.g., 211, 410, 470), each including a first gate spacer structure (e.g., 218, 440), one or more logic nominal transistors (e.g., 231), each including a second gate spacer structure (e.g., 218, 440), and one or more logic gate bias transistors (e.g., 251, 450, 480), each including a third gate spacer structure (e.g., 258, 460), the third gate spacer structure being thinner than the first gate spacer structure, the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each having the same contact poly pitch (CPP). Various aspects of the disclosure provide various technical advantages. For example, in at least some embodiments, the feature of having a thinner third gate spacer structure allows for improved leakage performance, while the relatively thicker first gate spacer structure of the SRAM and the relatively thicker second gate spacer structure of the logic nominal device allows for improved speed / operation frequency while maintaining the same CCP. The feature of having a thinner third gate spacer structure in the logic gate bias transistor versus the gate spacer structure in the SRAM or SRAM and / logic nominal device allows for improved yield and reliability while maintaining the same CPP, and also allows for improved manufacturability. The coexistence and joint optimization of both the nominal and gate bias devices is important in the overall leakage and performance of the product. Other technical advantages are recognized from various embodiments disclosed herein, and these technical advantages are provided merely as examples and should not be construed as limiting any of the various embodiments disclosed herein.

[0053] FIG. 7 illustrates an exemplary user device, according to some embodiments of the present disclosure. Referring now to FIG. 7, a block diagram of a user device, generally designated as user device 700, configured in accordance with an exemplary aspect is depicted. In some aspects, user device 700 may be configured as a wireless communication device. As shown, user device 700 includes a processor 701. Processor 701 may be communicatively coupled to memory 732 via a link, which may be a die-to-die link or a chip-to-chip link. User device 700 also includes a display 728 and a display controller 726, which is coupled to processor 701 and display 728.

[0054] In some aspects, FIG. 7 may include a coder / decoder (codec) 734 (e.g., an audio and / or voice codec) coupled to the processor 701, a speaker 736 and a microphone 738 coupled to the codec 734, and a wireless circuit 740 (which may include a modem, RF circuitry, filters, etc.) coupled to a wireless antenna 742 and the processor 701.

[0055] In certain aspects where one or more of the digital blocks described above (including SRAM, logic nominal transistors, and logic gate bias transistors) are present, the processor 701, display controller 726, memory 732, codec 734, and / or wireless controller 740 may be included in a system-in-package or system-on-chip device 722. The input device 730 (e.g., a physical or virtual keyboard), power source 744 (e.g., a battery), display 728, speaker 736, microphone 738, and wireless antenna 742 may be external to the system-on-chip device 722 and may be coupled to components such as interfaces or controllers of the system-on-chip device 722.

[0056] 7 illustrates a user device 700, a processor 701, and a memory 732, as well as wireless components, it should be noted that not all components may be used in various aspects of the disclosure. Accordingly, the user device 700 may also be a set-top box, a music player, a video player, an entertainment unit, a navigation device, a personal digital assistant (PDA), a fixed location data unit, a computer, a laptop, a tablet, a communication device, a mobile phone, or other similar device. Furthermore, the user device 700, the processor 701, and the memory 732 may also be integrated into automotive applications where reliability is important, such as advanced driver assistance systems.

[0057] FIG. 8 illustrates various electronic devices that may be integrated with any of the aforementioned integrated or semiconductor devices according to various embodiments of the present disclosure. For example, a mobile phone device 802, a laptop computer device 804, a fixed location terminal device 806, and a vehicle 808 may each be generally considered user equipment (UE) and may include a semiconductor device 800 including one or more of an SRAM transistor, a logic nominal transistor, and a logic gate bias transistor as described herein. The semiconductor device 800 may be, for example, any of the integrated circuits, dies, integrated devices, integrated device packages, integrated circuit devices, device packages, integrated circuit (IC) packages, and package-on-package devices described herein. The devices 802, 804, 806, and 808 illustrated in FIG. 8 are merely examples. Other electronic devices may also feature semiconductor device 800, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, in-vehicle devices including one or more processors such as advanced driver assistance systems, portable data units such as handheld personal communications system (PCS) units, personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), Internet of things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0058] The devices and functionality disclosed above may be designed and configured in computer files (e.g., Register-Transfer Level (RTL), Geometric Data Stream (GDS) Gerbers, etc.) stored on a computer-readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting products may include semiconductor wafers, which are then cut into semiconductor dies and packaged into semiconductor packages, integrated devices, system-on-chip devices, etc., which may then be used in the various semiconductor devices described herein.

[0059] It will be understood that various aspects disclosed herein may be described as functional equivalents of structures, materials, and / or devices described and / or recognized by those skilled in the art. For example, in one aspect, an apparatus may include means for performing the various functionality described above. It will be understood that the foregoing aspects are provided merely by way of example, and that the various aspects claimed are not limited to the specific references and / or figures cited as examples.

[0060] One or more of the components, processes, features, and / or functions shown in FIGS. 1-8 may be rearranged and / or combined into a single component, process, feature, or function, or integrated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It is also noted that FIGS. 1-8 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some implementations, FIGS. 1-8 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce an integrated device. In some implementations, the device may include a die, an integrated device, a die package, an integrated circuit (IC), a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, etc.

[0061] As used herein, terms such as "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal", and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, fixed location terminals, tablet computers, computers, wearable devices, laptop computers, servers, in-vehicle devices, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). These terms are also intended to include a device that communicates with another device capable of receiving wireless communication and / or navigation signals, such as by a short-range wireless connection, infrared connection, wireline connection, or other connection, regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing is performed on the device or on another device. A UE may be embodied by any of several types of devices, including, but not limited to, a Printed Circuit (PC) card, a Compact Flash device, an external or internal modem, a wireless or wireline phone, a smartphone, a tablet, a consumer tracking device, an asset tag, and the like.

[0062] Wireless communication between electronic devices can be based on various technologies, such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread), or other protocols that may be used in wireless or data communication networks.

[0063] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other embodiments. Likewise, the term "embodiment" does not imply that all embodiments include all discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0064] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, and may encompass the presence of an intermediate element between two elements that are "connected" or "coupled" together through the intermediate element, unless the connection is expressly disclosed as being directly connected.

[0065] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise specified, a set of elements can include one or more elements.

[0066] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0067] Nothing described or illustrated in this application is intended to publicly disclose any element, action, feature, benefit, advantage, or equivalent, whether or not that element, action, feature, benefit, advantage, or equivalent is recited in a claim.

[0068] Moreover, those skilled in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithmic actions described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate that hardware and software can be substituted for one another, the various illustrative components, blocks, modules, circuits, and actions have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may realize the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as departing from the scope of the present disclosure.

[0069] Although some aspects have been described with respect to devices, it will be understood that these aspects also constitute a description of the corresponding methods, and thus blocks or components of the device should also be understood as corresponding method actions or features of the method actions. Similarly, aspects described with respect to or as method actions also constitute a description of corresponding blocks, or details or features of the corresponding device. Some or all of the method actions can be performed by (or using) a hardware apparatus, such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, some or more of the most important method actions can be performed by such an apparatus.

[0070] In the above detailed description, it can be seen that various features are grouped together in each embodiment. This mode of disclosure should not be understood to intend that the exemplary clauses have more features than are expressly stated in each clause. Rather, various aspects of the disclosure may include fewer than all features of each exemplary clause disclosed. Thus, the following clauses should be considered to be incorporated in the description, and each clause can stand as a separate example in itself. Although each dependent clause may refer to a specific combination with one of the other clauses in the clause, the aspect(s) of that dependent clause are not limited to that specific combination. It will be understood that other exemplary clauses may also include combinations of the aspect(s) of the dependent clause with the subject matter of any other dependent clause or independent clause, or combinations of any features with other dependent clauses and independent clauses. Various aspects disclosed herein expressly include these combinations, unless it is expressly stated or readily inferred that a particular combination (e.g., inconsistent aspects, such as defining an element as both an insulator and a conductor) is not intended. It is further contemplated that aspects of a clause may be included in any other independent clause, even if the clause is not directly dependent on an independent clause.

[0071] The following numbered clauses describe example implementations.

[0072] Clause 1. An apparatus comprising a semiconductor device, the semiconductor device comprising one or more static random access memory (SRAM) transistors, each including a first gate spacer structure, one or more logic nominal transistors, each including a second gate spacer structure, and one or more logic gate bias transistors, each including a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, and the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP).

[0073] Clause 2. The device of clause 1, wherein the second gate spacer structure has the same thickness as the first gate spacer structure.

[0074] Clause 3. The device of clause 1, wherein the second gate spacer structure has the same thickness as the third gate spacer structure.

[0075] Clause 4. The device of any one of clauses 1 to 3, wherein the second gate spacer structure has at least one different material relative to the first gate spacer structure.

[0076] Clause 5. The device of any one of clauses 1 to 4, wherein the second gate spacer structure has a different number of spacer layers than the first gate spacer structure.

[0077] Clause 6. The device of clause 1, wherein the first gate spacer structure has a first thickness, the second gate spacer structure has a second thickness, and the third gate spacer structure has a third thickness, the first thickness and the second thickness being greater than the third thickness.

[0078] Clause 7. The device of any one of clauses 1 to 6, wherein the first gate spacer structure has a first thickness, the third gate spacer structure has a third thickness, and the first thickness is between 20 percent and 30 percent greater than the third thickness.

[0079] Clause 8. The device of any one of clauses 1 to 7, wherein the first gate spacer structure comprises the same material as the second gate spacer structure and the third gate spacer structure.

[0080] Clause 9. The device of any one of clauses 1 to 8, wherein the outer spacer layer of the third gate spacer structure is thinner than the outer spacer layer of the first gate spacer structure.

[0081] Clause 10. The device of any one of clauses 1 to 9, wherein the first gate spacer structure includes at least one additional spacer layer than the third gate spacer structure.

[0082] Clause 11. The device of clause 1, wherein the second gate spacer structure includes at least one additional spacer layer than the third gate spacer structure.

[0083] Clause 12. The device of any one of clauses 1 to 11, wherein the first gate spacer structure, the second gate spacer structure, and the third gate spacer structure comprise at least one of silicon nitride, silicon dioxide, silicon boride, silicon carbide, oxynitride, or a combination thereof.

[0084] Clause 13. An apparatus according to any one of clauses 1 to 12, wherein the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors are three dimensional transistors (3D transistors).

[0085] Clause 14. The device of clause 13, wherein the 3D transistor is at least one of a FinFET, a nanosheet, a nanowire, or a vertical FET.

[0086] Clause 15. An apparatus as described in any one of clauses 1 to 14, wherein the one or more SRAM transistors each have a first gate length, the one or more logic nominal transistors each have a second gate length, and the one or more logic gate bias transistors each have a third gate length, the third gate length being greater than the first gate length and the second gate length.

[0087] Clause 16. The device of clause 15, wherein the third gate length is less than 3 nanometers longer than the first gate length.

[0088] Clause 17. An apparatus as described in any one of clauses 1 to 16, wherein one or more SRAM transistors each have a first gate-to-gate space, one or more logic nominal transistors each have a second gate-to-gate space, and one or more logic gate bias transistors each have a third gate-to-gate space, the third gate-to-gate space being smaller than the first gate-to-gate space and the second gate-to-gate space.

[0089] Clause 18. The apparatus of any one of clauses 1 to 17, wherein the apparatus is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and an in-vehicle device.

[0090] Clause 19. A method for manufacturing a semiconductor device, comprising: forming one or more static random access memory (SRAM) transistors, each including a first gate spacer structure; forming one or more logic nominal transistors, each including a second gate spacer structure; and forming one or more logic gate bias transistors, each including a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, and the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP).

[0091] Clause 20. The method of clause 19, wherein the second gate spacer structure has the same thickness as the first gate spacer structure.

[0092] Clause 21. The method of clause 19, wherein the second gate spacer structure has the same thickness as the third gate spacer structure.

[0093] Clause 22. The method of any one of clauses 19 to 21, wherein the second gate spacer structure has at least one different material relative to the first gate spacer structure.

[0094] Clause 23. The method of any one of clauses 19 to 22, wherein the second gate spacer structure has a different number of spacer layers than the first gate spacer structure.

[0095] Clause 24. The method of clause 19, wherein the first gate spacer structure has a first thickness, the second gate spacer structure has a second thickness, and the third gate spacer structure has a third thickness, the first thickness and the second thickness being greater than the third thickness.

[0096] Clause 25. The method of any one of clauses 19 to 24, wherein the first gate spacer structure has a first thickness and the third gate spacer structure has a third thickness, the first thickness being between 20 percent and 30 percent greater than the third thickness.

[0097] Clause 26. The method of any one of clauses 19 to 25, wherein the first gate spacer structure comprises the same material as the second gate spacer structure and the third gate spacer structure.

[0098] Clause 27. The method of any one of clauses 19 to 26, wherein the outer spacer layer of the third gate spacer structure is thinner than the outer spacer layer of the first gate spacer structure.

[0099] Clause 28. The method of any one of clauses 19 to 27, wherein the first gate spacer structure includes at least one additional spacer layer than the third gate spacer structure.

[0100] Clause 29. The method of clause 19, wherein the second gate spacer structure includes at least one additional spacer layer than the third gate spacer structure.

[0101] Clause 30. The method of any one of clauses 19 to 29, wherein the first gate spacer structure, the second gate spacer structure, and the third gate spacer structure comprise at least one of silicon nitride, silicon dioxide, silicon boride, silicon carbide, oxynitride, or combinations thereof.

[0102] Clause 31. The method of any one of clauses 19 to 30, wherein the one or more SRAM transistors each have a first gate length, the one or more logic nominal transistors each have a second gate length, and the one or more logic gate bias transistors each have a third gate length, the third gate length being greater than the first gate length and the second gate length.

[0103] Clause 32. The method of clause 31, wherein the third gate length is less than 3 nanometers longer than the first gate length.

[0104] Clause 33. A method according to any one of clauses 19 to 32, wherein one or more SRAM transistors each have a first gate-to-gate space, one or more logic nominal transistors each have a second gate-to-gate space, and one or more logic gate bias transistors each have a third gate-to-gate space, the third gate-to-gate space being smaller than the first gate-to-gate space and the second gate-to-gate space.

[0105] Clause 34. The method of any one of clauses 19 to 33, further comprising incorporating the semiconductor device into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and an in-vehicle device.

[0106] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing the respective actions and / or functionality of the disclosed methods.

[0107] Furthermore, in some examples, an individual action may be subdivided into or include multiple sub-actions, and such sub-actions may be included in and part of the disclosure of the individual action.

[0108] Although the above disclosure illustrates exemplary embodiments of the present disclosure, it should be noted that various changes and modifications can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or actions of the method claims according to the embodiments of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and embodiments disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. An apparatus comprising a semiconductor device, the semiconductor device comprising: one or more static random access memory (SRAM) transistors, each including a first gate spacer structure; one or more logic nominal transistors each including a second gate spacer structure; and one or more logic gate bias transistors each including a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP), the first gate spacer structure includes at least one additional spacer layer than the third gate spacer structure, and the second gate spacer structure includes at least one additional spacer layer than the third gate spacer structure.

2. The device of claim 1 , wherein the second gate spacer structure has the same thickness as the first gate spacer structure.

3. The device of claim 1 , wherein the second gate spacer structure has at least one different material relative to the first gate spacer structure.

4. The device of claim 1 , wherein the second gate spacer structure has a different number of spacer layers than the first gate spacer structure.

5. 2. The device of claim 1, wherein the first gate spacer structure has a first thickness, the second gate spacer structure has a second thickness, and the third gate spacer structure has a third thickness, the first thickness and the second thickness being greater than the third thickness.

6. 2. The device of claim 1, wherein the first gate spacer structure has a first thickness and the third gate spacer structure has a third thickness, the first thickness being between 20 and 30 percent greater than the third thickness.

7. 2. The device of claim 1, wherein the first gate spacer structure comprises the same material as the second gate spacer structure and the third gate spacer structure.

8. 2. The device of claim 1, wherein an outer spacer layer of the third gate spacer structure is thinner than an outer spacer layer of the first gate spacer structure.

9. 10. The device of claim 1, wherein the first gate spacer structure, the second gate spacer structure, and the third gate spacer structure comprise at least one of silicon nitride, silicon dioxide, silicon boride, silicon carbide, silicon oxynitride, or combinations thereof.

10. 2. The apparatus of claim 1, wherein the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors are three-dimensional transistors (3D transistors).

11. 11. The device of claim 10, wherein the 3D transistor is at least one of a FinFET, a nanosheet, a nanowire, or a vertical FET.

12. 2. The device of claim 1, wherein the one or more SRAM transistors each have a first gate length, the one or more logic nominal transistors each have a second gate length, and the one or more logic gate bias transistors each have a third gate length, the third gate length being longer than the first gate length and the second gate length, and the third gate length being less than 3 nanometers greater than the first gate length.

13. 2. The device of claim 1, wherein the one or more SRAM transistors each have a first gate-to-gate space, the one or more logic nominal transistors each have a second gate-to-gate space, and the one or more logic gate bias transistors each have a third gate-to-gate space, the third gate-to-gate space being smaller than the first gate-to-gate space and the second gate-to-gate space.

14. 10. The device of claim 1, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, an access point, a base station, and an in-vehicle device.

15. 1. A method for manufacturing a semiconductor device, comprising: forming one or more static random access memory (SRAM) transistors, each including a first gate spacer structure; forming one or more logic nominal transistors each including a second gate spacer structure; forming one or more logic gate bias transistors each comprising a third gate spacer structure, wherein the third gate spacer structure is thinner than the first gate spacer structure, the one or more SRAM transistors, the one or more logic nominal transistors, and the one or more logic gate bias transistors each have the same contact poly pitch (CPP), the first gate spacer structure comprises at least one additional spacer layer than the third gate spacer structure, and the second gate spacer structure comprises at least one additional spacer layer than the third gate spacer structure.

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