In situ lithography pattern enhancement by localized stress treatment tuning using heat zones

Abstract

Aspects of the present disclosure provide a wafer processing apparatus for optimizing wafer shape. For example, the wafer processing apparatus can include a first hot plate, a second hot plate, and a controller. The first hot plate can be configured to heat the wafer. For example, the first hot plate can provide uniform heating across a surface of the first hot plate. The second hot plate includes multiple heating zones, each of which is individually controllable such that each heating zone can be set to a temperature value independent of the other heating zones. The controller is configured to control the first hot plate to provide uniform heating, receive a bow measurement value from the wafer deflection measurement value of the wafer, and set the multiple heating zones of the second hot plate to their respective temperature values ​​corresponding to the bow measurement value.

Description

[Technical field]

[0001] Incorporation by Reference This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 337,708, filed May 3, 2022, and U.S. Patent Application No. 18 / 171,989, filed February 21, 2023, which are incorporated by reference in their entireties.

[0002] The present disclosure relates to semiconductor manufacturing, and more specifically, to wafer bow, warpage, and overall wafer shape. [Background technology]

[0003] The background description provided herein is intended to generally present the background of the present disclosure. The inventors' work and described aspects of the present disclosure that would not otherwise be admitted as prior art at the time of filing to the extent described in this Background section are not expressly or implicitly admitted as prior art to the present disclosure.

[0004] Semiconductor manufacturing involves several different steps and processes. One typical manufacturing process is known as photolithography (also called microlithography). Photolithography uses radiation, such as ultraviolet or visible light, to create fine patterns in semiconductor device designs. Various semiconductor devices, such as diodes, transistors, and integrated circuits, can be constructed using semiconductor manufacturing techniques, including photolithography, etching, deposition, surface cleaning, metallization, and the like.

[0005] To implement photolithography techniques, an exposure system (also called an exposure tool) is used. An exposure system typically includes an illumination system, a reticle (also called a photomask) or a spatial light modulator (SLM) that creates the circuit pattern, a projection system, and a wafer alignment stage that aligns a semiconductor wafer covered with a photosensitive resist. The illumination system illuminates an area of ​​the reticle or SLM with a (preferably) rectangular slot illumination field. The projection system projects an image of the illuminated area of ​​the reticle pattern onto the wafer. For accurate projection, it is important to expose the light pattern to a relatively flat or planar wafer, preferably with a height deviation of less than 10 micrometers. Summary of the Invention [Means for solving the problem]

[0006] Aspects of the present disclosure provide a wafer processing apparatus for optimizing wafer shape. For example, the wafer processing apparatus can include a first hot plate, a second hot plate, and a controller. The first hot plate can be configured to heat the wafer. For example, the first hot plate can provide uniform heating across a surface of the first hot plate. The second hot plate has multiple heating zones, each of which is individually controllable such that each heating zone can be set to a temperature value independent of the other heating zones. The controller can be configured to control the first hot plate to provide uniform heating, receive a bow measurement from a wafer deflection measurement of the wafer, and set the multiple heating zones of the second hot plate to their respective temperature values ​​corresponding to the bow measurement.

[0007] In some embodiments, the second hot plate can be positioned adjacent to the first hot plate such that the first and second hot plates are in contact with each other. For example, the wafer processing apparatus further includes a wafer support for a wafer to be placed thereon, and the controller is further configured to control the wafer support to be closer to the second hot plate than the first hot plate. As another example, the wafer processing apparatus further includes a wafer support for a wafer to be placed thereon, and the controller is further configured to control the wafer support to be closer to the first hot plate than the second hot plate. In other embodiments, the second hot plate can be positioned opposite the first hot plate such that the wafer is positioned between the first and second hot plates.

[0008] In some embodiments, the second hot plate can include multiple channels corresponding to the multiple heating zones and a heat exchange fluid flowing through the channels and controlled by a controller based on the wafer bow measurements. In some embodiments, the controller can control the heat exchange fluid to cause a phase transition from a fluid state to a gas state. For example, the controller can control the temperature of the heat exchange fluid by varying its pressure.

[0009] Aspects of the present disclosure also provide a wafer processing system for optimizing wafer shape. For example, the wafer processing system can include a metrology module, a film formation module, and a bake module. The metrology module can be configured to measure the wafer to determine a bow measurement of the wafer. The film formation module can be configured to form a stress control film on the wafer. The stress control film is responsive to heat, which alters the internal stress of the stress control film. The bake module has multiple heating zones for differentially heating the stress control film corresponding to the bow measurement. The wafer can have a processing surface and a back surface opposite the processing surface, and the stress control film can be formed on the back surface of the wafer.

[0010] In one embodiment, the film formation module can be configured to form a stress control film by a spin-on deposition process. In another embodiment, the bake module can include a first hotplate configured to generate uniform heating across its surface and a second hotplate including multiple heating zones.

[0011] Aspects of the present disclosure also provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a processing surface and a back surface opposite the processing surface, measuring the wafer to determine a bow measurement of the wafer, and forming a stress control film on the back surface of the wafer. The stress control film can be responsive to heat such that the heat modifies an internal stress of the stress control film. The method can further include modifying the internal stress of the stress control film using a pattern of heat applied via a hot plate having multiple heating zones. The pattern of heat corresponds to the bow measurement of the wafer.

[0012] In some embodiments, the work surface of the wafer may have at least partially fabricated devices thereon, while in other embodiments, the wafer may have an amount of wafer bow resulting from one or more microfabrication steps.

[0013] It should be noted that this Summary section does not specify every embodiment and / or inherently novel aspect of the present disclosure or claimed invention. Rather, this Summary merely provides a preliminary discussion of various embodiments and corresponding aspects that are novel over the prior art. For additional details and / or anticipated aspects of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.

[0014] Various embodiments of the present disclosure, proposed by way of example, will now be described in detail with reference to the drawings, in which like numerals refer to like elements and in which: [Brief description of the drawings]

[0015] [Figure 1] 1 is a flowchart illustrating an exemplary method for correcting or correcting wafer bow, according to some embodiments of the present disclosure. [Figure 2A] 2 illustrates hardware used in the exemplary method shown in FIG. 1 . [Figure 2B] 2 illustrates hardware used in the exemplary method shown in FIG. 1 . [Figure 2C] 2 illustrates hardware used in the exemplary method shown in FIG. 1 . [Diagram 3] FIG. 1 illustrates a top view of an exemplary wafer processing system for correcting or correcting wafer bow, according to some embodiments of the present disclosure. [Figure 4A] FIG. 4 is a side view of an exemplary bake module of the wafer processing system shown in FIG. 3 according to some embodiments of the present disclosure. [Figure 4B] FIG. 4 is a side view of an exemplary bake module of the wafer processing system shown in FIG. 3 according to some embodiments of the present disclosure. [Figure 5A] 4C is a schematic diagram of three exemplary first hot plates of the bake module shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 5B] 4C is a schematic diagram of three exemplary first hot plates of the bake module shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 5C] 4C is a schematic diagram of three exemplary first hot plates of the bake module shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6A] 4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6B] 4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6C]4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6D] 4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6E] 4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. [Figure 6F] 4C is a schematic diagram of six exemplary second hot plates of the bake system shown in FIGS. 4A and 4B, according to some embodiments of the present disclosure. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The following disclosure provides various embodiments or examples for implementing various features of the presented subject matter. To simplify the disclosure, specific examples of components and configurations are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, a configuration of a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed in direct contact with each other, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact with each other. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself dictate a relationship between the various embodiments and / or configurations being discussed. Furthermore, spatially relative terms such as "top", "bottom", "lower", "lower", "lower", "lower side", "upper", "upper" and the like may be used herein to facilitate describing the relationship of one element or feature shown in the drawings to another element or feature. These spatially relative terms are intended to encompass orientations of the device during use or operation that are different from the orientation depicted in the drawings: the device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0017] The order of description of the different steps described herein is presented for clarity. In general, these steps can be performed in any suitable order. In addition, although each of the various features, techniques, configurations, etc. herein may be described in separate parts of this disclosure, it is understood that each concept can be performed independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0018] Semiconductor manufacturing includes a number of different steps and processes. One typical manufacturing process is known as baking. Typically, before any semiconductor manufacturing process, there is a bake process to set the substrate or wafer and process the stack to a target temperature. This temperature is generally as uniform as possible, since many processes during processing are affected by the temperature of the wafer. For example, in a spin-on deposition process, the wafer is placed in a bake module and cooled to stabilize the temperature of the wafer at 32° C., and further processing is performed after the temperature of the wafer is stabilized. After the spin-on deposition process is performed, the wafer with the film or photoresist deposited thereon is baked again on another hotplate stabilized at 90° C. to stabilize the deposited film or crosslink the exposed photoresist. The hotplate can be characterized as a low temperature hotplate (<50° C.), a hotplate (<400° C.), or an ultra-high temperature hotplate (<900° C.).

[0019] The microfabrication of semiconductor structures starts with a flat substrate or wafer. During the microfabrication of semiconductor structures, multiple processing steps are performed that may include deposition of materials on the wafer, removal of materials, implantation of dopants, annealing, and baking. The different materials and structural configurations thus formed may cause internal stresses in the wafer, resulting in bowing of the semiconductor structures, which in turn affects the overlay, typically resulting in overlay errors of various degrees. Simple bow correction or correction (e.g., primary correction) can be achieved by depositing a stress control film on the backside of the wafer. This approach may be useful to correct or correct a cone-shaped wafer. This typically requires transferring the wafer to a deposition tool before further processing can take place.

[0020] The technology disclosed herein defines a process flow and wafer processing apparatus and system for achieving optimal wafer shape (using localized stress engineering of the semiconductor wafer lattice) prior to the photo process used on the work surface of the wafer. The process flow disclosed herein includes, as one option, a disposable lattice alignment film on either the backside or work surface of the wafer. Another option is to leave the lattice alignment film in place for subsequent processing steps.

[0021] The technology disclosed in this application includes a hot plate with multiple heating zones used to generate a target thermal signature. The process flow can be adjusted / modified using the target thermal signature. The process flow uses a hot plate used as an independent processing step. Such stress modification of the wafer by a hot plate with multiple heating zones can be used with spin-on stress control films. The stress control material can be deposited by spin-on deposition and then a heater array is used to crosslink the stress material or stress signature to the stress control film using a coater developer without any lithographic exposure or etching. Thus, the wafer topography modification can be achieved by spin coating, followed by baking and then developing. It can be seen that without photolithographic correction, some correction signatures have a low resolution of stress modification, but this low resolution is sufficient for primary and secondary correction.

[0022] Additionally, the process flow can be repeated in the same or subsequent processing steps to preserve optimal wafer shape at all processing locations requiring lithography.One feature of the present application is that no mask is required for this in-situ pattern enhancement technique.

[0023] By modifying the initial internal stress from the deposition as-deposited using a stress-tuning film on the backside or working surface of the wafer that can be heated in different zones (either by the wafer chuck or laser as some examples). This is possible because available wafer chucks can be modified to have over 50 precise temperature locations on the backside of the wafer. One unique aspect is that the stress-controlling film deposited on the backside of the wafer can be either compressive, neutral or tensile in the deposition as-deposited state and then modified in various precise temperature regions to generate localized stresses (compressive, tensile, neutral) to reduce wafer bow and improve lithography accuracy (so that optimal wafer shape is achieved).

[0024] FIG. 1 is a flow chart of an exemplary method 100 for correcting or correcting wafer bow, according to some embodiments of the present disclosure. FIGS. 2A-2C show hardware, such as a metrology module and a bake module, used in the exemplary method 100. The method 100 can correct or correct primary, secondary, or higher order or complex bow of a wafer. The method 100 begins at step S110, where a wafer 210 (shown in FIG. 2A) is received having a backside 230 and a work surface (not shown) opposite the backside 230. The work surface may have at least partially fabricated devices, and the wafer 210 may have an amount of wafer bow as a result of the micro-fabrication process.

[0025] In step S120, the wafer 210 is measured to determine a bow measurement of the wafer 210. For example, the metrology module 220 (shown in FIG. 2A) is used to determine a bow measurement of the wafer 210, such as a relative z-height deviation.

[0026] In step S130, a stress control film 240 (or stress modified film) (shown in FIG. 2B) is formed on the backside 230 of the wafer 210. For example, the wafer 210 can be flipped over so that the backside 230 faces upward, and the stress control film 240 can be formed on the backside 230 by a film forming module (or coater) 250 during a spin-on deposition process, in which a quantity of stress control material 240 is deposited on the backside 230 of the wafer 210 while rotating the wafer 210, thus evaporating the solvent in the stress control material 240 to form the stress control film 240. The stress control film 240 is sensitive to heat, and the internal stress of the stress control film 240 is modified by the applied heat. Various materials can be selected for use in the stress control film 240, such as carbon nanotubes and boron nitride.

[0027] In step S140, the internal stress of the stress control film 240 is corrected or modified using a heat pattern corresponding to the bow measurement. For example, the stress control film 240 can be moved to a bake module 260 (shown in FIG. 2C), which includes a first hot plate with one or more channels for performing a uniform bake process and a second hot plate with multiple heating zones for performing a differential thermal signature bake process corresponding to the bow measurement of the wafer 210. The multiple heating zones can be controlled individually. Depending on the material selected, the differential thermal signature bake process can increase or decrease the internal compressive or tensile stress at a point location of the wafer 210, thereby changing the overall shape of the wafer 210. Steps S120-S140 can be repeated until the average z-direction height deviation value of the wafer 210 is below a threshold value, e.g., 10 micrometers, and is considered near flat or flat for overlay improvement purposes in this application. The wafer 210 can then be flipped over to continue processing on the work surface. The stress control film, whose intrinsic stress has been modified, can be removed or left in place during subsequent processing.

[0028] 3 is a plan view of an exemplary wafer processing system 300, e.g., a track lithography tool, for correcting or correcting wafer bow, according to some embodiments of the present disclosure. The wafer processing system 300 includes various wafer handling components or carriers along with several stages, e.g., a carrier stage 310 and a processing stage 320. The carrier stage 310 includes one or more pod assemblies 311, which are configured to receive one or more wafer cassettes 312 configured to accommodate one or more wafers 290, e.g., the wafer 210 shown in FIG. 2A, to be processed in the wafer processing system 300. A door 313 can be opened to access the wafers 290 stored in the wafer cassettes 312. A carrier transfer robot 314 can move up and down to transfer the wafers 290 from the wafer cassettes 312 to a shelf unit 321 mounted for temporary storage of the wafers 290 in the processing stage 320.

[0029] The processing stage 320 may include various processing modules, such as processing modules 323-328 and a processing transport robot 322. The processing transport robot 322 is configured to access the shelf unit 321 and the processing modules 323-328 and move the wafer 290 among the processing modules 323-328 for various processing. In an embodiment, the processing transport robot 322 may flip and rotate the wafer 290. The modules 323-328 may include one or more metrology modules 323, such as the metrology module 220 shown in FIG. 2A, configured to measure the amount of wafer bow of the wafer 290 and provide the bow measurement value to the wafer processing system 300. The bow measurement may include measuring the degree of protrusion or recession or mapping the z-height deviation value on the wafer 290 relative to one or more reference z-height deviation values. In other words, the z-height deviation values ​​are spatially mapped, such as at coordinate positions, to identify the z-height deviation value across the surface of the wafer 290. The z-height deviations can be mapped at a variety of resolutions depending on the type of metrology instrument used and / or the desired resolution.

[0030] The warpage measurements may include raw warpage data or may be expressed as a warpage signature in terms of relative z-height deviations. Note that in many embodiments, the reference z-height deviations may represent wafers that are all close to zero and therefore close to flat. For example, a wafer that is close to flat or considered flat for overlay improvement purposes herein may be a wafer whose average z-height deviation is less than 10 micrometers. In some embodiments, the reference z-height deviations may represent a non-flat shape, whose shape is nevertheless beneficial for overlay error correction, particularly for a particular stage of micro-machining. The techniques of the present application allow correction of warpage greater than 10 micrometers. The metrology module 323 is configured to measure a wafer 290 having a processing surface and a back surface opposite the processing surface. The wafer 290 may have an initial wafer warpage value resulting from one or more micro-machining processing steps performed to fabricate at least a portion of a semiconductor device on the processing surface of the wafer 290. For example, field effect transistors (FETs) may be completed or only partially completed on the work surface of wafer 290.

[0031] The processing modules 323-328 may also include one or more film formation modules 324, such as the film formation module 250 shown in FIG. 2B, configured to form one or more films on the front surface of the wafer 290 being processed. The film formation module 324 may be configured to deposit a stress-control film, such as the stress-control film 240 shown in FIG. 2B, on the back surface of the wafer 290 using a gas phase chemical vapor deposition, atomic layer deposition, spin-on deposition process, or other deposition method. For example, in spin-on deposition, a quantity of stress-control material is deposited on the back surface of the wafer 290 while the wafer 290 is rotating, thereby evaporating a solvent in the stress-control material and changing the properties of the deposited stress-control material to promote adhesion of the stress-control material to the back surface of the wafer 290. The film formation module 324 and the metrology module 323 may be mounted on a common platform, which may include an automated wafer handling system that automatically moves the wafer 290 from the metrology module 323 to the film formation module 324.

[0032] The processing modules 323-328 can also include one or more bake modules 325, such as the bake module 260 shown in FIG. 2C, configured to bake the wafer 290 to a target temperature. For example, the bake module 325 can bake and stabilize the wafer 290 at 32° C. or 90° C. As another example, the bake module 325 can bake the wafer 290 having a stress control film formed thereon with a heat pattern corresponding to a bow measurement of the wafer 290 to correct or modify the internal stress of the stress control film.

[0033] The wafer processing system 300 further includes a controller 380. The controller 380 can be a computer processor located within the wafer processing system 300 or located remotely but in communication with the components of the wafer processing system 300, such as the metrology module 323, the film formation module 324, and the bake module 325. In an embodiment, the controller 380 is configured to control the metrology module 323 to measure the wafer 290 to determine a bow measurement of the wafer 290, receive the measurement from the metrology module 323, control the film formation module 324 to form a stress control film on the backside of the wafer 290, and control the bake module 325 to differentially bake the wafer 290 having the stress control film formed thereon with a pattern of heat corresponding to the bow measurement to correct or modify the internal stress of the stress control film. The film formation module 324, the bake module 325, and the controller 380 are referred to as a wafer processing device. The wafer processing system 300 can also include other stages or components, such as a stepper / scanner 330. The stepper / scanner 330 can be decoupled from the processing stage 320 because the throughput of the stepper / scanner 330 is often many times greater than the throughput of the carrier stage 310 and processing stage 320, and therefore dedicating the stepper / scanner 330 to one processing stage would waste the excess throughput capacity of the stepper / scanner.

[0034] 4A and 4B are side views of an exemplary bake module (or wafer processing device) 400, such as bake module 325, according to some embodiments of the present disclosure. The bake module 400 is configured to bake a wafer, such as wafer 290, having a layer and / or film, such as a stress control film, formed on its processing surface and / or backside. The bake module 400 includes a first hot plate (or global hot plate) 410, a second hot plate (or localized hot plate) 420, and a wafer support (or holder) 450 for a wafer to be placed thereon and baked. The second hot plate 420 includes a number of heating zones 421-427. The first hot plate 410 and the second hot plate 420 can be made of aluminum, graphite, aluminum nitride, or other heat-conducting materials. The first hot plate 410, the second hot plate 420, and the wafer support 450 are housed within a housing 440. The housing 440 is configured to isolate the process taking place in the bake module 400 from the surrounding environment. For example, the housing 440 can insulate the bake module 400 to minimize contamination from the surrounding environment. In one embodiment, the housing 440 can include a lower portion 440A to which the first hot plate 410 can be attached and an upper portion (e.g., a lid) 440B to which the second hot plate 420 can be attached. The upper portion 440B can move vertically to open and close the bake module 400. For example, when a wafer is baked in the bake module 400, the upper portion 440B can move vertically downward toward the lower portion 440A until the housing 440 is closed and the second hot plate 420 is secured if it is integrated with the upper portion 440B.

[0035] A lift assembly 430, including, for example, three lift pins, is configured to raise and lower the wafer support 450. For example, the lift assembly 430 can lower the wafer support 450 so that a wafer 290 disposed thereon is closer to the first hot plate 410 during a global heating process, as shown in FIG 4A. In another example, the lift assembly 430 can raise the wafer support 450, for example, to various heights so that a wafer 290 disposed thereon is closer to the second hot plate 420 during a local heating process, as shown in FIG 4B.

[0036] In this exemplary embodiment, the wafer support 450 is positioned such that the wafer 290 can be positioned between the first hot plate 410 and the second hot plate 420. In other embodiments, the second hot plate 420 can be positioned above the first hot plate 410 and the wafer 290 can be positioned above the second hot plate 420. In yet other embodiments, the first hot plate 410 can be positioned above the second hot plate 420 and the wafer 290 can be positioned above the first hot plate 410. In some other embodiments, two sets of the first hot plate 410 and the second hot plate 420 can be positioned above and below the wafer 290, respectively.

[0037] The wafer 290 may rest on pins or protrusions (not shown) embedded in the surface of the first hot plate 410 or the second hot plate 420 such that only a small gap remains between the wafer 290 and the first hot plate 410 or the second hot plate 420, reducing particle generation. While reducing the number of particles generated, the pins also tend to reduce thermal coupling between the wafer 290 and the first hot plate 410 or the second hot plate 420. Thus, it is often desirable to reduce the height of the pins, i.e., the gap, from the surface of the first hot plate 410 or the second hot plate 420 to improve thermal coupling while ensuring that the wafer 290 does not come into contact with the surface of the first hot plate 410 or the second hot plate 420.

[0038] In one embodiment, the bake module 400 can further include a shuttering ring 460. The shuttering ring 460 can be controlled to move vertically to allow the wafer to move into the bake module 400 and seal the bake module 400 from the outside environment. For example, the shuttering ring 460 and the lift assembly 430 can be controlled to move vertically up and down simultaneously by a common lift cylinder (not shown).

[0039] 5A-5C are schematic diagrams of three exemplary first hot plates 500A, 500B, and 500C, such as the first hot plate 410, according to some embodiments of the present disclosure. Each of the first hot plates 500A-500C is configured to heat the wafer 290 globally and generate uniform heating across the surface of the first hot plate 500A-500C. The first hot plate 500A has one circular channel 510A, the first hot plate 500B has two concentric circular channels 510B and 520B, and the first hot plate 500C has three concentric circular channels 510C, 520C, and 530C. Each of the first hot plates 500A-500C can have any number and shape of channels. A heat exchange fluid (not shown) flows continuously through the channels. A fluid temperature controller, such as controller 380, can be configured to control the temperature of the heat exchange fluid and thus the temperature of the first hot plates 500A-500C. The heat exchange fluid can be, for example, a perfluoropolyether, which can be controlled to a temperature of about 30° C. to about 250° C. The heat exchange fluid can also be a temperature controlled gas, such as argon or nitrogen.

[0040] 6A-6F are schematic diagrams of six exemplary second hot plates 600A, 600B, 600C, 600D, 600E, and 600F, e.g., second hot plate 420, according to some embodiments of the present disclosure. Second hot plates 600A-600F include multiple heating zones, each individually controllable by a controller, e.g., controller 380, configured to locally heat wafer 290, where each heating zone can be set to a temperature value independent of the other heating zones. In some embodiments, controller, e.g., controller 380, can also individually control the rate of temperature change of each heating zone. For example, controller 380 can receive bow measurements of wafer 290 determined by metrology module 323 and individually control the heating zones of each of second hot plates 600A-600F, such that each of second hot plates 600A-600F has a spatial thermal signature corresponding to the bow measurements. The multiple heating zones can be arranged in one or two dimensions in one or more rectangular or other shaped strips. For example, second hotplate 600A includes rectangular heating zone 610A sandwiching heating zone 620A. As another example, second hotplate 600F includes multiple heating zones arranged in a row and divided into five heating groups 610F, 620F, 630F, 640F, and 650F, each containing one or more heating zones.

[0041] In an embodiment, each of the second hot plates 600A-600F includes multiple channels corresponding to their multiple heating zones. A heat exchange fluid (not shown) again flows continuously through the channels and can be controlled by the controller 380. Thus, the spatial thermal signature of the second hot plates 600A-600F can be controlled by the controller 380 based on the bow measurements of the wafer 290 determined by the metrology module 323. The heat exchange fluid can be a liquid such as water or a gas such as an inert gas, air, nitrogen, carbon dioxide, etc., and can enter each channel from its inlet using the ejector 660 after reaching a predetermined temperature. After flowing through the interior of, for example, the second hot plate 600E, the fluid is ejected from the outlet of the channel by the ejector 660. In an embodiment, a liquid such as water can be heated to its boiling point to cause a phase transition from a liquid state to a gaseous state. The phase transition between water and water can be due to the effect of temperature and / or pressure. In an embodiment, a predetermined temperature of the heat exchange fluid in a gaseous state can be achieved by applying a predetermined pressure.

[0042] The temperature and / or rate of temperature change within each of the respective heating zones of the first and second heating plates may be individually controlled by varying the fluid temperature, fluid flow rate, fluid pressure, and / or other known temperature control methods. Additionally, although the first and second heating plates are referred to by the term "heating," it should be understood that various "cooling" techniques may also be used to achieve individual temperature control of the heating zones according to embodiments of the present application. In some embodiments, thermoelectric heating and cooling, radiant heating, and other temperature control techniques may be used to facilitate individual control of the zones of the first and second heating plates.

[0043] In the above description, specific details are given, such as the specific geometry of the processing system and a description of the various components and processes used. However, it should be understood that the technology described herein can be practiced in other embodiments that differ from these specific details, and such details are for the purpose of explanation, not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numerical values, materials, and configurations are given to provide a sufficient understanding. However, the embodiments can be practiced without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and redundant descriptions may be omitted.

[0044] It should be understood that the order of description of the various steps described herein is presented for clarity of description. In general, the steps can be performed in any suitable order. In addition, although each of the various features, techniques, configurations, etc. described herein may be described in separate parts of this disclosure, it is understood that each concept can be performed independently of each other or in combination with each other. Thus, the present invention can be embodied and viewed in many different ways.

[0045] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0046] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may include, for example, a base substrate structure, such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, lower layer, or upper layer, whether patterned or not, but is intended to include such layers or base structures, and any combination of layers and / or base structures. Although the present specification may refer to a particular type of substrate, it is for illustrative purposes only.

[0047] Those skilled in the art will also appreciate that many variations are possible in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Thus, the above description of the embodiments of the present invention is not intended to be limiting. Rather, any limitations to the embodiments of the present invention are set forth in the following claims.

Claims

1. In wafer processing equipment, a first hotplate configured to heat a wafer, the first hotplate producing uniform heating across a surface of the first hotplate; a second hotplate configured to heat the wafer, the second hotplate having a plurality of heating zones, each of the heating zones being individually controllable and capable of being set to a temperature value independent of the other heating zones; a controller configured to control the first hotplate to generate the uniform heating, receive a warpage measurement value from a wafer deflection measurement of the wafer, and set the plurality of heating zones of the second hotplate to their respective temperature values ​​corresponding to the warpage measurement value; A wafer processing device comprising:

2. 2. The wafer processing apparatus of claim 1, wherein the second hot plate is positioned adjacent to the first hot plate such that the first hot plate and the second hot plate are in contact with each other.

3. 3. The wafer processing apparatus of claim 2, further comprising a wafer support for a wafer to be placed thereon, wherein the controller is further configured to control the wafer support to be closer to the second hot plate than to the first hot plate.

4. 3. The wafer processing apparatus of claim 2, further comprising a wafer support for a wafer to be placed thereon, wherein the controller is further configured to control the wafer support to be closer to the first hot plate than to the second hot plate.

5. 2. The wafer processing apparatus of claim 1, wherein the second hot plate is positioned opposite the first hot plate, and the wafer is positioned between the first hot plate and the second hot plate.

6. The second hot plate is a plurality of channels corresponding to the plurality of heating zones; a heat exchange fluid flowing through the channel, the temperature of which is controlled by the controller based on the bow measurement of the wafer; The wafer processing device according to claim 1 , comprising:

7. The wafer processing apparatus of claim 6 , wherein the controller controls the heat exchange fluid to cause a phase transition from a liquid state to a gas state.

8. The wafer processing apparatus of claim 6 , wherein the controller controls the temperature of the heat exchange fluid by varying its pressure.

9. A wafer processing apparatus as described in Claim 6, wherein the heating zones of the second hot plate are provided in the vertical projection area of ​​the wafer and are fixed to each other.

10. In a wafer processing system, a metrology module configured to measure a wafer to determine a bow measurement of the wafer; a film formation module configured to form a stress control film on the wafer, the stress control film being responsive to heat, the heat modifying an internal stress of the stress control film; a bake module having a plurality of heating zones for differentially heating the stress control film in response to the warpage measurements; A wafer processing system, wherein the heating zones of the bake module are provided in vertical projection areas of the wafer and are fixed to each other.

11. The wafer processing system of claim 10 , wherein the film formation module is configured to form the stress control film by a spin-on deposition process.

12. The bake module includes: a first hotplate configured to provide uniform heating across a surface of the first hotplate; a second hot plate including multiple heating zones; The wafer processing system of claim 10 , comprising:

13. The second hot plate is a plurality of channels corresponding to the plurality of heating zones; a heat exchange fluid flowing through the channel, the temperature of which is controlled based on the bow measurement of the wafer; The wafer processing system of claim 12 , comprising:

14. The wafer processing system of claim 13 , wherein the heat exchange fluid undergoes a phase transition from a liquid state to a gas state.

15. 15. The wafer processing system of claim 14, wherein the temperature of the heat exchange fluid is controlled by varying its pressure.

16. The wafer processing system according to claim 10 , wherein the wafer has a processing surface and a back surface opposite to the processing surface, and the stress control film is formed on the back surface of the wafer.

17. 1. A method comprising: receiving a wafer having a processing surface and a back surface opposite the processing surface; measuring the wafer to determine a bow measurement for the wafer; forming a stress control film on the backside of the wafer, the stress control film being responsive to heat, the heat changing the internal stress of the stress control film; modifying the internal stress of the stress control film using a pattern of heat applied via a hotplate having multiple heating zones, the pattern of heat corresponding to the warpage measurement of the wafer; The method, wherein the heating zones of the bake module are provided at vertical projection areas of the wafer and are fixed to each other.

18. 20. The method of claim 17, wherein the work surface of the wafer has at least partially fabricated devices.

19. 20. The method of claim 17, wherein the wafer has an amount of wafer bow resulting from one or more micro-machining steps.

20. the hot plate includes a plurality of channels corresponding to the plurality of heating zones; 20. The method of claim 17, further comprising injecting a heat exchange fluid to flow within the channels, wherein a temperature of the heat exchange fluid is controlled based on the bow measurement of the wafer.

21. 21. The method of claim 20, wherein the heat exchange fluid undergoes a phase transition from a fluid state to a gaseous state.

22. A wafer processing system as described in claim 12, wherein the bake module includes a housing having a lower portion on which a first hot plate is installed and an upper portion on which a second hot plate is installed, the upper portion being configured to move vertically to open and close the bake module.

Images