Carrier ring with tabs

Abstract

A carrier ring with tabs for use with semiconductor processing equipment is provided. The carrier ring may include a ring having an outer portion and an inner portion and defining a plane. The carrier ring may include tabs around an inner circumference of the inner portion. The ring and tabs may have physical characteristics configured to enable more backside deposition of a semiconductor substrate at locations of the semiconductor substrate corresponding to the tabs compared to a ring without the physical characteristics. Such characteristics of the ring and tabs may include an inner diameter of the ring, an inner diameter of the tabs, a quantity of tabs, a width of the tabs, and an angle of the tabs relative to the plane. These characteristics may reduce substrate contact area and increase deposition area near the substrate edge, which may increase film thickness uniformity.

Description

[Technical field]

[0001] [Incorporated by reference] A PCT application form is being filed contemporaneously herewith as part of this application. Each application to which this application claims benefit or priority, as identified in the contemporaneously filed PCT application form, is hereby incorporated by reference in its entirety and for all purposes. [Background technology]

[0002] Semiconductor device fabrication often involves the deposition of a stack of layers on a wafer substrate. Deposition and other processing to form devices is often performed on one side of the substrate, which is often referred to as the front side of the substrate. As deposition layers build up, they can introduce stresses into the substrate. Large net compressive or tensile stresses can cause the substrate to warp, where deviations from the plane of the substrate (e.g., the average mid-plane of the semiconductor substrate) occur, which is undesirable. Such substrates can be extremely sensitive to such deviations. Depositing a film on the backside of the substrate can offset the warping and increase the deposition area on the same substrate.

[0003] The background and context discussion contained herein is provided solely for the purpose of generally presenting the context of the present disclosure. Most of this disclosure presents the work of the inventors, and merely because such work is described in the Background section or presented as context elsewhere in this disclosure does not mean that such work is admitted to be prior art. Summary of the Invention

[0004] In one aspect of the present disclosure, a carrier ring is disclosed. In some embodiments, the carrier ring is configured to support a semiconductor substrate, the carrier ring includes a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner periphery having a first diameter of about 298.4 to 299.5 millimeters (mm), and a plurality of inwardly extending tabs disposed about an inner periphery of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0 to 298.5 mm.

[0005] In some variations, the first diameter of the inner portion of the ring is about 299.0 mm and the second diameter of the plurality of inwardly extending tabs is about 297.0 mm.

[0006] In some variations, the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs.

[0007] In some variations, at least one of the plurality of inwardly extending tabs has a width of about 0.5-1.5 mm.

[0008] In some variations, the width of the at least one of the plurality of inwardly extending tabs is about 1.0 mm.

[0009] In some variations, at least one of the plurality of inwardly extending tabs includes at least a portion of an upper surface that is at an angle other than parallel or perpendicular to the plane.

[0010] In some variations, the angle of the portion of the upper surface is between about 5 and 20 degrees relative to the plane.

[0011] In some variations, a top surface of the at least one of the plurality of inwardly extending tabs comprises a minimum contact area (MCA) configured to make physical contact with a semiconductor substrate.

[0012] In some variations, the outer portion is about 0.3-0.7 mm thick and the inner portion is about 0.1-0.5 mm thick.

[0013] In some variations, at least a portion of the plurality of inwardly extending tabs disposed about an inner circumference of the inner portion of the ring are configured to form one or more conductive ground points on the semiconductor substrate.

[0014] In some embodiments, the carrier ring is configured to support a semiconductor substrate, the carrier ring including a ring with an inner portion configured to support a semiconductor substrate during backside deposition on the semiconductor substrate, the ring defining a plane, and 8-15 inwardly extending tabs disposed about the inner portion of the ring and configured to contact the semiconductor substrate during backside deposition on the semiconductor substrate, at least one of the 8-15 inwardly extending tabs having a width of about 0.5-1.5 mm.

[0015] In some variations, the at least one of the 8-15 inwardly extending tabs has an upper surface that is at an angle of about 15 degrees or less relative to a plane.

[0016] In some variations, the 8-15 inwardly extending tabs have an inner edge defining a first diameter of about 296.0-298.5 mm and the 8-15 inwardly extending tabs have an outer edge attached to the ring and defining a second diameter of about 298.4-299.5 mm.

[0017] In some variations, at least a portion of the 8-15 inwardly extending tabs are configured to allow for formation of one or more conductive ground points on the semiconductor substrate.

[0018] In another aspect of the present disclosure, a method of depositing one or more layers on a backside of a semiconductor substrate is disclosed. In some embodiments, the method includes: (a) supporting the semiconductor substrate on a carrier ring, the carrier ring comprising a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner periphery having a first diameter of about 298.4 to 299.5 millimeters (mm), and a plurality of inwardly extending tabs disposed about an inner periphery of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0 to 298.5 mm; and (b) exposing the backside of the semiconductor substrate to process conditions that cause one or more layers to deposit on the backside of the semiconductor substrate.

[0019] In some variations, the process conditions that cause the one or more layers to deposit include exposure to a chemical precursor of at least one of the one or more layers.

[0020] In some variations, at least one of the one or more layers on the backside of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof.

[0021] In some variations, the first diameter of the inner portion of the ring is about 299.0 mm and the second diameter of the plurality of inwardly extending tabs is about 297.0 mm.

[0022] In some variations, the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs, and at least one of the at least eight inwardly extending tabs has a width of about 0.5-1.5 mm.

[0023] In some variations, at least one of the plurality of inwardly extending tabs has at least a portion of its top surface that is at an angle that is neither parallel nor perpendicular to the plane, the angle being between about 5 and 20 degrees relative to the plane.

[0024] These and other features of the disclosed embodiments are described in detail below with reference to the associated drawings. [Brief description of the drawings]

[0025] [Figure 1A] 1 is a block diagram illustrating a substrate processing system that may be used to perform a process on a substrate, according to some embodiments. [Figure 1B] 1 is a block diagram illustrating a substrate processing system that may be used to perform a process on a substrate, according to some embodiments.

[0026] [Figure 2A] 1 is a simplified diagram of a carrier ring and location of a tab according to some embodiments.

[0027] [Figure 2B] 2B is a graph of film thickness versus exemplary angular position of the carrier ring of FIG. 2A.

[0028] [Figure 3A] FIG. 2 illustrates a semiconductor substrate and various concentric radial points.

[0029] [Figure 3B] 1 is a map showing an example map of radial data points.

[0030] [Figure 3C] 1 is a table showing exemplary average thicknesses of deposited films at various radii.

[0031] [Figure 3D] 1 is a graph illustrating the difference between an exemplary maximum average film thickness and an exemplary film thickness along an angular position of a circle defined by a given radius.

[0032] [Figure 3E]13 shows a graph illustrating an exemplary level difference along an angular position determined by subtracting an exemplary given film thickness from an exemplary maximum average film thickness.

[0033] [Figure 4] 4 is a graph illustrating an exemplary variation in thickness differential versus radius of a substrate placed on a carrier ring.

[0034] [Figure 5A] 1 is a simplified diagram illustrating components of a substrate processing system according to some embodiments.

[0035] [Figure 5B] 5B is a close-up view of a cross-sectional portion of the carrier ring of FIG. 5A according to some embodiments. [Figure 5C] 5B is a close-up view of a cross-sectional portion of the carrier ring of FIG. 5A according to some embodiments.

[0036] [Figure 6A] 1 is a perspective view of a carrier ring according to some embodiments.

[0037] [Figure 6B] FIG. 6B is a top-down view of the carrier ring of FIG. 6A according to some embodiments.

[0038] [Figure 6C] FIG. 6B is a top-down close-up view of a tab of the carrier ring of FIG. 6A according to some embodiments.

[0039] [Figure 6D] FIG. 6D is a perspective view of the tab of FIG. 6C according to some embodiments.

[0040] [Figure 6E] 6D is a cross-sectional view of the tab and carrier ring across the cross section of FIG. 6C according to some embodiments.

[0041] [Figure 6F]6D is a cross-sectional view of a non-tab location and carrier ring taken through another cross section of FIG. 6C according to some embodiments.

[0042] [Figure 7] FIG. 13 illustrates an exemplary embodiment with various optimizations associated with at least one tab of the carrier ring.

[0043] [Figure 8] 1A-1C illustrate a comparison between existing carrying rings and tabs and example carrying rings and tabs disclosed herein in tabbed and non-tabbed positions according to some embodiments.

[0044] [Figure 9] 1 illustrates a semiconductor wafer disposed on a carrier ring having multiple tabs, according to some embodiments.

[0045] [Figure 10] 1 is a diagram of a processed substrate that may be clamped onto a pedestal chuck according to some embodiments.

[0046] [Figure 11] 1 is a flow diagram illustrating a method for obtaining an apparatus configured to support a semiconductor substrate, according to some embodiments.

[0047] [Figure 12] 1 is a flow diagram illustrating a method of depositing one or more layers on a backside of a semiconductor substrate according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] The present disclosure relates to carrier rings used for semiconductor processing.

[0049] The dimensions of features (e.g., lines, traces, circuits) fabricated on a wafer substrate can easily become distorted based on slight alignment or warping deviations of the substrate, since the features (which can reach the nanometer scale) may require precise processing. Moreover, such substrates are generally thin and prone to internal or tensile / compressive stresses, especially during the fabrication process (deposition, etching, heating, layering, etc.). Furthermore, some processing steps (e.g., photolithography) are extremely precise and may produce poor results if the substrate is not substantially flat. The problem is known as lithography defocus. Appearance Warping can occur especially when large stacks of material are deposited, for example in the context of 3D NAND (three-dimensional NOT AND) devices, a type of non-volatile flash memory in which memory cells are stacked in multiple layers. If the warping is significant, it can have a detrimental effect on subsequent processing steps. For example, a substrate may fail to chuck properly if it warps too much.

[0050] One exemplary stack that may cause these problems is a stack with alternating layers of oxide and nitride (e.g., silicon oxide, silicon nitride, silicon oxide, silicon nitride). Another exemplary stack that may cause warping includes alternating layers of oxide and polysilicon (e.g., silicon oxide, polysilicon, silicon oxide, polysilicon). Other examples of stack materials that may be problematic include, but are not limited to, tungsten and titanium nitride. The materials in the stack may be deposited by chemical vapor deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or by direct metal deposition (DMD), etc. These examples are not limiting.

[0051] Some techniques devised to prevent warping involve adjusting the deposition process to reduce or offset the internal stress of the deposition layer. For example, some processes involve depositing a film on the backside of the substrate, such as depositing a high-stress dielectric film using chemical vapor deposition (CVD) on the backside of the substrate. If the backside film has an internal stress that is of the same type (tensile or compressive) as the type of internal stress induced on the frontside, and of a comparable magnitude to the magnitude of the internal stress induced on the frontside, the backside film effectively offsets and compensates for the warping. As a result, the substrate may have a more neutral warping, which means that the substrate will be flatter with less warping.

[0052] The material deposited on the backside of the substrate may be a dielectric material in various embodiments. In some cases, oxides and / or nitrides (e.g., silicon oxide / silicon nitride) may be used. Examples of silicon-containing reactants that may be used include, but are not limited to, silanes, halosilanes, and aminosilanes. Silanes contain hydrogen and / or carbon groups, but do not contain halogens. Examples of silanes are silane (SiH4), disilane (Si2H6), and organosilanes, such as methylsilane, ethylsilane, isopropylsilane, t-butylsilane, dimethylsilane, diethylsilane, di-t-butylsilane, allylsilane, sec-butylsilane, thexylsilane, isoamylsilane, t-butyldisilane, and di-t-butyldisilane. Halosilanes contain at least one halogen group and may or may not contain hydrogen and / or carbon groups. Examples of halosilanes are iodosilane, bromosilane, chlorosilane and fluorosilane. Halosilanes, especially fluorosilanes, can form reactive halide species that can etch silicon materials, but in some embodiments described herein, no silicon-containing reactants are present when the plasma is struck. Specific chlorosilanes are tetrachlorosilane (SiCl4), trichlorosilane (HSiCl3), dichlorosilane (H2SiCl2), monochlorosilane (ClSiH3), chloroallylsilane, chloromethylsilane, dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, t-butylchlorosilane, di-t-butylchlorosilane, chloroisopropylsilane, chloro-sec-butylsilane, t-butyldimethylchlorosilane, thexyldimethylchlorosilane, and the like. Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens and carbon.Examples of aminosilanes are mono-, di-, tri-, and tetra-aminosilane (H3Si(NH2)4, H2Si(NH2)2, HSi(NH2)3, and Si(NH2)4, respectively), as well as substituted mono-, di-, tri-, and tetra-aminosilanes, such as t-butylaminosilane, methylaminosilane, tert-butylsilane amine, bis(tert-butylamino)silane (SiH2(NHC(CH3)3). 2) (BTBAS), tert-butylsilylcarbamate, SiH(CH3)-(N(CH3)2)2, SiHCl-(N(CH3)2)2, (Si(CH3)2NH)3, etc. A further example of an aminosilane is trisilylamine (N(SiH3)). Other potential silicon-containing reactants are tetraethylorthosilicate (TEOS) and tetramethoxysilane (TMOS), fluorotriethoxysilane (FTES), trimethylsilane (TMS), octamethyltetracyclosiloxane (OMCTS), tetramethylcyclotetrasiloxane (TMCTSO), dimethyldimethoxysilane (DMDS), hexamethyldisilazane (HMDS), hexamethyldisiloxane (HMDSO), hexamethylcyclotrisiloxane (HMCTSO), dimethyldiethoxysilane (DMDEOS), methyltrimethoxysilane (MTMOS), tetramethyldisiloxane (TMDSO), divinyltetramethyldisiloxane (VSI2), methyltriethoxysilane (MTE and cyclic and acyclic TEOS variants, such as TEOS, dimethyltetramethoxydisiloxane (DMTMODSO), ethyltriethoxysilane (ETEOS), ethyltrimethoxysilane (ETMOS), hexamethoxydisilane (HMODS), bis(triethoxysilyl)ethane (BTEOSE), bis(trimethoxysilyl)ethane (BTMOSE), dimethylethoxysilane (DMEOS), tetraethoxydimethyldisiloxane (TEODMDSO), tetrakis(trimethylsiloxy)silane (TTMSOS), tetramethyldiethoxydisiloxane (TMDEODSO), triethoxysilane (TIEOS), trimethoxysilane (TIMEOS), or tetrapropoxysilane (TPOS).

[0053] Exemplary nitrogen-containing reactants include, but are not limited to, ammonia, hydrazine, and amines (e.g., amines bearing carbon), such as methylamine, dimethylamine, ethylamine, isopropylamine, t-butylamine, di-t-butylamine, cyclopropylamine, sec-butylamine, cyclobutylamine, isoamylamine, 2-methylbutan-2-amine, trimethylamine, diisopropylamine, diethylisopropylamine, di-t-butylhydrazine, and aromatic-containing amines, such as aniline, pyridine, and benzylamine. The amines can be primary, secondary, tertiary, or quaternary (e.g., tetraalkylammonium compounds). The nitrogen-containing reactants may contain heteroatoms other than nitrogen, for example, hydroxylamine, t-butyloxycarbonylamine, and Nt-butylhydroxylamine are nitrogen-containing reactants.

[0054] Examples of oxygen-containing co-reactants include oxygen, ozone, nitrous oxide, carbon monoxide, nitric oxide, nitrogen dioxide, sulfur oxides, sulfur dioxide, oxygen-containing hydrocarbons (CxHyOz), water, mixtures thereof, and the like.

[0055] In modern semiconductor processing equipment, a substrate may rest on a pedestal during semiconductor processing operations. The pedestal may be a so-called shower pedestal, which is a pedestal-like structure with a number of gas distribution ports distributed over its upper surface (much like a showerhead with several gas distribution ports distributed over its underside). The gas distribution ports may be fluidly connected with one or more plenums located within the shower pedestal. The one or more plenums may be fluidly connected with one or more process gas sources, which may be controllable to allow process gases to be flowed from the shower pedestal through the gas distribution ports.

[0056] Such semiconductor processing tools may also have one or more carrier ring supports that may be configured to support a carrier ring, which in turn may support a substrate during processing operations. The one or more carrier ring supports may be designed to allow the carrier ring, and any substrate supported thereby, to be held at an elevated location above the shower pedestal, such that there is a gap intermediate the shower pedestal and the substrate, to which processing gases can be delivered. Such semiconductor processing tools thus allow the underside of the substrate to undergo substrate processing operations instead of the upper side of the substrate, allowing deposition of a film on the backside of the substrate.

[0057] However, the carrier ring may include tabs that impede backside film deposition on areas of the substrate that overlap the tabs. To allow for fabrication of additional or larger components, it is desirable to maximize or optimize the available space for deposition. Even an increase of a few square mm on the backside of a 200, 300, or 450 millimeter (mm) substrate can improve space efficiency for fabrication.

[0058] Therefore, a carrier ring with physical characteristics that balances the size, shape, quantity, and other parameters associated with the tabs of the carrier ring is desired.

[0059] The following terms are used throughout the specification.

[0060] "Wafer bow" as used herein may refer to deformation of a substrate or wafer. Wafer bow may occur during fabrication, for example, as a result of stress on a substrate during deposition of material on the active surface of the substrate. Wafer bow may occur during various types of fabrication, such as when large stacks of materials are deposited. Wafer bow may cause complications in subsequent processing steps. For example, a substrate may fail to chuck properly if the amount of bow is too large. Moreover, some processing steps (e.g., photolithography) may produce poor results when performed on an excessively bowed substrate.

[0061] Wafer bow may be measured as the deviation of the mean or median distance of the surface of the substrate relative to a reference plane. The central surface point of the substrate may be the center point (e.g., in the case of concave or dome-shaped bow) or the edge point of the substrate and / or the average edge point of the substrate (e.g., in the case of buckling or convex bow).

[0062] As used herein, "platen" refers to the upper surface of an electrostatic chuck (ESC) on which a substrate or wafer undergoing fabrication is placed. There may be a gap between the substrate and the platen surface (e.g., upper surface), which is generally referred to herein as "d."

[0063] As used herein, "pedestal" may refer to a structure or housing that supports or contains the platen.

[0064] The terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" may be used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" can refer to a semiconductor wafer during any of the many stages of integrated circuit fabrication on the semiconductor wafer. Wafers or substrates used in the semiconductor device industry generally have diameters of 200 mm, or 300 mm, or 450 mm. In addition to semiconductor wafers, other workpieces that may utilize the disclosed embodiments include various articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, display devices, or components such as backplanes for pixelated display devices, flat panel displays, micromechanical devices, and the like. Workpieces may be of various shapes, sizes, and materials.

[0065] As used herein, a "semiconductor device fabrication operation" is an operation performed during the fabrication of a semiconductor device. As referred to herein, such fabrication operations may simply be referred to as a "process" or "treatment." Examples of treatments include deposition of material on a substrate, selective etching of material from the substrate, and ashing of photoresist on the substrate. Generally, an overall fabrication process includes multiple semiconductor device fabrication operations, each of which is performed in its own semiconductor fabrication tool, such as a plasma reactor, an electroplating cell, a chemical mechanical planarization tool, a wet etching tool, etc. Categories of semiconductor device fabrication operations include subtractive processes, such as etching processes and planarization processes, and additive processes, such as deposition processes (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, electroless deposition). In the context of an etching process, a substrate etching process includes a process of etching a mask layer or, more generally, a process of etching any layer of material previously deposited on and / or otherwise present on the substrate surface. Such an etching process may etch a stack of layers in a substrate.

[0066] "Manufacturing equipment" refers to equipment in which a manufacturing process takes place. Manufacturing equipment often has a processing chamber within which a workpiece resides during processing. Generally, when in use, manufacturing equipment performs one or more semiconductor device fabrication operations. Examples of manufacturing equipment for semiconductor device fabrication include deposition reactors, such as electroplating cells, physical vapor deposition reactors, chemical vapor deposition reactors, and atomic layer deposition reactors, and removal process reactors, such as dry etch reactors (e.g., chemical and / or physical etch reactors), wet etch reactors, and ashers.

[0067] As referred to herein, manufacturing equipment may simply be referred to as a "process chamber." In various embodiments, a process chamber is generally a sealed enclosure in which a substrate is secured during processing. A process chamber may include components associated with gas delivery and removal. A process chamber may also include components associated with generating plasma and controlling the properties of the plasma within the chamber. A process chamber may include components for controlling pressure, including pulling a vacuum within the chamber. In the context of the present disclosure, a process chamber may include a pedestal upon which a substrate sits while it is being processed. The pedestal may be equipped with a chuck, such as an ESC, to hold the substrate in place during processing. Substrate Processing System

[0068] 1A is a block diagram illustrating a substrate processing system 100 used to perform processing on a substrate 128 (also referred to as a wafer), according to some embodiments. As shown, the substrate processing system may include a chamber 102. A central row may be configured to support a pedestal for when a top surface of the substrate 128 is being processed, for example, when a film is being formed on the top surface of the substrate 128 or on the backside of the substrate 128. The pedestal may be referred to as a showerhead pedestal ("show-ped") 106, according to some embodiments disclosed herein. A showerhead 104 may be disposed on the show-ped 106.

[0069] In some embodiments, the showerhead 104 may be electrically coupled to a power source 122 via a matching network 125. The power source 122 may be controlled by a control module 120, e.g., a controller. In some embodiments, power may be provided to the showerhead 104 instead of the showerhead 104. The control module 120 may be configured to operate the substrate processing system 100 by executing process inputs and controls for a particular process recipe. Depending on whether the top surface of the substrate 128 or the bottom surface of the substrate 128 is receiving a deposition film, the controller may Rule The module 120 may set various operational inputs for the process recipe, such as power levels, timing parameters, process gases, mechanical movement of the substrate 128, and / or height of the substrate 128 relative to the show-ped 106.

[0070] In some embodiments, the central row may also include lift pins controlled by the lift pin control. Such lift pins may be used to raise the substrate 128 from the show-ped 106 to allow an end effector (not shown) to pick up the substrate 128, and to lower the substrate 128 after it has been placed by the end effector. The end effector may also place the substrate 128 on a spacer 130. As described below, the spacer 130 may be sized to provide a controlled separation of the substrate 128 between the top surface of the showerhead 104 (facing the substrate 128) and the top surface of the show-ped 106 (facing the substrate 128).

[0071] In some embodiments, the substrate processing system 100 may further include a first gas manifold 108 connected to a first gas source 110, such as a gas chemistry supply and / or an inert gas from a facility. Depending on the process being performed on the top surface of the substrate 128, the control module 120 may control the delivery of the first gas source 110 through the first gas manifold 108. The selected gas is then delivered to the showerhead 104. Swept away, may be dispensed into a spatial volume defined between the surface of the showerhead 104 facing the substrate 128 when the substrate 128 rests on the pedestal.

[0072] In some embodiments, the substrate processing system 100 may further include a second gas manifold 112 connected to a second gas source 114, e.g., a gas chemical supply from a facility and / or an inert gas. Depending on the process being performed on the lower surface of the substrate 128, the control module 120 may control the delivery of the second gas source 114 through the second gas manifold 112. The selected gas may then be blown to the showerhead 104 and distributed into a spatial volume defined between the lower surface of the substrate 128 or a surface of the show-ped 106 facing the lower side (e.g., backside) when the substrate 128 rests on the spacer 130. The spacer 130 may provide isolation that optimizes deposition on the lower surface of the substrate 128 while reducing deposition on the upper surface of the substrate 128. In some embodiments, while deposition is targeted to the underside of the substrate 128, an inert gas may be splashed onto the top surface of the substrate 128 via the showerhead 104, which may push the reactant gases away from the top surface and allow the reactant gases provided from the shower-ped 106 to be directed toward the underside of the substrate 128.

[0073] Additionally, the gases may or may not be premixed. Appropriate valving and mass flow control mechanisms may be employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. Process gases may exit the chamber 102 via an outlet. A vacuum pump (e.g., a one- or two-stage mechanical dry pump and / or a turbomolecular pump) may draw the process gases and maintain an appropriately low pressure in the reactor by a closed-loop controlled flow restriction device, such as a throttle valve or pendulum valve.

[0074] In some embodiments, the carrier ring 124 may surround an outer region of the show-ped 106. When the top surface of the substrate 128 is being processed, e.g., when material is being deposited on the substrate 128, the carrier ring 124 may be configured to rest on a carrier ring support area that is stepped down from the wafer support area in the center of the show-ped 106. The top surface of the carrier ring 124 is generally flush with the top surface of the substrate 128. The carrier ring 124 may include an outer edge side of the disk structure of the carrier ring 124, e.g., an outer radius, and a wafer edge side of the disk structure of the carrier ring 124, e.g., an inner radius closest to where the substrate 128 rests. The carrier ring 124 may be associated with an inner diameter (ID). The inner diameter may extend to an inner periphery of the carrier ring and generally surround a substrate (e.g., substrate 128) in a processing chamber. The wafer edge side of the carrier ring 124 may also include a number of contact support structures or "tabs" that may be configured to lift the substrate 128 when the carrier ring 124 is held by the spacers 130. The carrier ring 124 may include a number of tabs with a range of selected amounts (e.g., six tabs are shown in FIG. 2A, described below) to support the substrate 128 during processing. Additional details regarding embodiments of the tabs are provided below.

[0075] 1B is a block diagram illustrating another substrate processing system 150 used to perform processing on a substrate 128, according to some embodiments. In some embodiments, spider forks 132 may be used to lift and maintain the carrier ring 124 at its processing height, for example, to enable deposition on the underside (backside) of the substrate 128. Thus, the carrier ring 124 may be lifted along with the substrate 128. In some implementations, the carrier ring 124 may be rotated to another station, for example, in a multi-station system. Film thickness variation

[0076] 2A is a simplified diagram of a carrier ring 200 and the location of tabs 202, according to some embodiments. In some embodiments, six tabs 202 may be disposed around an inner circumference of the carrier ring 200. The carrier ring tabs may result in a "shadow" where a backside deposition layer is not deposited on a substrate placed on the carrier ring, or the backside deposition layer is deposited less than on areas outside the tab shadow.

[0077] In some embodiments, the carrier ring 200 may have an inside dimension 204, e.g., 299.0 mm. In some embodiments, a notch tab 206 may be present. The notch tab 206 may assist in blocking plasma from reaching the front side of the substrate, since the substrate typically includes a wafer notch that may be susceptible to such leakage. The notch tab 206 may assist in aligning the semiconductor substrate with the carrier ring so that the substrate is in a desired orientation (e.g., for plasma blocking as described above) before processing is performed on the substrate. Processing may, for example, deposit a film on the back side of the substrate, as described elsewhere herein.

[0078] 2B is a graph of film thickness versus an exemplary angular position of the carrier ring 200. The film thickness may not be uniform across the surface of the substrate. In particular, at six angular positions corresponding to the locations of the six tabs 202 in FIG. 2A, the deposited film thickness is relatively smaller. In this case, the six tabs significantly reduced the film thickness at the edge of the substrate, as indicated by box 220.

[0079] 2A and 2B presents an opportunity to increase the deposition rate, for example, by allowing more process gas to diffuse under the tab. Increasing the deposition rate provides advantages such as more of the substrate being used during processing (reduced shadowing effects, as well as space- and cost-efficient use of "real estate") and / or reduced impedance variations in the carrier ring.

[0080] 3A is a diagram illustrating a semiconductor substrate 300 and various concentric radial points. For example, a first radial point 302 is located r away from the center point of the semiconductor substrate 300. 1 mm, and the second radial point 304 is r 17 The third radial point 306 is r mm from the center point. 6 mm. In FIG. 3A, the above-mentioned r 1 Radius to r 17 Range to radius Between Various other radial points of r can be seen. In one scenario, thickness variations and local deviations from planarity are mostly 1 Starting at a radius of r mm, 1 , r 6 , and r 17 represents the radius from the center point of the semiconductor substrate 300. Example values ​​for these radii may range from 120 mm to 148.2 mm, although a myriad of different values ​​and ranges (e.g., below 120 mm and / or above 148.2) may be evaluated depending on the semiconductor substrate and its implementation.

[0081] 3B is a map 310 illustrating an example map of radial data points defined by x,y coordinates with a center at the origin 312 of a circle corresponding to the shape of the semiconductor substrate 300. 17 A second radial point 304, corresponding to a radius in mm, can also be seen in FIG. 3B.

[0082] FIG. 3C is a table 320 showing exemplary average thicknesses of deposited films at various radii. For example, r 6 Assume that at a radius of 1 mm, the average deposition thickness is determined to be 6138 arbitrary units (e.g., nanometers (nm)). The film thickness may be measured using conventional means or measurement tools, such as spectroscopic ellipsometry, thickness monitors, interferometers, surface profilers, or scanning electron microscopy. In particular, in this example, r 6 = 6138 The average thickness in arbitrary units is r 1 mm~r 17 It is the highest of all the average thicknesses measured from a radius of mm.

[0083] 3D is a graph 330 illustrating the difference between an exemplary maximum average film thickness 332 and a given film thickness 334 along an angular position of a circle defined by a given radius along the carrier ring. In the example of FIG. 3D, the exemplary maximum average film thickness 332 (r 6 ) for comparison, r 17 A radius in mm, i.e., the outermost radius measured, was selected. Graph 330 shows an exemplary maximum average film thickness 332 in dotted lines and a given film thickness 334 in solid lines that represent data points (e.g., corresponding to map 310 shown in FIG. 3B) corresponding to the measured thickness (in degrees) at each radial position. Given film thickness 334 shows that the thickness may be relatively smaller at an angular position corresponding to a tab (e.g., tab 202 shown in FIG. 2A). The r 6 mm and r 17 A simplified diagram 340 showing the two radii in mm is also shown.

[0084] Using the above data, e.g., the data points associated with map 310, table 320, and / or graph 330, a "level difference" (D) between the maximum average film thickness and a given film thickness 334 can be measured. Existing measurement techniques only measure the percentage of non-uniformity or the average film thickness, which may provide an aggregate measure of uniformity. The level difference indicates the film thickness delta at individual points and may be a clearer indication of the severity of how wide the thickness range may be. FIG. 3E shows an exemplary maximum average film thickness 332. from Illustrated is a graph 350 showing an example level difference along an angular position, determined by subtracting a given film thickness 334. The solid line 351 showing the level difference clearly highlights the delta between angular positions corresponding to the tabs, where there is a peak 354.

[0085] Performing photolithography or other downstream processes that rely on substrate uniformity with little or no deviation from strict planarity anywhere on the substrate can introduce errors, especially in areas of the substrate where less backside material has been deposited. Therefore, it is desirable to keep the level difference below a certain amount. Some exemplary applications may specify that the level difference should remain below a prescribed amount in arbitrary units, e.g., below dashed line 352. One such example may be 700 nm. The above "level difference" problem, where the level difference is measured to be above a certain amount (e.g., peak 354, where the tab is located when D is above dashed line 352 or another threshold level), may indicate that the resulting substrate has non-uniform film deposition and / or unrealized deposition potential at the tab location. In some cases, depending on the application, the configuration (e.g., amount, physical shape) of the tabs and / or carrier rings, and / or post-processing of the resulting warpage, a level difference greater than a certain amount (e.g., dashed line 352) may result in yield loss and / or slower processing of the substrate (e.g., slower lithography process), which may be a costly or time-consuming, and therefore undesirable, outcome.

[0086] 4 is a graph 400 illustrating an example variation of thickness difference with respect to the radius of a substrate placed on a carrier ring. As shown, (e.g., radius r 1 The film thickness for the central portion of the substrate (greater than r mm) decreases as the radius approaches the far edge of the substrate (e.g., r 17 At radii approaching r mm, the thickness may fall off more quickly (the "derivative" of the thickness change). Portions of the carrier ring (e.g., portions against which the substrate may abut) may, for example, be at least partially physically blocked from reacting with the deposition gas. In some cases, the thickness may fall off more quickly at the very edge of the substrate (e.g., at r edge Near a radius of 1 mm), the thickness can drop to zero. In addition to the above problem of the level difference increasing sharply at the tab location (thickness variation with radial position), the drop in thickness near the edge of the substrate (the "edge effect" of thickness variation with radial distance) can lead to non-uniform film thickness. However, it is desirable to keep the film thickness consistent across the radius of the substrate during substrate processing.

[0087] Thus, the present disclosure describes, among other things, optimized carrier rings and associated structures (e.g., tabs) that minimize substrate contact area (which increases the deposition area near the substrate edge and therefore increases film thickness uniformity) and minimize edge effects. Carrier Ring Configuration

[0088] FIG. 5A is a simplified diagram illustrating components of a substrate processing system 500, according to some embodiments. In some embodiments, the substrate processing system 500 may be an example of the substrate processing system 100 or 150. The substrate processing system 500 may include a showerhead 502 disposed on a show-ped 504. A carrier ring 506 may be disposed between the showerhead 502 and the show-ped 504 and may be a structure having a ring-like shape. A cross-section of the carrier ring 506 is shown in FIG. 5A with cross-sectional portions 506a (also labeled "A") and 506b (also labeled "B"). These cross-sectional portions may have symmetry, and the dimensions of the cross-sectional portions may apply substantially equally to all cross-sections. For example, the cross-sectional portion 506a may have a thickness of about 0.1-0.5 mm (e.g., 0.3 mm in some embodiments) all around the carrier ring 506, and the cross-sectional portion 506b may have a thickness of about 0.1-0.5 mm (e.g., 0.3 mm in some embodiments) all around the carrier ring 506. 506b may have a thickness of 0.3-0.7 mm (e.g., 0.5 mm in some embodiments) all around the carrier ring 506. The carrier ring 506 may have an inner diameter (ID) 508 and an outer diameter (OD) 510 that allow a substrate (e.g., a wafer 512) to be placed on the carrier ring 506, for example, above the "A" portion and against the "B" portion. The wafer 512 may have a circular shape to fit onto the carrier ring 506. A plasma 514 may be formed or extinguished beneath the wafer 512.

[0089] In some embodiments, the carrier ring ID 508 may be selected from a diameter of 298.4 to 299.5 mm. For example, the carrier ring ID 508 may have a diameter of 299.0 mm in some cases. Thus, with a carrier ring ID of 299.0 mm, a 300 mm wafer may rest on the carrier ring 506 with a majority of the back surface of the wafer exposed for processing (backside deposition, etching, etc.).

[0090] 5B and 5C are close-up views of a cross-sectional portion of the carrier ring 506, according to some embodiments. In some portions of the carrier ring 506, as shown in FIG. 5B, the inner diameter includes a tab 506c. In some embodiments, the tab 506c can be a support structure for the wafer 512. The tab 506c can, for example, prevent the wafer 512 from falling through the carrier ring 506. In some implementations, the tab 506c can have an inclined or tapered surface at an angle 520 relative to one or more of the top surfaces 516a, 516b of the cross-sectional portions 506a, 506b. In various implementations, the angle 520 can be neither parallel nor perpendicular to a plane associated with the top surface 516a or 516b (or both). In some cases, the angle 520 can be between about 5 and 20 degrees, for example, about 15 degrees or less, for example, about 11.1 degrees, from a plane 518 defined by the top surface 516a. The top surface 516a from which the tabs extend inwardly may interface with (eg, support via physical contact with) the wafer 512.

[0091] In some implementations, the tabs may be disposed around the inner diameter of the carrier ring 506. Additionally, the tabs may be inwardly extending tabs having an outer edge attached to the ring and defining the inner diameter. In some cases, the inner diameter may be selected from a range of 296.0-299.5 mm, e.g., 297.0 mm. The amount of tabs may be selected (e.g., at least 8, or at least 5 to at most 15, or an amount selected from a range of at least 8 to at most 15, e.g., 12) to ensure that when the wafer 512 is placed on the carrier ring 506, the wafer 512 does not fall through the carrier ring 506 (e.g., if one or more of the tabs are deformed or broken) and does not result in tilting of the wafer 512. It is essential to keep the wafer perfectly level, since processing on a tilted wafer may render the resulting deposition, etching, etc., partially or completely unusable. For example, a good image may not be obtained for lithography, and, for example, line width may be lost. With fewer than a certain amount of tabs (e.g., three or four), the carrier ring 506 may also be at risk of tilting or falling through, for example, when moved. With more than a certain number of tabs (e.g., fifteen), excessive diminishing returns may result for the carrier ring 506 from unnecessary blocking of surface area (e.g., for backside deposition) and / or unnecessary manufacturing costs.

[0092] In some portions of the carrier ring 506, as shown in Figure 5C, the inner diameter does not have tabs, as shown by cross-sectional portion 506a having a relatively non-tapered surface. However, in some embodiments, cross-sectional portion 506a may have an angled portion 522. Locations that include tabs, such as those shown in Figure 5B, may have an angled portion that continues to extend to tab 506c.

[0093] FIG. 6A is a perspective view of a carrier ring 600, according to some embodiments. In some embodiments, the carrier ring 600 may be an example of the carrier ring 506 described with respect to FIG. 5A. The carrier ring 600 may have an inner diameter 602 measured between one end of an inner circumference 604 and an opposite end of the inner circumference 604. The inner circumference 604 may be defined by an inner wall of an inner portion of the carrier ring 600, where the cross-sectional portion 506a is an example of an inner portion. In some implementations, the inner diameter 602 may be selected from a range of 298.4 mm to 299.5 mm. An example of the inner diameter 602 may be 299.0 mm.

[0094] Figure 6B is a top-down view of carrier ring 600, according to some embodiments. An inner diameter 602 of carrier ring 600 may extend between opposite ends of an inner periphery 604, as also shown in Figure 6A. In some embodiments, a plurality of inwardly extending tabs, such as tab 606, may be disposed about inner periphery 604 (at the inner portion) of carrier ring 600 and separated by non-tab locations 607. A majority of the inner periphery may have no tabs and have a non-tab cross-sectional configuration, such as that shown in Figure 5C.

[0095] In various implementations of the carrier ring 600, between 5 and 15 tabs may extend inwardly from the inner periphery 604 of the carrier ring 600. For example, in one such implementation, 12 tabs may be disposed about the inner periphery 604. In some cases, the tabs may be spaced apart by substantially equal distances from one another. However, in some cases, the tabs may be spaced apart at defined locations that are unequal distances to one another. For example, the tabs may be grouped together, for example, in groups of two, at six equidistant and / or equiangular locations. In other cases, other grouping schemes may be possible, for example, equal groups of three, four, or six, unequal amounts of groups.

[0096] Figure 6C is a top-down close-up view of tab 606, according to some embodiments. Figure 6D is a perspective view of tab 606, according to some embodiments. In some embodiments, tab 606 extends or protrudes inwardly to at least partially support or provide support for a semiconductor substrate, e.g., wafer 512. Figure 6E is a cross-sectional view of tab 606 and carrier ring 600 across section AA of Figure 6C, according to some embodiments.

[0097] In some embodiments, the tab 606 may have a sloped top surface that provides an angle with respect to a plane defined by the top surface of the inner periphery 604. In some implementations, the angle may be about 11.1 degrees. The angle may be selected from a range, e.g., 5 to 20 degrees, inclusive, or 10 to 12 degrees, inclusive. In other implementations, the angle may not be parallel or perpendicular to the plane, e.g., may have an angle selected from 15 degrees or less, or 10 degrees or less. The sloped surface of the tab may, for example, allow deposition gases to reach the backside surface of the substrate. In some cases, some of the tabs may have different angles from one another. For example, at least one of the tabs may be sloped at 11.1 degrees from the plane and at least another one of the tabs may be sloped at 5 degrees from the plane. In some cases, the angle may be shaped to be non-uniform over the length of the tab. The angle may be measured at the base of the tab, closest to the inner diameter of the carrier ring. In some cases, some tabs may not have a sloped top surface, in which case the non-sloped tabs may be placed at a lower height relative to the sloped tabs to prevent direct contact of the non-sloped tabs with the substrate.

[0098] In some embodiments, the tabs may have an inner diameter selected from the range of 296.0-299.5 mm, e.g., 297.0 mm. In some cases, the inner diameter of the tabs may be defined by an inner edge of the tab that defines a circle, i.e., the inner edge that defines the circle may have a diameter of 296.0-299.5 mm, e.g., about 296.0-298.5 mm, e.g., 270.0 mm. In some embodiments, the tabs 606 may have a maximum length (e.g., length 608 shown in FIG. 6E) of 10.0 mm. That is, in some implementations, the tabs 606 may have a length 608 that is less than 10.0 mm, e.g., 2.0 mm, 1.5 mm, 1.0 mm. In some cases, some of the tabs may have different lengths from one another. For example, at least one of the tabs may be 2.0 mm long and at least another one of the tabs may be 1.5 mm long.

[0099] In some embodiments, the tab 606 may have a maximum width of 2.0 mm. That is, in some implementations, the tab 606 may have a width less than 2.0 mm, e.g., 0.5 From mm 1.5 mm, for example, 1.0 mm. In some embodiments, tab 606 may have a minimum width of about 0.5 mm. In some cases, some tabs may have different widths from one another. For example, at least one of the tabs may be 1.0 mm wide and at least another one of the tabs may be 0.7 mm wide. In some cases, the width may not be uniform over the length of the tab. The width may be measured at the terminating end portion of the tab, and the tab may be, for example, wider or narrower than 1.0 mm along the length of the tab.

[0100] 6F is a cross-sectional view of the non-tab location 607 and carrier ring 600 across section BB of FIG. 6C, in accordance with some embodiments. In some embodiments, the inner perimeter can include an angled portion on at least one of the edges, such as angled portion 522 shown in FIG.

[0101] In different implementations of the carrier ring 600 or inwardly extending tabs (e.g., tab 606), the amount of tabs, the angle of the tabs, the inner diameter of the carrier ring, the length of the tabs, and / or the width of the tabs can be selected based on the type of gas used, the presence of plasma, the required substrate real estate, and / or the application. The dimensions described above can be summarized as follows.

[0102] In some embodiments, the carrier ring 704 can have an inner diameter selected from the range of about 298.4 mm to 299.5 mm, e.g., 299.0 mm. In some embodiments, the carrier ring 704 can include a plurality of tabs (one of the tabs is shown). In some implementations, the plurality of tabs can have an inner diameter selected from the range of 296.0 to 299.5 mm, e.g., 297.0 mm. In some implementations, the amount of the plurality of tabs can be selected from the range of at least 5 to a maximum of 15 (e.g., 12), and above that, the tabs can give a diminishing return. In some embodiments, the width of at least one tab 702 can be about 0.5 to 2.0 mm, e.g., 1.0 mm. In some embodiments, the length of at least one tab 702 can have a maximum length of about 10.0 mm. In some implementations, the downward tilt angle with respect to the upper surface of at least one tab 702 can be selected from the range of 15 degrees or less, e.g., 11.1 degrees. FIG. 7 is a diagram showing an exemplary embodiment with various optimizations related to at least one tab 702 of the carrier ring 704.

[0103] The above physical characteristics of the carrier ring 704 and / or at least one tab 702 of the carrier ring 704 represent, in some cases, a reduction or increase of some dimensions or parameters related to the tabs and the carrier ring. For example, the tabs may have a larger inner diameter, the tab width and / or length may be reduced, and / or the tabs may include a sloped portion to accommodate increased deposition, for example, by allowing more process gas to reach the backside area. Moreover, the carrier ring may have a larger inner diameter to minimize edge effects. However, smaller tabs and larger inner diameters may increase the potential that a substrate held and supported by the carrier ring 704 may become unstable, for example, prone to tilt. For example, there may be a greater potential for a substrate to tilt while seated on the carrier ring or to fall through the inner periphery of the carrier ring. Thus, to further accommodate the potential risks, the number of tabs may be increased (e.g., to 12) to prevent such risks.

[0104] In one exemplary embodiment, at least one tab 702 may have a width of about 1.0 mm, a length of about 2.0 mm, and a downward tilt angle of about 11.1 degrees. Additionally, the carrier ring 704 may have an inner diameter of about 299.0 mm and twelve tabs that are substantially equidistant and / or substantially equiangularly spaced.

[0105] In other examples, the above considerations may be balanced. Consider an implementation where the width is selected to be slightly smaller (e.g., 0.8 mm width). To accommodate the smaller tabs, the number of tabs may be increased (e.g., to 14 or 15) to ensure that the substrate does not drop or tilt, for example. Consider another implementation where a smaller inner diameter (e.g., 298.5 mm) is preferred. Given the increased stability of the substrate, the angle may be significantly increased to ensure that the process gas reaches the tab area. Each of these implementations, as well as countless other combinations of these ring and tab characteristics, may contribute to reducing level differences, minimizing substrate contact area (e.g., minimum contact area, discussed below), and ultimately minimizing edge effects (e.g., softening the transition of film thickness with respect to radial distance) and allowing for consistent film thickness. Moreover, minimizing the substrate contact area based on the above-mentioned physical characteristics of the tabs (including selection of the inner diameter of the carrier ring, the inner diameter of the tabs, the amount of tabs, the width of the tabs, the downward angle of the tabs, or a combination thereof) allows for more backside deposition on the substrate (e.g., at the substrate locations corresponding to the tabs) compared to another carrier ring having tabs that do not have these physical characteristics. For example, the tabs of the other carrier ring (without the above-mentioned physical characteristics) will be larger, thus, for example, reducing backside deposition. FIG. 7 shows a comparison with increasing the inner diameter of at least one tab 702 and reducing the width of at least one tab 702.

[0106] FIG. 8 shows a comparison between existing carrier rings and tabs and exemplary carrier rings and tabs disclosed herein in tabbed and non-tabbed positions according to some embodiments. In some embodiments, the exemplary carrier ring and tab 806a may be characterized by a smaller minimum contact area (MCA) 808 compared to conventional implementations 802a and 804a. The MCA may refer to the area of ​​the carrier ring (e.g., the top surface of the inner portion of the carrier ring) that may interface with (e.g., physically contact and / or support) the substrate (e.g., wafer 810). It is desirable to reduce or minimize the MCA for reasons such as increasing the deposition area on the backside of the wafer 810 and reducing particles. Particles may refer to foreign matter (e.g., dust particles) that interfere with deposition, etching, or other processes performed on the wafer 810 and may originate from or be caused by contact with other surfaces, such as the carrier ring. Thus, by reducing the contact area with the carrier ring, particle formation may be minimized.

[0107] In some embodiments, the exemplary carrier ring and tab 806a may be characterized by a beveled tab portion 812. In some implementations, the bevel may be at an angle that is 15 degrees or less (e.g., about 11.1 degrees), where the angle is measured relative to a plane 814 defined by the top area of ​​the inner portion of the carrier ring. The beveled tab portion 812 may terminate in an end portion having a defined height (e.g., about 0.09 mm). In some variations, such height may be variable according to the geometry and physical characteristics of the tab (e.g., the angle of bevel, inner diameter, or length of the tab).

[0108] In contrast, in conventional implementations 802a and 804a, the MCA may be significantly larger. Furthermore, the slope may not be present at the tab. Thus, the wafer 810 may come into greater contact with the carrier ring.

[0109] In some embodiments, the non-tabbed location of the exemplary carrier ring and tab 806b may further provide a reduced MCA, for example, by a reduced carrier ring inner diameter 818 compared to one or more of the existing implementations 802b, 804b. In some embodiments, the thickness of the carrier ring may also be reduced. In some implementations, the thickness of the inner and outer portions of the carrier ring may be about 0.3 mm and 0.5 mm, respectively. The smaller thickness of the inner and outer portions may help tune or match the wafer impedance, which may result in more uniform deposition and minimization of the edge effects mentioned above. Backside ground

[0110] FIG. 9 is a diagram of a semiconductor wafer 900 disposed on a carrier ring 902 having multiple tabs, according to some embodiments. The backside of the semiconductor wafer 900 and the carrier ring are shown to illustrate one tab 904 of the multiple tabs. In some embodiments, some or all of the multiple tabs may be an example of the inwardly extending tabs described above, for example, with respect to FIGS. 5A-8. That is, the tabs may have physical characteristics (tab ID, narrower width, angle of inclination, etc.) selected from the specified ranges described above. Processing (backside deposition, etching, etc.) may be performed on the semiconductor wafer 900 while the semiconductor wafer 900 is supported by the carrier ring 902 and the tabs including the tabs 904.

[0111] It should be understood that the above is equally applicable to any or all of the tabs that may be present on the carrier ring 902. According to some implementations, there may be up to 6, 8, 12, or 15 tabs, any or all of which may have physical characteristics as described herein with respect to the embodiments of Figures 5A-8.

[0112] 10 is an illustration of a processed wafer 900′ (e.g., from FIG. 9 ) that may be clamped onto a pedestal chuck 1002 (e.g., ESC) according to some embodiments. One potential source of disturbance during subsequent processing on the processed wafer 900′ is that when the backside of the processed wafer 900′ is completely coated, current charge may build up. This may cause adverse effects. For example, electrons may be deflected by application of an electron beam 1004.

[0113] However, some shadowing effects from the inner periphery of the tab and / or carrier ring 902 as described herein (including FIG. 9) may remain. By preserving an area free of deposition under the carrier ring tab, a clear conductive path 1006 may be provided as a conductive ground point between the pedestal chuck 1002 and the processed wafer 900'. In some embodiments, as a result of preserving multiple areas free of deposition under the carrier ring tab, there may be multiple conductive ground points (e.g., one conductive ground point or area per carrier ring tab).

[0114] The larger the path-to-ground, the less backside deposition that occurs, so shadowing effects from the tabs may be an additional factor to balance with the above considerations. Such other considerations to balance may include increasing the deposition area, reducing the level difference, preventing frontside deposition while allowing backside deposition, and preventing the processed wafer 900' from tilting or falling through the inner perimeter of the carrier ring.

[0115] For example, some embodiments of the carrier ring and tabs described herein may balance the desirability of reduced level difference or reduced MCA (e.g., based on carrier ring ID, tab ID, tab width, tab angle) against allowing for open electrical contact area using more contact area depending on the application or desired result. However, in some cases, allowing for more open electrical contact area may also be achieved by having additional tabs, e.g., 12 or more, some of which are not angled and contact the processed wafer 900'. Myriad combinations of physical properties of the disclosed embodiments of the carrier ring and tabs may be balanced to achieve the advantages described herein. method

[0116] FIG. 11 is a flow diagram illustrating a method 1100 for obtaining an apparatus configured to support a semiconductor substrate, according to some embodiments. One or more of the functions of the method 1100 may be performed or caused by a computerized apparatus or system. Means for performing the functions illustrated in one or more of the steps illustrated in FIG. 11 may include hardware and / or software components of such a computerized apparatus or system, such as a controller apparatus, a computerized system, or a computer readable apparatus, including a storage medium that stores computer readable and / or computer executable instructions that, when executed by a processor apparatus, are configured to cause at least one processor apparatus or computerized apparatus to perform an operation. A controller may be an example of a computerized apparatus or system. A process chamber may be another example of a computerized apparatus or system. Exemplary components of a process chamber (including a controller) are illustrated in FIG. 1A and FIG. 1B, described in more detail above.

[0117] Also, it should be noted that the operations of method 1100 may be performed in any suitable order, not necessarily the order shown in Figure 11. Moreover, method 1100 may include additional or fewer operations to obtain a device than those shown in Figure 11.

[0118] At block 1102, the method 1100 may include creating a ring-like structure having an inner diameter. The ring-like structure may have a substantially circular structure (e.g., a carrier ring) having an inner portion and an outer portion. In some embodiments, the inner diameter of the ring-like structure may range from 298.4 to 299.5 mm and extend from a center of the substantially circular structure to an inner circumference of the inner portion. In some implementations, the inner diameter may be about 299.0 mm.

[0119] At block 1104, the method 1100 may include forming a plurality of inwardly extending tabs around an inner diameter of the ring-like structure. In some embodiments, the number of tabs may be selected from a range of 5 to 15. In some implementations, there may be 12 tabs positioned around the inner diameter of the ring-like structure. In some variations, the tabs may be formed at equidistant and equiangular locations. In some variations, the tabs may be 、 For example, two tabs at six positions equidistant and equiangular from each other can be formed in groups of .

[0120] In some embodiments, the inwardly extending tabs may have one or more physical characteristics that allow for greater backside deposition of the semiconductor substrate compared to a ring-like structure having the tabs formed without the one or more characteristics. In some implementations, the one or more physical characteristics may include one or more of an inner diameter associated with the tabs, a width of the tabs, and an angle of at least a portion of a top surface associated with the tabs relative to a plane defined by the ring-like structure.

[0121] In some variations, the inner diameter associated with the tabs may range from 296.0 to 299.5 mm. In some examples, the tab inner diameter may be about 297.0 mm.

[0122] In some variations, the angle of at least a portion of the top surface may be selected from a range of 15 degrees or less, where at least a portion of the top surface are collectively configured to interface with (e.g., physically contact and / or support) a semiconductor substrate. In some examples, the angle may be approximately 11.1 degrees downward relative to a plane defined by the ring-like structure. In some cases, the angle may be shaped to be non-uniform over the length of the tab. The angle may be measured at the base of the tab closest to the inner diameter of the carrier ring. Alternatively, an average value of the angle may be selected.

[0123] In some variations, the width of the tabs may range from 0.5 to 2.0 mm. In some examples, the width of the tab may be about 1.0 mm. In some cases, the width may not be uniform over the length of the tab. The width may be measured at the terminal end portion of the tab, and the tab may be wider or narrower than 1.0 mm along the length of the tab.

[0124] The above physical characteristics of the carrier ring and its tab may contribute to reduced MCA, increased processing or deposition (e.g., on the backside of the semiconductor substrate), reduced particles, reduced edge effects, and ultimately a more consistent film thickness (e.g., measurable by reduced level difference). More specifically, the above physical characteristics of the tab allow for more backside deposition by providing minimal coverage on the backside of the semiconductor substrate, for example, as compared to some existing carrier rings that may have larger tabs that cover more of the backside area, which would prevent the amount of deposition that can be performed with the carrier rings described herein.

[0125] FIG. 12 is a flow diagram illustrating a method 1200 of depositing one or more layers on a backside of a semiconductor substrate according to some embodiments. One or more of the functions of the method 1200 may be performed or caused by a computerized device or system. Means for performing the functions illustrated in one or more of the steps illustrated in FIG. 12 may include hardware and / or software components of such a computerized device or system, such as a controller device, a computerized system, or a computer readable device, including a storage medium storing computer readable and / or computer executable instructions that, when executed by a processor device, for example, are configured to cause at least one processor device or computerized device to perform an operation. A controller may be an example of a computerized device or system. A process chamber may be another example of a computerized device or system. Exemplary components of a process chamber (including a controller) are illustrated in FIG. 1A and FIG. 1B, described in more detail above.

[0126] Also, it should be noted that the operations of method 1200 may be performed in any suitable order, not necessarily the order shown in Figure 12. Furthermore, method 1200 may include additional or fewer operations to deposit a layer than those shown in Figure 12.

[0127] At block 1202, the method 1200 may include supporting the semiconductor substrate on a carrier ring. In some embodiments, the carrier ring may be the carrier ring 600 shown in Figures 6A-6F, the carrier ring 704 shown in Figure 7, or the example carrier ring shown in Figure 8. The carrier ring may possess one or more physical characteristics possessed by the carrier ring described above, including a specified inner diameter of the carrier ring, an inner diameter of the plurality of inwardly extending tabs, a quantity of the plurality of inwardly extending tabs, a width of the plurality of inwardly extending tabs, and / or an angle of the plurality of inwardly extending tabs.

[0128] In some embodiments, the semiconductor substrate may be an example of the substrate 128 shown in Figures 1A and 1B. In some embodiments, the semiconductor substrate may be an example of the wafer 512 shown in Figures 5A-5C, 6E and 6F, the wafer shown in Figure 8, or the semiconductor wafer 900 shown in Figure 9.

[0129] In some embodiments, the semiconductor substrate may be placed on top of an inner portion of a carrier ring and surrounded by an outer portion of the carrier ring, In some implementations, the inner portion may be defined by cross-sectional portion 506a and the outer portion may be defined by cross-sectional portion 506b, as shown in Figures 5A-5C.

[0130] At block 1204, the method 1200 includes exposing the backside of the semiconductor substrate to process conditions that cause one or more layers to deposit on the backside of the semiconductor substrate. In some embodiments, the process conditions include exposure to a chemical precursor of at least one of the one or more layers. For example, a silicon-containing reactant, a nitrogen-containing reactant, or an oxygen-containing co-reactant may be used as a chemical precursor. In some embodiments, at least one of the one or more layers on the backside of the semiconductor substrate includes polysilicon, silicon oxide, silicon nitride, or any combination thereof. In some implementations, the layers may be deposited or stacked in an alternating manner, for example, in alternating silicon oxide and silicon nitride layers. Other examples of chemical precursors and stacking materials are listed elsewhere herein.

[0131] In some implementations, the controller (e.g., 120) is part of a system, which may be part of the examples described above, including a process chamber or another system including an ESC. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.) for processing. These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as a "controller," which may control various components or sub-portions of one or more systems. The controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected to or interfaced with a particular system, depending on the processing requirements and / or type of system.

[0132] In general, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and the like. Integrated circuits may include firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or chips in the form of one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during processing of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0133] The controller, in some implementations, may be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or in all or part of a fab host computer system that may enable remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a processing operation, examine the history of past processing operations, and examine trends or performance metrics from multiple processing operations in order to change parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network that may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool the controller is configured to interface with or control. Thus, as described above, the controller may be distributed, such as by having one or more individual controllers networked together and functioning toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes would be one or more integrated circuits on the chamber in communication with one or more remotely located integrated circuits (such as at the platform level or as part of a remote computer) that are combined to control the process on the chamber.

[0134] Without being limited thereto, exemplary systems may include a plasma etch chamber or module, a deposition chamber or module, a spin clean chamber or module, a metal plating chamber or module, a clean chamber or module, a chamfer edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be related to or used in the processing and / or manufacturing of semiconductor wafers.

[0135] As described above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transfers carrying containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0136] Systems and methods are provided herein that provide improved chucking or clamping capabilities over conventional systems. The methods, apparatus, and systems described above allow for flexible use of various clamping modes (e.g., bipolar and / or monopolar) compared to conventional systems, and they do so while using modifications to existing technology. As a result, embodiments of improved chucking systems herein include configurations involving one or more power sources.

[0137] Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other implementations without departing from the spirit or scope of the disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with the disclosure, the principles and novel features disclosed herein.

[0138] Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable subcombination. Moreover, although features may be described above as working in some combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0139] Similarly, although operations are shown in the figures in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the shown operations be performed, to achieve desirable results. Additionally, the figures may depict one or more exemplary processes generally in the form of a flow diagram. However, other operations not shown may be incorporated into the illustrative process depicted generally. For example, one or more additional operations may be performed before, after, or after any of the depicted operations. AndThe various system components may be implemented simultaneously or in between. In some situations, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the program components and systems described may generally be integrated together in a single software product or packaged in multiple software products. Moreover, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve desirable results. The present invention can be realized, for example, in the following manner. Application example 1: 1. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner circumference with a first diameter of about 298.4 to 299.5 millimeters (mm); a plurality of inwardly extending tabs disposed about the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0 to 298.5 mm; A carrier ring equipped with Application example 2: The carrier ring according to Application Example 1, the first diameter of the inner portion of the ring is about 299.0 mm; the second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm; Career ring. Application example 3: 2. The carrier ring according to claim 1, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs. Application example 4: 2. The carrier ring according to claim 1, wherein at least one of the plurality of inwardly extending tabs has a width of about 0.5 to 1.5 mm. Application example 5: A carrier ring as described in application example 4, wherein the width of the at least one of the plurality of inwardly extending tabs is approximately 1.0 mm. Application example 6: A carrier ring as described in Application Example 1, wherein at least one of the plurality of inwardly extending tabs has at least a portion of an upper surface that has an angle that is neither parallel nor perpendicular to the plane. Example 7: A carrier ring according to application example 6, wherein the angle of the portion of the upper surface is between about 5 and 20 degrees with respect to the plane. Application example 8: A carrier ring as described in Application Example 6, wherein the upper surface of at least one of the multiple inwardly extending tabs has a minimum contact area (MCA) configured to make physical contact with the semiconductor substrate. Example 9: The carrier ring according to application example 1, wherein the outer portion is about 0.3 to 0.7 mm thick, and the inner portion is about 0.1 to 0.5 mm thick. Example 10: A carrier ring as described in Application Example 1, wherein at least a portion of the multiple inwardly extending tabs arranged around the inner circumference of the inner portion of the ring are configured to form one or more conductive ground points on the semiconductor substrate. Example 11: 1. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring having an inner portion configured to support the semiconductor substrate during backside deposition on the semiconductor substrate, the ring defining a plane; between 8 and 15 inwardly extending tabs disposed about the inner portion of the ring and configured to contact the semiconductor substrate during the backside deposition on the semiconductor substrate; Equipped with A carrier ring, wherein at least one of the 8-15 inwardly extending tabs has a width of about 0.5-1.5 mm. Example 12: A carrier ring as described in Application Example 11, wherein the at least one of the 8 to 15 inwardly extending tabs has an upper surface that has an angle of about 15 degrees or less with respect to the plane. Application example 13: 12. The carrier ring of claim 11, wherein the 8 to 15 inwardly extending tabs have an inner edge defining a first diameter of about 296.0 to 298.5 mm. the 8-15 inwardly extending tabs have an outer edge attached to the ring and defining a second diameter of about 298.4-299.5 mm; Career ring. Example 14: A carrier ring as described in Application Example 11, wherein at least a portion of the 8 to 15 inwardly extending tabs are configured to enable formation of one or more conductive ground points on the semiconductor substrate. Example 15: 1. A method for depositing one or more layers on a backside of a semiconductor substrate, the method comprising: (a) supporting the semiconductor substrate on a carrier ring, the carrier ring comprising: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner circumference with a first diameter of about 298.4 to 299.5 millimeters (mm); a plurality of inwardly extending tabs disposed about the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0 to 298.5 mm; supporting the semiconductor substrate on a carrier ring; (b) exposing the backside of the semiconductor substrate to process conditions that cause the one or more layers to deposit on the backside of the semiconductor substrate; A method comprising: Application example 16: The method of application example 15, wherein the process conditions that cause the one or more layers to deposit include exposure to a chemical precursor of at least one of the one or more layers. Example 17: The method of application example 15, wherein at least one of the one or more layers on the back side of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof. Application example 18: The method according to Application Example 15, the first diameter of the inner portion of the ring is about 299.0 mm; the second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm; method. Example 19: 16. The method of claim 15, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs, and at least one of the at least eight inwardly extending tabs has a width of about 0.5 to 1.5 mm. Example 20: The method of claim 15, wherein at least one of the plurality of inwardly extending tabs has at least a portion of an upper surface that is angled relative to the plane other than parallel and other than perpendicular, the angle being between about 5 and 20 degrees relative to the plane.

Claims

1. 1. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner circumference with a first diameter of about 298.4 to 299.5 millimeters (mm); a plurality of inwardly extending tabs disposed about the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0-298.5 mm; A carrier ring equipped with

2. 2. The carrier ring of claim 1, the first diameter of the inner portion of the ring is about 299.0 mm; the second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm; Career ring.

3. The carrier ring of claim 1 , wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs.

4. The carrier ring of claim 1 , wherein at least one of the plurality of inwardly extending tabs has a width of about 0.5 to 1.5 mm.

5. 5. The carrier ring of claim 4, wherein the width of the at least one of the plurality of inwardly extending tabs is approximately 1.0 mm.

6. 2. The carrier ring of claim 1, wherein at least one of said plurality of inwardly extending tabs comprises at least a portion of an upper surface that is at an angle other than parallel or perpendicular to said plane.

7. 7. The carrier ring of claim 6, wherein the angle of the portion of the top surface is between about 5 and 20 degrees with respect to the plane.

8. 7. The carrier ring of claim 6, wherein the top surface of the at least one of the plurality of inwardly extending tabs comprises a minimum contact area (MCA) configured to make physical contact with the semiconductor substrate.

9. 10. The carrier ring of claim 1, wherein the outer portion is about 0.3-0.7 mm thick and the inner portion is about 0.1-0.5 mm thick.

10. 2. The carrier ring of claim 1, wherein at least a portion of the plurality of inwardly extending tabs disposed about the inner circumference of the inner portion of the ring are configured to form one or more conductive ground points on the semiconductor substrate.

11. 1. A carrier ring configured to support a semiconductor substrate, the carrier ring comprising: a ring having an inner portion configured to support the semiconductor substrate during backside deposition on the semiconductor substrate, the ring defining a plane; between 8 and 15 inwardly extending tabs disposed about the inner portion of the ring and configured to contact the semiconductor substrate during the backside deposition on the semiconductor substrate; Equipped with At least one of the 8-15 inwardly extending tabs has a width of about 0.5-1.5 mm.

12. 12. The carrier ring of claim 11, wherein said at least one of said 8 to 15 inwardly extending tabs comprises an upper surface having an angle of about 15 degrees or less with respect to said plane.

13. 12. The carrier ring of claim 11, wherein the 8-15 inwardly extending tabs have an inner edge defining a first diameter of about 296.0-298.5 mm; the 8-15 inwardly extending tabs have an outer edge attached to the ring and defining a second diameter of about 298.4-299.5 mm; Career ring.

14. 12. The carrier ring of claim 11, wherein at least a portion of the 8-15 inwardly extending tabs are configured to enable formation of one or more conductive ground points on the semiconductor substrate.

15. 1. A method for depositing one or more layers on a backside of a semiconductor substrate, the method comprising: (a) supporting the semiconductor substrate on a carrier ring, the carrier ring comprising: a ring having an outer portion and an inner portion and defining a plane, the inner portion having an inner circumference with a first diameter of about 298.4 to 299.5 millimeters (mm); a plurality of inwardly extending tabs disposed about the inner circumference of the inner portion of the ring, the plurality of inwardly extending tabs having an inner edge defining a circle having a second diameter of about 296.0-298.5 mm; supporting the semiconductor substrate on a carrier ring; (b) exposing the backside of the semiconductor substrate to process conditions that cause the one or more layers to deposit on the backside of the semiconductor substrate; A method comprising:

16. 16. The method of claim 15, wherein the process conditions that cause the one or more layers to deposit include exposure to a chemical precursor of at least one of the one or more layers.

17. 16. The method of claim 15, wherein at least one of the one or more layers on the backside of the semiconductor substrate comprises polysilicon, silicon oxide, silicon nitride, or any combination thereof.

18. 16. The method of claim 15, the first diameter of the inner portion of the ring is about 299.0 mm; the second diameter of the plurality of inwardly extending tabs is approximately 297.0 mm; method.

19. 16. The method of claim 15, wherein the plurality of inwardly extending tabs comprises at least eight inwardly extending tabs, and at least one of the at least eight inwardly extending tabs has a width of about 0.5-1.5 mm.

20. 16. The method of claim 15, wherein at least one of the plurality of inwardly extending tabs comprises at least a portion of an upper surface that has an angle with respect to the plane that is neither parallel nor perpendicular, the angle being between about 5 and 20 degrees with respect to the plane.

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