Alignment unit capacitor having a plurality of metal layers

Abstract

The capacitor device includes a semiconductor substrate and a plurality of metal layers above the substrate. The first metal layer has a first plurality of lower terminals elongated in a first direction and a first plurality of upper terminals that are electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals. The second metal layer between the semiconductor substrate and the first metal layer has a second plurality of lower terminals elongated in the first direction and a second plurality of upper terminals that are electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims priority and the benefit thereof to U.S. Patent Application No. 17 / 740465, filed on May 10, 2022. The disclosure of the same application is incorporated herein by reference as if fully set forth below and for all applicable purposes.

[0002]

[0002] This application relates to semiconductor devices, systems, and methods, and more particularly to capacitor devices, systems, and methods.

[0003] Introduction

[0003] Capacitors are elements widely used in semiconductor devices to store charge. A parallel - plate capacitor can include two conductive plates separated by an insulator. In the case of a parallel - plate capacitor, the capacitance, or the amount of charge held by the capacitor per applied voltage, depends on several parameters such as the area of the plates, the distance between the plates, and the relative permittivity of the insulator between the plates (also called the "dielectric constant"). Capacitors can be used in filters, power supplies, analog - to - digital converters, memory devices, control applications, and many other types of semiconductor devices.

[0004]

[0004] In some semiconductor devices, such as successive approximation register (SAR) analog - to - digital converters (ADCs), capacitor arrays are used. In such applications, good matching between capacitors is desired to improve performance. The matching requirements can be hampered by unwanted parasitic capacitance and other mismatches. Furthermore, in devices that require a large number of capacitors, the capacitors can use a significant area of the semiconductor. Therefore, improved matched capacitor devices are needed.

Summary of the Invention

[0005]

[0005] In the following, in order to provide a basic understanding of the technology under discussion, some aspects of the present disclosure will be summarized. This summary is not an extensive overview of all conceivable features of the present disclosure, nor is it intended to identify the main or critical elements of all aspects of the present disclosure, or to delineate the scope of any or all aspects of the present disclosure. Its sole purpose is to present, in summary form, some concepts of one or more aspects of the present disclosure as an introduction to the more detailed description presented later.

[0006]

[0006] One aspect of the present disclosure includes a capacitor structure including a semiconductor substrate. The capacitor structure further includes a first metal layer above the semiconductor substrate, and the first metal layer has a first plurality of lower terminals elongated in a first direction and a first plurality of upper terminals electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals. The capacitor structure further includes a second metal layer between the semiconductor substrate and the first metal layer, and the second metal layer has a second plurality of lower terminals elongated in the first direction and a second plurality of upper terminals electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals.

[0007]

[0007] Another aspect of the present disclosure includes an analog-to-digital converter (ADC) including a comparator, a semiconductor substrate, and a plurality of unit capacitors electrically coupled to the comparator. The plurality of unit capacitors includes a first metal layer above the semiconductor substrate, and the first metal layer has a first plurality of lower terminals elongated in a first direction and a first plurality of upper terminals electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals. The ADC further includes a second metal layer between the semiconductor substrate and the first metal layer, and the second metal layer has a second plurality of lower terminals elongated in the first direction and a second plurality of upper terminals electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals.

[0008]

[0008] Another aspect of the present disclosure is a method for manufacturing a capacitor structure, including forming a first metal layer above a semiconductor substrate, the first metal layer having a first plurality of lower terminals elongated in a first direction and a first plurality of upper terminals that are electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals. The method further includes forming a second metal layer above the first metal layer, the second metal layer having a second plurality of lower terminals elongated in the first direction and a second plurality of upper terminals that are electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals.

[0009]

[0009] Another aspect of the present disclosure includes a capacitor structure including a semiconductor substrate and a first metal layer above the semiconductor substrate, the first metal layer having a first plurality of lower terminals elongated in a first direction. The capacitor structure further includes a second metal layer above the first metal layer, the second metal layer having a first plurality of upper terminals elongated in the first direction and directly above the first plurality of lower terminals, and a second plurality of lower terminals elongated in the first direction and arranged alternately with the first plurality of upper terminals. The capacitor structure further includes a third metal layer above the second metal layer, the third metal layer having a second plurality of upper terminals elongated in the first direction and directly above the first plurality of upper terminals, and a third plurality of lower terminals elongated in the first direction and arranged alternately with the second plurality of upper terminals. The capacitor structure further includes a fourth metal layer above the third metal layer, the fourth metal layer having a fourth plurality of lower terminals elongated in the first direction and directly above the second plurality of upper terminals. The capacitor structure further includes a fifth metal layer above the fourth metal layer, the fifth metal layer having a third plurality of upper terminals elongated in the first direction and directly above the fourth plurality of lower terminals, and a fifth plurality of lower terminals elongated in the first direction and arranged alternately with the third plurality of upper terminals.

[0010]

[0010] Other aspects, features, and embodiments will become apparent to those of ordinary skill in the art upon consideration of the following description of specific exemplary aspects in conjunction with the accompanying figures. Although features may be discussed with respect to some of the following aspects and figures, all aspects may include one or more of the advantageous features discussed herein. In other words, one or more aspects may be discussed as having certain advantageous features, but one or more of such features may also be used in accordance with the various aspects discussed herein. In a similar manner, exemplary aspects may be described below as aspects of a device, system, or method, but it should be understood that such exemplary aspects may be implemented in various devices, systems, and methods.

Brief Description of the Drawings

[0011]

Figure 1

[0011] A perspective view of an exemplary capacitor structure according to some aspects of the present disclosure.

Figure 2

[0012] A cross-sectional view of an exemplary capacitor structure according to some aspects of the present disclosure.

Figure 3

[0013] A top view of an exemplary capacitor structure according to some aspects of the present disclosure.

Figure 4

[0014] A flowchart showing an exemplary method for forming a capacitor structure according to some aspects of the present disclosure.

Figure 5

[0015] A flowchart showing an exemplary method for forming a capacitor structure according to some aspects of the present disclosure.

Modes for Carrying Out the Invention

[0012]

[0016] In connection with the accompanying drawings, the "Modes for Carrying Out the Invention" described below are intended as descriptions of various configurations and are not intended to represent the only configurations capable of practicing the concepts described herein. The "Modes for Carrying Out the Invention" include specific details aimed at providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some aspects, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0013]

[0017] Various other aspects and features of the present disclosure are further described below. It will be apparent that the teachings of this specification can be embodied in many diverse forms and that any specific structure, function, or both disclosed herein are merely representative and not limiting. Based on the teachings of this specification, those skilled in the art will understand that one aspect disclosed herein can be implemented independently of any other aspect, and that two or more of these aspects can be combined in various ways. For example, any number of the aspects described herein can be used to implement an apparatus or practice a method. In addition, in addition to or in lieu of one or more of the aspects described herein, other structures, functions, or structures and functions can be used to implement such an apparatus or practice such a method. For example, a method can be implemented as part of a system, device, apparatus, and / or as instructions stored on a computer-readable medium for execution on a processor or computer. Further, one aspect can comprise at least one element of a claim.

[0014]

[0018] The present disclosure generally relates to matching unit capacitors by using multiple metal layers. Tightly matched pairs or groups of capacitors have very close capacitance values, e.g., with capacitance variations of less than 1%. In various aspects, the techniques and apparatus can be used for successive approximation register analog-to-digital converters (SAR ADCs). In many SAR ADCs and other devices, an array of capacitors is used and the performance of the device depends on the matching between the capacitors. For example, mismatches in parasitic capacitance between capacitors in the array can degrade the accuracy of the ADC.

[0015]

[0019] In a typical capacitor design, only a single metal layer with interleaved metal fingers is utilized to create the capacitor structure. The internal metal layer is filled with a pattern of floating (not electrically connected to either terminal of the capacitor) metal to maintain a flat structure. Without the metal fill pattern, the silicon device may warp or deform, causing problems including capacitor mismatches. However, the presence of the floating metal fill pattern also contributes to mismatches between capacitors because the parasitic capacitance between the nodes of the capacitor device and the metal fill pattern can introduce mismatches across the capacitors.

[0016]

[0020] To mitigate these effects, instead of an unconnected metal fill layer, the internal metal layer can include additional fingers electrically connected to the capacitor's nodes. The characteristics of the internal fingers can include layers in which the fingers extend in an undesirable direction, based on the device's structure or manufacturing process. Elongated fingers in an undesirable direction (the Z direction in this example) can be wider than the fingers in other metal layers and can have a wider spacing between the fingers. The wider spacing may require that the fingers only include one of the two nodes of the capacitor. Additionally, due to the parasitic capacitance to the semiconductor substrate, problems including capacitor mismatches can occur. To mitigate this effect, the lower metal layer closest to the substrate can include only fingers for the "lower" capacitor node that can be used to shield the "upper" capacitor node in the next metal layer. The terms "upper" and "lower" are used to distinguish the two terminals of the capacitor structure described herein. However, it should be understood that the labels "upper" and "lower" are interchangeable when applied to the terminals. For example, referring to electrical terminals as "upper" and "lower" has come from several years ago when capacitors were metal sheets placed on two different layers. In a physical structure such as that described in FIGS. 1-3, there is always a terminal at the "lower" (closest to the substrate) of the structure. However, the upper (furthest from the substrate) of the structure has connections to both the "upper" and "lower" terminals. In other words, when applied to the terminals, "upper" and "lower" are not limited to a directional relationship. Rather, it is a way to distinguish one capacitor terminal from the other.

[0017]

[0021] One aspect of an embodiment is that, as described in more detail below, the "lower" terminal shields the "upper" terminal from the substrate at the lower part of the structure, thereby reducing the parasitics of the "upper" terminal to the substrate by trading off (increasing) the parasitics of the "lower" terminal to the substrate. This architecture can also increase the capacitor density.

[0018]

[0022] The systems and methods described herein provide numerous advantages. By using an internal metal layer, it is possible for a capacitor device to occupy less area of a semiconductor device, enabling more capacitors within an array to fit within the same area. Further, the absence of a floating metal fill pattern reduces parasitic capacitance and further improves capacitor matching. Shielding the "upper" node from the substrate by using the inserted "lower" node can reduce the parasitic capacitance to the substrate and further improve other performance metrics such as capacitor matching and dynamic range. These advantages can enable a device such as a SAR ADC to use a smaller footprint and / or generate more accurate measurements.

[0019]

[0023] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" can also be used herein to mean electrically connecting element A and element B (and any components electrically connected therebetween) using a wire, trace, or other conductive material.

[0020]

[0024] In the following description, certain terms may be used for reference purposes only and are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below", "bottom", and "top" refer to directions in the referenced drawings. Terms such as "front", "back", "rear", and "side" describe the orientation and / or position of portions of the component in question with respect to a consistent but arbitrary reference system, as made clear by reference to the text describing the component under discussion and the associated drawings. Such terms may include those specifically mentioned above, derivatives thereof, and words of similar meaning.

[0021]

[0025] FIG. 1 is a perspective view of an exemplary capacitor structure 100 according to some aspects of the present disclosure. The metal layers are identified as M1, M2, M3, M4, and M5, with M1 being closest to the substrate (not shown). The metal layers themselves may be separated from each other and from the substrate having an insulating material (not shown). Capacitor symbols indicate locations where significant capacitance exists between metal fingers. Capacitor nodes / terminals are labeled "upper" and "lower". In some aspects, the "upper" terminals are interconnected and the "lower" terminals are connected independently to the rest of the circuit, although multiple lower terminals may be connected to each other to form a larger capacitor. The upper terminals can be interconnected by a metal strip 260 extending in a second direction perpendicular to the fingers as shown, and connections to other metal layers are achieved by vias 290 that can be located at the junctions as shown. The structure shown in FIG. 1 may be a repeating structure and only a portion thereof is shown. FIGS. 2 - 3 show substantially the same structure as FIG. 1 but from different viewpoints and show different starting positions and numbers of repetitions of the repeating structure.

[0022]

[0026] Layer M1 includes lower terminal fingers 210 that extend in a first direction (the Z direction as shown). Layer M2 has lower terminal fingers 220 that are alternately arranged with upper terminal fingers 225. The upper terminal fingers 225 are located above the lower terminal fingers 210, such that the terminal fingers 225 are shielded from the substrate to minimize the parasitic capacitance between the upper terminals 225 and the substrate. Layer M3 includes lower terminals 230 that are alternately arranged with upper terminals 235 and are arranged substantially the same as layer M2.

[0023]

[0027] Layer M4 includes lower terminal fingers 240. In some embodiments, the lower terminal fingers 240 extend in a first direction (the Z direction as shown) that is an unfavorable direction for layer M4. In this example, favorable and unfavorable can be defined by the foundry. For example, the foundry can specify that the metal structures in layer M5 and layer M4 should be perpendicular, such that if layer M5 has a metal structure with a dominant Z - direction axis, M4 should have a dominant Y - direction axis. In this case, the metals in both layer M4 and layer M5 are laid out in the Z direction, which violates such rules.

[0024]

[0028] The example in FIG. 2 attempts to mitigate the rule violation by making the lower terminal fingers 240 wider than the metal fingers in other metal layers. Further, when using an unfavorable direction, the spacing between the metal fingers on layer M4 can be increased. To provide sufficient spacing, no upper terminal fingers are formed on layer M4, and only the lower terminal fingers 240 with sufficient spacing are left. The lower terminal fingers 240 may be formed on top of the upper terminal fingers 235 to enable capacitance between the terminals. Of course, the examples given in this specification of foundry rules for layer M4 and layer M5 are merely examples, and different foundry rules may be applied to different layers. It is understood that if one of the layers other than M4 adopts an unfavorable direction, the width and spacing of its metal structure may be adapted in the same way as shown in FIG. 2 and for M4.

[0025]

[0029] Layer M5 includes lower terminal fingers 250 arranged alternately with upper terminal fingers 255. The upper terminal fingers 255 can be formed on top of the lower terminal fingers 240, enabling capacitance between the terminals.

[0026]

[0030] The capacitor structure shown in FIG. 1 is exemplary, and other similar capacitor structures can be realized. For example, a semiconductor process having more metal layers (e.g., 7 or 11 metal layers) may be used. A similar configuration of upper and lower terminal fingers can be utilized across the metal layers to provide unit capacitors without the need for floating metal fill patterns. Additionally, capacitors formed using other numbers of metal layers may have other layers or additional layers where the fingers extend in an unfavorable direction. In this case, the plurality of layers may be formed with a larger spacing and a larger finger width on top of the layer where the fingers extend in an unfavorable direction.

[0027]

[0031] FIG. 2 is a cross-sectional view of an exemplary capacitor structure 200 according to some aspects of the present disclosure. The capacitor structure is the same as that in FIG. 1, but shows different parts of the repetitive structure and is shown from different viewpoints to clarify the arrangement of the upper and lower terminal fingers. Additionally, the substrate 280 is shown below the metal layers.

[0028]

[0032] As shown, there is capacitance between a plurality of lower terminal fingers and a plurality of upper terminal fingers. In some embodiments, the lower terminal fingers are interconnected in a group including at least two vertical columns of fingers. For example, the lower terminal fingers 250, 230, and 220 of the first column, and the lower terminal fingers 240 and 210 of the second column can be interconnected by vias (shown as via 290 in FIG. 3) and connecting metal, such that together with the adjacent upper terminal fingers 255, 235, and 225, they form a capacitor. In this example, there are six main capacitances that form a capacitor. The first is the capacitance 271 between the lower terminal finger 250 and the upper terminal finger 255, the second is the capacitance 272 between the lower terminal finger 240 and the upper terminal finger 255, the third is the capacitance 273 between the lower terminal finger 240 and the upper terminal finger 235, the fourth is the capacitance 274 between the lower terminal finger 230 and the upper terminal finger 235, the fifth is the capacitance 275 between the lower terminal finger 220 and the upper terminal finger 225, and the sixth is the capacitance 276 between the lower terminal finger 210 and the upper terminal finger 225.

[0029]

[0033] In some embodiments, these six capacitances together form a single unit capacitor. The unit capacitors can be connected to each other to form a larger capacitor. For example, unit capacitors can form capacitors of sizes such as 2, 4, 8, etc. In applications such as SAR DACs, such groups of unit capacitors can be utilized. In the illustrated example, each lower terminal finger 250 is positioned between two upper terminal fingers 255. Thus, the unit capacitors as described above may be paired, and the minimum capacitor size is 2 unit capacitors (2Cu). In some embodiments, a unit capacitor can also refer to a single pair of an upper terminal finger and a lower terminal finger.

[0030]

[0034] Figure 3 is a top view of an exemplary capacitor structure 300 according to some aspects of the present disclosure. The capacitor structure is the same as in FIGS. 1 and 2, but shows different portions of the repeating structure and emphasizes the elongated fingers from a different perspective. This perspective also shows the vias 290 that connect the lower terminals across the metal layers. The "jogs" 295 within the metal layers connect the lower terminal fingers 250 to the vias 290, enabling these two vertical columns to be connected to form unit capacitors as described above with reference to FIG. 1. Further, although the portion of metal layer M1 that includes finger 210 is hidden from view by finger 240 in the top view of FIG. 3, it is understood that finger 210 is also electrically coupled to the vias 290. Thus, the upper terminal fingers are electrically coupled to each other by the metal strap 260, and the lower terminal fingers are electrically coupled to each other by the vias 290 and the jogs 295.

[0031]

[0035] The number of unit capacitors that can be formed using the capacitor structure 300 of FIG. 3 is variable. For example, the leftmost jog 295 may remain uncoupled from other similar jogs 295, and those jogs 295 may also not be coupled to each other. Thus, the leftmost jog 295 by itself provides a single unit capacitor. The leftmost jog 295 may be coupled to the adjacent next jog 295, thereby providing two unit capacitors. The electrical coupling can be further extended in the right direction, so that three consecutive jogs 295 are coupled to each other from left to right, thereby providing three unit capacitors. By extending the electrical coupling in the right direction in this way, the number of unit capacitors provided by the capacitor structure 300 can be increased. The designer can select the number of unit capacitors suitable for a given application.

[0032]

[0036] FIG. 4 is a flowchart showing an exemplary method 400 for forming a capacitor structure according to some aspects of the present disclosure. The structure may be, for example, the capacitor structures 100-300 described with reference to FIGS. 1-3. As shown, method 400 includes several enumerated blocks, although aspects of method 400 can include additional blocks before, after, and between the enumerated blocks. In some aspects, one or more of the enumerated blocks can be omitted or performed in a different order.

[0033]

[0037] In block 405, a first metal layer is formed over a semiconductor substrate (e.g., substrate 280 of FIG. 2), the first metal layer having a first plurality of lower terminals elongated in a first direction and a first plurality of upper terminals electrically coupled to each other, elongated in the first direction, and alternating with the first plurality of lower terminals. For example, the first metal layer can be layer M3 of the capacitor structure described with reference to FIGS. 1-3.

[0034]

[0038] The metal layer formation in FIG. 4 (similarly in FIG. 5) can include any suitable semiconductor processing technique. For example, a layer of insulator can be formed over the substrate. A given insulator layer can be patterned, and the process can further include depositing metal over the patterned insulator layer. The metals of metal layers M1-M5 in FIG. 2 can be formed by deposition over a patterned insulator layer. Once the metal is deposited, the process can further include disposing an additional insulator layer over the patterned insulator layer and the metal layer. Thereafter, appropriate operations such as patterning the additional insulator layer and depositing an additional metal layer can be repeated. As described above, an example of the first metal layer can include M3 above M2 and below M4 and can be formed as described above. In the example of FIG. 2, layer M1 can be formed first, M2 second, then M3, then M4, then M5. Of course, the scope of implementation is not limited to any semiconductor processing technique.

[0035]

[0039] In block 410, a second metal layer is formed above the first metal layer. The second metal layer has a plurality of second lower terminals elongated in a first direction, and a plurality of second upper terminals that are electrically coupled to each other and to the plurality of first upper terminals, are elongated in the first direction, and are alternately arranged with the plurality of second lower terminals. For example, the second metal layer can be layer M5 of the capacitor structure described with reference to FIGS. 1-3.

[0036]

[0040] FIG. 5 is a flowchart showing an exemplary method 500 for forming a capacitor structure according to some aspects of the present disclosure. This structure can be, for example, capacitor structures 100-300 described with reference to FIGS. 1-3. As shown, method 500 includes several enumerated blocks, but aspects of method 500 can include additional blocks before, after, and between the enumerated blocks. In some aspects, one or more of the enumerated blocks may be omitted or executed in a different order.

[0037]

[0041] In block 505, a first metal layer is formed above a semiconductor substrate. The first metal layer has a plurality of first lower terminals elongated in a first direction. For example, the first metal layer can be layer M1 of the capacitor structure described with reference to FIGS. 1-3.

[0038]

[0042] In block 510, a second metal layer is formed above the first metal layer. The second metal layer has a plurality of first upper terminals elongated in a first direction and directly above the plurality of first lower terminals, and a plurality of second lower terminals elongated in the first direction and alternately arranged with the plurality of first upper terminals. For example, the second metal layer can be layer M2 of the capacitor structure described with reference to FIGS. 1-3. The plurality of first upper terminals can be located directly above the plurality of first lower terminals such that the plurality of first lower terminals shield the plurality of first upper terminals from the substrate.

[0039]

[0043] In block 515, a third metal layer is formed above the second metal layer. The third metal layer is elongated in a first direction and has a second plurality of upper terminals directly above the first plurality of upper terminals, and a third plurality of lower terminals that are elongated in the first direction and are alternately arranged with the second plurality of upper terminals. For example, the third metal layer can be layer M3 of the capacitor structure described with reference to FIGS. 1 to 3.

[0040]

[0044] In block 520, a fourth metal layer is formed above the third metal layer. The fourth metal layer is elongated in a first direction and has a fourth plurality of lower terminals directly above the second plurality of upper terminals. For example, the fourth metal layer can be layer M4 of the capacitor structure described with reference to FIGS. 1 to 3. In some embodiments, the first direction is an unfavorable direction in the fourth metal layer. The fourth plurality of lower terminals can be formed wider than the fingers of other metal layers in a second direction (the X direction shown in FIGS. 1 to 3) perpendicular to the first direction. Additionally, the metal fingers may be further spaced apart in the fourth metal layer.

[0041]

[0045] In block 525, a fifth metal layer is formed above the fourth metal layer. The fifth metal layer is elongated in a first direction and has a third plurality of upper terminals directly above the fourth plurality of lower terminals, and a fifth plurality of lower terminals that are elongated in the first direction and are alternately arranged with the third plurality of upper terminals. For example, the fifth metal layer can be layer M5 of the capacitor structure described with reference to FIGS. 1 to 3.

[0042]

[0046] As described above, the capacitor structure described in this specification can be used with various different circuits. For example, due to the improved consistency and manufacturability of the capacitor structure, among other circuits, this capacitor structure can be adopted in some analog-to-digital converters (ADCs) in particular. For example, an array of unit capacitors can be used to generate a voltage that is an input to a comparator of an ADC. The comparator of the ADC can compare the voltage generated using the array of unit capacitors with the voltage being measured. In one example, transistors can be formed in an active layer on a substrate (e.g., substrate 280 of FIG. 2), and those transistors can form a logic and power circuit for a given application (e.g., an ADC). The capacitor can be coupled to the transistors using vias or any other desired technique. For example, a via (not shown) can couple the source or drain of a first transistor in the active layer below M1 to an upper finger in one of the metal layers (e.g., M2), and another via (not shown) can couple the source or drain of a second transistor in the active layer to a lower finger in another one of the metal layers (e.g., M5). Next, the transistors can be turned on or off to appropriately direct the current through the capacitor structure. The scope of the embodiments is not limited to use in an ADC or in any particular device. For example, the capacitor structure described in this specification can be used in user equipment (e.g., smartphones, tablets, Internet-of-things devices, etc.), in an electrical communication network base station, or in any other suitable device.

[0043]

[0047] Further aspects of the present disclosure include the following.

[0044] Aspect 1. A capacitor structure comprising: a semiconductor substrate and a first metal layer above the semiconductor substrate, the first metal layer comprising: a first plurality of lower terminals elongated in a first direction; and a first plurality of upper terminals electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals. A first metal layer having A second metal layer between the semiconductor substrate and the first metal layer, A second plurality of lower terminals elongated in a first direction, Electrically coupled to each other and to a first plurality of upper terminals, the second plurality of upper terminals being elongated in the first direction and arranged alternately with the second plurality of lower terminals, A second metal layer having A capacitor structure comprising.

[0045] Aspect 2. A third metal layer between the first metal layer and the second metal layer, the third metal layer having a third plurality of lower terminals elongated in a first direction, Further comprising Each of the third plurality of lower terminals is disposed between the semiconductor substrate and each of the terminals of the first plurality of upper terminals, Each of the first plurality of lower terminals has a first width in a second direction perpendicular to the first direction, each of the third plurality of lower terminals has a second width in the second direction, and the second width is greater than the first width, The capacitor structure according to aspect 1.

[0046] Aspect 3. The first distance in the second direction between the respective lower terminals of the third plurality of lower terminals is greater than the second distance in the second direction between the upper terminals of the first plurality of upper terminals and the lower terminals of the first plurality of lower terminals. The capacitor structure according to aspect 2.

[0047] Aspect 4. The first plurality of lower terminals and the second plurality of lower terminals are electrically coupled to form a plurality of groups of unit capacitors. The capacitor structure according to any one of aspects 1 to 3.

[0048] Aspect 5. The capacitor structure according to aspect 4, further comprising a plurality of vias connecting the first plurality of lower terminals to the second plurality of lower terminals in the plurality of groups of unit capacitors.

[0049] Aspect 6. A third metal layer disposed between the semiconductor substrate and the second metal layer, a plurality of third lower terminals elongated in a first direction, electrically coupled to each other and to a first plurality of upper terminals, the plurality of third upper terminals being elongated in the first direction and arranged alternately with the plurality of third lower terminals, and having a third metal layer; a fourth metal layer between the semiconductor substrate and the third metal layer, a plurality of fourth lower terminals elongated in a first direction, each of the plurality of fourth lower terminals being disposed between the semiconductor substrate and one of the plurality of third upper terminals, and having a fourth metal layer; The capacitor structure according to any one of Aspects 1 to 5, further comprising.

[0050] Aspect 7. The capacitor structure according to any one of Aspects 1 to 6, further comprising a plurality of vias connecting the first plurality of upper terminals to the second plurality of upper terminals.

[0051] Aspect 8. A metal strip on the first metal layer, elongated in a second direction perpendicular to the first direction, further comprising, the first plurality of upper terminals being electrically coupled to each other by the metal strip. The capacitor structure according to any one of Aspects 1 to 7.

[0052] Aspect 9. The capacitor structure according to any one of Aspects 1 to 8, wherein the volume between the substrate and the first plurality of lower terminals does not contain electrically floating metal.

[0053] Aspect 10. An analog-to-digital converter (ADC), a comparator, a semiconductor substrate, a plurality of unit capacitors electrically coupled to the comparator, the plurality of unit capacitors being a first metal layer above the semiconductor substrate, A plurality of first lower terminals elongated in a first direction, electrically coupled to each other, a plurality of first upper terminals elongated in the first direction and arranged alternately with the plurality of first lower terminals, and a first metal layer having the same; A second metal layer between the semiconductor substrate and the first metal layer, comprising a plurality of second lower terminals elongated in the first direction, electrically coupled to each other and to the plurality of first upper terminals, and a plurality of second upper terminals elongated in the first direction and arranged alternately with the plurality of second lower terminals, and a second metal layer having the same; a plurality of unit capacitors provided therewith; and an ADC provided therewith.

[0054] Aspect 11. The plurality of unit capacitors further comprise a third metal layer between the first metal layer and the second metal layer, having a plurality of third lower terminals elongated in the first direction, each of the plurality of third lower terminals being disposed between the semiconductor substrate and each respective terminal of the plurality of first upper terminals, each of the plurality of first lower terminals having a first width in a second direction perpendicular to the first direction, each of the plurality of third lower terminals having a second width in the second direction, the second width being greater than the first width, and the ADC according to Aspect 10.

[0055] Aspect 12. The ADC according to Aspect 11, wherein a first distance in the second direction between each respective lower terminal of the plurality of third lower terminals is greater than a second distance in the second direction between an upper terminal of the plurality of first upper terminals and a lower terminal of the plurality of first lower terminals.

[0056] Aspect 13. The ADC according to any one of Aspects 10 to 12, wherein the plurality of first lower terminals and the plurality of second lower terminals are electrically coupled to form a plurality of groups of unit capacitors.

[0057] ​Aspect 14. The ADC according to any one of Aspects 10 to 13, wherein the plurality of unit capacitors further includes a plurality of vias connecting the first plurality of lower terminals to the second plurality of lower terminals.

[0058] Aspect 15. The plurality of unit capacitors A third metal layer disposed between the semiconductor substrate and the second metal layer, The third plurality of lower terminals elongated in a first direction, The third plurality of upper terminals electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and alternately arranged with the third plurality of lower terminals, And a third metal layer having A fourth metal layer between the semiconductor substrate and the third metal layer, The fourth plurality of lower terminals elongated in a first direction, each of the fourth plurality of lower terminals being disposed between the semiconductor substrate and one of each of the third plurality of upper terminals, the fourth plurality of lower terminals, And a fourth metal layer having And further includes The ADC according to any one of Aspects 10 to 14.

[0059] Aspect 16. The ADC according to any one of Aspects 10 to 15, wherein the plurality of unit capacitors further includes a plurality of vias connecting the first plurality of upper terminals to the second plurality of upper terminals.

[0060] Aspect 17. The plurality of unit capacitors A metal strip in the first metal layer elongated in a second direction perpendicular to the first direction, And further includes The first plurality of upper terminals are electrically coupled to each other by the metal strip. The ADC according to any one of Aspects 10 to 16.

[0061] Aspect 18. The ADC according to any one of Aspects 10 to 17, wherein the volume between the substrate and the first plurality of lower terminals does not contain electrically floating metal.

[0062] Aspect 19. A method for manufacturing a capacitor structure, comprising: forming a first metal layer over a semiconductor substrate, the first metal layer having: a first plurality of lower terminals elongated in a first direction; and a first plurality of upper terminals electrically coupled to each other, elongated in the first direction, and arranged alternately with the first plurality of lower terminals; forming; forming a second metal layer over the first metal layer, the second metal layer having: a second plurality of lower terminals elongated in the first direction; and a second plurality of upper terminals electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals; forming; the method including.

[0063] Aspect 20. forming a third metal layer having a third plurality of lower terminals elongated in the first direction between the first metal layer and the second metal layer; further including, each of the third plurality of lower terminals being disposed between the semiconductor substrate and a respective terminal of the second plurality of upper terminals; each of the second plurality of lower terminals having a first width in a second direction perpendicular to the first direction, each of the third plurality of lower terminals having a second width in the second direction, the second width being greater than the first width; the method according to aspect 19.

[0064] Aspect 21. The method according to aspect 20, wherein a first distance in the second direction between respective lower terminals of the third plurality of lower terminals is greater than a second distance in the second direction between an upper terminal of the second plurality of upper terminals and a lower terminal of the first plurality of lower terminals.

[0065] Aspect 22. The method according to any one of Aspects 19 to 21, wherein the first plurality of lower terminals and the second plurality of lower terminals are electrically coupled to form a plurality of groups of unit capacitors.

[0066] Aspect 23. In a plurality of groups of unit capacitors, forming a plurality of vias connecting the first plurality of lower terminals to the second plurality of lower terminals. The method according to Aspect 22, further comprising.

[0067] Aspect 24. Forming a third metal layer disposed between the semiconductor substrate and the second metal layer, the third metal layer including: a third plurality of lower terminals elongated in a first direction; a third plurality of upper terminals electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the third plurality of lower terminals; and having. Forming a fourth metal layer between the semiconductor substrate and the third metal layer, the fourth metal layer including: a fourth plurality of lower terminals elongated in a first direction, each of the fourth plurality of lower terminals being disposed between the semiconductor substrate and one of the third plurality of upper terminals; and having. The method according to any one of Aspects 19 to 23, further comprising. Aspect 25.

[0068] Aspect 26. Forming a plurality of vias connecting the first plurality of upper terminals to the second plurality of upper terminals. The method according to any one of Aspects 19 to 24, further comprising.

[0069] Aspect 27. Forming a metal strip elongated in a second direction perpendicular to the first direction on the second metal layer. The method according to any one of Aspects 19 to 26, further comprising. The second plurality of upper terminals are electrically coupled to each other by a metal strip. The method according to any one of aspects 19 to 25.

[0070] Aspect 27. The volume between the substrate and the second plurality of lower terminals does not contain electrically floating metal. The method according to any one of aspects 19 to 26.

[0071] Aspect 28. A capacitor structure, a semiconductor substrate, a first metal layer above the semiconductor substrate, the first metal layer having a first plurality of lower terminals elongated in a first direction, a second metal layer above the first metal layer, elongated in the first direction and having a first plurality of upper terminals directly above the first plurality of lower terminals, elongated in the first direction and having a second plurality of lower terminals alternately arranged with the first plurality of upper terminals, a second metal layer having, a third metal layer above the second metal layer, elongated in the first direction and having a second plurality of upper terminals directly above the first plurality of upper terminals, elongated in the first direction and having a third plurality of lower terminals alternately arranged with the second plurality of upper terminals, a third metal layer having, a fourth metal layer above the third metal layer, elongated in the first direction and having a fourth plurality of lower terminals directly above the second plurality of upper terminals, a fourth metal layer having, a fifth metal layer above the fourth metal layer, elongated in the first direction and having a third plurality of upper terminals directly above the fourth plurality of lower terminals, elongated in the first direction and having a fifth plurality of lower terminals alternately arranged with the third plurality of upper terminals, a fifth metal layer having, comprising a capacitor structure.

[0072]

[0048] The above describes the features of some aspects of the present disclosure. Those skilled in the art will understand that equivalent configurations can be made without departing from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present disclosure. As will now be understood by those skilled in the art, and depending on the specific application at hand, many modifications, substitutions, and variations can be made in and to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the spirit and scope thereof. In view of this, since the specific aspects illustrated and described herein are only by way of some examples thereof, the scope of the present disclosure should not be limited to the scope of such specific aspects, but rather should be fully equivalent to the scope of the claims appended hereinafter and the scope of their functional equivalents.

Claims

1. Capacitor structure, Semiconductor substrate and The first metal layer above the semiconductor substrate, A first set of elongated lower terminals in the first direction, They are electrically coupled to each other, are elongated in the first direction, and consist of a plurality of first upper terminals arranged alternately with a plurality of first lower terminals, A first metal layer having, A second metal layer between the semiconductor substrate and the first metal layer, A plurality of second lower terminals elongated in the first direction, Electrically coupled to each other and to the first plurality of upper terminals, the second plurality of upper terminals are elongated in the first direction and arranged alternately with the second plurality of lower terminals, A second metal layer having, A third metal layer between the first metal layer and the second metal layer, the third metal layer having a plurality of third lower terminals elongated in the first direction, Equipped with, Each of the third plurality of lower terminals is positioned between the semiconductor substrate and each of the terminals of the first plurality of upper terminals. A capacitor structure in which each of the first plurality of lower terminals has a first width in a second direction perpendicular to the first direction, and each of the third plurality of lower terminals has a second width in the second direction, the second width being greater than the first width.

2. The capacitor structure according to claim 1, wherein the first distance in the second direction between each of the lower terminals of the third plurality of lower terminals is greater than the second distance in the second direction between the upper terminals of the first plurality of upper terminals and the lower terminals of the first plurality of lower terminals.

3. The first plurality of lower terminals and the second plurality of lower terminals are electrically coupled to form a plurality of groups of unit capacitors. The capacitor structure according to claim 1, wherein the capacitor structure further comprises a plurality of vias in the plurality of groups of unit capacitors, connecting the first plurality of lower terminals to the second plurality of lower terminals.

4. A fourth metal layer disposed between the semiconductor substrate and the second metal layer, A fourth set of elongated lower terminals in the first direction, Electrically coupled to each other and to the first plurality of upper terminals, the fourth plurality of upper terminals are elongated in the first direction and arranged alternately with the fourth plurality of lower terminals, A fourth metal layer having, A fifth metal layer between the semiconductor substrate and the fourth metal layer, A fifth plurality of elongated lower terminals in the first direction, each of the fifth plurality of lower terminals being positioned between the semiconductor substrate and each of the fourth plurality of upper terminals, A fifth metal layer having, The capacitor structure according to claim 1, further comprising:

5. The capacitor structure according to claim 1, further comprising a plurality of vias connecting the first plurality of upper terminals to the second plurality of upper terminals.

6. A metal strip on the first metal layer, elongated in a second direction perpendicular to the first direction, Furthermore, The first plurality of upper terminals are electrically coupled to each other by the metal strip. The capacitor structure according to claim 1.

7. The capacitor structure according to claim 1, wherein the volume between the substrate and the first plurality of lower terminals does not contain electrically floating metal.

8. An analog-to-digital converter (ADC), Comparator and, Semiconductor substrate and A plurality of unit capacitors electrically coupled to the comparator, wherein the plurality of unit capacitors are formed by the capacitor structure described in any one of claims 1 to 7, ADC equipped with this.

9. A method for manufacturing a capacitor structure, The first metal layer is formed on top of the semiconductor substrate, and the first metal layer is The first set of elongated lower terminals in the first direction, They are electrically coupled to each other, are elongated in the first direction, and consist of a plurality of first upper terminals arranged alternately with a plurality of first lower terminals, Having, forming, The method involves forming a second metal layer above the first metal layer, wherein the second metal layer is A plurality of second lower terminals elongated in the first direction, Electrically coupled to each other and to the first plurality of upper terminals, elongated in the first direction, and arranged alternately with the second plurality of lower terminals and the second plurality of upper terminals Having, forming, A third metal layer having a plurality of third lower terminals elongated in the first direction is formed between the first metal layer and the second metal layer, Includes, Each of the third plurality of lower terminals is positioned between the semiconductor substrate and each of the terminals of the second plurality of upper terminals. A method wherein each of the second plurality of lower terminals has a first width in a second direction perpendicular to the first direction, and each of the third plurality of lower terminals has a second width in the second direction, the second width being greater than the first width.

10. The method according to claim 9, wherein the first distance in the second direction between each of the lower terminals of the third plurality of lower terminals is greater than the second distance in the second direction between the upper terminals of the second plurality of upper terminals and the lower terminals of the first plurality of lower terminals.

11. The first plurality of lower terminals and the second plurality of lower terminals are electrically coupled to form a plurality of groups of unit capacitors, and the method is In the aforementioned group of unit capacitors, a plurality of vias are formed connecting the first plurality of lower terminals to the second plurality of lower terminals. The method according to claim 9, further comprising:

12. To form a fourth metal layer disposed between the semiconductor substrate and the second metal layer, The fourth metal layer is A fourth set of elongated lower terminals in the first direction, Electrically coupled to each other and to the first plurality of upper terminals, the fourth plurality of upper terminals are elongated in the first direction and arranged alternately with the fourth plurality of lower terminals, It has, A fifth metal layer is formed between the semiconductor substrate and the fourth metal layer. The fifth metal layer has a plurality of elongated fifth lower terminals in the first direction, and each of the plurality of fifth lower terminals is positioned between the semiconductor substrate and each of the plurality of fourth upper terminals. Further including, The method according to claim 9.

13. To form multiple vias connecting the first multiple upper terminals to the second multiple upper terminals, The method according to claim 9, further comprising:

14. Forming an elongated metal strip on the second metal layer in a second direction perpendicular to the first direction, It further includes, The second set of upper terminals are electrically coupled to each other by the metal strip. The method according to claim 9.

15. The method according to claim 9, wherein the volume between the substrate and the second plurality of lower terminals does not contain electrically floating metal.

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