Automatic Mirror ROM

Abstract

The disclosed method may include a control circuit coupled to a first read-only memory (ROM) device and a second ROM device detecting a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output, and the second ROM device is disconnected from the common output. The method also includes, in response to detecting the failure, the control circuit switching the common output from the first ROM device to the second ROM device. Various other methods, systems, and computer-readable media are also disclosed.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the benefit of Chinese Patent Application No. 202210575524.8, filed on May 25, 2022, entitled "A MIRRORED SPI ROM DESIGN TO INCREASE SYSTEM STABILITY", and claims the priority of US Patent Application No. 17 / 855628, filed on June 30, 2022, entitled "AUTOMATIC MIRRORED ROM", the entire contents of which are incorporated herein by reference.

Background Art

[0002] A computing device may use a read - only memory (ROM) to store dedicated data and / or software such as firmware. The ROM chip can often be soldered onto the printed circuit board (PCB) of the computing device or can be incorporated into the computing device in a manner that makes it difficult to replace the ROM chip if it fails. Thus, many computing devices may incorporate a second ROM chip that functions as a backup ROM.

[0003] However, using a backup ROM chip may require a manual process. Detecting a failure in the first ROM chip itself may require manual intervention. Even if a failure is detected automatically, switching to the second ROM chip may require manual reconfiguration of the device. For example, the user may need to reconfigure the device to use different chip - select pins, update the device's BIOS, and / or perform other operations that often require rebooting the device. Thus, using a backup ROM chip can interfere with the normal operation of the device.

Summary of the Invention

Means for Solving the Problems

[0004] As will be described in more detail below, the present disclosure describes various systems and methods for automatically disconnecting a first ROM device from a common output and connecting a second ROM device to the common output in response to detecting a failure of the first ROM device. The second ROM device may mirror the first ROM device to function as a backup ROM device.

[0005] In one example, a method for automatic ROM switching may include a control circuit coupled to a first read-only memory (ROM) device and a second ROM device detecting a failure of a first output signal from the first ROM device to a common output. The first ROM device may be connected to the common output, and the second ROM device may be disconnected from the common output. The method may also include the control circuit switching the common output from the first ROM device to the second ROM device in response to detecting the failure.

[0006] In some examples, switching the common output from the first ROM device to the second ROM device may be responsive to the control circuit detecting a second output signal from the second ROM device. In some examples, detecting a failure of the first output signal may further include the control circuit comparing the first output signal to a second output signal from the second ROM device. In some examples, detecting the failure may further include detecting a logic low signal on the first output signal and a logic high signal on the second output signal. In some examples, detecting a failure of the first output signal may further include evaluating a delayed first output signal using the first output signal.

[0007] In some examples, the first ROM device and the second ROM device may operate simultaneously. In some examples, both the first ROM device and the second ROM device may be connected to a common input. In some examples, the second ROM device may mirror the first ROM device.

[0008] In one embodiment, a system for an automotive mirror ROM can include a first read-only memory (ROM) device coupled to a common output, a second ROM device decoupled from the common output, and a control circuit coupled to the first ROM device and the second ROM device, the control circuit configured to detect a failure of the first ROM device on the common output and, in response, switch the second ROM device to the common output.

[0009] In some examples, switching the second ROM device to the common output can further depend on the control circuit detecting a second output signal from the second ROM device. In some examples, detecting a failure of the first ROM device can further include the control circuit comparing a first output signal of the first ROM device to a second output signal of the second ROM device. In some examples, detecting a failure of the first ROM device can further include detecting at least one of a logic low signal on the first output signal and a logic high signal on the second output signal, a persistent logic signal on the first output signal that does not match the second output signal, or a first output signal that changes from a logic high signal to a logic low signal that does not match the second output signal.

[0010] In one embodiment, a system for an automotive mirror ROM can include at least one physical processor, physical memory, a first read-only memory (ROM) device coupled to a common output, a second ROM device decoupled from the common output, and a control circuit coupled to the first ROM device and the second ROM device, the control circuit configured to automatically couple the second ROM device to the common output in response to detecting a failure of the first ROM device.

[0011] Any of the characteristics of the embodiments described above may be used in combination with each other in accordance with the general principles described herein. These and other embodiments, features, and advantages will be more fully understood by reference to the following detailed description of the invention in conjunction with the accompanying drawings and the claims.

[0012] The accompanying drawings, which are a part of this specification, illustrate several exemplary embodiments. In conjunction with the following description, these drawings demonstrate and explain the various principles of the present disclosure. **Brief Description of the Drawings**

[0013]

Figure 1

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

[0014] Throughout the drawings, the same reference numerals and descriptions, while not necessarily identical, represent similar elements. The exemplary embodiments described herein are capable of various modifications and alternative forms, but specific embodiments are shown in the drawings as examples and described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the specific forms disclosed. Rather, the present disclosure encompasses all modifications, equivalents, and alternative forms within the scope of the appended claims.

[0015] This disclosure generally relates to dual ROM designs that can automatically switch from one ROM chip to another. As will be described in more detail below, embodiments of the present disclosure can detect a failure of a first output signal from a first ROM and switch to a second ROM accordingly. This disclosure provides a device having a mirrored ROM design that can automatically switch from a first ROM to a second ROM when the first ROM fails. Advantageously, the switch can be made seamlessly without requiring reconfiguration or reboot of the device.

[0016] Features according to any of the embodiments described herein can be used in combination with one another according to the general principles described herein. These and other embodiments, features, and advantages will be more fully understood by reference to the following detailed description of the invention in conjunction with the accompanying drawings and the claims.

[0017] A detailed description of an automatic mirrored ROM will be provided below with reference to FIGS. 1-4. A detailed description of an exemplary system having an automatic mirrored ROM is provided in connection with FIG. 1. A detailed description of an exemplary circuit and its signals for an automatic mirrored ROM is provided in connection with FIGS. 2A-2B. Another detailed description of an exemplary circuit and its signals for an automatic mirrored ROM is provided in connection with FIGS. 3A-3B. A detailed description of a corresponding computer-executed method is also provided in connection with FIG. 4.

[0018] FIG. 1 is a block diagram of an exemplary system 100 for a dual ROM design that can be automatically switched. System 100 can correspond to computing devices such as desktop computers, laptop computers, servers, tablet devices, mobile devices, smartphones, wearable devices, augmented reality devices, virtual reality devices, network devices, and / or electronic devices. As shown in FIG. 1, system 100 may also include one or more memory devices such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drive (HDD), Solid-State Drive (SSD), optical disk drive, cache, one or more modified forms or combinations thereof, and / or any other suitable storage memory.

[0019] As shown in FIG. 1, the exemplary system 100 may also include one or more physical processors, such as processor 110. Processor 110 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 may access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs) implementing softcore processors, application specific integrated circuits (ASICs), system on chips (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more portions of these, one or more variations or combinations of these, and / or any other suitable physical processor.

[0020] As further shown in FIG. 1, system 100 may include a control circuit 112, ROM 114, ROM 116, and a common output 160. ROM 114 may be a ROM device, and in some examples, ROM 116 may be a mirror of ROM 116 (e.g., having the same speed, size, data, etc.). The control circuit 112 may be coupled to both ROM 114 and ROM 116, and more specifically, in some examples, may be coupled to the outputs of ROM 114 and ROM 116. The control circuit 112 includes a switching circuit and / or element for switching between the outputs of ROM 114 and ROM 116 such that one of the outputs of ROM 114 and ROM 116 (e.g., the common output 160) can be coupled to the processor 110 and / or the memory 120 (e.g., to a bus connecting the processor 110 and / or the memory 120). In other words, the control circuit 150 can control which output of ROM 130 and ROM 140 is connected to the common output 160. Further, in some examples, a common input (e.g., a signal sent from the processor 110 and / or the memory 120) can be coupled to both ROM 130 and ROM 140. For example, any update to ROM 130 may be mirrored to ROM 140.

[0021] FIG. 2A shows an exemplary circuit 200, and FIG. 2B shows a signal diagram 201 of the circuit 200. The circuit 200 may include a ROM 230 (e.g., ROM#1) that may correspond to ROM 130, a ROM 240 (e.g., ROM#2) that may correspond to ROM 140, and a control circuit 250 that may correspond to control circuit 150. The control circuit 250 may include a logic block 251 that may include an inverter as shown in FIG. 2A to evaluate the output of the ROM 230. In other examples, the logic block 251 may include other components and / or circuits (see, e.g., FIG. 3A). Referring further to FIG. 2B, various signals are shown including a clock 270, a switching signal 252, an output 260, and a selection signal 254. In some examples, one or more components of the circuit 200 may communicate via a Serial Peripheral Interface (SPI), but in other examples, other interfaces may be used. The circuit 200 shows an example of a circuit for an auto-mirrored ROM.

[0022] As shown in FIG. 2B, the clock 270 may provide a clock signal for coordinating various circuit components, for example, by using a rising edge to synchronize. At time t0, the output signal of the ROM 240 may be logic high, while the ROM 230 is logic low. As described herein, the ROM 240 may mirror the ROM 230 such that the same logic signal (e.g., high or low) is expected at any given time. However, at time t0, the ROM 230 outputs a logic low when a logic high is expected (as indicated by the ROM 240), so the ROM 230 may be experiencing an impairment that prevents it from outputting the expected logic high.

[0023] The control circuit 250 can detect a failure of the ROM 230 and replace the output of the ROM 230 with the output of the ROM 240 for the output 260, as indicated by the arrow in FIG. 2B. More specifically, in the example shown in FIG. 2A, the control circuit 250 may use a switching signal 252. The switching signal 252 can be derived from the outputs of the ROM 230 and the ROM 240. At time t0, the logic low output from the ROM 230 can be inverted to logic high by an inverter (or NOT gate). The XOR gate can combine the logic low output from the ROM 230 and the logic high output from the ROM 240 to output a logic high (for example, the exclusive OR XOR can generate a logic high when only one of its two inputs is logic high). The inverted signal (for example, logic high at time t0) and the XOR signal (for example, logic high at time t0) can be combined with an AND gate that generates a logic high when both of its inputs are logic high to output the switching signal 252 that is logic high at time t0.

[0024] As further shown in FIG. 2A, the control circuit 250 may include an active-low tri-state buffer that is coupled to the outputs of each of the ROM 230 and the ROM 240 and passes data when a logic low is applied to a control line controlled by the switching signal 252. More specifically, the switching signal 252 may control the buffer coupled to the ROM 230, and the switching signal 252 inverted by an inverter may control the buffer coupled to the ROM 240. Thus, at time t0, the logic high for the switching signal 252 that controls the buffer for the ROM 230 can disable the output from the ROM 230. Further, at time t0, the logic high for the switching signal 252 inverted to logic low to control the buffer for the ROM 240 can enable the output from the ROM 240 to the output 260. Thus, the control circuit 250 can automatically switch the output 260 from the ROM 230 to the ROM 240 when the ROM 230 fails.

[0025] The switching signal 252 can switch the output 260 from the ROM 230 to the ROM 240 only when the switching signal 252 is logic high. When the switching signal 252 is logic low, (for example, since the switching signal 252 is inverted to logic high) the buffer for the ROM 230 can be enabled and the buffer for the ROM 240 can be disabled. When the ROM 230 outputs logic high and the ROM 240 outputs logic low (which may indicate a failure of the ROM 240), the first inverter coupled to the ROM 230 generates a logic low signal input to the AND gate such that the switching signal 252 becomes logic low. When the ROM 230 and the ROM 240 output the same signal (for example, both logic high or both logic low), the XOR gate generates a logic low signal input to the AND gate such that the switching signal 252 becomes logic low.

[0026] In some examples, the control circuit 250 can also use a selection signal 254 to select between the ROM 230 and the ROM 240. The selection signal 254 can correspond to a chip select signal for SPI in some examples that can command which component (for example, between the ROM 230 and the ROM 240) should send data and which component should be disconnected from the SPI bus. In some examples, the chip select can be active low logic such that when the selection signal 254 is logic high, the ROM 230 is connected (and the ROM 240 is disconnected), and when the selection signal 254 is logic low, the ROM 230 is disconnected (and the ROM 240 is connected).

[0027] FIG. 3A shows an exemplary circuit 300, and FIG. 3B shows a signal diagram 301 of the circuit 300. The circuit 300 may include a ROM 330 (e.g., ROM #1) that may correspond to ROM 130, a ROM 340 (e.g., ROM #2) that may correspond to ROM 140, and a control circuit 350 that may correspond to control circuit 150. The control circuit 350 may include a logic block 351 for evaluating the output of the ROM 330. As shown in FIG. 3A, the logic block 351 can include a NAND gate and 2N + 1 inverters, where N is an integer corresponding to a desired amount of signal delay (e.g., a clock cycle or other delay amount). Referring further to FIG. 3B, various signals are shown including a clock 370, an XOR output 356, a delayed ROM 332, a NAND output 358, a switching signal 352, a selection signal 354, and an output 360. In some examples, one or more components of the circuit 300 may communicate via SPI, but in other examples, other interfaces may be used.

[0028] The circuit 300 shows another example of a circuit for an auto-mirrored ROM, which may be a variation of the circuit 200 and may operate similarly, but a delayed output signal (e.g., delayed ROM 332) for the ROM 330 is added to determine a failure of the ROM 330 and / or to prevent a failure of the ROM 340 from triggering a switch. The outputs of the ROM 330 and the delayed ROM 332 may be the output of the ROM 330 that is delayed and inverted by only a single clock cycle and may be input to a NAND gate, which generates a logic low only when both of its inputs are logic high and generates a NAND output 358. The fact that both the ROM 330 and the delayed ROM 332 are logic high indicates that the output of the ROM 330 has changed from a logic low in the previous cycle to a logic high in the current cycle (e.g., time t0 in FIG. 3B), which does not indicate a failure so that the logic low of the NAND output 358 does not indicate a failure.

[0029] The switching signal 352 is output from the AND combination of the NAND output 358 and the XOR output 356. Similar to the switching signal 252, the switching signal 352 can switch the output 360 from the ROM 330 to the ROM 340 only when the switching signal 352 is high. Therefore, a logic low from the NAND output 358 may not trigger a switch.

[0030] The NAND output 358 can be logic high when both the ROM 330 and the delay ROM 332 are logic low, or when the ROM 330 and the delay ROM 332 are different. Both the ROM 330 and the delay ROM 332 being logic low indicates that the output of the ROM 330 has changed from logic high in the previous cycle to logic low in the current cycle, which can indicate a failure of the ROM 330 (e.g., a failure after the previous cycle) such that a logic high of the NAND output 358 can indicate a failure of the ROM 330. However, different ROM 330 and delay ROM 332 do not necessarily indicate a failure as the difference may be due to a valid sustained logic low or logic high at the output. The XOR output 356 can indicate whether a sustained logic low or logic high is valid.

[0031] As shown in FIG. 3A, the XOR output 356 can be an XOR combination of ROM 330 and ROM 340. The XOR output 356 goes logic high only when ROM 330 and ROM 340 output different signals, which may indicate that one of ROM 330 and ROM 340 has failed. Thus, when the XOR output 356 is logic low (indicating that ROM 330 and ROM 340 output the same signal) and the NAND output 358 is logic high (e.g., the sustained logic low or logic high of ROM 330 is verified by the XOR output 356), the switching signal 352 goes logic low so that no switching occurs. However, when the XOR output 356 is logic high (indicating a fault in one of ROM 330 and ROM 340) and the NAND output 358 is logic high (e.g., the sustained logic low or logic high of ROM 330 is not verified by the XOR output 356), the switching signal 352 goes logic high so that the switching is automatically performed. In other words, when ROM 330 maintains a logic signal or changes from logic high to logic low inconsistent with ROM 340, the control circuit 350 can automatically switch the output 360 from ROM 330 to ROM 340.

[0032] FIGS. 3A and 3B further show how a fault in ROM 340 can be prevented from causing the control circuit 350 to switch the output 360 from ROM 330 to ROM 340. A fault in ROM 340 can indicate a continuous logic low output from ROM 340, as shown in FIG. 3B. The XOR output 356 can indicate the difference between the output of ROM 330 and the output of ROM 340 (at time t0, etc.), while the NAND output 358 can indicate valid activity from ROM 330. For example, if ROM 340 fails to generate only logic low, the change of ROM 330 from logic low to logic high (generating a NAND output 358 of logic low, which further generates a switching signal 352 of logic low as seen at time t0) can prevent the switching.

[0033] In some examples, the control circuit 350 can also use a selection signal 354 to select between the ROM 330 and the ROM 340. The selection signal 354 can, in some examples, correspond to a chip select signal for SPI that can instruct which component (e.g., between the ROM 330 and the ROM 340) should send data and which component should be disconnected from the SPI bus. In some examples, the chip select can be active low logic such that when the selection signal 354 is logic high, the ROM 330 is connected (and the ROM 340 is disconnected), and when the selection signal 354 is logic low, the ROM 330 is disconnected (and the ROM 340 is connected).

[0034] FIG. 4 is a flowchart of an exemplary computer-executable method 400 for automatic switching of ROM devices. The steps shown in FIG. 4 may be performed by any suitable computer-executable code and / or computing system, including the systems shown in FIGS. 1, 2A, and / or 3A. In one example, each of the steps shown in FIG. 4 may represent an algorithm having a structure that includes and / or is represented by a plurality of sub-steps, examples of which are shown in detail below.

[0035] As shown in FIG. 4, in step 402, one or more of the systems described herein can detect a failure of a first output signal from a first read-only memory (ROM) device to a common output by a control circuit coupled to the first ROM device and a second ROM device. The first ROM device may be connected to the common output and the second ROM device may be disconnected from the common output. For example, the output of ROM 130 may be connected to the common output 160 and the output of ROM 140 may be disconnected from the common output 160. The control circuit 150 can detect a failure of the output signal from ROM 130.

[0036] The system described in this specification can execute step 402 in various ways. In one example, the first ROM device and the second ROM device can operate simultaneously. Further, both the first ROM device and the second ROM device can be connected to a common input so that any data input to the first ROM device can be input to the second ROM device. More specifically, the second ROM device can mirror the first ROM device. For example, ROM140 can share the same size, speed, data, etc. as ROM130 in order to function as a backup ROM of ROM130. Further, thus, ROM130 and ROM140 can operate and / or behave in the same way, but only one ROM can output to the common output 160.

[0037] In some examples, detecting a failure of the first output signal from the first ROM device may further include the control circuit comparing the first output signal with a second output signal from the second ROM device. For example, detecting a failure of the first output signal from the first ROM device may include detecting a logic low signal on the first output signal and a logic high signal on the second output signal.

[0038] Since ROM130 and ROM140 can be designed to behave in the same way, any difference between the outputs may indicate a failure of ROM130 or ROM140. For example, if a logic high signal is expected (as indicated by ROM140), and ROM140 outputs a logic high signal (indicating output data) while ROM130 outputs a logic low signal, this difference in the outputs may indicate that ROM130 is showing a failure.

[0039] In some examples, detecting a failure of the first ROM may include detecting at least one of a persistent logic signal on the first output signal that does not match the second output signal and a first output signal that changes from a logic high signal to a logic low signal that does not match the second output signal. As described above (see, e.g., FIGS. 3A and 3B), if the ROM 130 outputs the same logic signal in the previous clock cycle and the current clock cycle that does not match the output of the ROM 140 in the current clock cycle, the control circuit 150 may switch the common output 160 from the ROM 130 to the ROM 140. Further, if the ROM 130 outputs a logic high in the previous clock cycle and a logic low in the current clock cycle, and the ROM 140 outputs a logic high in the current clock cycle, the control circuit 150 can switch the common output 160.

[0040] In yet other examples, the control circuit 150 may detect a failure of the ROM 130 in other ways, such as detecting a weak (e.g., not reaching logic high) and / or corrupted signal, detecting an unexpected delay in the signal, detecting a failure via one or more sensors, etc.

[0041] In operation 404, one or more of the systems described herein may switch a common output from a first ROM device to a second ROM device by a control circuit in response to detecting a failure. For example, the control circuit 150 may automatically disconnect the ROM 130 from the common output 160 and connect the ROM 140 to the common output 160 in response to detecting a failure.

[0042] The systems described herein may perform operation 404 in various ways. In one example, switching the common output from the first ROM device to the second ROM device may further depend on the control circuit detecting a second output signal from the second ROM device. For example, as described above, the control circuit 150 may be able to detect a logic high signal from the ROM 140, while the ROM 130 outputs a logic low signal or no signal.

[0043] In other examples, the control circuit 150 may determine that the ROM 140 is also not faulty, or may prevent switching if the ROM 140 is faulty. For example, detecting a logic low output from the ROM 130 in the previous clock cycle and a logic high output from the ROM 130 in the current clock cycle may prevent the control circuit 150 from switching the common output 160 even though the ROM 140 is outputting a logic low signal in the current clock cycle (not matching the ROM 130).

[0044] As described above, many server / workstation designs may have a dual SPI ROM design to enhance system stability. The dual ROM design may provide a backup ROM if the primary ROM fails. However, the two ROMs may be on different chip select pins, and thus, if one ROM is damaged or otherwise fails, the user may need to reboot the system, and the firmware may need to be updated to fetch code from the other ROM by using a different chip select pin. The present disclosure enables the ROM to switch transparently to the end user. If one ROM is damaged, the system described herein can automatically switch to the backup ROM without requiring a power off, reboot, or change to the BIOS code.

[0045] The present disclosure provides a mirrored SPI ROM design where the second ROM is a backup chip. If the primary ROM is damaged or otherwise fails, the system described herein may detect the failure (e.g., by detecting no output from the primary ROM) and automatically switch to the backup ROM, such that the system may still fetch code from the backup ROM without requiring a power off or reboot to change the ROM. This can advantageously help increase system stability.

[0046] With this design, the dual ROM can operate as a mirrored ROM that shares the same SPI bus signals and the same chip select pins. However, only one ROM at a time may provide data output so that the second ROM functions as a backup and is connected as needed. When the primary ROM fails, the system can automatically switch to the second (backup) ROM. To further improve the current dual SPI ROM design, the system can keep the power on while switching from a bad ROM to a good ROM. Such a design can be advantageous for systems that require long execution times or that may not be easily rebooted or powered off. Additionally, switching can be prevented if the second ROM fails.

[0047] As described above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions. In their most basic configuration, each of these computing devices (s) may include at least one memory device and at least one physical processor.

[0048] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device may store, load, and / or maintain one or more of the modules described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), optical disk drive, cache, variations or combinations of one or more of these, or any other suitable storage memory.

[0049] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor may access and / or modify one or more modules stored in the memory device described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field programmable gate arrays (FPGAs) implementing softcore processors, application specific integrated circuits (ASICs), system on chips (SOCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more portions of these, one or more variations or combinations of these, or any other suitable physical processor.

[0050] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or holding computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, magnetic storage media (e.g., hard disk drives, tape drives, and floppy (registered trademark) disks), optical storage media (e.g., Compact Disk (CD), Digital Video Disk (DVD), and Blu-ray (registered trademark) disks), electronic storage media (e.g., solid state drives and flash media), and non-transitory media such as other distributed systems.

[0051] The process parameters and the order of steps described and / or illustrated in this specification are given by way of example only and can be changed as desired. For example, although the steps illustrated and / or described in this specification may be illustrated or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated in this specification may omit one or more of the steps described and / or illustrated herein, or may include additional steps in addition to those disclosed.

[0052] The foregoing description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit the disclosure to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects to be exemplary and not limiting. Reference should be made to the appended claims and their equivalents to determine the scope of the present disclosure.

[0053] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and the claims are to be construed to allow both direct and indirect connection (i.e., through other elements or components). In addition, the term "a" or "an" as used in this specification and the claims is to be construed to mean "at least one of". Finally, for the sake of brevity, the terms "comprising" and "having" (and their derivatives) as used in this specification and the claims are interchangeable with the word "including" and have the same meaning.

Claims

1. A method comprising: a control circuit coupled to a first read-only memory (ROM) device and a second ROM device detecting a failure of a first output signal from the first ROM device to a common output, the first ROM device being connected to the common output and the second ROM device being disconnected from the common output; and in response to detecting the failure, the control circuit switching the common output from the first ROM device to the second ROM device. The method.

2. The switching of the common output from the first ROM device to the second ROM device is performed in response to the control circuit detecting a second output signal from the second ROM device and the control circuit comparing the first output signal with the second output signal from the second ROM device. The method of Claim 1.

3. Detecting a failure of the first output signal from the first ROM device includes detecting a logic low signal on the first output signal and a logic high signal on the second output signal. The method of Claim 2.

4. Detecting a failure of the first output signal from the first ROM device includes evaluating a delayed first output signal using the first output signal. The method of Claim 2.

5. The first ROM device and the second ROM device operate simultaneously. The method of Claim 1.

6. Both the first ROM device and the second ROM device are connected to a common input. The method of Claim 1.

7. The second ROM device mirrors the first ROM device. The method of Claim 1.

8. A system comprising: a first read-only memory (ROM) device coupled to a common output; a second ROM device disconnected from the common output; and a control circuit coupled to the first ROM device and the second ROM device, the control circuit configured to detect a failure of the first ROM device on the common output and in response switch the second ROM device to the common output. The system.

9. Switching the second ROM device to the common output is performed by the control circuit in response to detecting a second output signal from the second ROM device. The system of claim 8. **Claim 10** Detecting a failure of the first ROM device includes the control circuit comparing a first output signal of the first ROM device with a second output signal of the second ROM device. The system of claim 9. **Claim 11** Detecting a failure of the first ROM device includes a logic low signal on the first output signal and a logic high signal on the second output signal, a persistent logic signal on the first output signal that does not match the second output signal, the first output signal changing from the logic high signal to a logic low signal that does not match the second output signal, including detecting at least one of them. The system of claim 10. **Claim 12** The first ROM device and the second ROM device operate simultaneously. The system of claim 8. **Claim 13** The second ROM device mirrors the first ROM device. The system of claim 8. **Claim 14** Both the first ROM device and the second ROM device are connected to a common input. The system of claim 8. **Claim 15** A system comprising: at least one physical processor; physical memory; a first read-only memory (ROM) device coupled to a common output; a second ROM device disconnected from the common output; a control circuit coupled to the first ROM device and the second ROM device, the control circuit being configured to automatically couple the second ROM device to the common output in response to detecting a failure of the first ROM device. System. **Claim 16** Detecting a failure of the first ROM device includes the control circuit comparing a first output signal of the first ROM device with a second output signal of the second ROM device. The system of claim 15. **Claim 17** Detecting a failure of the first ROM device includes a logic low signal on the first output signal and a logic high signal on the second output signal, a persistent logic signal on the first output signal that does not match the second output signal, the first output signal that changes from the logic high signal to the logic low signal that does not match the second output signal, including detecting at least one of the system of claim 16. **Claim 18** the first ROM device and the second ROM device operate simultaneously, the system of claim 15. **Claim 19** both the first ROM device and the second ROM device are connected to a common input, the system of claim 15. **Claim 20** the second ROM device mirrors the first ROM device, the system of claim 15.

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