Surface-emitting laser, method for manufacturing surface-emitting laser

Abstract

A vertical resonance surface emitting laser includes an oxide substrate having a first surface and a second surface opposite to the first surface; a semiconductor section disposed on the first surface; a dielectric filter layer disposed between the semiconductor section and the first surface and having a reflection spectrum configured to provide an optical window; a first DBR mirror; and a second DBR mirror disposed on the curved surface of the second surface. The first DBR mirror, the semiconductor section, the dielectric filter layer, the oxide substrate, and the second DBR mirror are arranged in a first axial direction to form an extended cavity. The semiconductor section is disposed between the dielectric filter layer and the first DBR mirror and includes a p-type group III nitride region, an n-type group III nitride region, and a group III nitride active region between the p-type group III nitride region and the n-type group III nitride region.

Description

Technical Field

[0001] The present disclosure relates to an extended cavity III-nitride vertical-cavity surface-emitting laser (VCSEL), and a method of manufacturing an extended cavity III-nitride VCSEL.

Background Art

[0002] Surface-emitting lasers are known as vertical-cavity surface-emitting lasers (VCSELs). A VCSEL includes a semiconductor active region disposed between an n-side semiconductor region and a p-side semiconductor region, and two distributed Bragg reflectors that function as high-reflection mirrors, and the distributed Bragg reflectors are referred to as DBRs. The semiconductor active region is also known as a gain medium, and is disposed between the two DBRs such that the two DBRs and the semiconductor active region form an optical cavity (optical resonator). The n-side region and the p-side region inject their respective carriers, that is, electrons and holes, into the active region, and these carriers recombine in the active region to generate light. The light or electromagnetic radiation thus generated is reflected multiple times by the DBRs and travels through the optical cavity, leading to laser oscillation. The VCSEL includes a low-reflectivity mirror on one of the DBRs for emitting a laser beam.

[0003] This application refers to several patent documents or non-patent documents throughout the specification by reference numbers in parentheses, that is, as indicated by " ". A list of the documents ordered according to these reference numbers is described in the section entitled "Non-Patent Documents" or "Patent Documents" below.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

[0005] The optical cavity defined by two planar DBR mirrors in a VCSEL suffers excessive diffraction losses as the cavity length increases. Using a curved mirror or lens in a VCSEL enables the VCSEL to have a long optical cavity. As shown in "Non-Patent Document 1" and "Non-Patent Document 2", the curved mirror or lens focuses the electric field of the laser light onto the gain medium to reduce the diffraction losses due to a longer cavity length. Adjusting the cavity mode to match the gain spectrum of the VCSEL can achieve high-efficiency operation. Using one or two laser oscillation wavelengths in a VCSEL with a very short cavity length, for example, increases the interval between cavity modes. Because the interval is wide, at least one of the cavity modes is unlikely to fall within the gain spectrum of the VCSEL, thereby reducing the yield and laser oscillation efficiency of the VCSEL. In contrast, increasing the cavity length reduces the mode interval. Due to the narrow interval, one of the cavity modes is likely to fall within the gain spectrum of the VCSEL, thereby increasing the yield of laser oscillation.

[0006] However, in VCSELs with long cavities, it is an attractive challenge that all device layers except the active region are made of materials that are transparent to the electromagnetic radiation propagating within the VCSEL. One of the DBR mirrors can be disposed on the curved back surface of the group-III nitride semiconductor host substrate, which is formed as a lens structure. Accordingly, the VCSEL of this structure does not use substrate removal, as the group-III nitride host substrate may introduce moderate losses into the cavity. This approach of the curved mirror is proposed in "Non-Patent Document 1" and "Non-Patent Document 2", and still provides a significant portion of the original host substrate to the cavity, where the lens structure is formed by etching and a curved n-side DBR mirror is formed thereon. This approach is designed for the homoepitaxy of GaN. In addition, the dopant concentration of the host substrate included in the long cavity should be as low as the loss level of pin absorption. Accordingly, the host substrate is first thinned to reduce the optical absorption loss in the cavity. Thinning the substrate is a difficult process to control and may damage the substrate, because the substrate has to be thinned from an initial thickness of 300 to 400 micrometers to a target thickness of 10 to 30 micrometers to provide the desired characteristics to the VCSEL.

[0007] Otherwise, including the host substrate in the cavity may cause unintentional absorption losses each time the electromagnetic radiation travels back and forth, which hinders the reduction of the oscillation threshold. However, the authors of "Non-Patent Document 3" have demonstrated the operation of GaN-based VCSELs in the extended cavity scheme, which is fabricated by directly growing GaN-based device layers on a sapphire substrate with low absorption. In such a scheme, the lattice mismatch between the sapphire substrate and the device layer still limits the crystal quality of the device layer, and accordingly, the lifetime and yield of such devices become problematic.

[0008] The following is desired: to keep the absorption source as thin as possible while maintaining stable laser operation, and that the lower mirror be arranged such that a cavity is formed with the upper and lower mirrors arranged close to each other, which results in the removal of the original substrate. In the heteroepitaxy technique, the group-III nitride device layer is grown on a hetero-substrate such as sapphire and silicon, and the hetero-substrate of the group-III nitride VCESL device can be easily removed by chemical etching or laser lift-off (referred to as "LLO") as in "Non-Patent Document 4", while the heteroepitaxy of GaN on a sapphire substrate cannot improve its crystal quality. However, the conventional LLO process cannot be accepted for GaN homoepitaxy. In another approach, the removal of the group-III nitride device layer from a GaN homoepitaxial structure has been reported in "Non-Patent Document 5" and is still very interesting as in "Non-Patent Documents 6" to "Non-Patent Document 10".

[0009] The longer the cavity, the better the stability in terms of oscillation and thermal drift. Alternatively, the design of an extended cavity VCSEL can be achieved by carefully removing the VCSEL device layer from the original growth substrate or hetero-substrate and then reattaching a lossless transparent oxide ("TO") material such as ZnO and group-III oxides, where the group-III oxides can include Al 2 O 3 and Ga 2 O 3 This design requires surface treatment to be achieved sub-nanometer-level both for the attached TO substrate and the device layer to be removed, and also generates potential unwanted reflections due to the refractive index difference at the GaN / oxide interface formed in this way by reattachment. If this reflection leads to a degradation in the device performance, the unwanted reflection can be suppressed by an anti-reflection coating at the interface. All of these procedures are time-consuming and cause problems regarding additional costs.

[0010] Taking into account all these drawbacks, an object of the present disclosure is to provide the characteristics of an extended cavity to the structure of an III-V VCSEL and to provide a method for manufacturing a VCSEL having the characteristics of an extended cavity. Another object of the present disclosure is to provide a single-step integrated solution that enables the formation of an extended cavity without involving complex bonding and substrate removal procedures.

Means for Solving the Problems

[0011] A vertical-cavity surface-emitting laser according to one configuration of the present disclosure includes an oxide substrate having a first surface and a second surface opposite to the first surface, wherein the second surface includes a curved surface, an oxide substrate, a semiconductor section disposed on the first surface of the oxide substrate, a dielectric filter layer disposed between the semiconductor section and the first surface of the oxide substrate and having a reflection spectrum, the reflection spectrum being configured to provide an optical window, a first distributed Bragg reflector (DBR) mirror, the semiconductor section being disposed between the dielectric filter layer and the first DBR mirror, a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor section, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged in a first axial direction to form an extended cavity, the semiconductor section including a p-type group-III nitride region, a group-III nitride region, and a group-III nitride active region between the p-type group-III nitride region and the group-III nitride region, the p-type group-III nitride region, the group-III nitride active region, and the group-III nitride region being arranged in the first axial direction, and the group-III nitride region including an n-type group-III nitride region, and a second DBR mirror.

[0012] A method of manufacturing a vertical cavity surface emitting laser according to another configuration of the present disclosure includes preparing a starting base, the starting base including an oxide base, a group III nitride template plug, and a dielectric filter layer, the oxide base having a first surface and a second surface opposite the first surface of the oxide base, the dielectric filter layer and the group III nitride template plug being disposed on the first surface of the oxide base, the dielectric filter layer having a reflection spectrum configured to provide an optical window; growing a group III nitride region from the group III nitride template plug on the dielectric filter layer; growing a semiconductor laminate including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region after growing the group III nitride region; processing the oxide base on the second surface of the oxide base to form an oxide substrate having a curved surface, the curved surface being disposed on the opposite side of the first surface of the oxide substrate; forming a first distributed Bragg reflector (DBR) laminate on the first surface of the oxide substrate after growing the semiconductor laminate; and forming a second DBR laminate on the curved surface of the oxide substrate.

Advantages of the Invention

[0013] The above configuration can provide the characteristics of an extended cavity to the structure of an III-V CSEL and to a method of manufacturing a VCSEL having extended cavity characteristics.

Brief Description of the Drawings

[0014]

Figure 1

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Figure 10

Embodiments for Carrying Out the Invention

[0015] The teachings of the present disclosure can be easily understood by considering the following detailed description with reference to the accompanying drawings shown by way of example. Hereinafter, with reference to the accompanying drawings, a schematic diagram showing a vertical-cavity surface-emitting laser (VCSEL) according to the present disclosure and a method for manufacturing the same will be described. For ease of understanding, the same reference numerals are used to denote the same elements common to each figure where possible.

[0016] FIG. 1 is a drawing schematically showing the layer structure of the VCSEL according to the present embodiment. FIG. 2 is a top view schematically showing the VCSEL according to the present embodiment. Specifically, FIG. 1 shows a cross section taken along line I-I of FIG. 2. FIGS. 1 and 2 show the VCSEL 11, and the VCSEL 11 is bonded to the submount 10a on the curved DBR side of the VCSEL 11 using solder bumps 10b. In each of parts (1), (2), and (3) of FIG. 1, the vertical axis represents reflectance (R), and the horizontal axis represents wavelength (W).

[0017] The VCSEL 11 includes a first distributed Bragg reflector (DBR) mirror 13, a semiconductor section 15, a dielectric filter layer 17, a second DBR mirror 19, and an oxide substrate 21. The dielectric filter layer 17 is disposed between the first DBR mirror 13 and the second DBR mirror 19. The oxide substrate 21 has a first surface 21a and a second surface 21b on the opposite side of the first surface 21a, and the second surface 21b includes a curved surface 21c. The semiconductor section 15 is disposed on the first surface 21a of the oxide substrate 21 and is disposed between the first DBR mirror 13 and the dielectric filter layer 17. The first DBR mirror 13, the semiconductor section 15, the dielectric filter layer 17, the oxide substrate 21, and the second DBR mirror 19 are arranged along a first axial direction Ax1 to form an extended optical cavity CAV. The first DBR mirror 13 is disposed on the semiconductor section 15, and the second DBR mirror 19 is disposed on the curved surface 21c of the oxide substrate 21. The dielectric filter layer 17 is disposed within the extended optical cavity CAV. The extended optical cavity CAV is formed by the first DBR mirror 13 and the second DBR mirror 19. The dielectric filter layer 17 has a reflection wavelength region and an optical window WIN defined by these reflection wavelength regions. The dielectric filter layer 17 functions as a bandpass filter near the wavelength λ0. The optical window WIN enables the light beam to travel within the optical cavity CAV at the laser oscillation wavelength, and the reflection wavelength region can block light of wavelengths outside the optical window WIN.

[0018] The semiconductor section 15 includes a p-type group-III nitride region 23, a group-III nitride active region 27, and a group-III nitride region 29, and the group-III nitride region 29 includes an n-type group-III nitride region 25. The group-III nitride active region 27 is disposed between the p-type group-III nitride region 23 and the group-III nitride region 29 (n-type group-III nitride region 25). The p-type group-III nitride region 23, the group-III nitride active region 27, and the group-III nitride region 29 (n-type group-III nitride region 25) are disposed in a first axial direction Ax1. In the VCSEL 11, the group-III nitride includes any compound of a group-III element such as aluminum, gallium, indium, and nitrogen, and specifically, binary alloys such as gallium nitride (GaN), aluminum nitride (AlN), and indium nitride (InN); ternary alloys such as gallium aluminum nitride (GaAlN), indium aluminum nitride (InAlN), and gallium indium nitride (GaInN); and quaternary alloys such as indium gallium aluminum nitride (InGaAlN), which may contain any trace impurities. The group-III nitride can be doped with a p-type dopant such as magnesium, carbon, and beryllium to form a p-type region, and can be doped with an n-type dopant such as silicon and tellurium to form an n-type region. The group-III nitride may be doped with both a p-type dopant and an n-type dopant.

[0019] The oxide substrate 21 includes one or more oxide materials, specifically, the following: aluminum oxide, such as Al 2 O 3 , whose bandgap is about 8.8 electron volts (eV); zinc oxide, such as ZnO, whose bandgap is about 3.37 eV; or gallium oxide, such as Ga 2 O 3 , whose bandgap is about 4.6 - 4.7 eV. These oxide materials such as aluminum oxide, zinc oxide, and gallium oxide are transparent to light in the visible, infrared, or ultraviolet wavelength range, and this light can pass through the oxide substrate 21.

[0020] The VCSEL 11 further includes a group-III nitride template plug 18 that extends from the first surface 21a of the oxide substrate 21 to the semiconductor section 15 within the through-hole 17a included in the dielectric filter layer 17. The through-hole 17a extends in the axial direction Ax1. The group-III nitride template plug 18 has an embedded portion 18a and a protrusion 18b as also shown in FIG. 3D. The embedded portion is located within the through-hole 17a and is disposed in contact with the first surface 21a of the oxide substrate 21, and the protrusion protrudes into the semiconductor section 15.

[0021] As shown in FIG. 1, the curved surface 21c of the oxide substrate 21 has a center line CNT, and the group-III nitride template plug 18 and the center line CNT of the curved surface 21c are misaligned.

[0022] The dielectric filter layer 17 has a reflection spectrum R3, and the reflection spectrum R3 is configured to provide an optical window WIN as shown in the (2) part of FIG. 1. Referring to FIG. 1, specifically, the dielectric filter layer 17 includes a plurality of dielectric layers 30 disposed on the oxide substrate 21, and the plurality of dielectric layers 30 are arranged to form a Fabry-Perot filter capable of providing the optical window WIN in the reflection spectrum R3.

[0023] The first DBR mirror 13 has a reflection spectrum R1 as shown in the (1) part of FIG. 1. The second DBR mirror 19 has a reflection spectrum R2 as shown in the (3) part of FIG. 1. The reflection spectra R1 and R2 each have a reflection wavelength bandwidth including the wavelength λ0.

[0024] The magnitude relationship of the reflection spectra R1, R2, and R3 is as follows. The reflectance values in each of the reflection spectra R1 and R2 are much larger than the reflectance value of the reflection spectrum R3. Also, the reflectance value of the reflection spectrum R2 may be larger than the reflectance value of the reflection spectrum R1.

[0025] The group-III nitride active region 27 has a quantum well structure, and the quantum well structure generates light, and the wavelength of this light is arranged within the first reflection spectrum R1, the second reflection spectrum R2, and the optical window WIN of the dielectric filter layer 17. The laser light is emitted, for example, through the first DBR mirror 13 having a reflectivity lower than that of the second DBR mirror 19.

[0026] Specifically, the first DBR mirror 13 includes a first dielectric layer 13a and a second dielectric layer 13b, and the first dielectric layer 13a and the second dielectric layer 13b are alternately arranged in the first axial direction Ax1, and the first DBR mirror 13 functions as, for example, a top mirror. The second DBR mirror 19 also has a third dielectric layer 19a and a fourth dielectric layer 19b, and the third dielectric layer 19a and the fourth dielectric layer 19b are alternately arranged in the first axial direction Ax1, and the second DBR mirror 19 functions as, for example, a bottom mirror. The dielectric filter layer 17 extends between the semiconductor section 15 and the first surface 21a of the oxide substrate 21.

[0027] In the VCSEL 11, the length of the extended optical cavity CAV can exceed 50 micrometers (>50 micrometers). The curved surface 21c has a radius of curvature exceeding 50 μm (>50 μm).

[0028] In the VCSEL 11, the first DBR mirror is planar, the second DBR mirror is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 may be greater than 50 μm. The semiconductor section 15 has a thickness exceeding 0.5 μm.

[0029] The VCSEL 11 further includes a conductive layer 35 disposed on the semiconductor section 15. The conductive layer 35 can include a group-III nitride semiconductor such as n-type GaN, or a conductive inorganic material such as indium tin oxide (ITO), or both. A part of the conductive layer 35 is disposed between the first DBR mirror 13 and the semiconductor section 15.

[0030] In VCSEL 11, the semiconductor section 15 has an aperture structure 39 that confines electric carriers and laser light. Optionally, the semiconductor section 15 may further include a tunnel structure on the uppermost layer of the semiconductor section 15 in addition to or instead of the aperture structure 39. The tunnel structure changes the type of conduction, i.e., changes one of electrons or holes to the other. The tunnel structure can be either a tunnel junction or an embedded tunnel junction. The tunnel junction can restrict the carrier path using the aperture structure 39, while the embedded tunnel junction can restrict the carrier path without using the aperture structure 39.

[0031] Referring to FIGS. 1 and 2, the semiconductor section 15 has a mesa structure 37. The mesa structure 37 includes a base region 37a and a mesa region 37b disposed on the base region 37a. The mesa region 37b is also provided with a p-type group III nitride region 23, a group III nitride active region 27, and a part of the n-type group III nitride region of the group III nitride region 25. The base region 37a includes the remaining portion of the group III nitride region 25. At the upper part of the base region 37a, the mesa region 37b may be surrounded by an n-type III nitride front surface 25a at the bottom of the n-type group III nitride region of the group III nitride region 25.

[0032] VCSEL 11 further includes a first electrode 31, e.g., an anode electrode, on the mesa region 37b and a second electrode 33, e.g., a cathode electrode, outside the mesa region 37b. In an exemplary VCSEL 11, the anode electrode is disposed in contact with ITO or a current diffusion layer (spread semiconductor layer), and the cathode electrode is disposed in contact with the upper surface 25a of the n-type group III nitride region 25 of the base region 37a. The first electrode 31 is disposed on the conductive layer 35 or the semiconductor section 15 outside the first DBR mirror 13 and may be in contact with the conductive layer 35 or the semiconductor section 15. The cathode electrode 33 may be disposed on the III-type nitride front surface 37c (25a) of the base region 37a outside the mesa region 37b.

[0033] In the VCSEL 11 including the conductive layer 31, the semiconductor section 15 has a first surface 15a and a second surface 15b opposite to the first surface 15a. The dielectric filter layer 17 is disposed in contact with the first surface 15a of the semiconductor section 15, and the conductive layer 31 is disposed in contact with the second surface 15b.

[0034] Referring to FIG. 1, FIG. 1 shows an overview of the VCSEL 11. The VCSEL 11 is provided with two high-reflection DBR mirrors 13 and 19, one of which is disposed on the curved surface of the oxide substrate 21. The oxide substrate 21 separates the two DBR mirrors 13 and 19 from each other and enables an extended optical cavity in a single-step integration. From the perspective of manufacturing the VCSEL 11, the semiconductor section 15 is grown along the dielectric filter layer 17 by epitaxial lateral overgrowth (ELO) from the group-III nitride template plug 18. Also, the dielectric filter layer 17 can have a Fabry-Perot multilayer film, and this Fabry-Perot multilayer film enables both a narrow optical bandpass at the wavelength and a large light-blocking region outside the narrow bandpass. The reflectivity of the dielectric filter layer 17 is designed to be very small at the laser oscillation wavelength compared to the reflectivity of each of the DBR mirrors 13 and 19.

[0035] Spacers 13 and 19 forming the extended cavity are widely spaced by oxide substrate 21, which allows the longitudinal mode spacing of the extended cavity to be very small, and this very small spacing facilitates having at least one of the longitudinal modes within the narrow bandpass window WIN of the dielectric filter layer 17. In contrast, spacers 13 forming the parasitic cavity and dielectric filter layer 17 are closely spaced by semiconductor section 15, which increases the longitudinal mode spacing of the parasitic cavity, and this large spacing facilitates having most or all of the longitudinal modes of the parasitic cavity located outside the narrow bandpass window WIN. There is a very high likelihood that all of the longitudinal modes of the parasitic cavity are located outside the narrow bandpass window WIN. The narrower bandpass window of dielectric filter layer 17, in combination with the broader reflection wavelength range of highly reflective DBR mirrors 13 and 19, realizes an extended optical cavity. The active region, i.e., the gain medium, can be aligned with DBR mirrors 13 and 19 such that the maximum value of the widely separated longitudinal mode field to be removed is offset from the location of the gain medium. VCSEL 11 includes several cavities, but at least one single longitudinal mode from the extended cavity within narrow bandpass window WIN is selected, and the light of the selected mode within narrow bandpass window WIN travels through the extended cavity between the flat mirror and the curved mirror and lases. Accordingly, the small mode spacing does not overly complicate aligning the selected mode with the gain spectrum, and the long cavity does not overly complicate aligning the selected mode with the gain medium.

[0036] VCSEL 11 is involved with the arrangement of the curved mirror on oxide substrate 21 and dielectric filter layer 17 such as a Fabry - Perot filter embedded between the flat mirror and the curved mirror of VCSEL 11. The curved mirror provides a lower diffraction loss with the extended optical cavity of VCSEL 11 by refocusing the incident electromagnetic radiation back to the gain medium with a reflectivity of approximately 90% by refocusing. In addition, oxide substrate 21 is made of a transparent oxide (TO) material, and the transparent oxide is ZnO, Ga 2 O3 or Al 2 O 3 comprising, wherein the transparent oxide material and the curved mirror can be made small enough to be negligible in light absorption therein, enabling lossless light propagation in a substantial part of the optical cavity of VCSEL11. This device structure enables a long cavity in VCSEL11 and better thermal performance.

[0037] Referring to FIG. 1, in VCSEL 11, a curved DBR mirror is provided as a bottom mirror, and the curved DBR mirror is disposed on the back surface of the substrate 21. From the perspective of manufacturing VCSEL 11, the curved DBR mirror is designed to be integrated in a simple manufacturing step, for example, by forming a patterned dielectric stack, i.e., DBR mirror 19, along the curved back surface of the substrate 21. In VCSEL 11, a planar DBR mirror is provided, and the planar DBR mirror is disposed on the front side of the substrate 21 as an upper mirror. From the perspective of manufacturing VCSEL 11, the planar DBR mirror is designed to be integrated in a simple manufacturing step, for example, by forming a patterned dielectric stack, i.e., DBR mirror 13, as an upper mirror along the plane of the semiconductor section 15. The planar DBR mirror 13 and the curved DBR mirror 19 form an extended cavity having a dielectric filter layer 17 embedded therebetween. The dielectric filter layer 17 preferably includes an antireflection coating or a Fabry - Perot structure, and the antireflection coating or the Fabry - Perot structure includes a dielectric material, exhibits narrow - band - pass characteristics near a desired wavelength, and reflects light of optical wavelengths outside the pass - band wavelength. From the perspective of manufacturing VCSEL 11, the semiconductor section 15 is formed by epitaxial lateral overgrowth (ELO) and is derived from a template plug 18, and the template plug 18 can be manufactured on the oxide substrate 21 by deposition and etching. The semiconductor section 15 includes a light - emitting structure, and in this light - emitting structure, a p - type group - III nitride region 23, an n - type group - III nitride region 25 of the group - III nitride region 29, and a group - III nitride active region 27 between the p - type group - III nitride region 23 and the n - type group - III nitride region 25 are provided.

[0038] The filter layer 17 can preferably be a Fabry - Perot structure made entirely of a dielectric. From the perspective of manufacturing the VCSEL 11, the dielectric filter layer 17 can function as an ELO mask, and the ELO mask enables epitaxial lateral overgrowth of III - nitrides from the III - nitride template plug 18 and prevents III - nitrides from depositing thereon. Also, the dielectric filter layer 17 functions as a support structure for the III - nitrides grown in this way by ELO on the oxide substrate. The ELO deposition of III - nitrides for the semiconductor section 15 embeds part of the dielectric filter layer 17. Accordingly, stacking the filter layer 17 is designed to provide an integration of simple steps of the thin semiconductor section 15 on the TO substrate 21 without substrate removal and bonding, and the filter layer 17 has an ELO mask structure. This filter layer 17 has optical properties that provide both a narrow - band pass that enables laser oscillation in the mode of the main optical cavity and a stop band that can prevent one or more modes of parasitic optical cavities from laser - oscillating.

[0039] The VCSEL 11 is provided with a first DBR mirror 13 on the semiconductor section 15, and the first DBR mirror 13 extends across the filter layer 17. The first DBR mirror 13 includes a first dielectric layer 13a and a second dielectric layer 13b alternately arranged in the first axial direction Ax1, and the material of the first layer 13a is different from that of the second layer 13b.

[0040] The VCSEL 11 is provided with a second DBR mirror 19, and the second DBR mirror 19 is separated from the first DBR mirror 13 by the semiconductor section 15 and the oxide substrate 21. The second DBR mirror 19 includes a third dielectric layer 19a and a fourth dielectric layer 19b alternately arranged in the first axial direction Ax1, and the material of the third layer 19a is different from the material of the fourth layer 19b.

[0041] The VCSEL 11 further includes an omnidirectional reflective layer 40. The omnidirectional reflective layer 40 covers the semiconductor section 15 and the dielectric filter layer 17, reflects stray light at the laser oscillation wavelength to the outside, thereby preventing the stray light from interfering with the laser oscillation in the cavity. The omnidirectional reflective layer 40 also functions as a passivation layer between the cathode electrode 33 and the anode electrode 31.

[0042] The cavity CAV can have an overall cavity length defined as the distance between a substantially flat surface disposed in contact with the first DBR mirror 19 and the curved surface 21c. In an exemplary structure of the VCSEL 11, the distance between the flat upper surface 21a of the TO substrate 21 and the curved surface 21c can be from 50 to 1000 μm, which is used as an extended cavity, and the thickness of the semiconductor section 15 is about 0.5 to 4 μm, which is also used as an extended cavity.

[0043] An aperture structure 39 is provided in the semiconductor section 15. The aperture structure 39 has a conductive opening 39a (conductive aperture portion) and a lower conductivity portion 39b surrounding the conductive opening 39a. The conductive opening 39a provides an electrical path between the anode electrode 31 and the cathode electrode 33 to the VCSEL 11. Carriers such as electrons and holes flow through the electrical path and recombine in the group III nitride active region to generate light, and this light exits from one of the DBR mirrors, for example, the first DBR mirror 13. The conductive opening 39a is disposed laterally away from the template plug 18 to reduce possible optical interference caused by the template plug 18. Preferably, the conductive opening 39a can be spaced at least about 3 micrometers from the sidewall of the template plug 18, and this distance is measured along the dielectric filter layer 17. The extended cavity has its main part constituted by the oxide substrate 21 and should be dimensionally designed such that the template plug 18 extends outside a substantial portion of the cone associated with the curved DBR mirror 19.

[0044] Referring to FIG. 2, the group-III nitride template plug 18, the curved surface 21c, and the aperture structure 39 are shown by dashed lines. In addition to the first axial direction Ax1, a second axial direction Ax2 and a third axial direction Ax3 are shown, and the three axial directions are orthogonal to each other. For example, the conductive opening 39a is arranged asymmetrically with respect to the linear template plug 18, and the asymmetric design facilitates both the arrangement of the anode electrode and the cathode electrode on the front side and the arrangement of the curved surface DBR mirror 19 on the back side. The semiconductor section 15 is formed by growing laterally outward on the dielectric filter layer from the upper surface and the exposed side wall surface of the group-III nitride template plug 18. This formation enables the group-III nitride template plug 18 to connect the semiconductor section 15 to the TO substrate 21, and the template plug 18 forms a heat path of group-III nitride that enables heat dissipation from the active region 27 to the oxide substrate 21. This structure provides a heat path to the VCSEL 11, ensuring that thermal energy is absorbed by the better thermally conductive TO substrate 21 through the template plug 18.

[0045] An exemplary manufacturing method of the VCSEL according to this embodiment will be described with reference to FIGS. 3A to 3R. FIGS. 3A to 3R are cross-sectional views each showing a certain step in the manufacturing method, and the cross-sectional views are taken along a line corresponding to the line I-I in FIG. 2. In order to avoid redundant descriptions below, the reference numerals used in FIGS. 1 and 2 are used whenever possible. In the following description, the group-III nitride can be deposited, for example, by metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0046] Referring to FIG. 3A, an oxide wafer 41 is prepared, which corresponds to the oxide substrate 21 of the VCSEL 11, and the oxide wafer 41 is ZnO, Ga 2 O 3 、Al 2 O 3It includes transparent materials such as this. Thereafter, a group III nitride film 43 such as gallium nitride (GaN) is deposited on the upper surface of the oxide wafer 41.

[0047] Referring to FIG. 3B, a resist mask 45 is formed on the group III nitride film 43, and the group III nitride film 43 is etched using the mask 45 to form one or more group III nitride template plugs 18. Each of the template plugs 18 has a width “W” and a height “H”. Each of the group III nitride template plugs 18 includes single-crystalline group III nitride having a very low defect density. For example, the group III nitride template plugs 18 may extend linearly along the upper surface of the oxide wafer 41 and may be arranged in parallel at a pitch of “P”.

[0048] Referring to FIG. 3C, a dielectric multilayer film 47 is deposited on the oxide wafer 41 and over the group III nitride template plugs 18. The dielectric multilayer film 47 has a thickness smaller than the thickness of the group III nitride film 43 and the height of the group III nitride template plugs 18, and may have a structure capable of forming a Fabry - Perot filter of the group III nitride film 43.

[0049] The dielectric multilayer film 47 for an exemplary dielectric Fabry - Perot structure has the following exemplary layer structure: “(HL)m2nH(LH)m”. Here, “H” and “L” represent a high - refractive - index layer and a low - refractive - index layer, respectively. Each of these layers has an optical thickness of a quarter - wavelength, and “m” and “n” are integers. Specifically, the notation “(HL)m” indicates that the high - refractive - index layer and the low - refractive - index layer are alternately laminated m times. The notation “2nH” indicates a thickness 2n times that of the high - refractive - index layer. The notation “(LH)m” indicates that the low - refractive - index layer and the high - refractive - index layer are alternately laminated m times. Designing the Fabry - Perot spectrum (R3) with respect to the refractive index and layer thickness of the dielectric material enables both a high - transmittance optical window at the central wavelength λ0 and high - reflection spectral regions on both sides of the high - transmittance optical window.

[0050] Referring to FIG. 3D, the dielectric filter layer 17 is fabricated from the dielectric multilayer film 47 by processing the dielectric multilayer film 47 by etching. A mask (not shown) is used in the etching process. The mask is formed on the dielectric multilayer film 47 and has respective openings at the positions of the group-III nitride template plugs 18. Each of the group-III nitride template plugs 18 is positioned in a corresponding opening of the dielectric filter layer 17 thus formed and has a lower part and an upper part. The lower part 18a of the group-III nitride template plug 18 is embedded in the opening of the dielectric filter layer 17, and the upper part 18b of the group-III nitride template plug 18 protrudes from the upper surface of the dielectric filter layer 17.

[0051] In the process of obtaining the intermediate product shown in FIG. 3D, a starting base 51 is prepared. The starting base 51 is provided with the arrangement of the group-III nitride template plugs 18, a dielectric filter, and an oxide base as the oxide wafer 41. The oxide wafer 41 has a first surface 41a and a second surface 41b opposite to the first surface 41a. The dielectric filter layer 17 and the group-III nitride template plugs 18 are disposed on the first surface 41a. The reflection spectrum (R3) of the dielectric filter layer 17 extends along the first surface 41a and is configured to provide an optical window (WIN). Light travels in the extended optical cavity between the planar DBR mirror 13 and the curved DBR mirror 19 and passes through the dielectric Fabry-Perot filter twice for each optical round trip. The dielectric filter layer 17 is provided with a Fabry-Perot filter structure, and the Fabry-Perot filter structure provides a narrow-band passband and rejection bands that provide rejection on both sides thereof. If necessary, the dielectric multilayer film 47 can be deposited and patterned to form strip-shaped openings. The strip-shaped openings are periodically arranged on the first surface 41a of the oxide wafer 41, and group-III nitride can be selectively grown in the strip-shaped openings to form the nitride template plugs 18.

[0052] Referring to FIG. 3E, after forming the starting base 51 including the arrangement of the dielectric filter layer 17 and the group III nitride template plug 18, the group III nitride region 52 is epitaxially grown on the starting base 51 from the group III nitride template plug 18 along the dielectric filter layer 17. The group III nitride region 52 is grown by ELO from the side and top surfaces of the group III nitride template plug 18 to form wing-shaped group III nitride islands, and adjacent group III nitride regions 52 are separated from each other. These group III nitride islands are formed by the deposition of group III nitride materials by ELO from the template plug 18 and define a dicing street "D" running between adjacent group III nitride islands. The dicing street "D" also defines individual VCSEL sections, and the VCSEL sections correspond to individual VCSEL section chips. The group III nitride region 52 may be partially or entirely doped with an n-type dopant and may extend outward from the template plug 18.

[0053] Referring to FIG. 3F, if necessary, before growing the subsequent semiconductor stack, the group III nitride region 52 is planarized by at least one of polishing or etching to form a group III nitride region 53 having a flat upper surface 53a.

[0054] Referring to FIG. 3G, after growing the group III nitride region 53, a semiconductor stack 55 is epitaxially formed, and the semiconductor stack 55 includes a group III nitride device layer. The group III nitride device layer is provided with an n-type group III nitride region 25, a group III nitride active region 27, and a p-type group III nitride region 23. Specifically, the n-type group III nitride region 25, the group III nitride active region 27, and the p-type group III nitride region 23 are grown in sequence on the flat surface of the group III nitride region 53.

[0055] Specifically, the nitride region 25 can include a GaN-based or AlN-based material doped with an n-type dopant, which enables the supply of electrons to the III-nitride active region 27. Also, the nitride region 25 can include a GaN-based or AlN-based material doped with a p-type dopant, which enables the supply of holes to the III-nitride active region 27. The III-nitride active region 27 can include a GaN-based or AlN-based material such as GaN, InGaN, AlN, AlGaN, or AlInGaN. The group-III nitride active region 27 may be provided with a single well layer or a quantum well structure such as a single quantum well (SQW) or a multiple quantum well (MQW). If necessary, an embedded tunnel junction or a plurality of tunnel junction layers can be grown after depositing the p-type group-III nitride region 23.

[0056] Referring to FIG. 3H, after growing the semiconductor stack 55, the oxide wafer 41 is processed on the second surface 41b to form a curved surface 41c and a newly formed back surface 41d, which are generated from the second surface 41b, and if necessary, the second surface 41b may be a polished surface. Specifically, the curved surface 41c of the oxide wafer 41 functions as a microlens 45a. The curved surface 41c of the oxide wafer 41 has a central axis CNT, and as shown in FIG. 3H, the group-III nitride template plug 18 and the central axis CNT of the curved surface 41c are not aligned with each other. The oxide wafer 41, such as a sapphire wafer, is processed on its polished surface to produce a curved surface 41c such as a microlens 45a and a back surface 41d. The curved surface 41c can be positioned at a predetermined position so that the focus of the microlens 45a helps to identify the position of the aperture structure that confines carriers. The aperture structure will be described later.

[0057] As shown in FIGS. 3H to 3J, the curved surface 41c functions as a microlens and can be manufactured using the thermal reflow technique referred to in Non-Patent Document 11. Specifically, as shown in FIG. 3I, a resist film is formed on the back side of the oxide wafer 41 and processed by standard photolithography to form a patterned resist 57 such as a photoresist microdisk 45a. Next, as shown in FIG. 3J, the patterned resist 57 is subjected to heat treatment at a high temperature, for example, using a hot plate. The high-temperature heat treatment deforms the patterned resist 57 into a lens-like shape, and the patterned resist 57 can be used as a sacrificial photoresist mask 58. Further, as shown in FIG. 3H, the lens-shaped resist 58 and the back surface 41b of the oxide wafer 41 can be processed by reactive ion etching (RIE). As a result, the shape of the lens-shaped resist 58 is transferred to the oxide wafer 41. Specifically, the oxide wafer 41 is thinned, and a curved surface 41c such as a microlens 45a remains on the back surface 41d of the thinned oxide wafer. The thinned oxide wafer is referred to as an oxide substrate 42. Thinning the oxide wafer 41 can adjust the length of the extended optical cavity. Accordingly, this process enables not only the formation of the curved surface 41c but also the adjustment of the cavity length.

[0058] Referring to FIG. 3K, a photoresist film 59 is formed on the front surface of the oxide substrate 42 to cover the semiconductor laminate 55 and the dielectric filter layer 17. Then, the curved surface 41c of the back surface 41d of the oxide substrate 42 is irradiated with exposure light 60 using a photomask 56 through which the exposure light 60 passes. The exposure light 60 passes through the curved surface 41c and focuses at a point, for example, on a portion of the photoresist film 59 covering the upper surface of the semiconductor laminate 55, thereby forming an exposed portion 59a of the photoresist film 59.

[0059] Referring to FIG. 3L, developing the exposed photoresist film 59 forms a resist mask 61 having a patterned opening 61a. Next, the film 63 is deposited both on the resist mask 61 and within the patterned opening 61a, and removal of the resist mask 61 leaves a mask 64 fabricated from the film 63. The film 63 can consist of Ti / Au or a dielectric layer.

[0060] Referring to FIG. 3M, to fabricate the VCSEL 11 without an embedded tunnel junction, it is necessary to form an aperture structure 65. Specifically, the mask 64 is used to perform ion implantation to form the aperture structure 65. The aperture structure 65 thus formed includes an opening region 65a and a separation region 65b surrounding the opening region 65a. Using the mask 64 to implant ions such as hydrogen atoms, n-type dopant atoms, and / or p-type dopant atoms into the semiconductor stack 51 generates the aperture structure 65 in the semiconductor stack 55. The aperture structure 65 includes a semiconductor opening region 65a capable of forming an electrical path for carriers to flow and a separation region 65b capable of confining light and carriers in the semiconductor opening region 65a. After ion implantation, the mask 64 is removed.

[0061] Alternatively, the fabrication of the VCSEL 11 in which the semiconductor stack 55 includes an embedded tunnel junction requires patterning a tunnel layer such as p ++ GaN and n ++ GaN, and the semiconductor stack 55 may include a tunnel layer. Specifically, the tunnel layer can be etched using the mask 64 to form an embedded tunnel junction. After etching, the mask 64 is removed, and then regrowth of the group III nitride is performed to deposit a doped semiconductor layer covering the embedded tunnel junction, and the doped semiconductor layer functions as a current spreader.

[0062] Referring to FIG. 3N, after removing the mask 64 in the manufacture of the VCSEL 11 without an embedded tunnel junction, the conductive layer 67 is deposited on the semiconductor laminate 55 so as to cover both the semiconductor opening region 65a and the separation region 65b. The conductive layer 67 can include a group III nitride semiconductor layer doped at a high concentration such as GaN or AlGaN, and / or an inorganic layer such as indium tin oxide (ITO), and is transparent to the light from the group III nitride active region 27. For example, the conductive layer 67 can be deposited on the oxide substrate 42 without using a mask.

[0063] Referring to FIG. 3O, a mesa structure 69 is fabricated from the semiconductor laminate 55. Specifically, a photoresist is formed on the oxide substrate 42a so as to cover the semiconductor laminate 55 and patterned to form a resist mask 71. The resist mask 71 is used to expose the n-type GaN region lying under the semiconductor laminate 55 by etching, thereby forming the mesa structure 69, which includes the group III nitride active region 27 and the p-type group III nitride region 23. Outside the mesa structure 69, an etched surface 69a of the n-type group III nitride region is formed from the semiconductor laminate 55.

[0064] Referring to FIGS. 3P and 3Q, after forming the mesa structure 69 with the resist mask 71 remaining on the oxide substrate 42, the omnidirectional reflector (ODR) layer 73 is formed by depositing an omnidirectional reflective film 73 over the oxide substrate 42 and the resist mask 71 and then removing the resist mask 71, i.e., by lift-off. As shown in FIG. 3P, the thus formed ODR layer 73 covers the side surface of the mesa structure 69 and the upper part of the dielectric filter layer 17 and has an opening at the upper part of the mesa structure 69. The ODR layer 71 functions as a reflector for stray light of the oscillation wavelength of the VCSEL 11 and also functions as a passivation layer between the anode electrode and the cathode electrode formed in a later process step.

[0065] Referring back to FIG. 3Q, after forming the ODR layer 73, the first distributed Bragg reflector (DBR) stack 75 and the first electrode 77 are formed by lift-off on the conductive layer 67, and the second electrode 79 is formed by lift-off on the etching surface 69a of the n-type group III nitride region 25 outside the mesa structure 69.

[0066] Specifically, the first DBR stack 75 can be formed by lift-off and is aligned with the aperture structure 65 or the embedded tunnel junction. The first electrode 77, such as an anode electrode, is disposed outside the first DBR stack 75 and is disposed in contact with the conductive layer 67 or the regrown semiconductor layer. The second electrode 79, such as a cathode electrode, can be disposed outside the mesa structure 69 after patterning the ODR layer 73 to form an opening in the ODR layer 73. This opening in the ODR layer 73 enables the second electrode 79 to be disposed in contact with the etched n-type group III nitride surface 69a of the group III nitride region 25.

[0067] Referring to FIG. 3R, the second DBR mirror stack 81 is formed on the curved surface 41c of the oxide substrate 42. If necessary, the second DBR mirror stack 81 can be patterned to expose a part of the back surface 41d of the oxide substrate 42, and then a bonding material such as a solder ball can be formed on the exposed back surface 41d of the oxide substrate 42.

[0068] The above steps complete a VCSEL, for example, VCSEL 11. This structure enables the thus fabricated VCSEL 11 to be bonded to the submount on the curved DBR side using solder bumps.

[0069] FIG. 4A is a perspective view showing one chip section including the template plug 18, the curved surface 41c as a lens structure, and the aperture structure 65 in the mesa structure 69. FIG. 4B is a plan view showing two chip sections on the oxide substrate 42 to which the above manufacturing process is applied.

[0070] In the above manufacturing method, the oxide substrate thus manufactured is separated into VCSEL chips by a separation process such as dicing and / or etching. It should be noted that the present oxide substrate is provided with an arrangement of a mesa structure and a dicing street extending between adjacent mesa structures. The dicing street of the present product thus manufactured does not contain any semiconductor structure. The non-directional filter layer covers the upper surface of the oxide substrate except for the upper part of the mesa structure and can be removed at the position of the dicing street by photolithography and etching if necessary. Since the second DBR laminate is patterned and arranged on and around the curved surface 41c, no material covers the dicing street at the position of the back surface of the oxide substrate.

[0071] In the VCSEL 11 manufactured in this way, the length of the extended optical cavity CAV can exceed 50 micrometers (>50 micrometers). The curved surface 41c has a radius of curvature exceeding 50 micrometers (>50 micrometers).

[0072] In the VCSEL 11, the first DBR mirror 13 is planar and the second DBR mirror 19 is curved, and the distance between the first DBR mirror 13 and the second DBR mirror 19 is greater than 50 μm. The thickness of the semiconductor section 15 is greater than 0.5 μm.

[0073] In FIGS. 4A and 4B, the hemispherical circle 44 indicates a virtual sphere extending along the curved surface 41c. For example, when the radius of curvature R0 of the curved mirror 21c is about 100 μm, the hemispherical circle 44 has a diameter "DIA" of 200 μm on the upper surface 21a.

[0074] The spacing between adjacent template plugs 18 is associated with a fill factor that indicates the ratio of the total area of the device sections on a single wafer to the upper area of the wafer. The dicing streets define the arrangement of the chip regions, and each of the chip regions is provided for a single VCSEL device. The template plugs 18 may be arranged periodically in one direction, may be long microstrips across the entire wafer, may be microstrips terminated in the length direction within a single chip dimension, or may be terminated stripes arranged in a checkerboard pattern. Also, the template plugs 18 may be partially interleaved at their ends, if necessary, to obtain an advantage of growth, namely, reduction of the edge effect.

[0075] The arrangement of the template plugs 18 is associated with the position of the dicing streets. The semiconductor sections grown from the template plugs cannot be enlarged due to ELO, and the ELO of the semiconductor sections ends before reaching adjacent semiconductor sections.

[0076] Preferably, the size of the semiconductor section should be provided with a certain size that is wider than the width of the aperture in the design of the aperture structure and smaller than the period of the array of the template plugs 18.

[0077] Preferably, the dicing streets should exclude the group III nitride material to be sliced. Slicing of the oxide substrate can be performed in the dicing streets by a dicing blade, laser scribing and / or plasma etching. One of the advantages of having no group III nitride material in the dicing streets is to save semiconductor layers from being discarded.

[0078] The conductive aperture portion of the aperture structure can be disposed near the end of the wing-shaped semiconductor island, and the wing-shaped semiconductor island is grown outward by ELO from a certain template plug. The advantages of this device are to accommodate electrical pads on the chip surface and to reduce crystal defects and irregularities that may be included in the immediate vicinity of the template plug. Another advantage is to separate the aperture structure from a reference plane extending perpendicular to the upper surface of the oxide substrate at the center of the template plug, thereby eliminating optical losses.

[0079] A narrower dicing street allows more device sections to be placed on a single wafer.

[0080] Figures 5 through 7 are schematic diagrams each showing an exemplary arrangement of device sections on a TO substrate. Referring to Figures 5 through 7, a typical arrangement of device sections on a TO substrate is shown. The device sections are arranged to form a two-dimensional array, and a dicing street D runs to define the array. In Figures 5 and 6, the hemispheres 44 are separated from each other. In Figure 7, the hemispheres 44 are partially overlapped while the curved surfaces 21 are separated from each other. The boundaries of the device sections 46 are indicated by dashed lines.

[0081] One skilled in the art will be able to understand various modifications from the above arrangements, for example, a denser version or a less dense version of the arrangement of the VCSEL device sections.

[0082] Figure 8 is a schematic drawing showing a VCSEL according to an embodiment of the present disclosure. The VCSEL 11 is provided with an aperture structure 39 and a conductive layer 35 for confining carriers and laser light. The conductive layer 35 forms an electrical path from the first electrode 31 to the conductive aperture 39a of the aperture structure 39. The first electrode 31 is disposed adjacent to the first DBR mirror 13 and the conductive aperture 39a is disposed directly below the first DBR mirror 13 in alignment with the cavity.

[0083] An exemplary process flow in the manufacturing method of VCSEL11 is described, where VCSEL11 includes a conductive layer that functions as a current diffusion layer.

[0084] This method includes the following steps. 1. Preparing a starting base. Here, preparing the starting base includes forming a GaN template plug that extends straight on the TO wafer in a second axis direction Ax2 perpendicular to the first axis direction Ax1; forming a dielectric Fabry - Perot filter structure over the entire TO wafer with the sidewalls of the template plug partially exposed and the top surface of the template plug fully exposed. 2. Growing an unintentionally doped GaN layer (n - GaN) from the exposed GaN of the template plug along the top surface of the Fabry - Perot filter structure by ELO to form a semiconductor base region with a total width of about 30 to 50 μm in a third axis direction Ax3 perpendicular to both the first axis direction Ax1 and the second axis direction Ax2. 3. Performing planarization of the semiconductor base region to form a planarized n - GaN layer. 4. Growing a semiconductor stack on the planarized n - GaN layer, where the semiconductor stack includes device layers, for example, n - GaN for cladding and n - contact, InGaN multiple quantum wells, an AlGaN electron blocking layer, and a p - GaN layer, and including a p ++ GaN layer if necessary. 5. Polishing the back surface of the TO wafer. 6. Transferring a resist pattern formed by reflow to the back surface of the TO wafer by reactive ion etching to form a monolithic microlens. 7. Fabricating a resist mask through back - side exposure from a resist film covering the device layer, where in the back - side exposure, the monolithic microlens is used to focus the exposure light at a focal point positioned around the resist film. 8. Forming a mask on the device layer using the resist mask. 9. Performing ion implantation using a mask to define an aperture structure. 10. Depositing a transparent conductive oxide (TCO). 11. Fabricating a mesa structure in a semiconductor laminate. 12. Depositing a passivation film of an omni-directional reflector (ODR) material having an opening on the upper surface of the mesa structure. 13. Depositing a dielectric distributed Bragg reflector laminate on the flat upper surface of the device layer of the mesa structure. 14. Depositing an electrode metal pad on a semiconductor laminate including the mesa structure. 15. Depositing a dielectric distributed Bragg reflector laminate on the curved surface of a TO substrate. 16. Placing an adhesive on the back surface of the TO substrate. 17. Separating the thus fabricated TO wafer to form a VCSEL chip. 18. Adhering the VCSEL chip to a submount.

[0085] The VCSEL chip can be used in user-defined applications such as a light source, a sensor, or both.

[0086] FIG. 9 is a drawing schematically showing a VCSEL according to another embodiment of the present disclosure. The VCSEL 11a is provided with a tunnel junction structure 36 and an aperture structure 39. The tunnel junction structure 36 forms an electrical path from the first electrode 31 to the conductive opening 39a. The first electrode 31 is disposed adjacent to the first DBR mirror 13, and the conductive opening 39a is disposed directly below the first DBR mirror 13 and confines carriers and laser light. The tunnel junction structure 36 includes a group III nitride layer 36a in the aperture structure 39 and an n-group III nitride layer 36b on the mesa structure 36. The p-group III nitride layer 36a and the n-group III nitride layer 36b are in contact with each other to form a tunnel junction. This tunnel junction is embedded by an additional group III nitride layer 36c. ++ Group III nitride layer 36a, and an n- ++ Group III nitride layer 36b on the mesa structure 36, and the p- ++ Group III nitride layer 36a and the n- ++ Group III nitride layer 36b are in contact with each other to form a tunnel junction. This tunnel junction is embedded by an additional group III nitride layer 36c.

[0087] An exemplary process flow in the manufacturing method of VCSEL11a is described. VCSEL11a includes a highly doped n ++ layer and an n-type semiconductor layer, and this layer functions as a current spreading layer (current spreader). The n ++ type semiconductor layer contacts the uppermost p ++ type semiconductor layer to form a tunnel junction 36.

[0088] This method includes the following steps. 1. Preparing a starting base, which includes forming a GaN template plug. The template plug runs straight on the TO wafer in a second axial direction Ax2 perpendicular to a first axial direction Ax1. While the sidewalls of the template plug are partially exposed and the upper surface of the template plug is completely exposed, a dielectric Fabry-Perot filter structure is formed across the entire TO wafer. 2. By ELO, an unintentionally doped GaN layer (n-GaN) is grown from the exposed GaN of the template plug along the upper surface of the Fabry-Perot filter structure to form a semiconductor base region having a total width of about 30 to 50 μm in a third axial direction Ax3 perpendicular to the first axial direction Ax1 and the second axial direction Ax2. 3. Performing planarization of the semiconductor base region to form a planarized n-GaN layer. 4. Growing a semiconductor stack on the planarized n-GaN layer. The semiconductor stack includes device layers, such as n-GaN for cladding and n-contact, InGaN multiple quantum wells, AlGaN electron blocking layers, p-GaN layers, and p ++ GaN layers. 5. Polishing the back surface of the TO wafer. 6. Transferring a resist pattern formed by reflow to the back surface of the TO wafer by reactive ion etching to form a monolithic microlens. 7. Fabricating a resist mask through backside exposure, where in the backside exposure, a monolithic microlens is used to focus the exposure light at a focal point positioned around the resist film. 8. Forming a mask on the device layer using the resist mask. 9. Performing ion implantation using the mask to define an aperture structure. 10. After forming the aperture structure, regrowing an n ++ GaN layer to complete the tunnel junction, and further depositing an n ++ GaN layer for contact and current diffusion on the n-GaN layer. 11. Fabricating a mesa structure from a semiconductor laminate including the device layer and the tunnel junction. 12. Depositing a passivation film of an omni-directional reflector (ODR) material having an opening for a contact area on the upper surface portion of the mesa structure. 13. Depositing a dielectric distributed Bragg reflector laminate on the flat upper surface of the device layer. 14. Depositing an electrode metal pad on the semiconductor laminate including the mesa structure. 15. Depositing a dielectric distributed Bragg reflector laminate on the curved surface of the TO substrate. 16. Placing an adhesive on the back surface of the TO substrate. 17. Separating the thus fabricated TO wafer to form a VCSEL chip. 18. Bonding the VCSEL chip to a submount.

[0089] The VCSEL chip can be used in user-defined applications such as a light source, a sensor, or both.

[0090] FIG. 10 is a drawing schematically showing a VCSEL according to still another embodiment of the present disclosure. The VCSEL 11b is provided with an embedded tunnel junction structure 38 without an aperture structure 39. The embedded tunnel junction 38 is arranged aligned with the cavity directly below the first DBR mirror 13, and is covered with a current diffusion layer (current spreader) to define an electrical path from the first electrode 31 to the embedded tunnel junction 38. The first electrode 31 is placed next to the first DBR mirror 13, and the embedded tunnel junction 38 is used to confine carriers and laser light.

[0091] An exemplary process flow in a method of manufacturing the VCSEL 11b is described. The VCSEL 11b includes an embedded tunnel junction structure 38, and the embedded tunnel junction structure 38 includes highly doped n ++ -type and p ++ -type semiconductor layers, and an n-type semiconductor layer. The n-type semiconductor layer covers the embedded tunnel junction structure 38 and functions as a current diffusion layer (current spreader). The embedded tunnel junction 38 includes a patterned p ++ -III nitride layer 38a and an n ++ -III nitride layer 38b. The p ++ -III nitride layer 38a and the n ++ -III nitride layer 38 are arranged on the mesa structure 36. The p ++ -III nitride layer 38a and the n ++ -III nitride layer 38 are in contact with each other to form a tunnel interface and are embedded by an additional III-nitride layer 38c. The additional group-III nitride layer 38c is grown on the mesa structure 37 so as to form a substantially flattened upper surface. The first electrode 31 is arranged in contact with the group-III nitride layer 38c, and the first DBR mirror 13 is arranged on the upper surface of the group-III nitride layer 38c.

[0092] This method includes the following steps. 1. Preparing a starting base, which includes forming a GaN template plug that runs straight on a TO wafer in a second axial direction Ax2 perpendicular to a first axial direction Ax1. Forming a dielectric Fabry - Perot filter structure across the entire TO wafer with the sidewalls of the template plug partially exposed and the top surface of the template plug fully exposed. 2. Growing an unintentionally doped GaN layer (n - GaN) from the exposed GaN of the template plug along the top surface of the Fabry - Perot filter structure by ELO to form a semiconductor base region having a total width of about 30 to 50 μm in a third axial direction Ax3 perpendicular to the first axial direction Ax1 and the second axial direction Ax2. 3. Performing planarization of the semiconductor base region to form a planarized n - GaN layer. 4. Growing a semiconductor stack on the planarized n - GaN layer, where the semiconductor stack includes device layers, such as n - GaN for cladding and n - contact, InGaN multiple quantum wells, AlGaN electron blocking layer, p - GaN layer, and p ++ GaN layer. 5. Polishing the back surface of the TO wafer. 6. Transferring a resist pattern formed by reflow to the back surface of the TO wafer by reactive ion etching to form a monolithic microlens. 7.p ++ Regrowing an n ++ GaN layer on the GaN layer to complete the tunnel junction. 8. Fabricating a resist mask from a resist film on the device layer through back - side exposure, where in the back - side exposure, the monolithic microlens is used to focus the exposure light at a focus arranged around the resist film. 9. Pattern - forming the tunnel junction using the resist mask to complete an embedded tunnel junction on the device layer. 10. After forming the embedded tunnel junction, deposit an n-GaN layer covering the embedded tunnel junction to form a planarized upper surface of the n-GaN. 11. Fabricate a mesa structure from the semiconductor stack. 12. Deposit a passivation film of an omni-directional reflector (ODR) material having an opening for a contact area on the upper surface of the mesa structure. 13. Deposit a dielectric distributed Bragg reflector stack on the flat upper surface of the device layer. 14. Deposit an electrode metal pad on the semiconductor stack including the mesa structure. 15. Deposit a dielectric distributed Bragg reflector stack on the curved surface of the TO substrate. 16. Place an adhesive on the back surface of the TO substrate. 17. Separate the thus fabricated TO wafer to form a VCSEL chip. 18. Bond the VCSEL chip to a submount.

[0093] The VCSEL chip can be used in user-defined applications such as a light source, a sensor, or both.

[0094] Furthermore, the manufacture of semiconductor chips in the background art surely includes growing an epitaxial device layer on a wafer and dicing both the device layer and the wafer. The area for dicing and singulating the chips may require at least 10% of the processing area of the wafer.

[0095] There are three approaches to manufacturing a semiconductor chip, such as an extended cavity VCSEL.

[0096] Approach 1 The entire device layer is first epitaxially grown on a flat GaN substrate. After growth, the GaN substrate is thinned by polishing its back surface, and then a curved surface for an optical cavity such as a microlens is formed on the polished back surface.

[0097] Approach 2 The entire device layer is first epitaxially grown on a flat GaN substrate. After growth, the GaN substrate is removed to form a device stack including the device layer, and then the device stack is bonded to a heterogeneous substrate, which has a curved surface for an optical cavity, such as a microlens, on its back surface.

[0098] Approach 3 Approach 3 includes a manufacturing flow according to the present disclosure. Compared with Approach 1 and Approach 2, the integration of the extended cavity in Approach 3 is a simple step procedure that does not require removing and thinning the substrate. The dicing street can be arranged between semiconductor sections. The manufacturing flow according to the present disclosure enables various arrangements of device sections, such as a high arrangement density of device sections on a wafer.

[0099] Multiple Exemplifications

[0100] Transparent Oxide (TO) Substrate Material The microlens is integrated with the device layer on the TO substrate. The device layer is also grown on the TO substrate. The material of the TO substrate includes ZnO, Ga 2 O 3 、Al 2 O 3 、and other materials, and these materials are transparent to infrared, visible, near-ultraviolet, and / or deep-ultraviolet wavelengths depending on the material. The VCSEL device of the present disclosure is provided with a cavity mainly occupied by a low-absorption TO substrate. This enables the use of large TO wafers, such as sapphire wafers with a size exceeding 6 inches, in the manufacture of VCSEL devices, which results in the ability to manufacture many devices from a single manufacturing run.

[0101] Template Plug Start with a TO wafer on which a group-III nitride template plug is mounted. The height of the group-III nitride template plug can be from 1 μm to 10 μm. The crystal quality of the group-III nitride layer for the template plug increases with the thickness. Increasing the thickness of the group-III nitride layer can terminate threading dislocations within the layer, and the threading dislocations originate from lattice mismatch at the substrate interface. Further, a larger thickness provides a thick Fabry-Perot filter structure to the dielectric filter layer, and the thick Fabry-Perot filter structure can help characterize and form a very narrow band-pass region and a better stop region outside the band-pass. The thicker Fabry-Perot filter fills the lower sidewall portion of the template plug, and the lower sidewall portion may contain most of the defects.

[0102] For example, the template plug may be in a stripe shape parallel to the <11-20> axis of a hexagonal group-III nitride such as GaN. When forming the template plug, etching a group-III nitride film having a (0001) polar orientation provides sidewalls of the (11-22) plane to the template plug stripes thus formed. Such sidewall orientation can promote subsequent lateral growth from the sidewalls. If necessary, another orientation that promotes lateral growth can be provided to the sidewalls of the group-III nitride template plug. Alternatively, the template plug may be provided with a desired orientation that enables the growth of the group-III nitride layer along the dielectric filter layer.

[0103] Fabry-Perot filter / antireflection The use of a Fabry-Perot filter structure is one of the desirable designs for creating a narrowband filter. The Fabry-Perot filter provides both a narrow passband and stopbands on both sides of the passband. The Fabry-Perot filter can be placed within a single laser cavity and includes a central spacer and two equivalent reflective mirrors sandwiching the central spacer. The central spacer has a certain thickness, generally half the thickness of the laser wavelength, and the two equivalent reflective mirrors are equivalent to a DBR mirror structure.

[0104] A typical all-dielectric structure is as follows: "Substrate 1 / (HL)m / 2nH / (LH)m / Substrate 2". Substrate 1 and Substrate 2 can be a GaN layer and a TO substrate, i.e., sapphire, respectively. "H" and "L" represent respective layers with a high refractive index and a low refractive index and their optical thickness of a quarter wavelength, and "m" and "n" are integers. The general thickness of the entire structure at an exemplary operating wavelength of 450 nm ranges from 1 to 2 μm, or can be made somewhat thicker. The Fabry-Perot structure in an optimized design enables a very narrow bandpass, e.g., an optical window "WIN", near the central operating wavelength "λ0", and the Fabry-Perot structure in an optimized design can be provided with a thickness exceeding 2 μm. "WIN" can be made even narrower by increasing the number of dielectric layers and finely adjusting the thickness of each layer. The Fabry-Perot structure can be provided with a surface roughness of less than 1 nm, preferably, the roughness can be from 0.1 to 1 nm in root mean square (RMS). The dielectric layers of the Fabry-Perot structure can be deposited by sputtering, atomic layer deposition, ion beam deposition, etc. The Fabry-Perot filter comprises two reflectors and a central layer of a high refractive index material. Each of the two reflectors includes a high refractive index material and a low refractive index material deposited alternately such as 2 and HfO 2 and each of these layers has a thickness of a quarter wavelength. The central layer of the high refractive index material has a thickness of half the central operating wavelength and is placed between these reflectors.

[0105] Epitaxial lateral overgrowth The group III nitride template plugs disposed on the TO substrate can be shaped in a stripe form, and the lower sidewalls of the template plugs are made of SiO 2 , Ta 2 O 5 , HfO 5 and are embedded in a Fabry-Perot filter structure made of all dielectric materials such as these. The upper surface of the template plug has few defects. The thickness of the plug is preferably designed to enable a thick Fabry-Perot filter that generates a very narrow bandpass width "WIN". The sidewalls of the plug are exposed to about 1 to 2 μm, and the width of the upper surface of the plug is about 1 to 10 μm. The stripes are arranged at a period of 50 to 200 μm. The stripes are provided with a length that matches the length of the device section or may be much longer than that. The polar template plug is provided with an upper surface orientation of the c-plane (0001), and accordingly, the stripes of the template plug can be oriented along the <11-20> axis. Alternatively, the non-polar template plug is provided with an upper surface orientation of the a-plane (11-20) or the m-plane (1100), and accordingly, the stripes of the template plug are oriented along the <0001> axis. Further, the semi-polar template plug is provided with an upper surface orientation of the (20-21) plane or the (20-2-1) plane, and accordingly, the stripes of the template plug are oriented along a direction parallel to [-1014] or [10-14], respectively. Other orientations can likewise be used for stripes oriented in the corresponding directions.

[0106] A TO wafer with a template plug mounted in a state where the sidewalls are partially exposed is loaded into an MOCVD reactor to grow group-III nitride islands. In one embodiment, the growth pressure ranges from 50 to 760 Torr, and the growth pressure is preferably in the range of 100 to 300 Torr, providing a wide width to the island-shaped (island-like) group-III nitride semiconductor layer. The growth temperature ranges from 900 degrees Celsius to 1200 degrees Celsius. The V / III ratio ranges from 10 to 30000. The range of the TMG flow rate is from 2 to 20 standard cubic centimeters per minute (sccm). The flow rate range of NH 3 is from 0.1 to 10 standard liters per minute (slm). Only hydrogen gas, or both hydrogen gas and nitrogen gas, are used as carrier gases. The growth conditions of the III-nitride islands can be optimized to obtain a smooth surface. Finally, a III-nitride layer, such as GaN layer 25, is grown by ELO, and the III-nitride islands grown in this way are arranged at intervals of about 15 micrometers from each other, and each island is completed so that the GaN layer 25 has a thickness of about 1 to 10 μm and a width of about 50 micrometers.

[0107] The TO wafer in a state where the sidewalls of the template plug are partially exposed has a group-III nitride interface (exposed template plug) and a dielectric interface (Fabry-Perot filter layer) above it, and the ratio of these two interfaces is referred to as the "filling rate". Inside the reactor, the group-III nitride can be deposited on the group-III nitride interface and cannot be deposited on the dielectric interface, which is expressed in terms of the phrase "filling rate". In this TO wafer, the filling rate is lower than 1. In a deposition where the filling rate deviates from 1, due to the abundant presence of group-III nitride atoms, the group-III nitride atoms in the reactor may further accumulate at the edge of the growth surface, which occurs near the boundary between the growth interface and the non-growth interface, and accordingly, a GaN layer may be formed thicker at the edge compared to the central region of the group-III nitride island.

[0108] Polishing Due to the abundant presence of group-III nitride atoms, the group-III nitride islands grown from each template plug may have a concave shape at the top. To obtain a flat device layer, the group-III nitride islands are initially grown to a thickness of 5 to 10 μm and then planarized by polishing or etching to form a group-III nitride base with a flat upper surface. On this flat upper surface, a device layer including p-GaN, n-GaN, InGaN, and AlGaN layers is regrown. Specifically, since the device layer including all of n-GaN, MQW, p-GaN, and / or the tunnel junction layer does not exceed 700 nm in thickness, in this regrowth, the edge growth caused by the abundant group-III nitride atoms may be negligibly small.

[0109] Growth of the device layer The group-III nitride-based semiconductor layer, and the tunnel junction layer or the buried tunnel junction layer are regrown on the group-III nitride base. The semiconductor laminate and the semiconductor section 15 each include a semiconductor device layer of a group-III nitride compound, and the group-III nitride compound can include dopants or impurities such as Mg, Si, Zn, O, C, and H in addition to In, Al, and / or B. The device layer of the group-III nitride-based semiconductor generally includes more than three layers including an n-type layer, an undoped layer, and a p-type layer. The device layer specifically includes gallium nitride-based materials such as GaN layer, AlGaN layer, InGaN layer, and AlGaInN layer. For example, the epitaxial growth of these device layers is performed in a semi-batch furnace of MOCVD or MBE. The device region includes a thick n-GaN layer, multiple quantum wells (e.g., MQW with a well thickness of 3 nm and a barrier thickness of 7 nm), a p-AlGaN electron blocking layer (EBL) with a thickness of 10 nm, a p-GaN layer with a thickness of 100 nm, and a p ++ GaN layer.

[0110] When ITO is used as the current spreading layer, the topmost device layer can be p ++ GaN. Otherwise, an n with a thickness of 10 nm ++The GaN layer is further p for a tunnel structure ++ deposited on the upper surface of the GaN. Regarding the design of the embedded tunnel junction and the tunnel junction, a current diffusion layer of an n-GaN layer with a thickness of 50 nm is added to the additional n ++ deposited across the GaN layer.

[0111] Specifically, in the tunnel junction design, the growth of the semiconductor laminate is stopped after the p ++ layer is grown, and then ion implantation is performed to form an aperture structure, and then the n ++ GaN layer and the n-type GaN layer are deposited on the aperture structure.

[0112] Specifically, in the embedded tunnel junction design, the growth of the semiconductor laminate is stopped after growing the n ++ GaN layer across the p ++ GaN layer, and then the p ++ GaN layer and the n ++ GaN layer are patterned to form a patterned tunnel junction, and then the n-type GaN layer is deposited on the patterned tunnel junction. Regrowth can be performed using either an MOCVD or an MBE (molecular beam epitaxy) reactor. Using MBE instead of MOCVD can eliminate the hydrogen re-passivation of p-GaN during the regrowth of the tunnel junction.

[0113] Alternatively, the design described in the embodiment may include processing an island-shaped (island-shaped) group III nitride device layer. To recover the re-passivation of hydrogen, the activation of a p-type gallium nitride-based material such as p-GaN can be achieved through lateral diffusion, and the p-GaN layer is embedded by a tunnel junction or a current diffusion layer (n-GaN) and can be activated. Accordingly, for the design of a specific device layer, MBE or MOCVD can be selected according to manufacturing parameters such as cost and yield.

[0114] Micro-lens formation The monolithic microlens is used in the aperture fabrication procedure. In particular, the back monolithic lens can focus the exposure light to the position of the aperture structure due to the effect of the curved lens. The curved lens forms the second DBR mirror with a curved surface in the VCSEL product.

[0115] The TO substrate can be a substrate polished on both sides. Accordingly, the back microlens pattern is positioned so that the obtained position and shape of the lens can help to be accurately aligned with the position of the aperture on the upper surface of the semiconductor section. The monolithic microlens is manufactured through the processes of photoresist (PR) reflow and dry etching. For example, the sapphire substrate polished on both sides can be a 2-inch wafer with (0001) orientation. If possible, wafers with a larger diameter may also be used. Specifically, an array of circular PR disks is patterned on the back side of the polished sapphire substrate by standard photolithography techniques. The PR pattern is then baked using a hot plate at a high temperature. After reaching the transition temperature of the PR, the PR pattern starts to reflow to form a convex shape with the center of each pattern being the thickest. Next, the convex shape is transferred to the sapphire substrate using, for example, an inductively coupled plasma (ICP) system. The optimized etching conditions can achieve a surface roughness of less than 1 nanometer. Preferably, the etched surface of the sapphire has a surface roughness of 0.1 nm to 0.5 nm to avoid optical scattering and the corresponding light loss.

[0116] Ion implantation Ion implantation is used to form electrical and optical apertures (openings) in GaN-based layers by damaging these GaN-based layers outside the apertures, and the damaged GaN-based material is no longer conductive. This method can keep the upper surface flat and can generate a very slight refractive index guide between the aperture region and the damaged region. The damaged region can have an absorption value higher than that of the unimplanted non-implanted material in the aperture region, and also, however, increased optical loss can be provided in the cavity in the damaged region. Heavy ions such as aluminum (Al) and boron (B) can be used in the ion implantation procedure. The basic idea of ion implantation is to generate a conductive aperture.

[0117] Transparent conductive layer After ion implantation, a transparent conductive layer is deposited over the device layer, or regrowth of group III nitrides for tunnel junctions is performed on the device layer with or without the ion implantation process. ITO can be used as a commonly used transparent current spreading layer (current spreader). Incorporating ITO into the VCSE causes additional absorption, but this absorption can be reduced by lowering the intensity of the electromagnetic wave around the ITO layer. Alternative approaches such as tunnel junctions can be used to spread the current and lower the optical absorption.

[0118] Tunnel junction The tunnel junction approach enables hole carriers to be injected into the active layer of the device through the n-type semiconductor because the junction between the highly doped n-type region and the highly doped p-type region allows electrons to tunnel from the valence band of the p-type region to the conduction band of the n-type region under reverse bias, thereby causing a change in the type of conduction carriers. Since the tunneling probability depends exponentially on the tunneling distance, highly doped regions are preferred (~10 19 / cm 3Generate a thin depletion width for efficient operation. After forming the aperture structure by ion implantation, n ++ / n-GaN layers (thickness 10 / 50 nm) are regrown epitaxially on the top p ++ GaN layer of the device layer to form a tunnel junction and a current spreading layer.

[0119] Embedded tunnel junction The embedded tunnel junction can function not only as a carrier converter but also as a current aperture, and is formed by growing a planar tunnel junction of a highly doped p ++ / n ++ layer (thickness 10 / 10 nm); forming a mask on the highly doped junction layer at the desired aperture position using a microlens of the TO substrate; etching the highly doped junction layer using the mask. The embedded tunnel junction does not necessarily have to be combined with a current aperture (opening), and the current aperture is formed by ion implantation and may be combined with the current aperture if necessary.

[0120] DBR mirror The DBR mirrors of the present disclosure each include alternating dielectric layers joined together to form a reflective mirror and are disposed on the top and bottom of the VCSEL to form an optical cavity. The dielectric DBR mirror can include, for example, a SiO 2 / Ta 2 O 5 layer having a thickness of a quarter wavelength of the dielectric. The number of pairs is related to the reflectivity, and in order to promote light emission, the reflectivity of the DBR mirror on the p side of the VCSEL may be smaller than the reflectivity of the curved surface.

[0121] Omnidirectional reflector (ODR) The ODR is disposed outside the optical cavity and can reflect light leaking from the propagation path. The ODR is also disposed between the anode electrode and the cathode electrode and functions to protect and / or passivate the device layer from potential contaminants and direct contact.

[0122] Metal pad Metals such as gold (Au), aluminum (Al), nickel (Ni), palladium (Pd), titanium (Ti), indium (In), etc. can be used as materials for metal pads in the manufacture of VCSELs. The metal layer can be formed by sputtering, evaporation, or plating.

[0123] Applications

[0124] Data center The increasing requirements for data communication with cloud computing and streaming services drive up the demand for information transfer hardware such as edge-emitting lasers and VCSELs, which provide server data transfer to servers within the data center. In most data communications, VCSELs operate at infrared (IR) wavelengths. The group III nitride VCSELs according to the foregoing embodiments can be used for data communication associated with data centers.

[0125] Illumination GaN-based light sources such as LEDs have brought about dramatic changes in residential and automotive lighting. Lighting combined with communication services is highly desirable in future smart cities and smart infrastructure. VCSELs may be a better alternative to LEDs and edge-emitting laser diodes. The procedures developed in the foregoing embodiments can be used to manufacture VCSEL units applicable to lighting applications.

[0126] Visible light communication Laser light can be used for data transfer and communication applications via light fidelity (LiFi). With the rapid increase in IoT devices, the demand for data transmission continues to grow. The RF spectrum is becoming saturated, and new frequencies are needed to meet the increasing demand. Employing GaN-based VCSELs in existing LED architectures is easier than replacing the LED architecture with edge-emitting lasers. The group III nitride VCSELs according to the above-described embodiments can be employed in visible light communication.

[0127] Near-eye display Near-eye displays are the next big wave in consumer electronics and are the basis for virtual reality (VR) and augmented reality (AR) technologies. Currently, micro-LEDs are the main choice for displays. However, despite the limited progress of current VCSEL research, VCSELs may be introduced as small displays and near-eye displays. VCSELs can provide relatively low optical power, which is convenient for maintaining eye safety, as well as low divergence and circular symmetry, which can reduce the number of additional optical elements and thus lead to device compactification. The integration of a two-dimensional (2D) array of VCSELs is easier than that of edge-emitting lasers. The group III nitride VCSELs according to the above-described embodiments can be applied to these applications.

[0128] According to the above embodiments, the following effects can be obtained. Using a sufficiently long cavity without excessive diffraction loss with two reflective mirrors defining the VCSEL cavity and a Fabry-Perot filter added to narrow down to single-mode operation, Providing better thermal management due to the sufficient length of the cavity and / or the arrangement of electrical contacts on the III nitride layer, Providing better heat conduction of the device by a GaN template plug in contact with the TO substrate, Using an inexpensive and large template substrate such as GaN on sapphire. Minimizing the waste of semiconductor layers by using island-shaped III-nitrides. Eliminating the substrate removal and bonding procedures in manufacturing, thereby improving production parameters, and Liberating the use of heterogeneous substrates in the manufacture of VCSELs by using ELO technology. It is expected that the foregoing embodiments provide a significant improvement in performance, a reduction in manufacturing cost, and the elimination of complex procedures. The foregoing embodiments propose the integration of a Fabry-Perot filter in a VCSEL, which enables epitaxial lateral overgrowth to improve the crystal quality of the device layer. Using a template TO material substrate including a structure similar to GaN / sapphire enables the device layer to grow on the wings of epitaxial lateral overgrowth, which generally provides defect-free or slightly defective, and thus leads to high crystal quality.

[0129] Side 1 A vertical cavity surface emitting laser includes an oxide substrate having a first surface and a second surface opposite to the first surface, wherein the second surface includes a curved surface, an oxide substrate, a semiconductor section disposed on the first surface of the oxide substrate, a dielectric filter layer disposed between the semiconductor section and the first surface of the oxide substrate and having a reflection spectrum, the reflection spectrum being configured to provide an optical window, a first distributed Bragg reflector (DBR) mirror, the semiconductor section being disposed between the dielectric filter layer and the first DBR mirror, a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor section, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged in a first axial direction to form an extended cavity, the semiconductor section including a p-type group III nitride region, a group III nitride region, and a group III nitride active region between the p-type group III nitride region and the group III nitride region, the p-type group III nitride region, the group III nitride active region, and the group III nitride region being disposed in the first axial direction, and the group III nitride region including an n-type group III nitride region, and a second DBR mirror.

[0130] Side 2 In the vertical cavity surface emitting laser according to Side 1, the dielectric filter layer has a through hole extending in the first axial direction, and the vertical cavity surface emitting laser further includes a group III nitride template plug disposed in the through hole and extending in the through hole from the first surface of the oxide substrate to the semiconductor section.

[0131] Side 3 In the vertical cavity surface emitting laser according to Side 2, the group III nitride template plug has an embedded portion in the through hole and a protruding portion protruding into the semiconductor section, and the embedded portion of the group III nitride template plug is disposed in contact with the first surface of the oxide substrate.

[0132] Side 4 In a vertical resonance surface emitting laser related to any one of Side 1 to Side 3, the curved surface of the oxide substrate has a center line, and the group III nitride template plug and the center line of the curved surface are displaced from each other.

[0133] Side 5 In a vertical resonance surface emitting laser related to any one of Side 1 to Side 4, the length of the extended cavity exceeds 50 micrometers.

[0134] Side 6 In a vertical resonance surface emitting laser related to any one of Side 1 to Side 5, the curved surface has a radius of curvature exceeding 50 micrometers.

[0135] Side 7 In a vertical resonance surface emitting laser related to any one of Side 1 to Side 6, the second DBR mirror is curved, the first DBR mirror is planar, and the distance between the first DBR mirror and the second DBR mirror is greater than 50 micrometers.

[0136] Side 8 In a vertical resonance surface emitting laser related to any one of Side 1 to Side 7, the semiconductor section includes a mesa structure, the mesa structure includes a base region and a mesa region disposed on the base region, and the vertical resonance surface emitting laser further includes a conductive layer disposed on the semiconductor section, a part of the conductive layer being disposed between the first DBR mirror and the semiconductor section, a first electrode disposed on the conductive layer outside the DBR mirror and in contact with the conductive layer, and a second electrode disposed on the surface of the base region of the mesa structure.

[0137] Side 9 In a vertical cavity surface emitting laser related to side surface 8, the semiconductor section has a first surface and a second surface opposite to the first surface of the semiconductor section, the dielectric filter layer is disposed on the first surface of the semiconductor section, and the conductive layer is disposed on the second surface.

[0138] Side surface 10 In a vertical cavity surface emitting laser related to any one of side surfaces 1 to 9, the semiconductor section includes an aperture structure, the aperture structure includes an aperture region extending in the first axial direction and a separation region surrounding the aperture region, and the first DBR mirror, the aperture region, and the second DBR mirror are arranged along an axis that does not pass through the group III nitride template plug.

[0139] Side surface 11 In a vertical cavity surface emitting laser related to any one of side surfaces 1 to 10, the total thickness of the semiconductor section exceeds 0.5 micrometers.

[0140] Side surface 12 In a vertical cavity surface emitting laser in any one of side surface modes from side surface 1 to side surface 11, the dielectric filter layer includes a Fabry-Perot filter configured to provide the reflection spectrum for the optical window.

[0141] Side surface 13 In a vertical cavity surface emitting laser related to any one of side surfaces 1 to 12, the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

[0142] Side surface 14 In a vertical cavity surface emitting laser related to any one of side surfaces 1 to 13, the first DBR mirror has a reflectivity lower than that of the second DBR mirror.

[0143] Side surface 15 In a vertical resonance surface emitting laser using any one of side surfaces 1 to 14, the group III nitride active region includes a quantum well structure configured to generate light, and the light has wavelengths within the first reflection spectrum of the first DBR mirror, the second reflection spectrum of the second DBR mirror, and the optical window of the dielectric filter layer.

[0144] Side surface 16 A method of manufacturing a vertical cavity surface emitting laser includes preparing a starting base, which includes an oxide base, a group III nitride template plug, and a dielectric filter layer. The oxide base has a first surface and a second surface opposite to the first surface of the oxide base. The dielectric filter layer and the group III nitride template plug are disposed on the first surface of the oxide base. The dielectric filter layer has a reflection spectrum configured to provide an optical window. The method further includes growing a group III nitride region from the group III nitride template plug on the dielectric filter layer, growing a semiconductor laminate including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region after growing the group III nitride region, processing the oxide base on the second surface of the oxide base to form an oxide substrate having a curved surface, where the curved surface is disposed on the opposite side of the first surface of the oxide substrate, forming a first distributed Bragg reflector (DBR) laminate on the first surface of the oxide substrate, and forming a second DBR laminate on the curved surface of the oxide substrate.

[0145] Side surface 17 The method according to side surface 16 further includes planarizing the group III nitride region by at least one of polishing or etching before growing the semiconductor laminate.

[0146] Side surface 18 The method according to side surface 16 or side surface 17 further includes depositing a conductive layer on the first surface of the oxide substrate and forming a first electrode on the conductive layer after growing the semiconductor laminate and before forming the first DBR laminate.

[0147] Side surface 19 The method according to any one of side surfaces 16 to 18 includes generating a mesa structure from the semiconductor laminate by etching to form an etched surface of the n-type group III nitride region, the mesa structure including the etched surface of the n-type group III nitride region including the group III nitride active region.

[0148] Side surface 20 The method according to side surface 19 further includes forming a second electrode on the etched surface of the n-type group III nitride region outside the mesa structure.

[0149] Side surface 21 In the method according to any one of side surfaces 16 to 20, the semiconductor laminate further includes one of a tunnel junction or an embedded tunnel junction.

[0150] Side surface 22 In the method according to any one of side surfaces 16 to 21, the oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide.

[0151] Side surface 23 In the method according to any one of side surfaces 16 to 22, preparing the starting base includes depositing a group III nitride layer on the first surface of the oxide base; patterning the group III nitride layer to form the group III nitride template plug; depositing a plurality of dielectric layers to cover the first surface of the oxide base and the group III nitride template plug; and processing the plurality of dielectric layers to form the dielectric filter layer such that the group III nitride template plug is disposed within the through-hole of the dielectric filter layer, wherein the group III nitride template plug has a height greater than the thickness of the dielectric filter layer, and forming the dielectric filter layer.

[0152] Side surface 24 In the method according to side surface 23, the plurality of dielectric layers are grown to form a Fabry-Perot filter configured to provide the reflection spectrum for the optical window.

[0153] Side surface 25 In the method according to any one of side surfaces 16 to 24, the group III nitride region is grown from the group III nitride template plug by epitaxial lateral overgrowth to form group III nitride islands.

[0154] Side surface 26 In the method according to side surface 25, the group III nitride islands extend outward along the upper surface of the dielectric filter layer from the group III nitride template plug, and the upper surface of the dielectric filter layer has a roughness of less than 1 nanometer.

[0155] Side surface 27 In the method according to any one of side surfaces 16 to 26, the group III nitride active region is grown to form a quantum well structure, and the quantum well structure is configured to generate light having wavelengths within the first reflection spectrum of the first DBR stack, the second reflection spectrum of the second DBR stack, and the optical window of the dielectric filter layer.

[0156] Side 28 In the method according to any one side from side 16 to side 27, processing the oxide base on the second surface of the oxide base includes forming a patterned resist layer on the second surface of the oxide base, heat-treating the patterned resist layer to form a convex resist region, and transferring the shape of the convex resist region to the oxide base by etching the convex resist region and the oxide base. Etching the convex resist region and the oxide base stops the etching of the convex resist region and the oxide substrate so as to satisfy the condition that the distance between the second DBR laminate and the first DBR laminate exceeds 50 μm after forming the first DBR laminate and the second DBR laminate.

[0157] Side 29 In the method according to any one side from side 16 to side 28, the curved surface has a radius of curvature exceeding 50 micrometers.

[0158] Side 30 The method according to any one side from side 16 to side 29 includes forming a resist film on the first surface of the oxide substrate after growing the semiconductor laminate and before forming the conductive layer; illuminating the resist film through the curved surface of the oxide substrate to generate a patterned mask from the resist film; and performing ion implantation using the patterned mask to form an aperture structure including an aperture region and a separation region surrounding the aperture region.

[0159] Although the principles of the present disclosure have been described and illustrated in its preferred embodiments, it will be understood by those skilled in the art that the present disclosure can be arranged and detailed without departing from such principles. Accordingly, we claim all modifications and variations within the spirit and scope of the following claims.

Explanation of Signs

[0160] 11, 11a, 11b, 11c VCSEL 13, 19 Distributed Bragg Reflector (DBR) 15 Semiconductor section 17 Dielectric filter layer 23 p-type Group III nitride region 25 n-type Group III nitride region 27 Group III nitride active region CAV Optical cavity 31 Anode electrode 33 Cathode electrode 35 Conductive layer 37 Mesa structure Ax1, Ax2, Ax3 Axial directions

Claims

1. A vertical cavity surface emitting laser (VCSEL), comprising: an oxide substrate having a first surface and a second surface opposite to the first surface, the second surface including a curved surface; a semiconductor section disposed on the first surface of the oxide substrate; a dielectric filter layer disposed between the semiconductor section and the first surface of the oxide substrate and having a reflection spectrum, the reflection spectrum being configured to provide an optical window; a first distributed Bragg reflector (DBR) mirror, the semiconductor section being disposed between the dielectric filter layer and the first DBR mirror; a second DBR mirror disposed on the curved surface of the oxide substrate, the first DBR mirror, the semiconductor section, the dielectric filter layer, the oxide substrate, and the second DBR mirror being arranged in a first axial direction to form an extended cavity, the semiconductor section including a p-type group III nitride region, a group III nitride region, and a group III nitride active region between the p-type group III nitride region and the group III nitride region, the p-type group III nitride region, the group III nitride active region, and the group III nitride region being arranged in the first axial direction, the group III nitride region including an n-type group III nitride region; and comprising: a vertical cavity surface emitting laser.

2. The dielectric filter layer has a through hole extending in the first axial direction. The vertical cavity surface emitting laser further includes a group III nitride template plug disposed in the through hole and extending in the through hole from the first surface of the oxide substrate to the semiconductor section. The vertical cavity surface emitting laser according to claim 1.

3. The group III nitride template plug has an embedded portion in the through hole and a protruding portion protruding into the semiconductor section, the embedded portion of the group III nitride template plug being disposed in contact with the first surface of the oxide substrate. The vertical cavity surface emitting laser according to claim 2.

4. The curved surface of the oxide substrate has a center line, and the group III nitride template plug and the center line of the curved surface are offset from each other. The vertical cavity surface emitting laser according to claim 2 or claim 3.

5. The length of the expansion cavity exceeds 50 micrometers. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

6. The curved surface has a radius of curvature exceeding 50 micrometers. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

7. The second DBR mirror is curved, the first DBR mirror is planar, and the distance between the first DBR mirror and the second DBR mirror is greater than 50 micrometers. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

8. The semiconductor section includes a mesa structure, and the mesa structure includes a base region and a mesa region disposed on the base region. The vertical cavity surface emitting laser further includes a conductive layer disposed on the semiconductor section, a part of the conductive layer being disposed between the first DBR mirror and the semiconductor section, a first electrode disposed on the conductive layer outside the first DBR mirror and in contact with the conductive layer, a second electrode disposed on the surface of the base region of the mesa structure, and includes The vertical cavity surface emitting laser according to any one of claims 1 to 3.

9. The semiconductor section has a first surface and a second surface opposite to the first surface of the semiconductor section, the dielectric filter layer is disposed on the first surface of the semiconductor section, and the conductive layer is disposed on the second surface. The vertical cavity surface emitting laser according to claim 8.

10. The semiconductor section includes an aperture structure, and the aperture structure includes an aperture region extending in the first axial direction and a separation region surrounding the aperture region. The first DBR mirror, the aperture region, and the second DBR mirror are disposed along an axis that does not pass through the group III nitride template plug. The vertical cavity surface emitting laser according to claim 2 or claim 3.

11. The total thickness of the semiconductor section exceeds 0.5 micrometers. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

12. The dielectric filter layer includes a Fabry - Perot filter configured to provide the reflection spectrum for the optical window. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

13. The oxide substrate contains one of aluminum oxide, zinc oxide, or gallium oxide. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

14. The first DBR mirror has a reflectivity lower than that of the second DBR mirror. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

15. The group III nitride active region includes a quantum well structure configured to generate light, and the light has a wavelength within the first reflection spectrum of the first DBR mirror, the second reflection spectrum of the second DBR mirror, and the optical window of the dielectric filter layer. The vertical cavity surface emitting laser according to any one of claims 1 to 3.

16. A method for manufacturing a vertical cavity surface emitting laser (VCSEL), Preparing a starting base, the starting base including an oxide base, a group III nitride template plug, and a dielectric filter layer, the oxide base having a first surface and a second surface opposite to the first surface of the oxide base, the dielectric filter layer and the group III nitride template plug being disposed on the first surface of the oxide base, the dielectric filter layer having a reflection spectrum configured to provide an optical window, preparing the starting base; Growing a group III nitride region from the group III nitride template plug on the dielectric filter layer; After growing the group III nitride region, growing a semiconductor laminate including an n-type group III nitride region, a group III nitride active region, and a p-type group III nitride region; Processing the oxide base on the second surface of the oxide base to form an oxide substrate having a curved surface, the curved surface being disposed on the opposite side of the first surface of the oxide substrate, processing the oxide base on the second surface of the oxide base; After growing the semiconductor laminate, forming a first distributed Bragg reflector (DBR) laminate on the first surface of the oxide substrate; Forming a second DBR laminate on the curved surface of the oxide substrate; A method comprising.

17. Before growing the semiconductor laminate, flattening the group-III nitride region by at least one of polishing or etching, further comprising, The method according to claim 16.

18. After growing the semiconductor laminate, before forming the first DBR laminate, depositing a conductive layer on the first surface of the oxide substrate; Forming a first electrode on the conductive layer; Further comprising, The method according to claim 16 or claim 17.

19. Generating a mesa structure from the semiconductor laminate by etching to form an etched surface of the n-type group-III nitride region, the mesa structure including the etched surface of the n-type group-III nitride region including the group-III nitride active region, further comprising, The method according to claim 16 or claim 17.

20. Forming a second electrode on the etched surface of the n-type group-III nitride region outside the mesa structure, further comprising, The method according to claim 19.

21. The semiconductor laminate further includes one of a tunnel junction or an embedded tunnel junction, The method according to claim 16 or claim 17.

22. The oxide substrate includes one of aluminum oxide, zinc oxide, or gallium oxide, The method according to claim 16 or claim 17.

23. Preparing the starting base includes, Depositing a group-III nitride layer on the first surface of the oxide base; Pattern-forming the group-III nitride layer to form the group-III nitride template plug; Depositing a plurality of dielectric layers to cover the first surface of the oxide base and the group-III nitride template plug; Processing the plurality of dielectric layers to form the dielectric filter layer such that the group-III nitride template plug is disposed within a through-hole of the dielectric filter layer, the group-III nitride template plug having a height greater than the thickness of the dielectric filter layer, forming the dielectric filter layer; Comprising, The method according to claim 16 or claim 17.

24. The plurality of dielectric layers are grown to form a Fabry-Perot filter configured to provide the reflection spectrum for the optical window, The method according to claim 23.

25. The group-III nitride region is grown from the group-III nitride template plug by epitaxial lateral overgrowth to form group-III nitride islands. The method according to claim 16 or claim 17. **Claim 26** The group-III nitride islands extend outward from the group-III nitride template plug along the upper surface of the dielectric filter layer, and the upper surface of the dielectric filter layer has a roughness of less than 1 nanometer. The method according to claim 25. **Claim 27** The group-III nitride active region is grown to form a quantum well structure, and the quantum well structure is configured to generate light having wavelengths within the first reflection spectrum of the first DBR stack, the second reflection spectrum of the second DBR stack, and the optical window of the dielectric filter layer. The method according to claim 16 or claim 17. **Claim 28** Processing the oxide base on the second surface of the oxide base comprises: forming a patterned resist layer on the second surface of the oxide base; heat-treating the patterned resist layer to form a convex resist region; transferring the shape of the convex resist region to the oxide base by etching the convex resist region and the oxide base; comprising Etching the convex resist region and the oxide base stops the etching of the convex resist region and the oxide substrate so as to satisfy the condition that the distance between the second DBR stack and the first DBR stack exceeds 50 μm after the first DBR stack and the second DBR stack are formed. The method according to claim 16 or claim 17. **Claim 29** The curved surface has a radius of curvature exceeding 50 micrometers. The method according to claim 16 or claim 17. **Claim 30** After growing the semiconductor stack and before forming the conductive layer, forming a resist film on the first surface of the oxide substrate; illuminating the resist film through the curved surface of the oxide substrate to generate a patterned mask from the resist film; performing ion implantation using the patterned mask to form an aperture structure including an aperture region and a separation region surrounding the aperture region; further comprising The method according to claim 18.

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