A method for configuring memory placement within a computing device

Abstract

A system and method for allocating memory locations to several processing modules on a computing device having a predefined memory layout, the method being executed by a processor and comprising the steps of: receiving, via a graphical user interface, the predefined memory layout of the computing device; displaying, via the graphical user interface, the configuration of the predefined memory layout of the computing device; receiving a user input memory placement request for the allocation of data to a memory location; generating configuration data for the allocation of data to a memory location within the predefined memory layout of the computing device; and displaying, via the graphical user interface, a consumption guide indicating an estimated consumption level for the allocation of data to the memory location determined by the configuration data.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to Provisional Application No. 202241020656, filed in India on April 6, 2022, the entire content of which is incorporated herein by reference.

[0002] This disclosure relates to memory placement in a computing device, and more particularly to configuring the memory latency of a computing device.

Background Art

[0003] Computing devices such as digital signal processors (DSPs) are processors that execute algorithms for mathematically manipulating digitized signals such as, but not limited to, voice, audio, video, sonar, radar, etc. Signal processing is performed using one or more processors or microprocessors that include one or more data memory systems. For example, among others, internal memory, cached memory, external memory, etc.

[0004] The performance of a computing device is measured in many ways, but the most common metric is the time required for the processor to achieve a task, which depends on the placement of data in memory and shortens the processing time by achieving the shortest access time. There are multiple memory types for a processor. Lower - level memory types, i.e., level 1, are "faster" because they are smaller in size and have a shorter access time. Higher - level memory types, i.e., levels 2 - 16, are "slower" because they are larger in size and have a longer access time. The hierarchy from the fastest to the slowest is level 1 (L1) as the fastest and level 16 (L16) as the slowest. The number of memory types varies from system to system. Memory latency correlates with the duration required to start a request to access memory and read or write data in the requested memory.

[0005] Typically, to place data in memory, it is necessary to: 1) calculate the amount of memory required by the processing pipeline; 2) understand how each type of memory is used and how frequently it is used; 3) place memory blocks so that the fastest memory is allocated to the parts of the process that require the fastest access; 4) compile the code after the memory placement is complete; and 5) flash files to a flash-based memory storage device.

[0006] To optimize the performance of the processor, the above code changes are repeatedly executed. After each code change, the code is compiled and flashed before the impact on the processor can be measured. In practice, multiple code changes are required because multiple blocks compete for the minimum latency / highest speed memory. The drawback of this current approach is that it is a monotonous and time-consuming task that does not provide much flexibility to the engineer. This approach is temporally complex, time-consuming, and usually results in underutilization of processing resources. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0007] The subject matter of the present invention includes one or more embodiments of an interface system for configuring the memory layout of a computing device having a plurality of processing modules, wherein the plurality of processing modules are each stored at a plurality of memory locations of the computing device being accessed and have data communicated to the system for execution. The interface system includes a communication protocol for receiving a memory layout from the computing device, a graphical user interface for displaying a configuration for each of the plurality of processing modules at a memory location within the memory layout, and a memory placement request for a change to the configuration, the memory placement request being input by a user via the graphical user interface and correlating a processing module with a latency level for a memory location within the plurality of memory locations. There is also configuration data generated by the graphical user interface, the configuration data representing the placement of data stored at the plurality of memory locations based on the memory placement requests of each processing module and the memory capacity of the computing device.

[0008] In one or more embodiments, the graphical user interface includes a plurality of options for a user to select a memory placement request, and configuration data is generated using one or more user-selected placement requests.

[0009] In one or more embodiments, a consumption guide indicating a consumption level of the configuration data is displayed.

[0010] In one or more embodiments, an allocator on the computing device allocates a memory layout according to the configuration data.

[0011] In one or more embodiments, a result profile is displayed to show the result of the configuration of the memory layout changed according to the configuration data.

[0012] The subject matter of the present invention includes one or more embodiments of a method for allocating memory locations to a predetermined number of processing modules, the memory locations being on a computing device having a predefined memory layout, the processing modules having instructions that are stored in the memory locations according to a configuration and can be accessed and executed by the computing device, and the method being executed by a processor of a graphical user interface that communicates with the computing device. The method includes receiving, at the graphical user interface, the predefined memory layout of the computing device; displaying, at the graphical user interface, the configuration of the predefined memory layout of the computing device; receiving a user input memory allocation request for the allocation of data to the memory locations, the user input memory allocation request being input at the graphical user interface; generating, in the processor of the graphical user interface, configuration data for the allocation of data to the memory locations within the predefined memory layout of the computing device, the configuration data being based on the user input memory allocation request for the memory allocation and the memory capacity of the computing device; and displaying, at the graphical user interface, a consumption guide indicating an estimated consumption level for the allocation of data to the memory locations determined by the configuration data.

[0013] In one or more embodiments, the method further includes presenting a plurality of options for a user selection of a memory allocation request and generating a configuration database based on the user selection.

[0014] In one or more embodiments, the method further includes sending the configuration data to the computing device, which is allocated to the memory locations according to the configuration data.

[0015] In one or more embodiments, the method further includes displaying, on a graphical user interface, a result profile that indicates a memory allocation performed according to the configuration data.

[0016] In one or more embodiments, the method further includes prioritizing user input memory placement requests based on the estimated consumption levels and the result profile. BRIEF DESCRIPTION OF THE DRAWINGS

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[0023] Elements and steps in the drawings are shown for simplicity and clarity and are not necessarily presented in any particular order. For example, steps that may be performed simultaneously or in a different order are shown in the drawings to assist in improving the understanding of embodiments of the present disclosure.

Best Mode for Carrying Out the Invention

[0024] Although various aspects of the present disclosure are described with reference to FIGS. 1-5, the present disclosure is not limited to such embodiments, and additional modifications, applications, and embodiments may be implemented without departing from the present disclosure. In the figures, like reference numerals are used to indicate the same components. Those skilled in the art will understand that the various components shown herein may be modified without departing from the scope of the present disclosure.

[0025] FIG. 1 is a block diagram of a system 100 for configuring a memory arrangement on a computing device 102. The computing device 102 has at least one processor, programming for executing instructions and calculations, and a memory for program and data storage. The computing device 102 has a program memory 104 that stores programs used by the computing device 102 to process data. The data memory 106 stores information (data) to be processed. The computing engine 108 (CPU) accesses programs from the program memory 104 and accesses information from the data memory 106 for mathematical operations.

[0026] The CPU 108 has an internal memory 110, which is divided into L1 112, L2 114 to Ln 116 (n depends on the processor architecture), and these are intended to be used in a way that minimizes the time for memory access. This is called local memory, and as described above, the levels are distinguished by size and access speed. The memory on the CPU 108 is usually accessed faster than external memories such as the program memory 104 and the data memory 106. The level L1 112 may be considered the fastest, and the level Ln 116 may be considered the slowest. The level L2 114 is slower than the level L1 112 but faster than the level Ln 116. Data is supplied between the computing device 102 via the input / output (I / O) block 118.

[0027] Each type of memory, the program memory 104, the data memory 106, and the internal memory levels 112, 114, 116 each have their own fetch time. Depending on where or how the data is arranged within the memory layout, the CPU 108 can fetch the data faster and execute operations faster. In one or more embodiments, the graphical user interface (GUI) 120 receives a user input 122 that indicates a configuration of the memory layout adapted to the signal flow within the computing device 102. The GUI 120 provides the user with the function of inputting changes to the memory layout. From the GUI 120, the user can select the specific levels at which the program and data are arranged in the memory and test and preview the impact that the selection has on the computing device 102.

[0028] The GUI 120 generates configuration data 124, which is communicated to the computing device 102 via the general-purpose communication port 126 and reflects changes to the configuration for the memory layout requested by the user in the memory layout of the computing device. The general-purpose communication port 126 is used to transmit and receive all configuration and feedback data between the GUI and the computing device 102. Once generated, the configuration data 124 may be transmitted to the computing device 102 via the communication protocol 123, and the configuration data is stored in the persistent memory 105 of the program memory 104 and / or the data memory 106 by the computing device 102. Hard coding is not required. Compilation and flashing are not required, and the allocator 128 within the computing device 102 configures the memory layout according to the configuration data 124.

[0029] The framework 107 connects to the GUI 120 via the communication protocol 123 and provides information regarding the memory capacity of the computing device 102. The memory capacity of the computing device is presented to the user and used by the GUI when generating the configuration data 124. The GUI 120 presents options for the user to select as user input 122. The selection is used to generate the configuration data 124. For example, an object such as an audio module within a multi-channel audio system has a memory type and size. The user selects, using the GUI 120, the latency requested to be assigned to the module.

[0030] The configuration data 124 is generated in the GUI and sent back to the computing device 102, where the allocator 128 determines whether the computing device can execute the requested allocation based on the memory capacity of the computing device. The allocator 128 maximally utilizes the memory capacity of the computing device to adapt the configuration data 124.

[0031] If the allocator 128 cannot adapt to the latency assignment requested by the user and set in the configuration data 124, the default settings are applied on the computing device 102. The allocator 128 provides details regarding the allocation performed, sends the profiling results to the GUI, where the profiling results are displayed to the user as a result profile. The result profile shows the user how the configuration data allocates data to memory locations and how that affects the memory capacity and processing performance of the computing device. Using the profiling results and the configuration of the memory layout, the memory with the fastest fetch time can be allocated to the objects considered most critical to the user.

[0032] Figure 2 is a flowchart of one or more embodiments of a method 200 for allocating memory to the placement of data stored at one or more memory locations of a memory layout on a computing device. The placement of data stored in the memory on the computing device is configured by the user in the GUI (202). To configure the memory placement, the user enters one or more requests for the memory placement of data by selecting the latency level of the memory blocks. The latency level of the memory blocks determines where the data allocation should occur when the configuration data is generated in the GUI, communicated to the computing device, and implemented on the computing device.

[0033] Configuration data is generated in a GUI (204) and includes all such requirements for the desired memory allocation of the user to "test" how the memory placement requirements affect the performance of the computing device. The configuration data is sent to the computing device via a communication protocol (206), and the configuration data is allocated to the computing device memory by an allocator (208). The allocator allocates memory based on the memory capacity of the computing device. Whether the computing device can meet the requested allocation is reported back to the GUI (210) and presented to the user. Since the user's goal is to optimize the performance of the computing device, the user can evaluate the results and determine whether a change in memory placement needs to be requested.

[0034] Configuration data is communicated to the computing device and tested without the need to compile and flash code changes before measuring its effect on the computing device. This scenario allows the user, via the GUI and its connection to the computing device, to obtain the flexibility to perform performance tests through memory placement to efficiently and quickly optimize the performance of the computing device without the need for time-consuming hard-coded memory placement.

[0035] As an example, the system and method are described as an adjustment tool for an audio system. FIG. 3 is a flowchart of one or more embodiments of a method 300 for configuring the memory layout of data within a computing device of an audio system. The audio system has a framework composed of audio modules. Each audio module includes separate audio processing logic that instructs an amplifier within the audio system to perform functions. In the examples described hereinafter, the computing device may be a digital signal processor (DSP) within the audio system. However, it should be noted that the DSP is described for illustrative purposes only, and the subject matter of the invention may be applied to other types of computing devices and other types of systems that benefit from memory allocation to improve performance capabilities. The terms computing device and DSP may be used interchangeably throughout the following description.

[0036] According to method 300, the adjustment tool connects to the audio system via a communication protocol (302), and upon connection, the audio system transmits its core layout and memory configuration to a graphical user interface (GUI). The GUI displays the core configuration and the existing layout within the computing device of the audio system (304). The audio system has an associated signal flow that becomes viewable in the GUI.

[0037] FIG. 4 is a screenshot of a GUI showing the signal flow as a layout view 400, where the user can view an overview of the memory layout and the configuration of the signal flow 402 of the connected audio system. In the layout view, the user can also enter a memory placement request 404. In the screenshot of FIG. 4, only a part of the memory configuration of the audio system is visible. In this embodiment, a first core 406 and a second core 408 of the memory configuration are shown.

[0038] Referring to method 300 shown in FIG. 3, the user inputs or adds (306) an instance of an audio framework (which may be, for example, data or programming instructions), and arranges an audio module in the instance (308) according to the user's memory placement requirements, for example, based on memory latency. The user's requirements for memory placement are input by selecting those requirements for each memory block from a drop-down menu. This is shown as an example in FIG. 4. The first core 402 has a first audio module 406 and a second audio module 408. The first audio module has three memory blocks 414a, 414b, and 414c. Each audio module may have a plurality of memory blocks, and each memory block may have configurable memory latency. The memory latency 416 is selected by the user in a drop-down menu. Each of the memory blocks 414a, 414b, 414c defines an area of memory that requires an allocation for the audio module 406.

[0039] Referring again to FIG. 3, the user inputs the details of each audio module into an adjustment tool (310), and the adjustment tool displays a memory layout including descriptions of parameters such as, for example, ID numbers, labels, memory types, file sizes, etc. (312). The user also inputs requirements for the memory placement of each memory block within the audio module (314) to generate configuration data. For example, in FIG. 4, the GUI displays an overview of the signal flow 402 of the current memory placement configuration, and the user can determine what changes to make to the memory latency level 416 for the memory block 414c. In this step, the user combines knowledge of current resource consumption with the performance metrics displayed in the GUI to change the latency of the memory block in a way that the system can be optimized to operate as fast as possible, for example.

[0040] Referring back to FIG. 3, once the configuration data is generated, it is sent (316) to the audio system via the communication protocol, thereby applying changes to the allocation strategy without requiring code modification and / or re - flashing of the audio system.

[0041] The performance metrics of the consumption guide 500 are displayed on the GUI as shown in FIG. 5. Each audio module 502 is shown with its consumption level in the form of average MIPS 504 and maximum MIPS 506. The information presented in the consumption guide 500 provides valuable feedback and information to the user regarding the DSP resource consumption when memory placement requests are sent to the computing device by the user.

[0042] The allocator on the computing device of the audio system allocates (322) the memory placement according to the configuration data, and the DSP memory capacity and system performance are checked on the computing device. The results are presented to the GUI as a result profile of CPU consumption data (per audio module) and the actual memory allocation (depending on the audio system). Next, the memory placement allocated by the allocator becomes visible (324) on the GUI where the user can view a visual representation of the individual memory blocks and their latencies.

[0043] FIG. 6 is a screenshot of an exemplary result profile 600. The result profile 600 includes the memory block ID 604 for each audio module in addition to a list of audio modules 602. The information presented in the result profile 600 provides valuable feedback and information to the user regarding the DSP performance metrics when the configuration data generated by the GUI is allocated to the DSP, thereby enabling the user to change the latency of the memory blocks in a way that optimizes the system performance.

[0044] In the foregoing specification, the present disclosure has been described with reference to specific exemplary embodiments. The specification and drawings are illustrative rather than limiting, and variations are intended to be included within the scope of the present disclosure. Accordingly, the scope of the present disclosure should be determined not by the merely described examples, but by the claims and their legal equivalents.

[0045] For example, the steps recited in any method or process claim may be executed in any order, may be repeated, and are not limited to the specific order presented in the claim. Additionally, the components and / or elements recited in any apparatus claim may be assembled or otherwise configured to operate in various permutations and are thus not limited to the specific configuration recited in the claim. For example, the latencies of multiple memory blocks can be simultaneously modified in an Excel file and imported into an adjustment tool in the GUI.

[0046] According to the subject matter of the present invention, the memory layout is no longer hard-coded, and the DSP engineer can easily and quickly improve the utilization of MIPS. Instead of modifying the code, recompiling, and reflashing to modify the memory layout, the user may simply modify the memory layout by entering selections in the GUI to generate a configuration file. The configuration file is transmitted to the DSP via xTP, resulting in a much more flexible and faster method for optimizing the performance of the processor and the memory layout.

[0047] Any of the methods or processes described may be performed, by way of example only, by executing instructions using one or more devices such as a processor or controller, a memory (including non-transitory ones), a sensor, a network interface, an antenna, a switch, an actuator, and the like.

[0048] Advantages, other advantages, and solutions to problems have been described above with respect to certain embodiments. However, no element that could generate or make more explicit any advantage, advantage, solution to a problem, or any particular advantage, advantage, or solution shall be construed as an important, required, or essential feature or component of any or all of the claims.

[0049] The terms "comprise," "comprises," "comprising," "having," "including," "includes," or any variation thereof are intended to refer to non-exclusive inclusion, such that a process, method, article, composition, or apparatus that comprises a list of elements includes not only those elements that are recited, but also other elements not expressly listed or other elements particular to such process, method, article, composition, or apparatus. In addition to what is specifically recited, the above-described structures, arrangements, uses, ratios, elements, materials, or other combinations and / or modifications of components used in the practice of this disclosure may be varied or otherwise adapted to particular environments, manufacturing specifications, design parameters, or other operating requirements without departing from its general principles.

Claims

1. An interface system for configuring memory placement in a computing device having a plurality of processing modules, wherein each of the plurality of processing modules is stored at a plurality of memory locations of the computing device being accessed and has data communicated to the system for execution, and the interface system comprises: A communication protocol for receiving a memory layout from the computing device; A graphical user interface for displaying, at memory locations within the memory layout, a configuration for each of the plurality of processing modules; A memory placement request for a change to the configuration, the memory placement request being input by a user via the graphical user interface and correlating a processing module with a latency level for a memory location within the plurality of memory locations; Configuration data generated via the graphical user interface, the configuration data representing an arrangement of data stored at the plurality of memory locations based on the memory placement request for each processing module and the memory capacity of the computing device; The interface system comprising the foregoing.

2. The interface system according to claim 1, wherein the graphical user interface further comprises a plurality of options for the user to select the memory placement request, and the configuration data is generated using the one or more user-selected memory placement requests.

3. The interface system according to claim 2, wherein the graphical user interface further comprises a consumption guide for displaying a consumption level for one or more user-selected memory placement requests.

4. The interface system according to claim 3, wherein the consumption level is presented to the user for the user to input a memory placement request, and the most prioritized processing module may be assigned to a memory location having the fastest fetch time among all the memory locations.

5. The graphical user interface transmits the configuration data to the computing device via the communication protocol, and the computing device comprises: An allocator for allocating the data to the memory layout according to the configuration data The interface system according to claim 1, further comprising **Claim 6** The interface system according to claim 5, further comprising a result profile displayed on the graphical user interface, the result profile showing a profiling result of the configuration of the memory layout changed according to the configuration data, and the profiling result being transmitted to the graphical user interface via the communication protocol. **Claim 7** A method for allocating memory locations to a predetermined number of processing modules, the memory locations being on a computing device having a predefined memory layout, the processing modules being stored in the memory locations according to a configuration and having instructions that can be accessed and executed by the computing device, the method being executed by a processor of a graphical user interface communicating with the computing device, the method comprising receiving, at the graphical user interface, the predefined memory layout of the computing device; displaying, at the graphical user interface, the configuration of the predefined memory layout of the computing device; receiving a user input memory placement request for the allocation of data to a memory location, the user input memory placement request being input at the graphical user interface; generating, in the processor of the graphical user interface, configuration data for the allocation of the data to a memory location within the predefined memory layout of the computing device, the configuration data being based on the user input memory placement request for the memory allocation and the memory capacity of the computing device; displaying, at the graphical user interface, a consumption guide indicating an estimated consumption level for the allocation of the data to the memory location determined by the configuration data; The method comprising. **Claim 8** presenting, at the graphical user interface, a plurality of options for user selection of a user input request for memory allocation generating the configuration data based on one or more user selections; The method according to claim 7, further comprising.

9. transmitting the configuration data to the computing device; allocating the data to memory locations within the pre-defined memory layout according to the configuration data; The method according to claim 7, further comprising.

10. displaying, on the graphical user interface, a result profile of the allocation of data to memory locations based on the configuration data, the result being transmitted to the graphical user interface as the layout of the data at each of the memory locations of the pre-defined memory layout, the method according to claim 8, further comprising the step of displaying.

11. The method according to claim 7, further comprising prioritizing the user input memory allocation requirements based on the estimated consumption level and the result profile.

12. An adjustment tool for an audio system having a digital signal processor (DSP) and a plurality of audio modules controlled by the DSP, a communication protocol for communication between the adjustment tool and the audio system; a graphical user interface for receiving the memory layout of the DSP transmitted from the audio system, the graphical user interface displaying the configuration of the memory layout; a memory allocation requirement input by a user on the graphical user interface, the memory allocation requirement changing the configuration of the memory layout; configuration data generated by the graphical user interface, the configuration data representing a change in the allocation of the audio modules at the memory locations of the memory configuration based on the memory allocation requirement and the memory capacity of the DSP, the configuration data being displayed on the graphical user interface; The adjustment tool, comprising.

13. The adjustment tool according to claim 12, wherein the graphical user interface further comprises a plurality of options for user selection, and one or more selections of user options from the plurality of options are used to generate the configuration data.

14. The adjustment tool according to claim 13, further comprising, in the graphical user interface, a consumption guide that displays an estimated consumption level for one or more user-selected memory placement requirements.

15. The DSP further includes an allocator, the graphical user interface transmits the configuration data to the DSP via the communication protocol, and the allocator in the DSP allocates the audio module stored in the memory layout at the corresponding memory location according to the configuration data. The adjustment tool according to claim 12.

16. The adjustment tool according to claim 15, further comprising a result profile displayed on the graphical user interface, the result profile showing a profiling result of the configuration of the memory layout changed according to the configuration data, and the profiling result being transmitted to the graphical user interface via the communication protocol and displayed as the result profile on the graphical user interface.

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