Resistive change type random access memory device having a non-reactive compound electrode

Abstract

The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode, a second electrode including a first conductive material, and an oxide switching layer positioned between the first electrode and the second electrode. The oxide switching layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer formed on the metal nitride layer. The metal layer includes a metal that is non-reactive with the at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and / or tantalum nitride. The metal layer includes a layer of a noble metal such as platinum, palladium, iridium, ruthenium, etc.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to resistive random access memory (RRAM) devices, and more particularly to RRAM devices having non-reactive compound electrodes.

Background Art

[0002] A resistive random access memory (RRAM) device is a two-terminal passive device having an adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying an appropriate programming signal to the RRAM device. RRAM devices can be used to form crossbar arrays for implementing in-memory computing applications, non-volatile solid-state memories, image processing applications, neural networks, and the like.

Summary of the Invention

[0003] A simplified summary of some aspects of the present disclosure is presented below. This summary is not an extensive overview of the present disclosure. Nor is it intended to identify key features or essential elements of the present disclosure or to delineate the scope of particular embodiments of the present disclosure or the claims. Its purpose is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description that follows.

[0004] According to one or more aspects of the present disclosure, a resistive random access memory (RRAM) device includes a first electrode, a second electrode including a conductive material, and an oxide switching layer positioned between the first electrode and the second electrode. The first electrode includes a metal nitride layer including a metal nitride and a metal layer formed on the metal nitride layer. The oxide switching layer includes at least one transition metal oxide. In some embodiments, the metal layer includes a metal that is non-reactive with the at least one transition metal oxide.

[0005] In some embodiments, the metal nitride includes at least one of titanium nitride and tantalum nitride.

[0006] In some embodiments, the metal that is non-reactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

[0007] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0008] In some embodiments, the thickness of the metal layer is from 3 nm to 10 nm.

[0009] In some embodiments, the thickness of the metal nitride layer is from 20 nm to 50 nm.

[0010] In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≤ 2.0 and y ≤ 2.5.

[0011] In some embodiments, the conductive material of the second electrode includes tantalum.

[0012] In some embodiments, the RRAM device further includes an interface layer located between the oxide switching layer and the second electrode. In some embodiments, the interface layer includes aluminum oxide.

[0013] In some embodiments, the RRAM device further includes an adhesion layer including at least one of titanium and tantalum, and the metal nitride layer is formed on the adhesion layer.

[0014] According to one or more aspects of the present disclosure, a method for manufacturing a resistive random access memory (RRAM) device includes forming a first electrode, forming an oxide switching layer on the first electrode, and forming a second electrode including a conductive material on the oxide switching layer. The oxide switching layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer formed on the metal nitride layer. In some embodiments, the metal layer includes a metal that is non-reactive with the at least one transition metal oxide.

[0015] In some embodiments, the metal nitride includes at least one of titanium nitride and tantalum nitride.

[0016] In some embodiments, the metal that is non-reactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

[0017] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0018] In some embodiments, the thickness of the metal layer is from 3 nm to 10 nm.

[0019] In some embodiments, the thickness of the metal nitride layer is from 20 nm to 50 nm.

[0020] In some embodiments, the at least one transition metal oxide includes at least one of HfO x and TaO y where x ≦ 2.0 and y ≦ 2.5.

[0021] In some embodiments, the method further includes forming an interface layer on the oxide switching layer, the interface layer being located between the oxide switching layer and the second electrode, and the interface layer including aluminum oxide.

[0022] In some embodiments, the method further comprises forming an adhesive layer comprising at least one of titanium and tantalum, and the metal nitride layer is formed on the adhesive layer.

[0023] According to one or more aspects of the present disclosure, a method for manufacturing a non-reactive electrode includes forming an adhesive layer including at least one of titanium and tantalum, forming a metal nitride layer including at least one metal nitride on the adhesive layer, forming a metal layer including a noble metal on the metal nitride layer, and selectively removing one or more portions of the adhesive layer, the metal nitride layer, and the metal layer to form a non-reactive electrode, wherein the metal nitride includes at least one of titanium nitride and tantalum nitride.

Brief Description of the Drawings

[0024] The present disclosure will be more fully understood from the following detailed description of various embodiments of the present disclosure. However, the drawings are not intended to limit the present disclosure to specific embodiments, but are for explanation and understanding.

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DETAILED DESCRIPTION OF THE INVENTION

[0025] Aspects of the present disclosure provide a resistive random access memory (RRAM) device and a method of manufacturing the same. The RRAM device is a two-terminal passive device having variable resistance. The RRAM device may include a first electrode, a second electrode, and an oxide switching layer positioned between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the bottom electrode and the top electrode of the RRAM device, respectively. In some embodiments, the first electrode and the second electrode may be the top electrode and the bottom electrode of the RRAM device, respectively. The first electrode may include a non-reactive metal such as platinum (Pt), palladium (Pd), ruthenium (Ru), etc. The second electrode may include a reactive metal such as tantalum (Ta). The electrode including the non-reactive metal is also referred to herein as a "non-reactive electrode". The electrode including the reactive metal is also referred to herein as a "reactive electrode". The oxide switching layer is hafnium oxide (HfO x ) or tantalum oxide (TaO x) may include transition metal oxides such as these. Before receiving an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device), the RRAM device is in an initial or unused state and may have an initial high resistance. The RRAM device may be adjusted from the unused state to the low resistance state through a forming process, or from the high resistance state (HRS) to the low resistance state (LRS) through a setting process. The forming process refers to programming the device from the unused state. The setting process refers to programming the device from the high resistance state (HRS). After the reactive metal electrode is deposited on the oxide switching layer, the reactive metal can absorb oxygen from the oxide switching layer, generating oxygen vacancies in the oxide switching layer, and oxygen ions can move within the oxide switching layer through a vacancy mechanism. During the forming process, when an appropriate programming signal (e.g., a voltage or current signal) is applied to the RRAM device, oxygen ions can be moved from the oxide switching layer to the reactive electrode. As a result, a conductive channel or filament is formed through the oxide switching layer (e.g., from the reactive electrode to the non-reactive electrode). Next, the RRAM device is reset to the high resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause oxygen to flow back into the oxide switching layer, blocking the conductive filament. The RRAM device can be electrically switched between the high resistance state and the low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device. In a crossbar array circuit, the programming signal can be supplied to a specified RRAM device through a selector such as a transistor or a diode.

[0026] An RRAM device including platinum (Pt) as the non-reactive electrode can provide high RRAM performance such as reliability, durability, multi-valuedness, and retention. The lower electrode of Pt, TaO x including an oxide switching layer, Ta (also referred to as the Pt / TaO x / Ta system) having an upper electrode in an RRAM, TaO xThe Ta filament in it showed excellent operations such as linearity, analog nature, retention, and durability for in-memory computing (IMC) applications. Pt / HfO x In the / Ta system, Ta moves into HfO x and can form Ta-rich filaments in HfO x showing excellent operations such as linearity, analog nature, retention, and durability for IMC applications. However, the material and process cost of Pt are high, and major manufacturing plants may not be ready to incorporate Pt into the process.

[0027] According to some embodiments of the present disclosure, the non-reactive compound electrode of the RRAM device may include a metal nitride layer and a metal layer. The metal nitride layer may include one or more metal nitrides such as TiN, TaN. The metal layer may include a non-reactive metal such as Pt, Pd, Ru, Ir. The metal layer may be substantially thinner than the metal nitride layer. For example, the metal nitride layer may be from about 20 nm to 25 nm, and the metal layer may be from about 3 nm to about 8 nm.

[0028] Both TiN and TaN are electrically conductive materials, compatible with the CMOS (complementary metal-oxide-semiconductor) process, mass-producible, and have a much lower manufacturing cost than Pt. The RRAM device including TiN or TaN in the non-reactive electrode may exhibit specific characteristics desirable for IMC applications such as multi-valued switching resistance and / or analog operation. Compared with the RRAM device with a non-reactive electrode including only TiN or TaN, the RRAM device with a non-reactive electrode including Pt has better performance but may be more expensive. By incorporating a metal nitride layer and a metal layer substantially thinner than the metal nitride layer (for example, a layer such as Pt, Pd, Ru, Ir), the structure for manufacturing the non-reactive compound electrode described herein provides a cost-effective solution for manufacturing RRAM devices with desirable switching and analog resistance operations.

[0029] Compared with the conventional RRAM devices using Pt-based non-reactive electrodes, the RRAM devices using the non-reactive compound electrodes described herein have low material and process costs, are compatible with the CMOS process, and are suitable for mass production. The RRAM devices disclosed herein exhibit appropriate performance and the ability of multi-valued switching and analog operation.

[0030] FIG. 1 is a schematic diagram of an example of a crossbar circuit 100 according to an embodiment of the present disclosure. As shown, the crossbar circuit 100 may include a plurality of interconnected electrically conductive wires such as one or more row wires 111a, 111b ··· 111i ··· 111n and column wires 113a, 113b ··· 113j ··· 113m for an n-row m-column crossbar array. The crossbar circuit 100 may further include cross-point elements 120a, 120b ··· 120z and the like. Each cross-point element may connect a row wire and a column wire. For example, the cross-point element 120ij can connect the row wire 111i and the column wire 113j. In some embodiments, the crossbar circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and / or other suitable circuit components for implementing a crossbar-based device. The numbers of the column wires 113a-m and the row wires 111a-n may be the same or different.

[0031] The row wires 111 may include a first row wire 111a, a second row wire 111b ··· 111i ··· an nth row wire 111n. Each of the row wires 111a ··· 111n may be and / or include a suitable electrically conductive material. In some embodiments, each of the row wires 111a-n may be a metal wire.

[0032] The column wires 113 may include a first column wire 113a, a second column wire 113b ··· an m-th column wire 113m. Each of the column wires 113a-m may be and / or include a suitable electrically conductive material. In some embodiments, each column wire 113a-m may be a metal wire.

[0033] Each cross-point element 120 may be and / or include a suitable variable resistance element such as a memristor, a PCM (phase change memory) element, a floating gate, a spintronics element, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more cross-point elements 120 may include the RRAM elements described in relation to FIGS. 3A-9C.

[0034] The crossbar circuit 100 can perform parallel weighted voltage multiplication and current addition. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar circuit 100. The input signal can flow through the cross-point elements of the rows of the crossbar circuit 100. The conductance of the cross-point elements can be adjusted to a specific value (also called "weight"). According to Ohm's law, the input voltage multiplies the cross-point conductance to generate a current from the cross-point elements. According to Kirchhoff's law, the sum of the currents passing through the elements of each column generates a current as the output signal (e.g., the output of an ADC) that can be read from the column. According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I = VG. Here, I represents the output signal matrix as current, V represents the input signal matrix as voltage, and G represents the conductance matrix of the cross-point elements. Thus, the input signal is weighted by the conductance at each cross-point element according to Ohm's law. The weighted current is output via each column wire and can be accumulated according to Kirchhoff's current law. This enables in-memory computing (IMC) by parallel multiplication and addition performed in the crossbar array.

[0035] FIG. 2 is a schematic diagram of an example of a cross-point element 200 according to an embodiment of the present disclosure. As shown, the cross-point element 200 can connect bit lines (BL) 211, selection lines (SEL) 213, and word lines (WL) 215. The bit lines 211 and the word lines 215 may be the column wires and the row wires described in connection with FIG. 1, respectively.

[0036] The cross-point element 200 may include an RRAM element 201 and a transistor 203. The transistor is a three-terminal element and may be labeled as gate (G), source (S), and drain (D), respectively. The transistor 203 may be connected in series to the RRAM element 201. As shown in FIG. 2, the first electrode of the RRAM element 201 may be connected to the drain of the transistor 203. The second electrode of the RRAM element 201 may be connected to the bit line 211. The source of the transistor 203 may be connected to the word line 215. The gate of the transistor 203 may be connected to the select line 213. The RRAM element 201 may include one or more RRAM elements described in connection with FIGS. 3A-9C below. The cross-point element 200 is also referred to as a one-transistor-one-resistance (1T1R) configuration. The transistor 203 can function as a selector and as a current controller that sets current compliance for the RRAM element 201 during programming. The gate voltage of the transistor 203 can set current compliance for the cross-point element 200 during programming, thereby controlling the conductance and analog operation of the cross-point element 200. For example, when the cross-point element 200 is set from a high-resistance state to a low-resistance state, a set signal (e.g., a voltage signal, a current signal) may be supplied via the bit line (BL) 211. While the word line (WL) 215 is grounded, another voltage, also referred to as a select voltage or a gate voltage, can be applied to the transistor gate via the select line (SEL) 213 to open the gate and set the current compliance. When the cross-point element 200 is reset from a low-resistance state to a high-resistance state, the gate voltage can be applied to the gate of the transistor 203 via the select line 213 to open the transistor gate. On the other hand, while the bit line 211 is set to ground, a reset signal can be sent to the RRAM element 201 via the word line 215.

[0037] Figures 3A, 3B, and 3C show cross-sectional views of RRAM devices 300a, 300b, and 300c according to some embodiments of the present disclosure. The RRAM devices 300b and 300c may respectively correspond to the low-resistance state and the high-resistance state of the RRAM device 300a.

[0038] As shown in FIG. 3A, the RRAM device 300a may include a substrate 310, a first electrode 320 formed on the substrate 310, an oxide switching layer 330, and a second electrode 340. The oxide switching layer 330 is formed between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of a suitable material that can function as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnect, an integrated circuit, etc. In some embodiments, the substrate may include a drive circuit including one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal-oxide-semiconductor (CMOS) drivers.

[0039] The first electrode 320 is electrically conductive and may include a metal nitride that is non-reactive with the formed oxide switching layer. The metal nitride may have suitable chemical stability so as not to react with oxygen during RRAM switching. The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The first electrode 320 may further include a non-reactive metal that is electrically conductive and does not react with oxygen during RRAM switching, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), etc. An RRAM device having a metal nitride and a non-reactive metal in the non-reactive electrode has desirable multi-valued resistance and analog operation for IMC applications.

[0040] In some embodiments, the first electrode 320 is, and / or may include, a compound bottom electrode as described in connection with FIG. 4. For example, the first electrode 320 may have a metal nitride layer including one or more metal nitrides (e.g., TiN, TaN, etc.). The first electrode 320 may further include a metal layer including one or more noble metals (e.g., Pt, Pb, Ir, Ru, etc.) formed on the metal nitride layer. The metal layer is thinner than the metal nitride layer in some embodiments.

[0041] In some embodiments, a layer of Ta and / or Ti (not shown in FIG. 3C) may be formed between the first electrode and the substrate 310 to enhance the adhesion between the substrate 310 and the components of the RRAM device 300a.

[0042] The oxide switching layer 330 may include one or more transition metal oxides of binary oxides, ternary oxides, and higher-order oxides such as TaO x , HfO x , TiO x , NbO x , ZrO x , etc. In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than that of the transition metal oxide in the oxide switching layer 330. In some embodiments, the transition metal oxide includes at least one of HfO x and TaO x , where x is used to indicate that the oxide is oxygen-deficient compared to the complete oxide, and the value of x may vary depending on the atomic ratio of oxygen to metal in the stoichiometry of the complete oxide. For example, for HfO x , x ≤ 2.0, HfO2 is the complete oxide, and for TaO x , x ≤ 2.5, Ta2O5 is the complete oxide.

[0043] The second electrode 340 is electrically conductive and may include a suitable metal material that reacts with the oxide switching layer. For example, the metal material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the oxide switching layer, have an oxygen solubility suitable for adsorbing oxygen from the oxide switching layer 330 and generating oxygen vacancies in the oxide switching layer 330. In other words, the reactive metal material in the second electrode 340 may have a suitable oxygen solubility and / or oxygen mobility. In some embodiments, the second electrode 340 can not only generate oxygen vacancies in the oxide switching layer 330 (e.g., by capturing oxygen), but also function as an oxygen reservoir or source to the oxide switching layer 330 during device programming.

[0044] The RRAM element 300a may have an initial resistance (also referred to as "unused resistance") after manufacturing. The initial resistance of the RRAM element 300a can be changed, and the RRAM element 300a can be switched to a lower resistance state through a forming process. For example, an appropriate voltage or current can be applied to the RRAM element 300a. Applying a voltage to the RRAM element 300a can cause the metal material at the second electrode to absorb oxygen from the oxide switching layer 330, generating oxygen vacancies in the oxide switching layer 330. As a result, a conductive channel (e.g., a filament) rich in oxygen vacancies can be formed within the oxide switching layer 330. For example, as shown in FIG. 3B, a conductive channel 335a can be formed within the oxide switching layer 330. As shown in FIG. 3B, the conductive channel 335a can be formed across the oxide switching layer 330 from the second electrode 340 to the first electrode 320. The RRAM element 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM element 300b during the reset process. In some embodiments, the set signal and the reset signal may have opposite polarities, i.e., a positive signal and a negative signal respectively. Applying the reset signal can cause oxygen to flow back into the oxide switching layer 330 and recombine with one or more oxygen vacancies. For example, as shown in FIG. 3C, a disrupted conductive channel 335b can be formed within the oxide switching layer 330 during the reset process. As shown in FIG. 3C, the conductive channel can be interrupted with an oxide gap between the disrupted conductive channel 335b and the first electrode 320. The lateral dimension of the disrupted conductive channel 335b may be smaller than that of the conductive channel 335a. In some embodiments, the disrupted conductive channel 335b does not continuously connect the first electrode 320 and the second electrode 340. The RRAM elements 300a-c can be electrically switched between a high resistance state and a low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM elements.

[0045] In one embodiment, the second electrode 340 may include one or more alloys. Each alloy may include two or more metal elements. Each alloy may include a binary alloy (e.g., an alloy including two metal elements), a ternary alloy (e.g., an alloy including three metal elements), a quaternary alloy (e.g., an alloy including four metal elements), a quinary alloy (e.g., an alloy including five metal elements), a senary alloy (e.g., an alloy including six metal elements), and / or a higher-order alloy (e.g., an alloy including more than six metal elements). In some embodiments, the second electrode 340 may include one or more alloys including a first metal element and one or more second metal elements. Each second metal element may be less or more reactive with respect to the transition metal oxide in the oxide switching layer than the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. In some embodiments, the ratio of the first metal element to the second metal element in the alloy in the second electrode 340 may be about 50 atomic %. In some embodiments, an appropriate ratio of the first metal element to the second metal element in the alloy can be optimized from the entire composition range. During the formation process, the second metal element may generate fewer oxygen vacancies in the oxide switching layer than the first metal element. Thus, the lateral size of the filament formed within the RRAM device having the second electrode including the alloy may be smaller than that of the filament formed within the RRAM device having the second electrode made of only the first metal.

[0046] In some embodiments, the second electrode 340 may include a plurality of layers of different metal materials. For example, the second electrode 340 may include a layer of titanium (Ti) and a layer of tantalum (Ta). The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between about 0.2 nm and 5 nm. The thickness of the Ta layer may be about 50 nm. In some embodiments, the thickness of the Ti layer may be between 0.3 nm and 2 nm. Both Ti and Ta can trap and release oxygen during device operation. Incorporation of a thin Ti layer into the RRAM device can change the unused resistance of the RRAM device, result in a less abrupt forming process, reduce the forming voltage, reduce the reset current, and reduce the voltage and / or current requirements in subsequent operation processes.

[0047] FIG. 4 shows a cross-sectional view of a non-reactive compound electrode 400 according to another embodiment of the present disclosure.

[0048] As shown, the non-reactive electrode 400 may include a metal nitride layer 410 and a metal layer 420. The metal layer 420 may be formed on the metal nitride layer 410. The metal nitride layer 410 may include one or more layers of one or more metal nitrides. Examples of metal nitrides include TiN, TaN, and the like. The metal layer 420 may include one or more noble metals (e.g., Pt, Pb, Ru, etc.). In some embodiments, the metal layer 420 may be thinner than the metal nitride layer 410. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 25 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 50 nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20 nm and about 30 nm. The thickness of the metal layer 420 may be between about 3 nm and about 10 nm. In some embodiments, the metal layer 420 may be thicker than 2 - 3 nm and include a continuous film of noble metal covering the metal nitride layer 410.

[0049] FIG. 5 shows a cross-sectional view of an RRAM device 500 including a compound non-reactive electrode according to an embodiment of the present disclosure.

[0050] The RRAM device 500 may include an adhesion layer 510, a first electrode 520, an oxide switching layer 530, an interface layer A (ILA) 550, and a second electrode 540. The first electrode 520, the oxide switching layer 530, and the second electrode 540 may be the same as the first electrode 320, the oxide switching layer 330, and the second electrode 340 described in connection with FIG. 3A, respectively. As shown in FIG. 5, the first electrode 520 may include the metal nitride layer 410 and the metal layer 420 described in connection with FIG. 4. In some embodiments, the adhesion layer 510 may be regarded as part of the first electrode 520.

[0051] The adhesion layer 510 may include one or more suitable metal materials that can enhance the adhesion between the substrate and the components of the RRAM device 500. In some embodiments, the adhesion layer 510 may include one or more layers such as Ti, Ta, etc.

[0052] The ILA 550 (also referred to as the "first interface layer") may include a first material that is more chemically stable than the transition metal oxide in the oxide switching layer. The first material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. The ILA 550 may include a discontinuous film of the first material and / or a continuous film of the first material. In some embodiments, the thickness of the ILA 550 may be between about 0.2 nm and about 0.5 nm. In some embodiments, the ILA 550 may include an Al2O3 film with a thickness of 0.5 nm or less. In some embodiments, the ILA 550 may be, and / or may include, an Al2O3 film with a thickness of less than 1 nm. The RRAM device 500 having an ILA 550 including aluminum oxide may be a high-resistance and annealing-resistant RRAM device.

[0053] FIG. 6 shows a cross-sectional view of an RRAM device 600 including a compound non-reactive electrode according to a further embodiment of the present disclosure.

[0054] The RRAM device 600 may include an adhesive layer 610, a first electrode 620, an interface layer B (ILB) 660, an oxide switching layer 630, an interface layer A (ILA) 650, and a second electrode 640. The first electrode 620, the oxide switching layer 630, and the second electrode 640 may be the same as the first electrode 320, the oxide switching layer 330, and the second electrode 340 described in connection with FIG. 3A, respectively. The adhesive layer 610 may be the same as the adhesive layer 510 of FIG. 5. The ILA 650 may be the same as the ILA 550 of FIG. 5. In some embodiments, the RRAM device 600 may further include a substrate (not shown) described in connection with FIG. 3A.

[0055] The ILB 660 may include a second material that is more chemically stable than the transition metal oxide in the oxide switching layer 630. The second material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. The ILB 660 may include a discontinuous film of the second material and / or a continuous film of the second material. In some embodiments, the thickness of the ILB 660 may be between about 0.2 nm and about 0.5 nm. In some embodiments, the ILB 660 may include an Al2O3 film with a thickness of 0.5 nm or less. In some embodiments, the ILB 660 may be, and / or may include, an Al2O3 film with a thickness of less than 1 nm. The RRAM device 600 having the first interface layer and the second interface layer may be a high-resistance and annealing-resistant RRAM device.

[0056] In some embodiments, the ILA 650 may be omitted from the RRAM device 600. For example, as shown in FIG. 7, the RRAM device 700 may include the adhesive layer 610, the first electrode 620, the interface layer B (ILB) 660, the oxide switching layer 630, and the second electrode 640 described in connection with FIG. 6.

[0057] FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, FIG. 8E, and FIG. 8F are schematic diagrams showing cross-sectional views of structures for forming non-reactive electrodes of RRAM devices according to embodiments of the present disclosure.

[0058] As shown in FIG. 8A, a substrate 810 may be provided. The substrate 810 may include one or more layers of a suitable material that can function as a substrate for manufacturing RRAM devices. For example, it may include silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 810 may include a diode, a transistor, an interconnection, an integrated circuit, etc. The substrate 810 may include a drive circuit including one or more individually controllable electrical circuits (e.g., an array of electrical circuits). In some embodiments, the drive circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers. In some embodiments, the substrate 810 may include one or more dielectric layers, interconnection layers, transistors, and / or other suitable components (not shown) for forming a crossbar circuit. Each interconnection layer can include one or more metal pads and / or metal vias and can provide electrical connections between the devices formed on the substrate 810.

[0059] As shown in FIG. 8A, the substrate 810 may have an interconnect layer including one or more metal interconnects (e.g., metal pads and / or metal vias). For example, the first interconnect layer may have metal interconnects 811a and 811b (also referred to as the "first metal interconnect" and the "second metal interconnect"). In some embodiments, the metal interconnects 811a and 811b may be metal pads including tungsten (W), Al, Cu, and other suitable metals. In some embodiments, the metal interconnects 811a and 811b may be metal vias including aluminum (Al), copper (Cu), tungsten (W), etc. Each of the metal interconnects 811a and 811b may be connected to another element (not shown) such as a transistor, a diode, etc. In some embodiments, the metal interconnects 811a - b may include tungsten (W) vias and doped polycrystalline Si (polysilicon) terminals, and the polysilicon terminals can be connected to transistor or diode terminals (not shown).

[0060] As shown in FIG. 8B, an adhesion layer 821 may be formed on the metal interconnects 811a and 811b and the substrate 810. The adhesion layer 821 may include Ta, a layer of Ti, and / or other suitable materials that can enhance the adhesion between the substrate 810 and the components of the RRAM device formed on the substrate 810.

[0061] As shown in FIG. 8C, a metal nitride layer 823 may be formed on the adhesion layer 821. The metal nitride layer 823 may have one or more layers of one or more metal nitrides that are electrically conductive and non - reactive with respect to the oxide switching of the RRAM device formed on the substrate 810. The metal nitride may include, for example, TiN, TaN, etc.

[0062] As shown in FIG. 8D, a metal layer 825 may be formed on the metal nitride layer 823. The metal layer 825 may include one or more layers of one or more suitable metals (also referred to as “non-reactive metals”) that are electrically conductive and non-reactive with respect to the oxide switching of the RRAM device formed on the substrate 810. Examples of non-reactive materials include Pt, Pd, Ir, Ru, and the like.

[0063] To form one or more bottom electrodes, one or more portions of the adhesion layer 821, the metal nitride layer 823, and the metal layer 825 can be selectively removed. For example, as shown in FIG. 8E, by patterning and etching the adhesion layer 821, the metal nitride layer 823, and the metal layer 825, a first bottom electrode 820a and a second bottom electrode 820b can be formed on the metal interconnects 811a and 811b, respectively. The first bottom electrode 820a may include a first adhesion layer 821a, a first metal nitride layer 823a, and a first metal layer 825a. The second bottom electrode 820b may include a second adhesion layer 821b, a second metal nitride layer 823b, and a second metal layer 825b. The first adhesion layer 821a and the second metal nitride layer 821b may correspond to the etched adhesion layer 821. The first metal nitride layer 823a and the second metal nitride layer 823b may correspond to the etched metal nitride layer 823. The first metal layer 825a and the second metal layer 825b may correspond to the etched metal layer 825. In some embodiments, the lateral dimension of the bottom electrodes 820a-b may be larger than that of the metal interconnects 811a-b. The first bottom electrode 820a can form an ohmic contact by directly contacting the metal interconnect 811a. The second bottom electrode 820b can form an ohmic contact by directly contacting the second metal interconnect 811b. The first bottom electrode 820a and the second bottom electrode 820b can further contact one or more portions of the substrate 810, such as one or more portions of the surface 801 (e.g., the upper surface) of the substrate 810.

[0064] As shown in FIG. 8F, the RRAM layers 830a and 830b may be formed on the first bottom electrode 820a and the second bottom electrode 820b, respectively. Each of the RRAM layers 830a and 830b may include an oxide switching layer, a top electrode, and one or more interface layers, as described in connection with FIGS. 3A-7 above. In some embodiments, the RRAM layers 830a and 830b may be formed using the techniques described in U.S. Patent Application Nos. 17 / 654,476 and 17 / 936,830, which are incorporated herein by reference.

[0065] FIG. 9A is a drawing 900A showing the I-V (current-voltage) characteristics of an exemplary RRAM device including a non-reactive compound electrode according to some embodiments of the present disclosure. FIG. 9B shows an I-V curve 900B showing the analog operation of the RRAM device. FIG. 9C is a drawing 900C showing the device read current characteristics over time of an exemplary RRAM device.

[0066] As shown in FIG. 9A, the RRAM device performs a repeatable and desirable set / reset operation on a plurality of switches (e.g., switch 1, switch 2, and switch 3), demonstrating stability for multi-valued switching operation. As shown in FIG. 9B, the RRAM device performs a desirable analog operation. That is, the resistance of the device can be adjusted to a multi-valued (or analog operation) by controlling the current compliance, and the current is linearly proportional to the voltage (or operates linearly) in each resistance state. As shown in FIG. 9C, drawing 900C can represent the results of a device retention test for the ability of the RRAM device to maintain a resistance level over time, and the results of a read stability test for the ability of the RRAM device to maintain a resistance level over time under a constant read (at a read voltage of 0.2V). As shown in FIG. 9C, the RRAM device exhibits desirable device read stability over time.

[0067] FIG. 10 is a flowchart showing an example 1000 of a method of manufacturing an RRAM device including the RRAM devices 500, 600, and 700 of FIGS. 5, 6, and 7 according to some embodiments of the present disclosure.

[0068] In block 1010, the first electrode may be formed on the substrate. Forming the first electrode may include depositing one or more layers of a metal nitride such as TiN or TaN. For example, forming the first electrode may include depositing one or more layers of TiN using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Ti, and / or other suitable deposition technologies. Forming the first electrode may further include depositing one or more non-reactive metals on the metal nitride. The first electrode may be, and / or may include, the non-reactive compound electrode described in relation to FIG. 4 above. In some embodiments, forming the first bottom electrode may include performing one or more operations described in relation to FIG. 11 below.

[0069] In block 1020, an interface layer B (ILB) may be formed on the first electrode. The ILB may include a material that is chemically more stable than the transition metal oxide of the oxide switching layer described below (for example, AlO such as Al2O3). For example, forming the interface layer B may include depositing AlO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Al, and / or other suitable deposition technologies. The interface layer B may be, and / or may include, the ILB660 described in relation to FIG. 6 above. In some embodiments, block 1020 may be omitted from method 1000. x ) may be included. For example, forming the interface layer B may include depositing AlO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Al, and / or other suitable deposition technologies. The interface layer B may be, and / or may include, the ILB660 described in relation to FIG. 6 above. In some embodiments, block 1020 may be omitted from method 1000. x In block 1030, an oxide switching layer including one or more transition metal oxides may be formed on the interface layer B. The transition metal oxide may include, for example, HfO. For example, forming the oxide switching layer may include depositing HfO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Hf, and / or other suitable deposition technologies.

[0070] In block 1030, an oxide switching layer including one or more transition metal oxides may be formed on the interface layer B. The transition metal oxide may include, for example, HfO. For example, forming the oxide switching layer may include depositing HfO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Hf, and / or other suitable deposition technologies. x may be included. For example, forming the oxide switching layer may include depositing HfO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Hf, and / or other suitable deposition technologies. xmay include depositing. The oxide switching layer may be and / or may include the oxide switching layer 630 described in connection with FIG. 6 above.

[0071] In block 1040, an interface layer A (ILA) may be formed on the oxide switching layer. The ILA may include a material that is chemically more stable than the transition metal oxide of the oxide switching layer, such as AlO such as Al2O3. x For example, forming the interface layer A may utilize atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, reactive sputtering technology of Al, and / or other suitable deposition technologies to deposit AlO. x may include depositing. The interface layer A may be and / or may include the ILA 650 described in connection with FIG. 6 above.

[0072] In block 1050, a second electrode may be formed on the interface layer A. Forming the second electrode may include forming one or more layers of one or more metal materials that are electrically conductive and reactive to oxide switching. For example, forming the second electrode may include depositing one or more layers of Ta using physical vapor deposition (PVD) technology and / or other suitable deposition technologies. The second electrode may be and / or may include the second electrode 640 described in connection with FIG. 6 above.

[0073] FIG. 11 is a flowchart showing an example 1100 of a method for manufacturing a non-reactive electrode as described in connection with FIGS. 4 and 8A-8F according to some embodiments of the present disclosure.

[0074] In block 1110, an adhesion layer may be formed on the substrate. Forming the adhesion layer may include depositing a layer of a metal such as Ta or Ti that can strengthen the adhesion between the substrate and the bottom electrode and / or other components of the RRAM device formed on the substrate. In some embodiments, forming the adhesion layer may include depositing a Ti film or a Ta film having a thickness between about 2 nm and 5 nm. The adhesion layer may be deposited using suitable PVD techniques and / or other suitable deposition techniques for depositing metals. In some embodiments, block 1110 may be omitted from method 1100.

[0075] In block 1120, a metal nitride layer may be formed on the adhesion layer. Forming the metal nitride layer may include depositing a layer of a metal nitride that is non-reactive with the transition metal oxide in the oxide switching layer formed on the bottom electrode. For example, forming the metal nitride layer may include depositing a layer such as TiN or TaN using ALD, PVD, reactive sputtering techniques, or other suitable deposition techniques.

[0076] In block 1130, a metal layer may be formed on the metal nitride layer. Forming the metal layer may include depositing one or more of the non-reactive metals described herein. In some embodiments, forming the metal layer may include depositing Pt, Pd, Ir, Ru, etc. on the metal nitride layer using PVD techniques or other suitable deposition techniques. In some embodiments, forming the metal layer may include depositing a layer of Pt, Pd, Ir, or Ru having a thickness between about 3 nm and about 10 nm.

[0077] In some embodiments, in block 1140, one or more portions of the adhesion layer, the metal nitride layer, and the metal layer may be selectively removed to form one or more bottom electrodes. For example, as described in connection with FIG. 8E, the adhesion layer, the metal nitride layer, and the metal layer may be patterned and etched to form a first bottom electrode 820a and a second bottom electrode 820b.

[0078] To simplify the description, the methods of the present disclosure are depicted and described as a series of operations. However, the operations in accordance with the present disclosure can be performed in various orders and / or simultaneously, as well as with other operations not presented and described herein. Further, not all of the operations shown are necessary to implement the methods in accordance with the present disclosure. Additionally, as would be understood and recognized by those skilled in the art, the methods can alternatively be represented as a series of interrelated states via a state diagram or events.

[0079] As used herein, "about", "approximately", and "substantially" can mean within ± 20% of the target dimension in some embodiments, within ± 10% of the target dimension in some embodiments, within ± 5% of the target dimension in some embodiments, within ± 2% of the target dimension in some embodiments, within ± 1% of the target dimension in some embodiments, and within ± 0.1% of the target dimension in some further embodiments, etc., within the normal tolerances in the art, e.g., within 2 standard deviations of the mean. "About" and "approximately" may include the target dimension. Unless otherwise specified or apparent from the context, all numerical values described herein are modified by "about".

[0080] Ranges used herein include all values within that range. For example, a range from 1 to 10 may include any number, any combination of numbers, any sub - range, and fractions thereof from the numbers 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0081] In the foregoing description, numerous details are set forth. However, it is apparent that the present disclosure can be practiced without these specific details. In some instances, well - known structures and elements are shown in block diagram form in order to avoid obscuring the present disclosure.

[0082] As used herein, terms such as "first", "second", "third", "fourth", etc. are meant as labels to distinguish different elements and do not necessarily have an ordinal meaning according to their numerical designation.

[0083] As used herein, the terms "example" or "exemplary" are used to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms "example" or "exemplary" is intended to present concepts in a concrete form. As used in this application, "or" is intended to mean an inclusive "or" unless otherwise specified or clear from the context. That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to be satisfied under any of the following cases: when X includes A, when X includes B, or when X includes both A and B. Additionally, the articles "a" and "an" used in this application and the appended claims should generally be construed to mean "one or more" unless otherwise specified or clear from the context that they refer to the singular form. References throughout this specification to "an embodiment" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "an embodiment" or "one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.

[0084] As used herein, when an element or layer is referred to as being "on" another element or layer, that element or layer may be directly on the other element or layer or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on" another element or layer, no intervening elements or layers are present.

[0085] Many variations and modifications of the present disclosure will be apparent to those skilled in the art after reading the foregoing description. Although illustrated and described by way of example of specific embodiments, it is in no way intended to be construed that any particular embodiment is limiting. Accordingly, references to details of various embodiments are not intended to limit the scope of the claims, which recite only those features described in the claims.

[0086] [Cross - reference to related applications] This application claims the benefit of U.S. Patent Application No. 18 / 163,272, filed on February 1, 2023, entitled "Resistive Random Access Memory Element with a Non - Reactive Compound Electrode", which is a continuation - in - part of U.S. Patent Application No. 17 / 843,347, filed on June 17, 2022, entitled "Resistive Random Access Memory Element with a Metal Nitride Compound Electrode", each of which is hereby incorporated by reference in its entirety.

Claims

1. A resistive random access memory (RRAM) device, comprising: a first electrode including a metal nitride layer containing a metal nitride and a metal layer formed on the metal nitride layer; a second electrode including a conductive material; an oxide switching layer positioned between the first electrode and the second electrode; and the oxide switching layer includes at least one transition metal oxide; the metal layer includes a metal that is non-reactive with the at least one transition metal oxide; RRAM device.

2. The RRAM device according to claim 1, wherein the metal nitride includes at least one of titanium nitride and tantalum nitride.

3. The RRAM device according to claim 1, wherein the metal that is non-reactive with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

4. The RRAM device according to claim 3, wherein the metal layer is thinner than the metal nitride layer.

5. The RRAM device according to claim 4, wherein the thickness of the metal layer is between 3 nm and 10 nm.

6. The RRAM device according to claim 5, wherein the thickness of the metal nitride layer is between 20 nm and 50 nm.

7. The at least one transition metal oxide includes HfO ｘ and at least one of TaO ｙ and The RRAM device according to claim 1, wherein x ≤ 2.0 and y ≤ 2.

5.

8. The RRAM device according to claim 1, wherein the conductive material of the second electrode includes tantalum.

9. further comprising an interface layer positioned between the oxide switching layer and the second electrode, wherein the interface layer includes aluminum oxide; The RRAM device according to claim 1.

10. further comprising an adhesion layer including at least one of titanium and tantalum, wherein the metal nitride layer is formed on the adhesion layer; The RRAM device according to claim 1.

11. A method for manufacturing a resistive random access memory (RRAM) device, comprising: forming a first electrode including a metal nitride layer containing a metal nitride and a metal layer formed on the metal nitride layer; forming an oxide switching layer on the first electrode; forming a second electrode including a conductive material on the oxide switching layer; wherein the oxide switching layer includes at least one transition metal oxide; the metal layer includes a metal that is non-reactive with the at least one transition metal oxide; method.

12. The method according to claim 11, wherein the metal nitride contains at least one of titanium nitride and tantalum nitride.

13. The method according to claim 12, wherein the metal that is non-reactive with the at least one transition metal oxide contains at least one of platinum, palladium, iridium, and ruthenium.

14. The method according to claim 13, wherein the metal layer is thinner than the metal nitride layer.

15. The method according to claim 14, wherein the thickness of the metal layer is between 3 nm and 10 nm.

16. The method according to claim 15, wherein the thickness of the metal nitride layer is between 20 nm and 50 nm.

17. The at least one transition metal oxide includes HfO ｘ and TaO ｙ and includes at least one of them, The method according to claim 11, wherein x ≤ 2.0 and y ≤ 2.

5.

18. Further comprising forming an interface layer on the oxide switching layer, wherein the interface layer is located between the oxide switching layer and the second electrode, The method according to claim 11, wherein the interface layer contains aluminum oxide.

19. Further comprising forming an adhesive layer containing at least one of titanium and tantalum, The method according to claim 11, wherein the metal nitride layer is formed on the adhesive layer.

20. A method for manufacturing a non-reactive electrode, comprising: forming an adhesive layer containing at least one of titanium and tantalum; forming a metal nitride layer containing at least one metal nitride on the adhesive layer; forming a metal layer containing a noble metal on the metal nitride layer; selectively removing one or more portions of the adhesive layer, the metal nitride layer, and the metal layer to form the non-reactive electrode; and wherein the metal nitride contains at least one of titanium nitride and tantalum nitride. method

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