Method for manufacturing a power semiconductor device and a power semiconductor device

Abstract

The present disclosure relates to a method for manufacturing a power semiconductor device (20), the method comprising forming at least one insulating layer (3) on a surface (2a) of a crystal growth substrate (2), the at least one insulating layer (3) comprising at least one cavity (4) extending in a lateral direction (22) within the at least one insulating layer (3); selectively growing a wide bandgap (WBG) semiconductor material within the cavity (4) to form a lateral epitaxial layer (9), wherein a surface region of the growth substrate (2) exposed via at least one passage (5) formed between the at least one cavity (4) and the growth substrate (2) is used as a seed region for epitaxially growing the WBG semiconductor material; forming at least one semiconductor junction, in particular a pn junction (6), an np junction or a Schottky junction (8), inside or at an end of the selectively grown WBG semiconductor material. The present disclosure further relates generally to a power semiconductor device (20), and in particular to a MISFET (25).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a power semiconductor device and a corresponding power semiconductor device having an epitaxial layer including a wide bandgap semiconductor material.

Background Art

[0002] Wide bandgap (WBG) semiconductor materials such as silicon carbide (SiC) have advantageous properties including a high critical electric field and electron mobility or high-frequency switching. Therefore, they provide a much larger Baliga Figure-Of-Merit (BFOM) compared to commonly used semiconductor materials such as silicon, making them a good option for power semiconductor devices such as power MISFETs. These advantages enable several applications for energy efficiency and electrical transport. However, the relatively high cost and processing complexity associated with the manufacture of power semiconductor devices including an epitaxial growth layer (epi-layer) of WBG materials limit their use in many fields.

Summary of the Invention

Means for Solving the Problems

[0003] Embodiments of the present disclosure relate to a method for manufacturing a power semiconductor device and a corresponding power semiconductor device comprising a selectively grown lateral epi-layer, which can be manufactured using a semiconductor material with a narrower bandgap and / or in a shorter time.

[0004] According to a first aspect, a method for manufacturing a power semiconductor device is disclosed. The manufacturing method is - forming at least one insulating layer on a surface of a crystal growth substrate, the at least one insulating layer comprising at least one cavity extending laterally within the at least one insulating layer; - Selectively growing a wide bandgap (WBG) semiconductor material in a cavity to form a lateral epitaxial layer, wherein a surface region of a growth substrate exposed through at least one passage formed between at least one cavity and the growth substrate is used as a seed region for epitaxially growing the WBG material, and growing; - Forming at least one semiconductor junction, particularly a pn junction, np junction or Schottky junction, inside or at an end of the selectively grown WBG semiconductor material.

[0005] In particular, the inventors have found that when the WBG material used, for example, in the active region of a device is selectively grown rather than etched from a bulk epitaxial layer of the WBG material, the amount of WBG material required for manufacturing a power semiconductor device can be reduced. In other words, an additive manufacturing technique is used instead of a subtractive manufacturing technique. The growth of the WBG material can be controlled in a desired direction, for example, laterally, by at least one insulating layer having a cavity acting as a growth template. This also enables the growth of a WBG material such as 3C, 4H or 6H silicon carbide (SiC) on a substrate made of different materials such as doped or undoped silicon (Si), SiC on Si, SiC on insulator (SiCOI), sapphire or gallium nitride (GaN), further reducing the amount of WBG material required.

[0006] In at least one embodiment, at least one passage is configured as a defect filter for the WBG material such that the lateral epitaxial layer is essentially defect-free. The smoother surface of the selectively grown essentially defect-free WBG structure improves the carrier mobility in the grown epitaxial layer compared to a dry-etched epitaxial layer.

[0007] In at least one embodiment, at least one semiconductor junction is formed by incorporating at least one dopant during the selective growth of a WBG semiconductor material, particularly during the growth of a lateral epitaxial layer. In this way, the growth and doping of the active region can be performed in a single processing step, further simplifying the manufacturing process and enabling, for example, a clear difference in carrier concentration in each region of the epitaxial layer corresponding to a process or box related to the concentration of at least one dopant. Additionally, it substantially reduces manufacturing costs by avoiding the ion implantation and / or high-temperature dopant activation processes required in some existing WBG semiconductor manufacturing methods.

[0008] In at least one embodiment, forming at least one insulating layer includes forming a first dielectric layer, particularly a first silicon dioxide layer, on the surface of a growth substrate, forming at least one hole in the first dielectric layer to form at least one via, depositing and structuring a sacrificial material in a region corresponding to at least one cavity, forming a second dielectric layer, particularly a second silicon dioxide layer, on the first dielectric layer and the sacrificial material, and removing the sacrificial material to form at least one cavity between the first dielectric layer and the second dielectric layer. In this way, the cavity for forming the growth template can be formed using well-established semiconductor processing steps and environments, such as CMOS industrial reactors used to process conventional non-WBG semiconductor wafers, e.g., 200 mm silicon wafers.

[0009] According to a second aspect, a power semiconductor device is disclosed. The device comprises - a substrate comprising a first material, - at least one insulating layer disposed on the surface of the substrate and comprising at least one cavity, wherein at least one cavity extends laterally within the at least one insulating layer, - at least one via formed between the at least one cavity and the substrate, - At least one epi-layer comprising a second material, wherein a first portion of the at least one epi-layer extends laterally within at least one cavity, and at least a second portion of the at least one epi-layer extends vertically through an opening to contact a first material, and the second material is a wide bandgap (WBG) semiconductor material different from the first material, the at least one epi-layer; - At least one semiconductor junction, in particular a pn junction, an np junction or a Schottky junction, formed inside or at an end of the at least one epi-layer.

[0010] Such a device combines the advantageous electrical properties of an epi-layer containing a WGB semiconductor material with the simple connectivity of a lateral power semiconductor device such as a lateral power MOSFET, and the use of a substrate formed from a different, potentially less expensive bulk material.

[0011] The disclosed structure provides a significant improvement in device capabilities compared to existing power semiconductor devices. In particular, it makes it possible to avoid mobility degradation, which is a major problem in conventional SiC MOSFETs. The high density of interface states in SiC MOS structures limits the potential of WBG materials. In contrast, the potentially very high surface-to-volume ratio of the proposed lateral epi-layer increases, for example, the channel density of a MOSFET, reduces the off-current, and thus provides lower electrostatic power consumption.

[0012] In at least one embodiment, the first material includes at least one of doped silicon (Si), undoped Si, 4H, 6H, or 3C silicon carbide (SiC), such as 3C-on-Si, silicon carbide on insulator (SiCOI), semi-insulating SiC, sapphire, or gallium nitride (GaN). Alternatively or additionally, the second material includes at least one of 3C, 4H, or 6H silicon carbide. Alternatively or additionally, at least one insulating layer includes silicon dioxide. The above materials are suitable for established semiconductor manufacturing processes and include many advantageous properties such as low cost or good insulating properties compared to devices that include only a single WBG material. Thus, these materials enable the economical manufacture of power semiconductor devices having an epitaxial layer that includes a WBG semiconductor material.

[0013] In at least one embodiment, a first portion of at least one epitaxial layer extends laterally from 5 to 10 μm and / or a first portion of at least one epitaxial layer extends vertically from 0.1 to 0.5 μm. Alternatively or additionally, a first portion of at least one epitaxial layer extends laterally by a first length, which is more than 10 times the depth of the lateral cavity, resulting in a very high surface-to-volume ratio of the proposed lateral epitaxial layer.

[0014] Alternatively or additionally, the power semiconductor device includes a plurality of lateral portions of at least one epitaxial layer and / or a plurality of passages formed between at least one cavity and the substrate, and the pitch distance of the plurality of lateral portions and / or the plurality of passages is respectively in the range of 50 to 5000 nm, such as 50 to 500 nm. For example, the active region of each cell of a multi-cell semiconductor device can include a high-density array of grown platelets having diameters and pitches of only tens to hundreds of nanometers.

[0015] In at least one embodiment, the power semiconductor device comprises a lateral drift structure, the lateral drift structure comprising at least a first section of a first portion of at least one epi-layer, the first section containing a first dopant for forming a first type of semiconductor material, in particular an n-type WBG semiconductor material. When grown on a suitable substrate such as a high purity semi-insulating (HPSI) substrate, a lateral drift layer of only a few μm may be sufficient to block voltages up to 1 kV.

[0016] In at least one embodiment, the power semiconductor device comprises a lateral and / or vertical npn structure, the lateral and / or vertical npn structure comprising at least one semiconductor junction formed within at least one epi-layer. Further, the cavity enables the formation of both lateral and / or vertical npn structures as required for the intended power semiconductor device.

[0017] In at least one embodiment, the power semiconductor device comprises at least two lateral drift structures and / or lateral npn or pnp structures, the at least two lateral drift structures and / or lateral npn or pnp structures being connected in at least one of a back-to-back or series fashion. This enables the distribution of high current or high voltage across multiple active structures by electrically connecting individual structures such as the switching cells of a multi-cell switching device in parallel or in series, respectively.

[0018] In at least one embodiment, the power semiconductor device comprises one of a metal insulator semiconductor field effect transistor (MISFET), in particular a lateral superjunction MISFET, an IGBT, or an AccuFET. The MISFET comprises at least one gate electrode that at least partially or completely surrounds at least one epi-layer, in particular the central part of a lateral or vertical npn or npn structure formed therein, at least one source region arranged at a first lateral end and / or a central section of the epi-layer, and at least one of at least one drain region arranged at the central section and / or a second lateral end of the epi-layer. In particular, the described design enables excellent gate control using a gate that is at least partially wound around a selectively grown epi-layer. The coupling of such a wrapping gate results in a thicker inversion charge layer, which can improve the inversion channel carrier mobility, for example, by reducing Coulomb scattering at the gate dielectric / SiC interface trap. Thereby, the drain current density is further increased. This also makes it possible to eliminate, for example, the p+ plugs that have conventionally been used to ground the well region in state-of-the-art SiC MOSFETs.

[0019] In at least one alternative embodiment, the power semiconductor device comprises a lateral power diode.

[0020] In at least one embodiment, the power semiconductor device has a voltage class or rating of 0.6 to 1.2 kV per device. Such a device can be used, for example, in inverters and other power control circuits of electric vehicles (EVs).

[0021] The manufacturing method according to the first aspect is particularly suitable for manufacturing a power semiconductor device according to the second aspect. Therefore, the features and advantages described in relation to the method can be used in the device, and vice versa. Thus, all features described in relation to one aspect are disclosed herein in relation to the other aspects, even if each feature is not explicitly mentioned in the context of a particular aspect.

[0022] The accompanying drawings are included to provide further understanding. In the drawings, elements having the same structure and / or function may be referred to by the same reference numerals, even if they are not identical in all respects. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale.

Brief Description of the Drawings

[0023]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0024] Before describing a specific power semiconductor device and processing steps in detail, first, with reference to FIG. 1, selective growth of a lateral epitaxial layer (epi-layer) will be described.

[0025] FIG. 1 shows a semiconductor structure 1 including a substrate 2 and an insulating layer 3 formed on a main surface 2a (the upper surface in the case of FIG. 1) of the substrate 2. A cavity 4 is formed inside the insulating layer 3. The cavity 4 is connected to the surface 2a of the substrate 2 by a passage 5. The cavity 4 further extends to two openings 7a and 7b up to the upper surface 3a of the insulating layer 3.

[0026] A suitable WBG material such as 3C SiC can be grown at a low temperature on a suitable substrate 2 such as a Si substrate to form an epitaxial growth layer 9. The crystal material of the substrate 2 functions as a seed material for forming a selectively grown epi-layer 9 in the cavity 4. For example, chemical vapor deposition (CVD) can be used to introduce the growth material through the openings 7a and / or 7b. During epitaxy, the insulating layer 2 in which the cavity 4 is formed acts as a hollow growth mask for the WBG material, enabling the epi-layer 9 to be selectively grown into a shape and dimensions suitable for forming a power semiconductor device.

[0027] Growth begins at the seed region 10 at the bottom of the passage 5 and then first extends vertically to form the first vertical portion 11 of the epi-layer 9. When the growth front reaches the larger lateral portion of the cavity 4, the growth extends laterally on both sides to form the lateral portion 12 of the epi-layer 9. When the growth material reaches each lateral end of the cavity 4, the growth extends vertically again to form the respective second vertical portions 13a and 13b of the epi-layer 9 that extend towards the openings 7a and 7b respectively.

[0028] Preferably, the seed region 10 of the surface 2a exposed through the passage 5 is kept relatively small. For example, the diameter may be from 10 to 500 nm. If the seed region 10 is very small and the growth of the wide bandgap material starts only from a single growth seed, defects due to lattice mismatch between the grown WBG material of the epi-layer 9 and the material of the substrate 2 can be avoided. Even if there are some defects due to the larger openings of the passage 5 for example, such defects can be removed in the first vertical portion 11 before the WBG material reaches the larger lateral portion 12 of the epi-layer 9 which is used to form the active part of the completed semiconductor device as described later. Thus, the passage 5 functions effectively as a defect filter and as a result, provides a substantially defect-free lateral portion 12 and second vertical portions 13a and 13b of the epi-layer 9.

[0029] In the example described, the substrate 2 may be a wafer formed from doped or undoped silicon, such as Si(001), Si(011) or Si(111). The substrate 2 may also be formed from another crystalline material such as a hexagonal crystal, such as hexagonal SiC, such as 4H or 6H SiC. Alternatively, the substrate may also be formed from or include a semi-insulating (S) material such as gallium nitride (GaN), Ga2O3, SiC (on-axis), or other crystalline materials such as Si or C-plane SiC substrates. GaN, 3C SiC, 4H SiC, Ga2O3 or diamond can be used as a suitable wide bandgap material for the selectively grown epi-layer 9.

[0030] FIG. 1 further shows that two semiconductor junctions are formed inside or at the ends of the selectively grown epi-layer 9. In particular, the pn or np junction 6 is formed in the lateral portion 12 close to the second vertical portion 13a. Also, a Schottky junction 8 is formed between the upper end of the second vertical portion 13b and the metal material of the electrode 19 formed above it. To form such junctions, any dopant, and thus any desired doping level, can be incorporated along the growth direction during the selective growth of the epi-layer, as will be described in detail later.

[0031] FIGS. 2 - 8 show in more detail how the corresponding semiconductor structure 1 can be formed.

[0032] FIG. 2 shows the first stage of the manufacturing procedure in which the first dielectric layer 14 is formed on the upper surface 2a of the substrate 2. For example, a dielectric layer such as SiO2, Si3N4, Al2O3 or the like can be formed on a silicon or SiC substrate. At this stage, holes 15 are formed in the first dielectric layer 14, which will later form the passage 5. The holes 15 may be formed, for example, by dry etching.

[0033] Although not shown in FIG. 2, two or more holes 15 may be formed at a given pitch. Using multiple holes, multiple seed regions 10 for one or more cells of a semiconductor device can be formed simultaneously, as will be described later.

[0034] FIG. 3 shows the deposition of the sacrificial layer 16 on the previously formed dielectric layer 14. The sacrificial layer 16 can include amorphous silicon (a - Si), carbon, or another suitable material.

[0035] Figure 4 shows the formation of the growth template 17. As shown in Figure 4, the growth template 17 is formed by dry-etching a part of the previously formed sacrificial layer 16. The growth template 17 corresponds to the lateral portion 12 of the epi-layer 9 that will be formed later by selective growth. As shown in the figure, the growth template 17 can take the form of a plate or platelet, particularly a nanoplatelet. Alternatively, the growth template 17 can also take the form of a tree-like network of one or more interconnected bars, fins or wires, particularly nanowires (not shown).

[0036] Figure 5 shows the formation of the second dielectric layer 18 or cover within the region of the growth template 17. Effectively, the second dielectric layer 18 covers the remaining sacrificial material of the growth template 17 on the top and side surfaces, completely embedding the growth template 17 between the first dielectric layer 14 and the second dielectric layer 18. Similar to the first dielectric layer 14, the second dielectric layer 18 may be formed of SiO2, Si3N4, Al2O3, or other suitable insulating materials.

[0037] Figure 6 shows the formation of various openings in the second dielectric layer 18. Such openings may be formed using dry-etching. The openings may correspond to the terminal regions of the completed power semiconductor device, or may be auxiliary openings that allow the introduction of growth material into the cavities to be formed later. In the example described, two opposing first openings 7a correspond to the source regions of the dual MOSFET structure, and two second openings 7b correspond to the respective drain openings. The second openings 7b are arranged at the central part of the growth template 17 in the center of the two opposing first openings 7a.

[0038] FIG. 7 shows the removal of the sacrificial material of the growth template 17. At this time, the cavity 4 is formed in the insulating materials of the first dielectric layer 14 and the second dielectric layer 18. This can be achieved, for example, by etching the sacrificial material using TMAH, KOH, XeF2, or a similar etching agent that can be introduced through the openings 7a and 7b.

[0039] In the process shown in FIG. 8, the cavity 4 is filled with a suitable WBG material to form the epi-layer 9 therein. This is achieved by selectively growing the WBG material starting from the holes 15 (no longer visible in FIG. 8) and then continuing throughout the cavity 4 until the growth front reaches the respective openings 7a and 7b. This growth can be achieved, for example, using conventional semiconductor processing methods such as CVD.

[0040] During growth, dopants can be introduced into the evaporated WBG material to form regions where the charge carrier concentration is increased or decreased as desired. Since the growth surface of the WBG material progresses along the channel defined by the cavity 4, the process or box function of the dopant profile is well-defined as will be described later for a specific power semiconductor device.

[0041] FIG. 9 shows a power semiconductor device 20 comprising a plurality of cells 21. Specifically, the power semiconductor device 20 shown in FIG. 9 comprises a total of four device cells 21 arranged in parallel on the upper surface 2a of the substrate 2. Each of the device cells 21 has a semiconductor structure 1 similar to that described above with respect to FIGS. 2-8. Since each of the device cells 21 has essentially the same structure, they can be processed and grown in parallel using conventional semiconductor processing methods using potentially different materials.

[0042] FIG. 9 further shows that each of the semiconductor structures extends mainly in a first lateral direction corresponding to the x-axis and extends over a length that is considerably longer than a second lateral direction orthogonal to the x-axis or a vertical direction 24 corresponding to the z-axis.

[0043] As described below, each of the cells 21 realizes a dual MISFET structure connected back-to-back in the drain region 27. When the respective opposing source regions 31 are electrically connected in parallel, the voltage drop spreads over half the length of the lateral structure and the current is halved.

[0044] Furthermore, in order to distribute a larger current, individual device cells 21 can be connected in parallel to enable higher current switching. This is particularly advantageous for the manufacture of power semiconductor devices having a relatively high operating voltage, for example in the range from 600 V to 1.2 kV, and / or a current in the range from, for example, 10 to 1000 A per device.

[0045] FIG. 10 shows a cross-sectional view of a specific power semiconductor device in the form of a MISFET 25. The MISFET 25 comprises a semi-insulating substrate 2 formed, for example, of high-purity semi-insulating (HPSI) silicon carbide (SiC), and an insulating layer 3 such as an SiO2 layer. The substrate 2 may be the actual growth substrate of the MISFET 25 or another substrate used to support the insulating layer 3 of the MISFET 25. A plurality of lateral nanowires and / or nanosheets are selectively grown within the cavity 4 of the insulating layer 3 as detailed above with respect to FIGS. 2 to 9, for example.

[0046] FIG. 10 shows that two separate switching structures are formed in two separately grown epitaxial layers 9 selected from two separate channels 5. The two switching structures differ with respect to the configuration of respective pnp structures 28 and 29 that realize their respective switching functions. Although not shown, depending on the materials used and the desired active structure, an npn structure can also be implemented in the epitaxial layer 9 (not shown). It should be noted that the specific architecture shown in FIG. 10 is used for illustrative purposes only, and in a typical power semiconductor device, both parts of the MISFET 25 can have similar or even the same configuration.

[0047] Each of the switching structures is formed of a WBG semiconductor material doped with a charge donor to form an n-region within the epi-layer 9. The drift region 26 includes a drift region 26 formed of a WBG semiconductor material doped with a charge donor to form an n-region within the epi-layer 9. The drift region 26 may have a length l of 5 to 10 μm and a thickness d of 0.1 to 0.5 μm. In a central portion located between the two channels 5, a drain region 27 is formed by creating an n-doped region. In the illustrated embodiment, the drain region 27 is overgrown with the WBG material of each drift region 26. The other portion of the drain region 27 is connected to a drain electrode located outside the cross-section visible in FIG. 10. ー Each of the switching structures is formed of a WBG semiconductor material doped with a charge donor to form an n-region within the epi-layer 9. The drift region 26 includes a drift region 26 formed of a WBG semiconductor material doped with a charge donor to form an n-region within the epi-layer 9. The drift region 26 may have a length l of 5 to 10 μm and a thickness d of 0.1 to 0.5 μm. In a central portion located between the two channels 5, a drain region 27 is formed by creating an n-doped region. + In the illustrated embodiment, the drain region 27 is overgrown with the WBG material of each drift region 26. The other portion of the drain region 27 is connected to a drain electrode located outside the cross-section visible in FIG. 10.

[0048] On the left side of FIG. 10, a lateral npn structure 28 is shown. The lateral npn structure 28 includes, from right to left, a first lateral end of the drift region 26 located in the vertical portion of the epi-layer 9, a channel region 30 also disposed in the vertical portion of the epi-layer 9, and another n-doped portion of the epi-layer 9 that forms a source region 31 starting in the lateral portion of the epi-layer 9 and further extending into its second vertical portion 13a. The gate electrode 32 is disposed on top of the channel region 30 above the cavity 4 and is used to selectively switch the channel region 30 from a conductive state to a non-conductive state or vice versa.

[0049] On the right side of FIG. 10, a vertical npn structure 29 is shown disposed in the second vertical portion 13b of the epi-layer 9. The vertical npn structure 29 includes, from bottom to top, a second lateral end of each drift layer 26, a positively doped channel region 30, and a source region 31 formed on or near the upper surface 3a of the insulating layer 3. The channel region 30 is surrounded by the gate electrode 32. In the illustrated embodiment, the second vertical portion 13b of the epi-layer 9 as well as the channel region 30 itself form a relatively thin structure similar to a nanowire. Also, by surrounding the channel region 30 with the gate electrode 32 from all sides, the switching response of the vertical npn structure 29 can be made particularly fast.

[0050] Note that the horizontal length of the channel region 30 of the horizontal npn structure 28 and the vertical length of the channel region 30 of the vertical npn structure 29 are shorter than the vertical length of their respective drift layers 26. In the described embodiment, the length of the channel region 30 can be in the range of 100 to 1000 nm, while the length of the drift layer 26 can be in the range of 1 μm to 30 μm.

[0051] Note that in the described embodiment, the drift region 26 is composed of an n-type semiconductor material. For example, a relatively low concentration of dopant can be used during the selective growth of the drift region 26. On the other hand, the source region 31 is composed of an n-type semiconductor material. For example, a higher concentration of dopant can be used during the selective growth of the source region 31. Therefore, each np and pn junction of the npn structures 29 and 30 is asymmetric in that the drift layer 26 has a lower dopant concentration than its respective source region 31.

[0052] In the embodiment shown in FIG. 10, a passivation layer 33 formed from an insulating material covers the source region 31 and the overgrown portions of the drain region 27. Also, since the horizontal npn structure 28 and the vertical npn structure 29 use a common drain electrode 26, they can be connected in parallel for higher currents. They can also be connected in series, i.e., form part of a switching bridge between their respective source regions 31 and the common drain region 27. Although not shown in FIG. 10, the drain region 27 may also be disposed on top of the cavity 4 such that their respective drift regions 26 are directly connected.

[0053] FIG. 11 shows another embodiment of a power semiconductor device 20 in the form of a MISFET having a plurality of cells 21. In the embodiment shown in FIG. 11, a total of eight cells 21, each including a lateral epi-layer 9, are formed in an array structure. Each of the cells 21 is configured with a lateral npn structure 28 as described above with respect to the left side of FIG. 10. Each gate electrode 32 may be switched individually or may be formed as a common gate bar (not shown). Connections to the central drain region 27 and the source region 31 at the lateral ends of the cell 21 are also not shown.

[0054] FIG. 11 further shows the dimensions of a power semiconductor device that can be used in a voltage range from 600 V to 1.2 kV. In particular, the drift region 26 extends over a length l of about 1 to 30 μm and has a width w of about 1 μm. The height of the drift region 26 may be from 0.1 to 0.5 μm (not shown). Thus, the lateral portion 12 of the epi-layer essentially forms a nanosheet of a WBG material. Instead of the nanosheet, fins or nanowires can also be used.

[0055] The described lateral WBG epi-layer can be used in different types of power semiconductor devices such as superjunction MISFETs and / or AccuFETs. Further, to obtain a power diode, instead of the npn structure, a single pn or np junction may be implemented in the epi-layer. Also, such a pn junction may be replaced with a Schottky junction. In this case, the WBG semiconductor may extend to metal electrodes formed on one or both of its lateral ends.

[0056] Unlike conventional, i.e., non-power semiconductor devices, a power semiconductor device needs to be able to block a relatively high voltage in the so-called third quadrant, i.e., under reverse conditions. The above-described device structure and dimensions including a relatively long drift layer having a length in the micrometer range are useful for enabling such blocking ability for a voltage of about 1 kV. Thus, a power semiconductor device can also be defined as one that preferably has a drift structure suitable for a desired voltage class, preferably in a lateral configuration.

[0057] This disclosure can accept various modifications and alternative forms, the details of which are shown by way of example in the drawings and described above. However, it should be understood that the intention is not to limit this disclosure to the specific embodiments described. Rather, the intention is to cover all modifications, equivalents, and alternative forms that fall within the scope of the disclosure as defined by the appended claims.

Explanation of Reference Signs

[0058] Reference Sign 1 Semiconductor Structure 2 Substrate 2a (Surface of the Substrate) 3 Insulating Layer 3a (Surface of the Insulating Layer) 4 Cavity 5 Passage 6 pn Junction 7a, 7b Opening 8 Schottky Junction 9 Epitaxial Layer 10 Seed Region 11 First Vertical Portion 12 Lateral Portion 13a, 13b Second Vertical Portion 14 First Dielectric Layer 15 Hole 16 Sacrificial Layer 17 Growth Template 18 Second Dielectric Layer 19 Electrode 20 Power Semiconductor Device 21 cells 25 MISFETs 26 drift region 27 drain region 28 lateral npn structure 29 vertical npn structure 30 channel region 31 source region 32 gate electrode 33 passivation layer

Claims

1. A method for manufacturing a power semiconductor device (20), comprising: - forming at least one insulating layer (3) on a surface (2a) of a crystal growth substrate (2), wherein the at least one insulating layer (3) comprises at least one cavity (4) extending laterally within the at least one insulating layer (3); - selectively growing a wide bandgap semiconductor material (WBG semiconductor material) within the cavity (4) to form a lateral portion (12) of the epitaxial layer (9) including a lateral drift region (26) within a first section of at least a lateral epitaxial layer (9), wherein a surface region of the growth substrate (2) exposed through at least one passage (5) formed between the at least one cavity (4) and the growth substrate (2) is used as a seed region (10) for epitaxially growing the WBG semiconductor material, and the first section of the lateral portion (12) of the epitaxial layer (9) comprises a first dopant for forming a first type of WBG semiconductor material, particularly an n-type WBG semiconductor material; - forming at least one semiconductor junction, particularly a pn junction (6), np junction or Schottky junction (8), inside or at an end of the selectively grown WBG semiconductor material.

2. The method according to claim 1, wherein the WBG material comprises at least one of 3C, 4H or 6H silicon carbide (SiC).

3. The method according to claim 1 or 2, wherein the growth substrate (2) comprises at least one of doped silicon (Si), undoped Si, 4H, 6H or 3C SiC, particularly 3C-on-Si, silicon carbide on insulator (SiCOI), semi-insulating SiC, sapphire or gallium nitride.

4. The method according to any one of claims 1 to 3, wherein the opening and / or length of the at least one passage (5) is selected such that the at least one passage (5) functions as a defect filter for the WBG material by removing defects caused by lattice mismatch between the crystal growth substrate (2) and the WBG material before the selectively grown WBG material reaches the lateral portion (12) of the epitaxial layer (9).

5. The method according to any one of claims 1 to 4, wherein during the selective growth of the WBG material, a dopant is introduced into the evaporated WBG material to form a region where the charge carrier concentration is increased or decreased.

6. - Selectively growing the WBG semiconductor material within the cavity (4) further includes selectively growing the vertical portion (13a) of the epitaxial layer (9). - Forming at least one semiconductor junction includes forming a pn or np junction (6) within the lateral epitaxial layer (9) close to the vertical portion (13a) of the epitaxial layer (9). The method according to claim 5.

7. - doping the first section of the WBG semiconductor material with a charge donor to form an n － region in the lateral epi-layer (9) to form the lateral drift region (26), The method according to any one of claims 1 to 6.

8. The at least one semiconductor junction is formed by incorporating at least one dopant during the selective growth of the WBG semiconductor material, particularly during the growth of the lateral portion (12) of the epitaxial layer (9). The method according to any one of claims 1 to 7.

9. The dopant profile used during the selective growth of the WBG semiconductor material includes at least one step or box with respect to the concentration of the at least one dopant. The method according to claim 8.

10. Forming at least one insulating layer (3) includes: - Forming a first dielectric layer (14), particularly a first silicon dioxide layer, on the surface (2a) of the growth substrate (2). - Forming at least one hole (15) in the first dielectric layer (14) to form the at least one via (5). - Depositing and structuring a sacrificial material in a region corresponding to the at least one cavity (4). - Forming a second dielectric layer (18), particularly a second silicon dioxide layer, on the first dielectric layer (14) and the sacrificial material. - Removing the sacrificial material to form the at least one cavity (4) between the first dielectric layer (14) and the second dielectric layer (18). The method according to any one of claims 1 to 9.

11. - The power semiconductor device (20) includes one of a metal insulator semiconductor field effect transistor (MISFET), particularly a lateral superjunction MISFET, an IGBT, or an AccuFET. - In selectively growing the WBG semiconductor material, a lateral drift region (26) of the MISFET (25) grows. - The at least one semiconductor junction is formed as a lateral npn structure (28), a lateral pnp structure, a vertical npn structure (29), or a part of a vertical npn structure of the MISFET (25). The method according to any one of claims 1 to 10.

12. - Further comprising forming at least one gate electrode (32) that at least partially surrounds the selectively grown WBG semiconductor material. The method according to claim 11.

13. - Forming a source region (31) in a first lateral end and / or a central section of the lateral portion (12) of the epi-layer (9), and / or - Further comprising at least one of forming a drain region (27) in the central section and / or a second lateral end of the lateral portion (12) of the epi-layer (9). The method according to claim 11 or 12.

14. A power semiconductor device (20), comprising - a substrate (2) including a first material, - at least one insulating layer (3) disposed on a surface (2a) of the substrate (2) and having at least one cavity (4), wherein the at least one cavity (4) extends laterally within the at least one insulating layer (3), - at least one passage (5) formed between the at least one cavity (4) and the substrate (2). - At least one epi-layer (9) comprising a second material, wherein a first portion (12) of the at least one epi-layer (9) extends in the lateral direction within the at least one cavity (4), and at least a second portion (11) of the at least one epi-layer (9) extends in the vertical direction through the passage (5) for contacting the first material, the second material is a wide bandgap (WBG: Wide Bandgap) semiconductor material different from the first material, at least one epi-layer (9); - A lateral drift region (26) comprising at least a first section of the first portion (12) of the at least one epi-layer (9), the first section comprising a first dopant for forming a first type of semiconductor material, in particular an n-type WBG semiconductor material, a lateral drift region (26); - At least one semiconductor junction, in particular a pn junction (6), np junction or Schottky junction (8), formed inside or at an end of the at least one epi-layer (9), a power semiconductor device (20).

15. - The first material comprises at least one of doped silicon (Si), undoped Si, 4H, 6H or 3C silicon carbide, in particular 3C on Si, SiC on insulator, SiCOI, semi-insulating SiC, sapphire or gallium nitride; - The second material comprises at least one of 3C, 4H, or 6H SiC, and / or - The at least one insulating layer (3) is SiO ２ , Si ３ N ４ , or Al ２ O ３ and includes at least one of them. The power semiconductor device (20) according to claim 14.

16. - The first portion (12) of the at least one epi-layer (9) extends in the lateral direction by 1 to 30 μm, preferably 5 to 10 μm; - The first portion (12) of the at least one epi-layer (9) extends in the vertical direction by 0.1 to 0.5 μm, and / or - The first portion (12) of the at least one epi-layer (9) extends in the lateral direction by a first length, the first length exceeding 10 times the depth of the cavity (4) in the vertical direction (24); The power semiconductor device (20) according to claim 14 or 15.

17. The lateral drift region (26) has a length of 5 to 10 μm and / or a thickness of 0.1 to 0.5 μm, the power semiconductor device (20) according to any one of claims 14 to 16.

18. - The power semiconductor device (20) includes a plurality of lateral portions of the at least one epi-layer (9) and / or a plurality of passages (5) formed between the at least one cavity (4) and the substrate (2), and a pitch distance of the plurality of lateral portions and / or the plurality of passages (5) is respectively in a range of 50 to 5000 nm. The power semiconductor device (20) according to any one of claims 14 to 17.

19. - A lateral npn structure (28) and / or a vertical npn structure (29), including at least one semiconductor junction formed in the at least one epi-layer (9). The power semiconductor device (20) according to any one of claims 14 to 18.

20. The lateral npn structure (28) and / or the vertical npn structure (29) - An np junction between an n-type semiconductor material forming the lateral drift region (26) and a p-type semiconductor material forming the channel region (30), - A pn junction between the p-type semiconductor material forming the channel region (30) and an n-type semiconductor material forming the source region (31). - A doping concentration in the source region (31) is higher than a doping concentration in the lateral drift region (26). The power semiconductor device (20) according to claim 19.

21. The power semiconductor device (20) according to claim 19 or 20, including at least two lateral drift regions (26) and / or a lateral npn structure (28), and the at least two lateral drift structures (26) and / or the lateral npn structure (28) are connected in at least one of a back-to-back or series manner.

22. The at least two lateral drift regions (26) and / or the lateral npn structure (28) form a part of a switching bridge between respective source regions (31) and a common drain region (27). The power semiconductor device (20) according to claim 21.

23. The power semiconductor device (20) comprises one of a metal insulator semiconductor field effect transistor (MISFET), in particular a lateral superjunction MISFET, an IGBT, or an AccuFET, and the MISFET (25) comprises - at least one gate electrode (32, 36) that at least partially or completely surrounds a central portion of at least one epi-layer (9), in particular a lateral npn structure (28) or a vertical npn structure (29) formed therein, and - at least one source region (31) disposed at a first lateral end of the epi-layer (9), and - at least one drain region (27) disposed at a second lateral end or a central section of the epi-layer (9), the power semiconductor device (20) according to any one of claims 14 to 22. **Claim 24** The power semiconductor device has a voltage class or rating of 0.6 to 1.2 kV per device, the power semiconductor device (20) according to any one of claims 14 to 23.

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