Method and system for updating device firmware while maintaining state and connectivity

Abstract

A system and related method including a first processor core, a second processor core, and a control circuit that receives a request to update existing firmware of the first processor core to new firmware. The control circuit loads the existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuit stops transaction execution by the first processor core while causing the second processor core to execute transactions instead of the first processor core. The control circuit restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuit stops transaction execution of the second processor core and causes the first processor core to execute transactions.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for updating existing firmware on a device to new firmware. More particularly, the present disclosure relates to updating existing firmware on a device to new firmware while maintaining state data and connectivity on the device.

Background Art

[0002] A device (e.g., a storage device) can be connected to a peripheral component interconnect express (PCIe) interface or other interface. During operation of the device, the firmware of the processor core may need to be updated while at least one core is executing a command or instruction, thereby causing throughput inefficiencies.

Summary of the Invention

[0003] According to the present disclosure, systems and methods are provided for a dynamic firmware update application operating on a device, such as a solid state drive (SSD) device, while maintaining the operating state, data, and connectivity. For example, an SSD device having existing firmware on a controller, multi-core processor, processor core, and currently executing a transaction receives a request to update the existing firmware to new firmware. The dynamic firmware update application can be implemented on the controller using at least in part software, hardware, or a combination thereof. In some embodiments, the firmware cannot be updated until all outstanding transactions are executed and all cores are available to be reset to load the new firmware. This can take a long time and thus poses a problem when there is a need to update the firmware quickly. Further, updating the firmware of a processor core can cause compatibility issues between that processor core and other processor cores.

[0004] According to the present disclosure, in some embodiments, while an unprocessed transaction can continue to execute on a first processor core, a dynamic firmware update application searches for available processor cores capable of functioning as a stand-alone processor core to load the existing firmware while the first processor core is being updated to new firmware. In some embodiments, the dynamic firmware update application further includes determining that a second processor core is available before proceeding with the firmware update. Data such as unprocessed transactions, operating states, and connection states are migrated from the first processor core to the second processor core, and thus the first processor core can stop execution, restart, and have its existing firmware replaced with new firmware. In this manner, the dynamic firmware update application is executed with two data migration handoffs to ensure that unprocessed transactions are executed while the firmware on the first processor core is being updated.

[0005] In some embodiments, the dynamic firmware update application receives a request to update the existing firmware of the first processor core to new firmware. The dynamic firmware update application then loads the existing firmware onto the second processor core and migrates data associated with the operating state of the existing firmware on the first processor core to the second processor core. In some embodiments, the dynamic firmware update application further stops the execution of transactions on the first processor core while causing the second processor core to execute transactions using the existing firmware instead of the first processor core. In some embodiments, the dynamic firmware update application further restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data associated with the operating state of the existing firmware on the second processor core to the first processor core. In some embodiments, the dynamic firmware update application further stops the execution of transactions on the second processor core and causes the first processor core to execute transactions using the new firmware.

[0006] In some embodiments, a dynamic firmware update application can be used to update the firmware of any suitable device having multiple cores coupled to a Peripheral Component Interconnect (PCIe) interface. In some embodiments, the device can be any suitable storage device that can communicate through the PCIe interface, for example, by using the Non-Volatile Memory Express (NVMe) standard protocol. In the Non-Volatile Memory Express (NVMe) industry standard protocol, a register-level interface is defined for a host system to communicate with a device (e.g., SSD or HDD) through a Peripheral Component Interconnect Express (PCIe) bus. In some embodiments, a dynamic firmware update application can be used to update the firmware of any suitable device having multiple cores coupled to an Ethernet (R) interface.

[0007] In some embodiments, migrating the data associated with the operating state of the existing firmware on the first processor core to the second processor core further includes loading the data associated with the operating state of the existing firmware on the first processor core onto an available area of the memory associated with the second processor core. In some embodiments, the data associated with the operating states of the existing firmware on the first processor core and the new firmware on the second processor core includes a plurality of unprocessed transactions, the state of each firmware, and the input / output connection state of each firmware, each of which can be migrated between processor cores. In some embodiments, restarting the first processor core is performed after the second processor core begins execution of a transaction and before the existing firmware on the first processor core is replaced.

[0008] In some embodiments, a solid state drive (SSD) device having a processor and a controller communicatively coupled to each other is provided. In some embodiments, the processor includes at least a first processor core and a second processor core. In some embodiments, the processor is a multi-core processor having more than two processor cores. In some embodiments, the controller is configured to receive a request to update the existing firmware to the new firmware, load the existing firmware onto the second processor core, and migrate data associated with the operating state of the existing firmware on the first processor core to the second processor core. The controller is further configured to stop the execution of transactions on the first processor core while causing the second processor core to execute transactions using the existing firmware and while restarting the first processor core. In some embodiments, the controller is further configured to replace the existing firmware on the first processor core with the new firmware, migrate data associated with the operating state of the existing firmware on the second processor core to the first processor core, stop the execution of transactions on the second processor core, and cause the first processor core to execute transactions using the new firmware.

Brief Description of the Drawings

[0009] The following description includes discussions of figures with illustrations given as examples of implementations of embodiments of the present invention. The drawings should be understood as examples, not limitations. As used herein, the reference to one or more "embodiments" is to be understood as describing certain features, structures, and / or characteristics included in at least one implementation. Thus, phrases such as "in one embodiment" or "in an alternate embodiment" that appear herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive either.

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DETAILED DESCRIPTION OF THE INVENTION

[0016] According to the present disclosure, a system and method for updating firmware on a first processor core that is currently processing a transaction are provided. Features of the present disclosure regarding updating firmware on a device are applicable to devices having multiple processors, one or more multi-core processors, or both. For example, in some embodiments, the device is a solid-state drive (SSD) device having a multi-core processor with a buffer for read and write commands executed by the processor cores. Using a multi-core processor enables multiple instructions to be executed simultaneously by using multiple cores with shared data and instruction memory. For example, each processor core can receive commands from the buffer in sequence and process each command so that there are no data hazards or conflicts in writing to or reading from the memory of the SSD device. A multi-core processor is useful for processing multiple instructions of a program simultaneously or for executing multiple programs simultaneously. Although the present disclosure is mainly described in the context of a device having a multi-core processor, it will be understood that the features of the present disclosure may be similarly applied to separate processors (whether they are single-core, multi-core, or both).

[0017] In some embodiments, it may be necessary to update the firmware of the processor core of this exemplary SSD device. The firmware of the processor may include a set of instructions or microcode required to define the functionality of the processor. The firmware is loaded onto the processor core of the processor as microcode stored in a reserved area of local memory accessible to the processor. For example, when a firmware update request is received by an SSD controller within the SSD device, the first processor core may be executing commands or instructions, and additional commands or instructions may be temporarily stored in a buffer and wait to be executed. The update of the firmware may change how the processor should manage and execute transactions, and since the transactions are being sent to be processed by the firmware currently loaded on the first processor, the firmware of the first processor core cannot be updated while it is processing transactions.

[0018] In some embodiments, available processor cores (i.e., not executing any commands or instructions) are identified. For example, an SSD device can store available status bits for each processor core indicating whether each processor core is currently in a standby state and available to process a command or instruction. In some embodiments, the status bits may be stored as a data structure (e.g., an array, bitmap, etc.) in non-volatile memory or volatile memory. When a second processor core is determined to be available by checking its available status bit, the data associated with the processing of the command or instruction, as well as the link to the controller and the connection to the external device, are migrated from the first processor core to the second (i.e., available) processor core. In this way, the second processor core mirrors the operating state and role of the first processor core so that the first processor core becomes available for dynamic firmware updates. When the first processor core becomes available by checking its available status bit, the dynamic firmware update application restarts the first processor core. The restart clears any volatile memory associated with the core and flushes any old data in the first processor core, the corresponding firmware, and the traffic manager. In some embodiments, in addition to the first processor core, there may be additional processor cores to restart. When all processor cores except the second processor core are restarted, the controller can update the firmware for each of these restarted processor cores. The existing firmware on the first processor core is replaced with the new firmware. In some embodiments, the new firmware may include updates to a new traffic manager, the input / output porting of the first processor core, and the transport protocol (e.g., PCIe, Ethernet®, etc.). Next, the data associated with the operating state of the existing firmware on the second processing core is migrated to the first processor core.When new firmware is loaded onto the first processor core, the first processor core becomes available to execute transactions. The operating state of the firmware on the second processor core includes the firmware state, the connection state to external devices (e.g., PCIe devices, Ethernet devices, etc.), the traffic manager, and the outstanding transactions of the second processor core. The dynamic firmware update application halts the transaction execution of the second processor core. Finally, the dynamic firmware update application causes the first processor core to execute transactions using the new firmware. The first processor core continues to execute transactions using the new firmware.

[0019] The subject matter of the present disclosure can be better understood by referring to FIGS. 1-6.

[0020] FIG. 1 shows an exemplary diagram of a system 100 having a multi-core processor 104 and a controller 110, according to some embodiments of the present disclosure. In some embodiments, system 100 may include an SSD device 102 that includes a multi-core processor 104 having a first processor core 106, a second processor core 108, and a data bus interface 116. It will be understood that embodiments of the present disclosure are not limited to solid state drives (SSDs). For example, in some embodiments, system 100 may include a hard disk drive (HDD) device in addition to, or instead of, an SSD.

[0021] An SSD device, such as SSD device 102, is a data storage device that uses an integrated circuit assembly as memory to permanently store data. The SSD device has no moving mechanical components, which distinguishes it from conventional electromechanical magnetic disks such as hard disk drives (HDDs) or floppy disks that include spinning disks and movable read / write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, operate quietly, have a short access time, and low latency.

[0022] Many types of SSDs use NAND-based flash memory that retains data without power, including a type of non-volatile storage technology. For example, in some embodiments, the SSD may use NAND-based flash memory, NOR-based flash memory, or any other non-volatile memory, or any combination thereof. The quality of service (QoS) of an SSD may relate to the predictability of low latency and the consistency of high input / output operations per second (IOPS) while processing read / write input / output (I / O) workloads. This means that the latency or I / O command completion time needs to fall within a specified range without having unexpected outliers. The throughput or I / O rate may also need to be tightly regulated without causing a sudden drop in the performance level.

[0023] The first processor core 106 is currently executing existing firmware 112, which is the firmware that is to be updated by the dynamic firmware update application. The existing firmware is also loaded on the second processor core 108. In some embodiments, the firmware loaded on the second processor core 108 is called stand-alone firmware 114, because the second processor core 108 is the single available processor core that continues execution, while all other processor cores including the first processor core 106 are updating the firmware. Additionally, the SSD device 102 includes a controller 110 and non-volatile memory 118. In some embodiments, the non-volatile memory 118 includes any one or more of phase change memory (PCM), PCM and switch (PCMS), ferroelectric random access memory (FeRAM), or ferroelectric transistor random access memory (FeTRAM), and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. The first processor core 106, the second processor core 108, and the data bus interface 116 are communicatively coupled to each other through a data bus within the processor 104. In some embodiments, the data bus interface 116 can transport data packets to devices compatible with PCIe using the Peripheral Component Interconnection Express (PCIe) protocol. In some embodiments, the data bus interface 116 can transport data packets to devices compatible with Ethernet under the Ethernet® protocol.In some embodiments, the data bus interface 116 may transport data packets using shared processor memory. The data bus provides a network bus for data migration between the first processor core 106 and the second processor core 108 and for reading or writing data from other components, such as non-volatile memory 118, through the data bus interface 116. Migration between the two processor cores includes data associated with the operating state of one of the processor cores. In some embodiments, the data includes firmware state, connection state to external devices (e.g., PCIe devices, Ethernet® devices), and outstanding transactions of another processor core. The processor 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The controller 110, also referred to herein as a control circuit, may include any suitable software, hardware, or both for controlling the data bus interface 116, data migration, and firmware updates. The controller 110 is communicatively coupled to the processor 104 to send, for example, instructions for processor firmware updates. The non-volatile memory 118 may include hardware elements for non-transitory storage of commands or instructions that, when executed by the processor 104, operate the processor 104 according to the embodiments described herein.

[0024] The present disclosure is mainly described in the context of a solid state drive device 102 having, for example, a multi-core processor 104. However, the features of the present disclosure may be equally applicable to separate processors (whether they be single-core, multi-core, or both). Thus, the solid state drive device 102 can include multiple processors, where each processor core of a first processor on which existing firmware is loaded requires a firmware update, and the solid state drive device 102 can migrate data and existing firmware to processor cores on a second processor.

[0025] The controller 110 includes a control manager 111 that links to a traffic manager 113 of the first processor core 106 and a stand-alone traffic manager 115 of the second processor core 108. The control manager 111 is configured to transmit control signals from the controller to each of the processor cores 106, 108. The traffic manager 113 and the stand-alone traffic manager 115 provide management thereof when commands or instructions are received by the first processor core 106 and the second processor core 108, respectively. The traffic manager 113 and the stand-alone traffic manager 115 are set up to comply with a transport protocol (e.g., PCIe, Ethernet®, etc.) corresponding to an external device communicatively coupled to the system output unit 120.

[0026] A solid state storage device (e.g., an SSD device) can include one or more packages of non-volatile memory dies, and each die includes storage cells. In some embodiments, the storage cells are grouped into pages, and the pages are grouped into blocks. Each storage cell can store one or more bits of information. The solid state storage device may further include a multi-core processor and a storage controller. In some embodiments, an input / output (I / O) command from an external device, such as a write command, is buffered in a temporary storage (buffer) within the SSD storage device before being processed to the memory or storage cells.

[0027] System 100 shows an embodiment in which a PCIe interface SSD device is configured to update its firmware according to the present disclosure, but it will be understood that any other suitable device of another suitable interface may update its firmware in a similar manner. For example, an Ethernet® device may have its firmware updated by a network controller. In some embodiments, other storage devices, peripheral devices, or other devices of a PCIe interface may update the firmware on one or more processors or processor cores.

[0028] For purposes of clarity and brevity, and not by way of limitation, the present disclosure is provided in the context of a dynamic firmware update application that provides the features and functions disclosed herein. The dynamic firmware update application may be any suitable software, hardware, or both for implementing such features and functions. The dynamic firmware update application may be implemented, at least in part, for example, in system 100 (e.g., as part of SSD device 102 or any other suitable device where the firmware is being updated). For example, in the case of SSD device 102, the dynamic firmware update application may be implemented in controller 110. In some embodiments, the dynamic firmware update application may be implemented, at least in part, as part of an operating system for the system in which system 100 is integrated. In some embodiments, the dynamic firmware update application may be implemented, at least in part, in a dedicated circuit (e.g., as a processor or one or more processor cores).

[0029] Figure 2 shows a flowchart illustrating a process 200 for updating existing firmware of a first processor while continuing to execute a transaction on a second processor core, according to some embodiments of the present disclosure. In some embodiments, the traffic manager, stand-alone traffic manager, first processor core, second processor core, and controller referred to may be implemented as traffic manager 113, stand-alone traffic manager 115, first processor core 106, second processor core 108, and controller 110, respectively. In some embodiments, process 200 may be modified, for example, by reordering, changing, adding, and / or removing steps.

[0030] In step 202, the dynamic firmware update application receives a request to update the existing firmware to the new firmware. Generally, when the firmware update request is received by the controller, the first processor core will have unprocessed transactions to execute. On the other hand, the dynamic firmware update application determines when the second processor core has completed execution and when it becomes available for this dynamic firmware update to be executed. For example, in some embodiments, the dynamic firmware update application can use the status bit associated with the second processor core to determine that the second processor core is available. Then, in step 204, the dynamic firmware update application loads the existing firmware onto the second processor core.

[0031] In step 204, the dynamic firmware update application loads the existing firmware onto the second processor core. The existing firmware is currently also being executed on the first processor core and is loaded onto the second processor core to ensure firmware compatibility between the first processor core and the second processor core. When the dynamic firmware update application migrates the data associated with the operating state of the first processor core to the second processor core in step 206, both processor cores should have the same existing firmware to avoid any differences in transaction execution.

[0032] In step 206, the dynamic firmware update application migrates data associated with the operating state of the existing firmware on the first processor core to the second processor core. The transmission of data from the first processor core to the second processor core includes packaging the data into packets to be transmitted along the data bus interface and received by the second processor core. The operating state of the firmware on the first processor core includes the firmware state, the connection state to external devices, and the outstanding transactions of the first processor core.

[0033] In step 208, the dynamic firmware update application causes the first processor core to stop executing transactions. The dynamic firmware update application has completed the handoff from the first processor core to the second processor core, and thus the first processor core should stop executing transactions so that the second processor core can continue executing outstanding transactions when the firmware update process resumes. When the second processor core stops executing transactions, it becomes available and can remain available until after the update to the new firmware.

[0034] In step 210, the dynamic firmware update application causes the second processor core to execute transactions using the existing firmware instead of the first processor core. The second processor core continues executing outstanding transactions from where the first processor core handed off. The second processor core with the existing firmware loaded enables the execution of outstanding transactions while the dynamic firmware update application restarts and updates the firmware on the first processor core. Additionally, the stand-alone traffic manager of the second processor core stores any newly received transactions in a buffer while the second processor core is executing.

[0035] In step 212, the dynamic firmware update application restarts the first processor core. The restart clears any volatile memory associated with the core and flushes any old data in the processor core, the corresponding firmware, and the traffic manager. In some embodiments, in addition to the first processor core, there may be additional processor cores to restart. When all processor cores except the second processor core are restarted, the dynamic firmware update application can update the firmware for each of these restarted processor cores.

[0036] In step 214, the dynamic firmware update application replaces the existing firmware on the first processor core with new firmware. The new firmware may include updates for another traffic manager, the input / output porting of the first processor core, and transport protocols (such as PCIe, Ethernet®, etc.). The new firmware may be pre-stored in the non-volatile memory 118 to which the controller is communicatively coupled, or may be received from a database to which the controller is communicatively coupled via wireless communication. However, the existing firmware does not necessarily need to be overwritten, deleted, or otherwise modified on the first processing core.

[0037] In step 216, the dynamic firmware update application migrates data associated with the operating state of the existing firmware on the second processing core to the first processor core. When the new firmware is loaded onto the first processor core, the first processor core becomes available to execute transactions. The operating state of the firmware on the second processor core includes the firmware state, the connection state to external devices (such as PCIe devices, Ethernet® devices, etc.), the traffic manager, and the outstanding transactions of the second processor core.

[0038] In step 218, the dynamic firmware update application causes the second processor core to stop executing transactions. After data migration from the second processor core to the first processor core, the second processor core no longer has any outstanding transactions to execute and can thus stop transaction execution.

[0039] In step 220, the dynamic firmware update application causes the first processor core to execute transactions using the new firmware. The first processor core continues to execute transactions using the new firmware. In some embodiments with additional processor cores, the additional processor cores are also available for transaction execution using the new firmware.

[0040] FIG. 3 shows a flowchart illustrating a process 300 for migrating data from a first processor to a second processor according to some embodiments of the present disclosure. Sub-process 300 is executed as part of a process for updating the existing firmware currently operating on the first processor core while continuing to execute transactions. In some embodiments, the traffic manager, stand-alone traffic manager, first processor core, second processor core, control manager, and controller referred to are traffic manager 113, stand-alone traffic manager 115, first processor core 106, second processor core 108, control manager 111, and controller 110, respectively. In some embodiments, process 300 may be modified by, for example, reordering, changing, adding, and / or removing steps.

[0041] In step 302, the dynamic firmware update application disconnects the traffic manager from the control manager. In some embodiments, the control manager is linked to the traffic manager to send a control signal from the controller to the first processor core. In the embodiment shown in the flowchart, the existing firmware of the first processor core will be updated to new firmware while there are still outstanding transactions to be executed. However, when updating the firmware by replacing the existing firmware with new firmware, the first processor core cannot process outstanding transactions. Therefore, the link between the traffic manager and the control manager may be disconnected.

[0042] In step 304, the dynamic firmware update application migrates the traffic manager from the first processor core to the second processor core as a stand-alone traffic manager. The migration of the traffic manager to the stand-alone traffic manager includes linking the stand-alone traffic manager to the control manager and ensuring that the stand-alone is configured to output signals from the system output unit to an external device using some transport protocol (e.g., PCIe, Ethernet (registered trademark)).

[0043] In step 306, the dynamic firmware update application migrates data from the first processor core to the second processor core. The data to be migrated may include outstanding transactions, operating states, and connection states. This data may be used to configure the firmware of the second processor core and the stand-alone traffic manager, and the second processor core can execute commands or instructions and continue to receive them when the firmware of the first processor core is being updated.

[0044] In step 308, the dynamic firmware update application resumes the operation of the second processor core. In some embodiments, the second processor core resumes the execution of the transaction from where the first processor core last interrupted before the first processor core stopped transaction execution. In some embodiments, the instruction pointer for any command or instruction processed by the core may be stored and updated. This instruction pointer may also be moved as part of the data migration between the first processor core and the second processor core. Thus, by using the same configuration of the traffic manager, transport layer protocol, and control manager and the connection to the external device, the second processor core should operate as a mirror of the first processor core when the firmware of the first processor core is being updated.

[0045] In step 310, the dynamic firmware update application resets all cores except the second processor core. The second processor core is set up and begins to execute transactions, while the first processor core is reset to clear any volatile memory associated with the first processor core, and any old data in or associated with the first processor core, the corresponding firmware, and the traffic manager is flushed. In some embodiments, there may be additional processor cores to reset in addition to the first processor core. In some embodiments, the reset of the processor core may be completed by a warm reboot, and the existing firmware and traffic manager of each processor core are reset without powering off each processor core.

[0046] This sub - process 300 is used for data migration and firmware setup of the second processor core. However, sub - process 300 only allows resetting all processor cores except the second processor core for firmware update. The method of the present disclosure also enables making the second processor core available for firmware update by handing off the execution of transactions back to the first processor core after all processor cores except the second processor core have booted with the updated firmware.

[0047] Figure 4 shows a flowchart depicting a process 400 for migrating data from a second processor core to a first processor core and resuming execution of transactions on the first processor core, according to some embodiments of the present disclosure. Sub - process 400 is executed as part of a process for updating the existing firmware currently operating on the first processor core while continuing the execution of transactions. In some embodiments, the traffic manager, stand - alone traffic manager, first processor core, second processor core, control manager, and controller referred to are, respectively, the traffic manager 113, stand - alone traffic manager 115, first processor core 106, second processor core 108, and control manager 111 and controller 110 as seen in FIG. 1. In some embodiments, process 400 may be modified, for example, by re - arranging, changing, adding, and / or removing steps.

[0048] In step 402, the dynamic firmware update application migrates data from the second processor core to the first processor core. The existing firmware of the first processor core has been updated to the new firmware, and the first processor core is available for transaction execution. The data migration from the second processor core to the first processor core is a handoff of the transaction execution responsibility to make the second processor core available for firmware update if necessary. The data migration may include unprocessed transactions, instruction pointers, operating states, and connection states. This data may be used to configure the new firmware and traffic manager of the first processor core, and the first processor core can execute commands or instructions through the traffic manager and continue to receive them as before the firmware update.

[0049] In step 404, the dynamic firmware update application halts the second processor core. The second processor core has already handed off any remaining unprocessed transactions to the first processor core, so the second processor core is halted to ensure that there is no further transaction execution that could cause any conflicts or hazards between the first and second processor cores.

[0050] In step 406, the dynamic firmware update application migrates the traffic manager from the second processor core to the first processor core. The second processor core is no longer processing transactions, so the stand-alone traffic manager can be migrated from the second processor core to configure the traffic manager of the first processor core. Additionally, the migration includes disconnecting the stand-alone traffic manager from the control manager of the controller.

[0051] In step 408, the dynamic firmware update application connects the traffic manager of the first processor core to the control manager of the controller. The dynamic firmware update application links the control manager to the traffic manager such that the control manager can send a control signal to the traffic manager of the first processor core. Linking the traffic manager of the first processor core to the control manager includes configuring the traffic manager to output signals from the system output section to an external device using some transport layer protocol (e.g., PCIe, Ethernet (registered trademark)).

[0052] In step 410, the dynamic firmware update application de-asserts the suspend processing bit. The suspend processing bit is a control signal bit used by the system to easily determine whether a processor core is suspended during its operation. In some embodiments, there is a suspend processing bit for each processor core within the processor. The suspend processing bit may be stored in volatile memory in the form of a searchable data structure (e.g., lookup table, array, etc.).

[0053] FIG. 5 shows a flowchart of a process 500 for updating existing firmware of a first processor core while continuing execution of a transaction on a second processor core, according to some embodiments of the present disclosure. In some embodiments, process 500 may be modified by, for example, reordering, changing, adding, and / or removing steps.

[0054] In step 502, the dynamic firmware update application starts a stand-alone traffic manager on the second processor core. The stand-alone traffic manager is initialized on the second processor core and is available to process transactions when the existing firmware of the first processor core is updated to new firmware.

[0055] In step 504, the dynamic firmware update application asserts a halt processing bit. The dynamic firmware update application sets and asserts a halt processing bit for the first processor core indicating that the operation of the first processor core is halted. In embodiments having more than two processor cores, the dynamic firmware update application sets a halt processing bit for each processor core except the second processor core.

[0056] In step 506, the dynamic firmware update application halts all processor cores except the second processor core. The dynamic firmware update application may halt the processor cores in parallel with asserting a halt processing bit for each processor core, with the second processor core being an exception.

[0057] In subprocess 300, the dynamic firmware update application executes subprocess 300, thereby migrating data from the first processor to the second processor.

[0058] In step 508, the dynamic firmware update application loads new firmware onto all processor cores except the second processor core. The dynamic firmware update application boots the new firmware on each of the processor cores except the second processor core, while the second processor core continues to receive and execute transactions. When the new firmware is fully booted on the processor core, an assertion check on the processor core's halt processing bit is used to make each of the newly updated processor cores available for processing.

[0059] In subprocess 400, the dynamic firmware update application executes subprocess 400, whereby data is migrated from the second processor core to the first processor core, and the execution of transactions on the first processor core resumes.

[0060] FIG. 6 shows a diagram of the time-series data flow between the first and second processor cores that simultaneously execute a program or routine according to some embodiments of the present disclosure. Each timeline 602, 604 is represented by columns that follow a vertical sequential order for each processor core, along with a time-varying indicator. The timelines show the relative parallelism between the execution stages of the first and second processor cores. In addition, FIG. 6 shows data migrations 606, 608 between the two processor cores, which is a routine that requires meeting timing constraints to avoid any write or read conflicts or hazards. For example, the second processor core cannot resume execution until the first data migration 606 is received by the second processor core. However, while the second processor core is executing a transaction, the first processor core can be reset and new firmware can be loaded.

[0061] The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments" unless explicitly specified otherwise.

[0062] The terms "including", "comprising", "having", and variations thereof mean "including but not limited to" unless explicitly specified otherwise.

[0063] A list of listed items does not imply that any or all of the items are mutually exclusive unless explicitly specified otherwise.

[0064] The terms "a", "an", and "the" mean "one or more" unless explicitly specified otherwise.

[0065] Devices that communicate with each other do not necessarily need to continuously communicate with each other unless explicitly specified otherwise. Additionally, multiple devices that communicate with each other may communicate directly or indirectly via one or more intermediate media.

[0066] The description of embodiments having several components communicating with each other does not imply that all such components are necessary. On the contrary, various optional components are described to illustrate a wide variety of possible embodiments. Further, process steps, method steps, algorithms, or the like may be described in a sequential order, but such processes, methods, and algorithms may be configured to function in an alternative order. In other words, any sequence or order of steps that may be described does not necessarily imply that the steps should be performed in that order. The steps of the processes described herein may be performed in virtually any order. Further, some steps may be performed simultaneously.

[0067] When a single device or article is described herein, it will readily be apparent that more than one device / article (regardless of whether they cooperate or not) may be used instead of the single device / article. Similarly, when more than one device or article (regardless of whether they cooperate or not) is described herein, it will readily be apparent that a single device / article may be used instead of the more than one device or article, or that a different number of devices / articles may be used instead of the number of devices or programs shown. The functions and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functions / features. Thus, other embodiments need not include the device itself.

[0068] At least some of the operations that may be shown in the figures indicate that some events occur in a certain order. In alternative embodiments, some operations may be performed, modified, or removed in a different order. Further, steps may be added to the above logic and still be consistent with the described embodiments. Further, the operations described herein may occur sequentially or some operations may be processed in parallel. Still further, the operations may be performed by a single processing unit or by distributed processing units.

[0069] The foregoing description of the various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. A method for updating existing firmware currently operating on a first processor core while continuing to execute a transaction, comprising: receiving a request to update the existing firmware to new firmware; loading the existing firmware onto a second processor core; migrating data associated with an operating state of the existing firmware on the first processor core to the second processor core; causing the first processor core to stop executing the transaction; causing the second processor core to execute the transaction using the existing firmware instead of the first processor core; restarting the first processor core; replacing the existing firmware on the first processor core with the new firmware; migrating data associated with an operating state of the existing firmware on the second processor core to the first processor core; causing the second processor core to stop executing the transaction; and causing the first processor core to execute the transaction using the new firmware A method comprising the above steps.

2. The method according to claim 1, wherein the first processor core and the second processor core are coupled to a Peripheral Component Interconnect Express (PCIe) interface.

3. The method according to claim 1, wherein the first processor core and the second processor core are coupled to an Ethernet (registered trademark) interface.

4. The method according to claim 1, further comprising determining that the second processor core is available.

5. The method according to claim 1, wherein the step of migrating data associated with the operating state of the existing firmware on the first processor core to the second processor core further comprises loading the data associated with the operating state of the existing firmware on the first processor core onto an available area of memory associated with the second processor core.

6. The data associated with the operating state of the existing firmware on the first processor core, and the data associated with the operating state of the new firmware on the second processor core are a plurality of unprocessed transactions; the state of each of the firmware; and the input / output connection state of each of the firmware respectively, the method according to claim 1.

7. The restarting step is performed after the second processor core starts executing the transaction and before the existing firmware on the first processor core is replaced, the method according to any one of claims 1 to 6.

8. A first processor core; A second processor core; and A control circuit, the first processor core, the second processor core, and the control circuit are communicatively coupled, and the control circuit receives a request to update existing firmware to new firmware; loads the existing firmware onto the second processor core; migrates the data associated with the operating state of the existing firmware on the first processor core to the second processor core; causes the first processor core to stop executing transactions; causes the second processor core to execute transactions using the existing firmware instead of the first processor core; restarts the first processor core; replaces the existing firmware on the first processor core with the new firmware; migrates the data associated with the operating state of the existing firmware on the second processor core to the first processor core; causes the second processor core to stop executing transactions; and causes the first processor core to execute transactions using the new firmware system.

9. The first processor core and the second processor core are coupled to a Peripheral Component Interconnect Express (PCIe) interface, the system according to claim 8.

10. The first processor core and the second processor core are coupled to an Ethernet (registered trademark) interface, the system according to claim 8.

11. The system according to claim 8, wherein the control circuit further determines that the second processor core is available. **Claim 12** The system according to claim 8, wherein the control circuit loads the data associated with the operating state of the existing firmware on the first processor core onto an available area of a memory associated with the second processor core. **Claim 13** The data associated with the operating state of the existing firmware on the first processor core and the data associated with the operating state of the new firmware on the second processor core include a plurality of unprocessed transactions; the state of each of the firmware; and the input / output connection state of each of the firmware respectively, in the system according to claim 8. **Claim 14** The system according to any one of claims 8 to 13, wherein the control circuit restarts the first processor core after the second processor core starts executing the transaction and before the existing firmware on the first processor core is replaced. **Claim 15** A processor having a first processor core; and a second processor core and a controller communicably connected to the processor, the controller receives a request to update existing firmware to new firmware; loads the existing firmware onto the second processor core; migrates data associated with the operating state of the existing firmware on the first processor core to the second processor core; stops the first processor core from executing transactions; causes the second processor core to execute transactions using the existing firmware instead of the first processor core; restarts the first processor core; replaces the existing firmware on the first processor core with the new firmware; migrates data associated with the operating state of the existing firmware on the second processor core to the first processor core; stops the second processor core from executing transactions; and causes the first processor core to execute transactions using the new firmware ​ , Solid State Drive (SSD) device.

16. The SSD device according to claim 15, wherein the first processor core and the second processor core are coupled to a Peripheral Component Interconnect Express (PCIe) interface.

17. The SSD device according to claim 15, wherein the first processor core and the second processor core are coupled to an Ethernet (registered trademark) interface.

18. The SSD device according to claim 15, wherein the controller further determines that the second processor core is available.

19. The SSD device according to claim 15, wherein the controller loads the data associated with the operating state of the existing firmware on the first processor core onto an available area of memory associated with the second processor core.

20. The data associated with the operating state of the existing firmware on the first processor core and the data associated with the operating state of the new firmware on the second processor core are a plurality of unprocessed transactions; the state of each of the firmware; and the input / output connection state of each of the firmware respectively, and the SSD device according to claim 15 includes each of them.

21. The SSD device according to any one of claims 15 to 20, wherein the controller restarts the first processor core after the second processor core starts executing the transaction and before the existing firmware on the first processor core is replaced.

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