Integrated GaN-based logic level converter
The GaN-based level shifter circuit addresses the challenge of converting CMOS logic levels to control GaN FETs by using a resistor network with a GaN differential comparator, ensuring stable operation despite process and temperature variations, effectively turning on GaN FETs with low voltage CMOS signals.
Patent Information
- Application Number
- JP2024576520
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-28
- Filing Date
- 2023-06-28
- Publication Date
- 2025-07-03
AI Technical Summary
Existing GaN FETs require a control voltage of at least 4V to turn on, while CMOS logic levels typically provide 1.4V or 2.0V, necessitating a dedicated circuit to convert CMOS logic levels to a sufficient voltage for GaN FET control, and existing level shifters are prone to process and temperature variations.
A GaN-based level shifter circuit using a resistor network with a GaN differential comparator and voltage dividers to generate a level-shifted and scaled signal, ensuring operation at the optimal bias point and incorporating hysteresis to stabilize the comparator output, independent of process and temperature variations.
The circuit effectively converts low voltage CMOS signals to a level sufficient to turn on GaN FETs, maintaining consistent performance across varying conditions, and is suitable for controlling GaN FETs with threshold levels influenced by process and temperature.
Smart Images
Figure 2025520801000001_ABST
Abstract
Description
Background Art
[0001] Generally, modern microprocessors implemented within a power control system use logic levels derived from a 1.8V or 3.3V power supply. Thus, the input control logic level for a power integrated circuit (IC) can drop to as low as 1.4V when supplying 1.8V to the microprocessor, or to as low as 2.0V when supplying 3.3V to the microprocessor. Silicon-based CMOS field-effect transistors (FETs) generally have a threshold voltage Vth within the range of 0.6 - 0.7V. Thus, an input high voltage of 1.4V from a CMOS controller is sufficient to turn on a CMOS FET.
[0002] However, GaN FETs have a threshold voltage Vth within the range of 1.5 - 2.5V and generally require a control voltage of at least 4V to fully turn on. Thus, using a control signal of 2.4V from a CMOS controller cannot reliably guarantee the turn-on of a GaN FET. Therefore, in order for a GaN FET to be controllable using CMOS logic levels, a dedicated circuit capable of converting a CMOS logic level signal to a signal having a voltage level sufficient to turn on the GaN FET is required.
[0003] FIG. 1 shows a general logic level shifter circuit 100. Circuit 100 includes a supply voltage V connected to an FET transistor 102 via a resistor 101. The source of FET 102 is connected to the gate of FET 104 within an inverter stage X connected to a higher supply voltage V. ddX Resistors 101 and 103 are selected based on the drive strength (final output level) required for a particular application. The output provided from inverter stage X switches between 0V and voltage V. ddX In circuit 100, FETs 102 and 104 are connected to the supply voltage V for proper operation of the circuit.
[0004] dd must have a significantly lower threshold voltage Vth. V dd is less than or equal to the threshold voltage Vth of FET102, or the threshold voltage Vth of FET102 increases over time and becomes greater than V dd In this case, the level shifter circuit 100 will not function properly.
[0005] FIG. 2 shows a conventional differential latch-based logic level shifter circuit 200. The differential latch-based logic level shifter circuit 200 includes input Xn and inverted X with opposite polarities, which are supplied to a differential cross-coupled structure that latches the output to a supply voltage V ddH higher than the input. The input Xn and X are at a low voltage V ddH lower than the supply voltage V ddL As in the circuit of FIG. 1, the circuit of FIG. 2 functions properly only when the threshold voltage Vth of NFETs 201 to 204 is significantly lower than the input voltage level V ddL When the input voltage level is less than or equal to the threshold voltage Vth of FETs 201 to 204, the differential latch-based logic level shifter circuit 200 will not function properly.
[0006] FIG. 3 shows a general common-gate-based logic level shifter circuit 300. The common-gate-based logic level shifter circuit 300 includes a FET102 having a source S, a drain D, and a gate G. The input (low side) is supplied to the source S of FET102, and the gate G of FET102 is DC-biased. The high-side output at the drain D of FET102 swings in phase with the low-side input. Therefore, when the input to the source S swings high to the gate voltage level, FET102 turns off, and the high side swings to a higher V dd pull-up voltage. The input threshold level is set by the gate voltage bias (supplied from a voltage divider formed by resistors 104 and 106) such that FET102 turns off when the input level reaches the threshold voltage V th of FET102.
[0007] In the circuit of FIG. 3, an input signal level lower than the threshold voltage V of FET102 can be used to obtain a level-shifted output that swings between V and ground. However, the trip level of the common-gate-based logic level-shifting circuit 300 depends on the threshold voltage V of FET102, and its value is highly process-dependent and temperature-dependent. In addition, the hysteresis level achieved by changing the gate voltage level is also affected by variations in the threshold voltage V of FET102. Therefore, the trip voltage and hysteresis level of the common-gate-based logic level-shifting circuit 300 change with changes in the threshold voltage V of FET102. th A lower input signal level can be used to obtain a level-shifted output that swings between V and ground. dd However, the trip level of the common-gate-based logic level-shifting circuit 300 depends on the threshold voltage V of FET102, and its value is highly process-dependent and temperature-dependent. In addition, the hysteresis level achieved by changing the gate voltage level is also affected by variations in the threshold voltage V of FET102. Therefore, the trip voltage and hysteresis level of the common-gate-based logic level-shifting circuit 300 change with changes in the threshold voltage V of FET102. th depends on the threshold voltage V of FET102, and its value is highly process-dependent and temperature-dependent. In addition, the hysteresis level achieved by changing the gate voltage level is also affected by variations in the threshold voltage V of FET102. Therefore, the trip voltage and hysteresis level of the common-gate-based logic level-shifting circuit 300 change with changes in the threshold voltage V of FET102. th is also affected by variations in the threshold voltage V of FET102. Therefore, the trip voltage and hysteresis level of the common-gate-based logic level-shifting circuit 300 change with changes in the threshold voltage V of FET102. th changes with changes in the threshold voltage V of FET102.
[0008] FIG. 4 shows a prior art voltage divider level-shifting circuit 400. The voltage divider level-shifting circuit 400 includes a differential comparator 402 powered by a 5V power supply and a resistive network at the input that converts a negative pulse train into a level-shifted complementary bipolar output. The voltage divider formed by resistors 406 and 408 scales the input signal level, and that input signal is then applied to the inverting input of differential comparator 402. A second voltage divider formed by resistors 404 and 410 is connected to the non-inverting input of differential comparator 402. This circuit advantageously level-shifts an input signal having a voltage lower than the threshold voltage V of the GaN FET to an output signal that swings between V and ground. th A lower voltage input signal is level-shifted to an output signal that swings between V and ground. cc and ground.
[0009] However, in the circuit of FIG. 4, the floating input to differential comparator 402 sets the output of the voltage-divided logic level shifter circuit 400 to positive (or negative based on the input configuration). Additionally, since the input to differential comparator 402 is not biased at the optimal gain of differential comparator 402, the output swing depends only on the large swing of the input signal. If the circuit of FIG. 4 is implemented in GaN for use within a GaN IC, the low gain of the GaN comparator will result in a relatively slow response for input signal swings that are not near the optimal bias point of the comparator. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION
[0010] Therefore, it is desirable to provide a level shifter circuit implemented in GaN that converts a low voltage CMOS signal to a level sufficient to turn on a GaN FET and avoids the disadvantages of the above circuit. MEANS FOR SOLVING THE PROBLEMS
[0011] The present invention achieves the object described above by providing a GaN-based level shifter circuit that overcomes the disadvantages and converts a low voltage CMOS signal to a level sufficient to turn on a GaN FET.
[0012] More specifically, the present invention is an integrated GaN-based logic level shifter that includes a GaN differential comparator and a resistor network as described herein. The resistor network includes a first voltage divider for receiving a single-ended input signal and outputting a level-shifted and scaled signal, and a second voltage divider for generating a trip voltage. The second voltage divider circuit includes a resistor hysteresis circuit. The level-shifted and scaled signal is connected to a first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to a second input of the GaN differential comparator, whereby the positive and negative outputs of the GaN differential comparator include positive and negative complementary bipolar level-shifted signals corresponding to the input signal.
[0013] The present invention also provides an integrated GaN-based logic level shifter for differential input signals. In the case of differential inputs, the resistor network includes two voltage divider branches, one for each input. Each branch of the resistor network receives an input signal and outputs a level-shifted and scaled signal to the corresponding input of the comparator. The resistor hysteresis circuit may also be included within the negative resistor branch of this embodiment of the present invention.
[0014] The resistor network-based level shifter of the present invention is not affected by process and temperature, and is particularly well-suited for level-shifting CMOS-level inputs and LVDS-type differential signals to a higher level in order to control GaN FETs having a gate threshold level that depends on process and temperature. The resistor network of the present invention advantageously supplies a level-shifted input at the optimal bias point of the GaN comparator. The trip level range of the logic level shifter of the present invention is much narrower than that of a common gate level shifter because the range of trip thresholds is limited only by the input offset level of the comparator.
[0015] Additional features and advantages of the present disclosure will be described in the following specification, become apparent to some degree from the specification, or may be learned by practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. These and other features of the invention will become more fully apparent from the following description and appended claims, or may be learned by practice of the invention as set forth hereinafter.
[0016] To further clarify the above and other advantages and features of the present invention, a more detailed description of the invention is given by reference to those specific embodiments shown in the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are, therefore, not to be considered limiting of its scope. The invention is described and explained with additional specificity and detail through the use of the accompanying drawings.
Brief Description of the Drawings
[0017]
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Modes for Carrying Out the Invention
[0018] It should be understood that the drawings and description of the present invention are simplified to show only appropriate elements for a clear understanding of the present embodiment. Those skilled in the art will recognize that other elements may be desirable and / or necessary for implementing the present embodiment. It should also be understood that the drawings included herein provide only a schematic representation of the presently preferred embodiments of the present invention. Next, drawings in which similar structures are given similar reference numerals are referred to.
[0019] FIG. 5 shows a resistor network-based logic level shifter of the present invention designed to level shift a low voltage input signal (e.g., a CMOS level signal) to a voltage level exceeding the maximum threshold voltage Vth of a GaN transistor integrated within a GaN IC. The level shifter circuit 500 includes a resistor network 502, a GaN differential comparator 520, a single-ended input signal In, and (input Off for pulling the input signal low), as well as power supply sources Vdd and Vss. The GaN differential comparator 520 connected to the power supply sources Vdd and Vss receives the input signals InP and Vtrip from the resistor network 502 and creates inverted-phase level-shifted output signals OutP and OutN (complementary bipolar). Vtrip is the level that the input signal "In" must exceed as the minimum V inHi_Low level for the output OutP to transition high.
[0020] More specifically, as shown in FIG. 5, the input signal In is connected to a voltage divider between Vdd and Vss, which includes a resistor 504, a scale resistor 506, and an offset resistor 508 connected in series to form a voltage divider for level shifting and scaling the input In to the input InP. The values of the resistor 504 and the scale resistor 506 are set such that InP transitions near the optimal bias point of the GaN comparator 520, thereby improving the speed of the comparator. The offset resistor 508 ensures that when the input “In” is floating, the output OutP remains low and the output OutN remains high. The value of the offset resistor 508 depends on the amount of the maximum input offset expected in the comparator 520.
[0021] The voltage of the Vtrip input to the GaN comparator 520 is determined by the values of the resistors 510 and 512 that form a voltage divider to set the voltage at the Vtrip input to the comparator 520. In a manner similar to the voltage divider for the input signal, the resistors 510 and 512 are set such that Vtrip transitions near the optimal bias point for the input to the comparator 520. Vtrip is also determined by a hysteresis circuit H formed by resistors 516 and FET 518, which is controlled by one of the positive outputs of the comparator 520 in the same way as the output OutP. The hysteresis circuit H ensures that any noise voltage within a range near the trip point of the comparator 520 does not reset the output of the comparator 520. This is achieved by increasing (or decreasing) the reference voltage by a scaled amount that exceeds the noise level expected when the comparator 520 makes its first trip. Since the hysteresis is set by a resistor divider, it is not affected by process or temperature variations, similar to the rest of the resistor network 502.
[0022] The level shifter circuit 500 creates both a positively level-shifted output signal OutP and a negatively level-shifted output signal OutN based on a single-ended input signal. The level shifter circuit 500 can be turned off by applying a logic high signal to the "Off" terminal, which turns on FET514, shorts the input InP to Vss (ground), and drives OutP low and OutN high.
[0023] FIG. 6 shows a resistor network 602 designed for differential signal input instead of the single-ended input of FIG. 5. In the differential input embodiment of FIG. 6, both input branches of the resistor network 602 follow the topology of the "In" branch of FIG. 5. Thus, in FIG. 6, the differential signal inputs InP and InM are each connected to corresponding resistor voltage dividers between Vdd and Vss. The voltage divider for the positive input InP includes resistors 604, scale resistor 606, and offset resistor 608 connected in series. Similarly, the voltage divider for the input InM includes resistors 624, scale resistor 626, and offset resistor 628 connected in series. Although not shown, the signals Pos and Neg from the voltage dividers are each connected as inputs to the non-inverting and inverting terminals of a GaN differential comparator, similar to the connection of InP and Vtrip to the GaN comparator 520 shown in FIG. 5. Also, similar to FET514 in FIG. 5, FET614 is provided to short Pos to Vss (ground) and drive OutP low and OutN high when the input signal Off is set to logic high. Although not shown, a hysteresis circuit as shown in FIG. 5 and described above can be connected to the negative resistance branch to create hysteresis for the corresponding logic converter.
[0024] The value of the offset resistor 628 for the InM input is made slightly higher than the value of the offset resistor 608 for the InP input to ensure that the output remains low when the input signals InP and InM are floating. The difference in the values of the offset resistors 608 and 628 depends on the amount of the maximum input offset expected in the GaN comparator to which the voltage divider outputs Pos and Neg are connected. The values of the offset resistors 608 and 628 can also be set to enable level shifting of low voltage differential signals (LVDS). A typical LVDS common mode voltage is about 1.3V, which is much lower than the value of the threshold voltage V th of the GaN FET.
[0025] FIG. 7 shows a resistor network-based logic level shifter circuit of the present invention having differential inputs similar to those of FIG. 6 but having series input resistors to accommodate large input signals. Specifically, the logic level shifter circuit 700 includes series resistors 716 and 718 at the inputs InP and InM, respectively, to pull down the large input signal voltage to a lower level. In FIG. 7, a hysteresis circuit as shown in FIG. 5 can be connected to the negative resistance branch to create hysteresis for the corresponding logic converter. Thus, the logic level shifter of FIG. 7 with the resistor network 700 achieves both input attenuation and the level shift necessary to interface with the GaN FET, and moreover, guarantees that the maximum input voltage swing does not damage the input GaN FET.
[0026] Briefly, in various embodiments described above, the present invention advantageously provides a circuit topology that can be used as a single - ended or differential level - shift interface for GaN ICs that enables the IC to be controlled by standard low - voltage CMOS - level inputs. The level - shift circuit of the present invention is based on a resistor network and, therefore, is not affected by process and temperature variations and is particularly suitable for implementation within GaN ICs. The resistor network of the level - shifter of the present invention includes an offset resistor circuit, whereby the input to the GaN comparator can be set to transition near the optimal bias point of the comparator. The circuit of the present invention also includes hysteresis, which is also set by a resistor circuit and is, therefore, also not affected by process and temperature variations. The input resistance can be provided to reduce the high - voltage input signal commonly found in old analog control systems in order to avoid damage to the input GaN FET.
[0027] The present invention may be embodied in other specific forms without departing from its gist or essential characteristics. The embodiments described are to be considered in all respects only as illustrative and not restrictive. Therefore, the scope of the present invention is indicated not by the foregoing description but by the appended claims. All modifications that come within the meaning and range of equivalents of the claims are to be embraced within their scope.
Description of Reference Numerals
[0028] 100 Logic level - shift circuit 101 Resistor 102 FET transistor, FET 103 Resistor 104 FET, resistor 106 Resistor 108 Resistor 200 Conventional differential - latch - based logic level - shift circuit 201 NFET 202 NFET 203 NFET 204 NFET 300 Common gate-based logic level shifter circuit 400 Prior art voltage divider level shifter circuit 402 Differential comparator 404 Resistor 406 Resistor 408 Resistor 410 Resistor 500 Level shifter circuit 502 Resistor network 504 Resistor 506 Resistor 508 Resistor 510 Resistor 512 Resistor 514 FET 516 Resistor 518 FET 520 GaN comparator 602 Resistor network 604 Resistor 606 Resistor 608 Resistor 614 FET 624 Resistor 626 Resistor 628 Resistor 700 Logic level shifter circuit 704 Resistor 706 Resistor 708 Resistor 714 FET 716 Resistor 718 Resistor 724 Resistor 726 Resistor 728 Resistor
Claims
1. a GaN differential comparator having first and second inputs and corresponding positive and negative outputs, a resistor network including a plurality of resistors, the resistor network including a first voltage divider for receiving an input signal and outputting a level-shifted and scaled input signal, and a second voltage divider for generating a trip voltage, the second voltage divider including a resistor hysteresis circuit, wherein the level-shifted and scaled input signal from the first voltage divider is connected to the first input of the GaN differential comparator, and the trip voltage from the second voltage divider is connected to the second input of the GaN differential comparator, whereby the positive and negative outputs of the GaN differential comparator include a complementary bipolar level-shifted signal corresponding to the input signal, an integrated GaN-based logic level shifter.
2. The integrated GaN-based logic level shifter according to claim 1, wherein the first voltage divider includes a first resistor arranged in series between a voltage source and a lower voltage, a scale resistor, and an offset resistor.
3. The integrated GaN-based logic level shifter according to claim 2, wherein the input signal is connected between the scale resistor and the offset resistor, and the first input of the GaN differential comparator is connected between the first resistor and the scale resistor.
4. The integrated GaN-based logic level shifter according to claim 2, wherein the values of the first resistor and the offset resistor are set such that the level-shifted and scaled input signal to the first input of the comparator transitions near the optimal bias point of the comparator.
5. The integrated GaN-based logic level shifter according to claim 4, wherein the second voltage divider generates a trip voltage that transitions near the optimal bias point of the comparator.
6. The integrated GaN-based logic level shifter according to claim 2, wherein the GaN differential comparator is configured to control the hysteresis circuit by outputting a signal to the gate of a FET connected across the hysteresis circuit.
7. An integrated GaN-based logic level shifter for differential inputs having first and second input signals, A GaN differential comparator having first and second inputs and corresponding positive and negative outputs, A resistor network including a plurality of resistors, A first voltage divider for receiving the first input signal and outputting a first level-shifted and scaled input signal, A second voltage divider for receiving the second input signal and outputting a second level-shifted and scaled input signal Including a resistor network, The first level-shifted and scaled input signal from the first voltage divider of the GaN differential comparator is connected to the first input of the GaN differential comparator, and the second level-shifted and scaled input signal from the second voltage divider is connected to the second input of the GaN differential comparator, whereby the positive and negative outputs of the GaN differential comparator include complementary bipolar level-shifted signals corresponding to the first and second input signals, an integrated GaN-based logic level shifter. Claim 8 The integrated GaN-based logic level shifter according to claim 7, wherein the first voltage divider and the second voltage divider each include a first resistor, a scale resistor, and an offset resistor arranged in series between a voltage source and a lower voltage. Claim 9 The first and second input signals are respectively connected between the scale resistor and the offset resistor of each of the first and second voltage dividers, and the first and second inputs of the GaN differential comparator are connected between the first resistor and the scale resistor of each of the first and second voltage dividers. The integrated GaN-based logic level shifter according to claim 8. Claim 10 The values of the first resistors and the offset resistors of the first and second voltage dividers are set such that the level-shifted and scaled input signals at the first and second inputs of the comparator transition near the optimal bias point of the comparator. The integrated GaN-based logic level shifter according to claim 8. Claim 11 The integrated GaN-based logic level shifter according to claim 7, wherein the first and second voltage dividers each further include a respective resistor hysteresis circuit. Claim 12 The integrated GaN-based logic level shifter according to claim 7, further comprising first and second input resistors for pulling down the voltage levels of the first and second input signals respectively.