Logic gate

Abstract

A logic gate comprising a semiconductor device is provided. The semiconductor device includes a charge reservoir layer disposed between a first charge receiving layer and a second charge receiving layer. The first charge receiving layer defines a first current flow path connected at one end to a common output contact and at the other end to a drive contact. The second charge receiving layer defines a current flow path connected at one end to the common output contact and at the other end to a ground contact. The charge reservoir layer comprises a potential well having the lowest energy state of mobile charge carriers, which is at an energy lower than the lowest energy state of the mobile charge carriers of both the first and second charge receiving layers. The logic gate further comprises a control gate and a ground electrode separated from the charge receiving layers by a non-conductive layer. The control gate and the ground electrode are configured to apply input voltages to both ends of the semiconductor device such that mobile charge carriers confined within the charge reservoir layer move to the first charge receiving layer at a first applied input voltage and to the second charge receiving layer at a second applied input voltage.

Description

Technical Field

[0001] The present invention relates to logic gates, and more particularly to digital logic gates for use in digital circuits.

Background Art

[0002] Logic gates are devices that function as fundamental elements of digital circuits and perform basic logic functions that are the basis of those digital circuits. Digital computing is based on complementary metal oxide semiconductor (CMOS) logic gates, which are composed of pairs of devices (transistors or switches) that exhibit complementary behavior during use. That is, during use, when one of the pair is on, the other of the pair is off, and vice versa. In all known configurations of CMOS logic gates, this is achieved by having one of the pair be an n-type semiconductor (nMOS) and the other of the pair be a p-type semiconductor (pMOS).

[0003] The principle of a conventional CMOS gate will be described with reference to FIG. 1 showing the simplest NOT gate of a conventional logic gate. The NOT gate 1 in FIG. 1 consists of a p-MOS 10 and an n-MOS 20 connected in series. Throughout the operation, a high drive voltage V DD (for example, +2.5 V) is applied to the gate 1, and an input voltage V IN can be applied to the gate 1 to control the behavior of the pMOS 10 and the nMOS 20.

[0004] For example, when the input voltage V IN is high, a high resistance is generated across the pMOS 10, and a low resistance is generated across the nMOS 20. As a result, current flow across the pMOS 10 is prevented, which means that all of the drive voltage V DD drops across the pMOS 10, and the output voltage V OUT is zero.

[0005] In contrast, when the input voltage VIN When it is low, a low resistance is generated across pMOS10 and a high resistance is generated across nMOS20. As a result, current can flow across pMOS10, which means that all of the drive voltage V DD is recognized at the output voltage V OUT .

[0006] As a result, when the input voltage V IN is high, the output voltage V OUT is low, and when the input voltage V IN is low, the output voltage V OUT is high. This arrangement depends on a pair of devices that have the peculiar requirement that, for the same input, when one is in a high-resistance state, the other is in a low-resistance state, and vice versa. Using this same principle, other logic gates such as AND gates, NAND gates, OR gates, and NOR gates are constructed.

[0007] Since one of the pMOS and nMOS is always in the "off" state, a CMOS logic gate only consumes a large amount of power instantaneously during the switching between the "on" state and the "off" state. As a result, CMOS devices generally generate less waste heat and are thus preferred over other logic forms.

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, the inventors have recognized that further advantages can be achieved beyond what is accomplished by CMOS logic gates. And an improved logic device has been devised that overcomes or substantially reduces the disadvantages associated with the prior art.

Means for Solving the Problems

[0009] According to a first aspect of the present invention, a logic gate is provided that includes a semiconductor device. The semiconductor device includes a charge reservoir layer disposed between a first charge receiving layer and a second charge receiving layer. The first charge receiving layer defines a first current flow path connected at one end to a common output contact and at the other end to a drive contact. The second charge receiving layer defines a current flow path connected at one end to the common output contact and at the other end to a ground contact. The charge reservoir layer includes a potential well having a lowest energy state of mobile charge carriers that is lower in energy than the lowest energy state of mobile charge carriers in both the first and second charge receiving layers. The logic gate further includes a control gate and a ground electrode separated from the charge receiving layers by a non-conductive layer. The control gate and the ground electrode are configured to apply an input voltage across the semiconductor device such that mobile charge carriers confined within the charge reservoir layer move to the first charge receiving layer at a first applied input voltage and move to the second charge receiving layer at a second applied input voltage.

[0010] At the first applied input voltage, the lowest energy state of mobile charge carriers in the first charge receiving layer can be lower in energy than the lowest energy state of mobile charge carriers in both the charge reservoir layer and the second charge receiving layer.

[0011] At the second applied input voltage, the lowest energy state of mobile charge carriers in the second charge receiving layer can be lower in energy than the lowest energy state of mobile charge carriers in both the charge reservoir layer and the first charge receiving layer.

[0012] The present invention can be advantageous in that the logic gate according to the present invention reduces the number of devices required to implement a digital logic gate. For example, as described above, compared to the simplest NOT gate of a conventional logic gate, the logic gate according to the present invention requires half the number of devices required by a conventional CMOS gate. When a conventional CMOS gate requires one nMOS device and one pMOS device, the logic gate according to the present invention provides a first charge receiving layer that effectively acts as the pMOS of the conventional CMOS gate and a second charge receiving layer that effectively acts as the nMOS of the conventional CMOS NOT gate. Thereby, the logic gate of the present invention and any circuit provided with the logic gate of the present invention become much more compact.

[0013] The present invention can be further advantageous in that the logic gate of the present invention operates symmetrically. That is, the application of the first applied input voltage has a first effect on the movement of mobile charge carriers, and the application of the second applied input voltage has an equal and opposite effect on the movement of mobile charge carriers. In contrast, in a conventional CMOS gate, it is difficult to implement nMOS and pMOS having equivalent but opposite characteristics. The fundamental reason for this is thought to be that electrons move more easily than holes because the movement of holes actually requires the movement of electron deficiencies. For this reason, in conventional CMOS, the pMOS performance is inferior to that of the nMOS, and the performance of the entire logic gate is limited to that of the pMOS. In contrast, the logic gate of the present invention requires only one type of charge carrier. This problem is alleviated when these charge carriers are electrons.

[0014] The present invention is also considered to be advantageous in reducing power dissipation. The main source of power dissipation in conventional CMOS logic gates is caused by both the nMOS and pMOS being instantaneously in the "on" state when switching the input voltage, i.e., between the first applied input voltage and the second applied input voltage. However, since the input voltage is switched very frequently, a large amount of power is dissipated over time due to the high speed of the latest digital logic circuits. In contrast, simulations of the logic gate according to the present invention suggest that power dissipation is reduced because there is no applied input voltage and both charge-receiving layers are simultaneously conductive, i.e., in the "on" state. In particular, simulations of the logic gate according to the present invention suggest that there is no applied input voltage and there are sufficient mobile charge carriers in both charge-receiving layers to enable both receiving layers to be simultaneously sufficiently conductive, i.e., in the "on" state.

[0015] The logic gate may comprise a substrate layer. The semiconductor device may be grown on the substrate layer.

[0016] The first charge-receiving layer, the second charge-receiving layer, and the charge reservoir layer may form an active layer. The control gate may be disposed on a first outer surface of the active layer. The ground electrode may be disposed on a second outer surface of the active layer. The first and second outer surfaces may be different surfaces. The first and second outer surfaces may be opposing surfaces of the active layer. For example, the control gate may be disposed on the upper surface of the active layer, and the ground electrode may be disposed on the bottom surface of the active layer.

[0017] Alternatively, the semiconductor device may comprise one or more additional layers disposed between the active layer and the control gate and / or the ground electrode.

[0018] For example, the control gate may be separated from the first charge receiving layer by a first external charge barrier disposed on the outer surface of the first charge receiving layer, i.e., on the opposite side of the first charge receiving layer with respect to the charge reservoir layer. Further, the ground electrode may be separated from the second charge receiving layer by a second external charge barrier disposed on the outer surface of the second charge receiving layer, i.e., on the opposite side of the second charge receiving layer with respect to the charge reservoir layer. Thus, the external charge barrier may also be referred to as a non-conductive layer or even an insulating layer. When the logic gate further includes a substrate layer, the second external charge barrier may be disposed between the second charge receiving layer and the substrate.

[0019] In this arrangement, the control gate may be disposed on the outer surface of the first external charge barrier, i.e., on the opposite side of the first external charge barrier with respect to the first charge receiving layer, and the ground electrode may be disposed on the outer surface of the second external charge barrier, for example, between the second external charge barrier and the substrate.

[0020] The input voltage may be applied across each of the charge reservoir layer, the first charge receiving layer, and the second charge receiving layer.

[0021] The drive contact and the ground contact may be for applying a drive voltage across the device. The drive voltage may be applied across each of the charge reservoir layer, the first charge receiving layer, and the second charge receiving layer. The drive voltage may be a constant voltage.

[0022] The common output contact may be for providing an output voltage. The output voltage may depend on the conductivity of the first and second charge receiving layers. The conductivity of the first and second charge receiving layers depends on the presence of mobile charge carriers in those layers, and the presence of mobile charge carriers in those layers depends on the input voltage, so the output voltage may depend on the input voltage. Thus, the output voltage may be controlled by controlling the input voltage.

[0023] Some or all of the control gate, ground electrode, common output contact, drive contact, and ground contact may be connectable to other parts of the device, such as another part of an integrated circuit, ground, or another logic gate. This connection may enable a drive voltage to be applied to the logic gate via the drive contact and / or an input voltage to be applied to the logic gate via the control gate. This may also enable an output voltage to be output from the logic gate via the common output contact. That is, any of the drive voltage, input voltage, and output voltage may be provided by or to an external source.

[0024] Some or all of the control gate, ground electrode, common output contact, drive contact, and ground contact may be formed of a metallic material. Alternatively, some or all of the control gate, ground electrode, common output contact, drive contact, and ground contact may be formed of a semiconductor material. For example, the control gate may be formed by a conductive layer disposed between a first charge receiving layer and a first outer surface of the semiconductor device. Similarly, the ground electrode may be formed by a conductive layer disposed between a second charge receiving layer and a second outer surface. This arrangement can shorten the distance between the control gate and the ground electrode in use, and thus increase the electric field for a given input voltage, and can also provide a common ground electrode for a plurality of devices integrated on the same chip to which different input voltages can be applied, and may thus be advantageous in many embodiments.

[0025] Although not essential, the common output contact and / or the drive contact and / or the ground contact may be either n-doped or p-doped.

[0026] The charge reservoir layer may be doped. The charge reservoir layer may be doped before the application of the input voltage. Thereby, charge carriers can be induced in the charge reservoir layer. The semiconductor device may be configured such that, when there is no input voltage, those induced charge carriers remain in the charge reservoir layer. Alternatively, the first charge receiving layer and the second charge receiving layer may also be doped, and the charge reservoir layer may be doped to a different extent, for example, to a greater or lesser extent. Thereby also, charge carriers can be induced in the charge reservoir layer. The semiconductor device may be configured such that, when there is no input voltage, those induced charge carriers remain in the charge reservoir layer.

[0027] The semiconductor device may include a heterostructure. The semiconductor device may have a heterojunction at the interface between the first charge receiving layer and the charge reservoir layer. The semiconductor device may have a heterojunction at the interface between the charge reservoir layer and the second charge receiving layer. The potential well of the charge reservoir layer may include a quantum well. The quantum well of the charge reservoir layer may be defined between the first charge receiving layer and the second charge receiving layer. The quantum well of the charge reservoir layer may be formed by a charge reservoir layer having offset conduction and / or a valence band, and may form a heterojunction at the interface between the charge reservoir layer and the first charge receiving layer and / or between the charge reservoir layer and the second charge receiving layer. For example, the charge reservoir layer may have a conduction band minimum energy lower than the conduction band minimum energy of the first charge receiving layer and the conduction band minimum energy of the second semiconductor layer, and thus may form a quantum well.

[0028] The offset conduction band and / or valence band of the charge reservoir layer is achieved by selecting different semiconductors for the adjacent layers, thereby defining quantum wells in the conduction band and / or valence band. That is, the offset conduction band and / or valence band of the charge reservoir layer can be achieved by forming the charge reservoir layer with a semiconductor different from the semiconductor or semiconductors used to form the first charge receiving layer and the second semiconductor layer. When the first charge receiving layer and / or the second charge receiving layer includes two or more semiconductors, the offset conduction band and / or valence band of the charge reservoir layer can be achieved by forming the charge reservoir layer with a semiconductor different from the semiconductor used in the adjacent layer of the first charge receiving layer and / or the second semiconductor layer.

[0029] Accordingly, the charge reservoir layer is formed by a narrower bandgap semiconductor disposed between two wider bandgap semiconductors, thereby providing a heterojunction structure. That is, the charge reservoir layer may be formed by a semiconductor with a narrower bandgap, and the adjacent first and second charge receiving layers may be formed by semiconductors with a wider bandgap. "Bandgap" means the energy gap between the valence band and the conduction band of a semiconductor.

[0030] The semiconductor of the charge reservoir layer and the semiconductors of the first and second charge acceptor layers may be formed from any semiconductor that provides the necessary barrier potential, e.g., any semiconductor that provides the necessary heterojunction. For example, the semiconductor may include a Group IV semiconductor such as Si, or an alloy of Group IV semiconductors such as SiGe, or the semiconductor may include Group II-VI semiconductors and their alloys, or the semiconductor may include other materials such as those known as 2D materials. In presently preferred embodiments, the semiconductor includes a Group III-V semiconductor, or an alloy of Group III-V semiconductors. For example, the charge reservoir layer may be formed from gallium arsenide (GaAs), and the first and / or second charge acceptor layers may be formed from aluminum gallium arsenide (AlGaAs). Alternatively, the charge reservoir layer may be formed from indium arsenide (InAs), and the first and / or second charge acceptor layers may be formed from indium gallium arsenide (InGaAs).

[0031] Or alternatively, the charge reservoir layer and the first and / or second charge acceptor layers may be formed of the same semiconductor material, and the necessary barrier potential may be provided by variations in any of the components of the semiconductor material. For example, the charge reservoir layer and the first and second charge acceptor layers may all be formed from AlGaAs, and the Al content in the charge reservoir layer may be lower than that in the first and second charge acceptor layers. Alternatively, the charge reservoir layer and the first and second charge acceptor layers may all be formed from InGaAs, and the Ga content in the charge reservoir layer may be lower than that in the first and second charge acceptor layers.

[0032] The quantum well of the charge reservoir layer may have discrete internal energy levels for accommodating mobile charge carriers within the charge reservoir layer. The discrete energy levels of the charge reservoir layer may correspond to one or more confined internal states through which (and from which) mobile charge carriers can pass.

[0033] The lowest energy state in which mobile charge carriers can be present in the conduction band of the first charge receiving layer and / or the second charge receiving layer can have an energy higher than the lowest discrete energy level of the charge reservoir layer. Thus, the first charge receiving layer and / or the second charge receiving layer may not be occupied by mobile charge carriers when there is no input voltage, i.e., when the applied bias or the applied electric field is zero. Thus, the first charge receiving layer and / or the second charge receiving layer can provide a high resistance to the flow of current when there is no input voltage. Thus, the first charge receiving layer and / or the second charge receiving layer can be non-conductive, i.e., insulating, when there is no input voltage.

[0034] The application of an input voltage across the semiconductor device can modify either the charge reservoir layer, the first charge receiving layer, and the second charge receiving layer, or any combination thereof. The shape and / or size of the conduction band of either the third charge reservoir layer, the first charge receiving layer, and the second charge receiving layer, or any combination thereof may be modified. Alternatively or additionally, the Fermi level of the logic gate may be modified. For example, the conduction band of either the charge reservoir layer, the first charge receiving layer, and the second charge receiving layer, or any combination thereof can become inclined across the applied electric field. In particular, an increase or decrease in the height of the conduction band across any of these layers can be proportional to the distance across the applied electric field.

[0035] In response to the application of a first input voltage, the lowest energy state of at least a portion of the charge reservoir layer can have an energy higher than the conduction band minimum energy of at least a portion of the first charge receiving layer. In response to the application of a first input voltage, at least a portion of the conduction band minimum energy of the first charge receiving layer may have an energy lower than the Fermi energy of the first charge receiving layer. Thus, mobile charge carriers can flow from the charge reservoir layer to the first charge receiving layer in response to the application of a first input voltage.

[0036] Therefore, the first charge receiving layer may come to be occupied by mobile charge carriers in response to the application of the first applied input voltage. Therefore, the first charge receiving layer may provide a low resistance to the flow of current in response to the application of the first applied input voltage. Therefore, the first charge receiving layer may become conductive in response to the application of the first applied input voltage.

[0037] Therefore, the number of mobile charge carriers in the charge reservoir layer may decrease in response to the application of the first applied input voltage. Therefore, the charge reservoir layer may come to be unoccupied by mobile charge carriers in response to the application of the first applied input voltage.

[0038] In response to the application of the first applied input voltage, the lowest energy state of the charge reservoir layer may have an energy lower than the conduction band minimum energy of the second charge receiving layer. In response to the application of the first applied input voltage, the conduction band minimum energy of the second charge receiving layer may have an energy higher than the Fermi energy of the second charge receiving layer.

[0039] Therefore, the second charge receiving layer may remain without mobile charge carriers, that is, mobile charge carriers may not flow from the charge reservoir layer to the second charge receiving layer in response to the application of the first applied input voltage. Therefore, the second charge receiving layer may remain unoccupied by mobile charge carriers in response to the application of the first applied input voltage. Therefore, the second charge receiving layer may continue to provide a high resistance to the flow of current in response to the application of the first applied input voltage. Therefore, the second charge receiving layer may remain non-conductive, that is, insulating, in response to the application of the first applied input voltage.

[0040] In response to the application of the second input voltage, the lowest energy state of at least a portion of the charge reservoir layer can have an energy higher than the conduction band minimum energy of at least a portion of the second charge acceptor layer. In response to the application of the second applied bias, at least a portion of the conduction band minimum energy of the second charge acceptor layer may have an energy lower than the Fermi energy of the second charge acceptor layer. Thus, mobile charge carriers can flow from the charge reservoir layer to the second charge acceptor layer in response to the application of the second input voltage.

[0041] Thus, the second charge acceptor layer can come to be occupied by mobile charge carriers in response to the application of the second input voltage. Thus, the second charge acceptor layer can provide a low resistance to the flow of current in response to the application of the second input voltage. Thus, the second charge acceptor layer can become conductive in response to the application of the second input voltage.

[0042] Thus, the number of mobile charge carriers in the charge reservoir layer can decrease in response to the application of the second input voltage. Thus, the charge reservoir layer can cease to be occupied by mobile charge carriers in response to the application of the second input voltage.

[0043] In response to the application of the second input voltage, the lowest energy state of the charge reservoir layer can have an energy lower than the conduction band minimum energy of the first charge acceptor layer. In response to the application of the second input voltage, the conduction band minimum energy of the first charge acceptor layer can have an energy higher than the Fermi energy of the first charge acceptor layer.

[0044] Therefore, the first charge receiving layer may remain without mobile charge carriers, i.e., the mobile charge carriers may not flow from the charge reservoir layer to the first charge receiving layer in response to the application of the second applied input voltage. Therefore, the first charge receiving layer may remain unoccupied by mobile charge carriers in response to the application of the second applied input voltage. Therefore, the first charge receiving layer may continue to provide a high resistance to the flow of current in response to the application of the second applied input voltage. Therefore, the first charge receiving layer may remain non-conductive, i.e., insulating, in response to the application of the second applied input voltage.

[0045] The mobile charge carriers may be electrons or holes. When the mobile charge carriers are electrons, the first applied input voltage may be a positive applied input voltage, and the second applied input voltage may be a negative applied input voltage. Alternatively, the first applied input voltage may be a positive applied input voltage, and the second applied input voltage may be a less positive applied input voltage. This may be the case, for example, when a positive input voltage is applied in the stationary state to form a potential well in the charge reservoir layer. Further alternatively, the second applied input voltage may be a negative applied input voltage, and the first applied input voltage may be a less negative applied input voltage. This may be the case, for example, when a negative input voltage is applied in the stationary state to form a potential well in the charge reservoir layer.

[0046] When the mobile charge carriers are holes, the first applied input voltage may be a negative applied input voltage, and the second applied input voltage may be a positive applied input voltage. Alternatively, the first applied input voltage may be a negative applied input voltage, and the second applied bias may be a less negative applied input voltage. This may be the case, for example, when a negative input voltage is applied in the stationary state to form a potential well in the charge reservoir layer. Further alternatively, the second applied input voltage may be a positive applied input voltage, and the first applied input voltage may be a less positive applied input voltage. This may be the case, for example, when a positive input voltage is applied in the stationary state to form a potential well in the charge reservoir layer.

[0047] The semiconductor device may also have a heterojunction at the interface between the first external charge barrier and the first charge-receiving layer and / or between the second charge-receiving layer and the second external charge barrier. The external charge barriers may be formed from an insulator or semiconductor material that defines a suitably large potential barrier for the first and second charge-receiving layers, respectively. The external charge barriers may be formed of a dielectric material. The external charge barriers may be formed of a semiconductor material. The semiconductor may be an undoped semiconductor material. The external charge barriers may be formed from a group III-V semiconductor material, such as aluminum arsenide (AlAs), or from a suitable oxide such as silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0048] In an alternative embodiment, the semiconductor device may further comprise a first internal charge barrier disposed between the first charge-receiving layer and the charge reservoir layer and / or a second internal charge barrier disposed between the charge reservoir layer and the second charge-receiving layer. The semiconductor device may have a heterojunction at the interface between any or any combination of the first charge-receiving layer and the first internal charge barrier, the first internal charge barrier and the charge reservoir layer, the charge reservoir layer and the second internal charge barrier, and the second internal charge barrier and the second charge-receiving layer. In this arrangement, the quantum well of the charge reservoir layer may be defined between the first internal charge barrier and the second internal charge barrier.

[0049] The internal charge barrier may be a charge trap barrier such as that known from U.S. Patent No. 10,243,086. In particular, the internal charge barrier may be formed as a potential barrier that prevents the passage of mobile charge carriers between the charge reservoir layer and the first charge receiving layer and / or between the charge reservoir layer and the second charge receiving layer. The internal charge barrier may be a resonant tunneling barrier. These features can be advantageous in that the effect of the applied bias remains even when the input voltage is no longer applied. For example, when a first input voltage is applied and mobile charge carriers move within the first charge receiving layer, when the application of the first applied input voltage is stopped, at least a portion of the mobile charge carriers remain within the first charge receiving layer, and thus the first charge receiving layer remains conductive. Similarly, when a second input voltage is applied and mobile charge carriers move within the second charge receiving layer, when the application of the second applied input voltage is stopped, at least a portion of the mobile charge carriers remain within the second charge receiving layer, and thus the second charge receiving layer remains conductive. This reduces the energy consumption of the logic gate and enables operation as a composite memory and logic device.

[0050] In this arrangement, the first charge receiving layer may also include a potential well, such as a quantum well, in addition to the quantum well of the charge reservoir layer. The quantum well of the first charge receiving layer may be defined between the first external charge barrier and the first internal charge barrier. The quantum well of the first charge receiving layer may be formed by the first charge receiving layer having an offset conduction band and / or valence band, forming a heterojunction at the interface between the first charge receiving layer and the first external charge barrier and / or between the first charge receiving layer and the first internal charge barrier. For example, the first charge receiving layer may have a minimum energy state of mobile charge carriers that is lower than the conduction band minimum energy of the first external charge barrier and the conduction band minimum energy of the first internal charge barrier, and thus may form a quantum well.

[0051] In this arrangement, the second charge - receiving layer may also include potential wells, such as quantum wells, in addition to the quantum wells of the charge - reservoir layer. The quantum wells of the second charge - receiving layer may be defined between a second external charge barrier and a second internal charge barrier. The quantum wells of the second charge - receiving layer are formed by a second charge - receiving layer having an offset conduction band and / or valence band, and can form heterojunctions at the interfaces between the second charge - receiving layer and the second external charge barrier and / or between the second charge - receiving layer and the second internal charge barrier. For example, the second charge - receiving layer has a lowest - energy state of mobile charge carriers that is lower than the conduction - band minimum energy of the second external charge barrier and the conduction - band minimum energy of the second internal charge barrier, and thus can form quantum wells.

[0052] The quantum wells of the first charge - receiving layer and / or the second charge - receiving layer are formed by the first charge - receiving layer and / or the second charge - receiving layer having an offset conduction and / or valence band, and can form heterojunctions at the interfaces between those charge - receiving layers and their respective barrier layers. The offset conduction band and / or valence band of the first charge - receiving layer and / or the second charge - receiving layer can be achieved by selecting different semiconductors for adjacent layers, thereby defining quantum wells in the conduction band and / or valence band. That is, the offset conduction band and / or valence band of the first charge - receiving layer and / or the second charge - receiving layer can be achieved by forming the first charge - receiving layer and / or the second charge - receiving layer from a semiconductor different from the semiconductor or semiconductors used to form the adjacent charge - barrier layer. If the adjacent charge - barrier layer comprises two or more semiconductors, the offset conduction band and / or valence band of the first charge - receiving layer and / or the second charge - receiving layer can be achieved by forming the first charge - receiving layer and / or the second charge - receiving layer from a semiconductor different from the semiconductor used in the adjacent layer of the adjacent barrier layer.

[0053] Therefore, the first charge-receiving layer and / or the second charge-receiving layer can be formed by a semiconductor with a narrower bandgap disposed between two semiconductors with wider bandgaps, thereby providing a heterojunction structure. That is, the first charge-receiving layer and / or the second charge-receiving layer may be formed by a semiconductor with a narrower bandgap, and the adjacent charge barrier layer may be formed by a semiconductor with a wider bandgap. "Bandgap" means the energy gap between the valence band and the conduction band of a semiconductor.

[0054] The semiconductor of the first charge-receiving layer and / or the second semiconductor layer, as well as the semiconductor of the charge barrier layer, can be formed from any semiconductor that provides the necessary barrier potential, for example, any semiconductor that provides the necessary heterojunction.

[0055] The quantum wells of the first charge-receiving layer and / or the quantum wells of the second charge-receiving layer can have discrete internal energy levels for accommodating mobile charge carriers within those layers. The discrete energy levels of these layers can correspond to one or more bound internal states through which mobile charge carriers can pass (and exit).

[0056] The lowest energy state of the first charge-receiving layer and / or the lowest energy state of the second charge-receiving layer can have an energy higher than the lowest energy state of the charge reservoir layer. Therefore, the first charge-receiving layer and / or the second charge-receiving layer may not be occupied by mobile charge carriers when there is no applied input voltage, i.e., when the applied bias is zero. Therefore, the first charge-receiving layer and / or the second charge-receiving layer can provide a high resistance to the flow of current when there is no applied input voltage. Therefore, the first charge-receiving layer and / or the second charge-receiving layer can be non-conductive, i.e., insulating, when there is no applied input voltage.

[0057] Applying an input voltage across the logic gate can change any one of, or any combination of, the charge reservoir layer, the first charge receiving layer, the second charge receiving layer, the first internal charge barrier, and the second internal charge barrier. The shape and / or size of the conduction band of any one of, or any combination of, the charge reservoir layer, the first charge receiving layer, the second charge receiving layer, the first internal charge barrier, and the second internal charge barrier may be changed. Alternatively or additionally, the Fermi level of the logic gate may be changed. For example, the conduction band of any one of, or any combination of, the charge reservoir layer, the first charge receiving layer, the second charge receiving layer, the first internal charge barrier, and the second internal charge barrier may become inclined across the applied electric field. In particular, an increase or decrease in the height of the conduction band across any one of these layers may be proportional to the distance across the applied electric field.

[0058] In response to the application of the first input voltage, the lowest energy state of the charge reservoir layer may have an energy higher than the lowest energy state of the first charge receiving layer. In response to the application of the first input voltage, at least a portion of the lowest energy state of the first charge receiving layer may have an energy lower than the Fermi energy of the first charge receiving layer. Thus, mobile charge carriers may flow from the charge reservoir layer to the first charge receiving layer in response to the application of the first input voltage.

[0059] Thus, the first charge receiving layer may become occupied in response to the application of the first input voltage. Thus, the first charge receiving layer may provide a low resistance to the flow of current in response to the application of the first input voltage. Thus, the first charge receiving layer may become conductive in response to the application of the first input voltage.

[0060] Thus, the number of mobile charge carriers in the charge reservoir layer may decrease in response to the application of the first input voltage. Thus, the charge reservoir layer may become unoccupied by mobile charge carriers in response to the application of the first input voltage.

[0061] In response to the application of the first input voltage, the lowest energy state of the charge reservoir layer may have an energy lower than the lowest energy state of the second charge receiving layer. In response to the application of the first input voltage, the lowest energy state of the second charge receiving layer may have an energy higher than the Fermi energy of the second charge receiving layer.

[0062] Accordingly, the second charge receiving layer may remain without mobile charge carriers, i.e., the mobile charge carriers may not flow from the charge reservoir layer to the second charge receiving layer in response to the application of the first input voltage. Accordingly, the second charge receiving layer may remain unoccupied by mobile charge carriers in response to the application of the first input voltage. Accordingly, the second charge receiving layer may continue to provide a high resistance to the flow of current in response to the application of the first input voltage. Accordingly, the second charge receiving layer may remain non-conductive, i.e., insulating, in response to the application of the first input voltage.

[0063] In response to the application of the second input voltage, the lowest energy state of the charge reservoir layer may have an energy higher than the lowest energy state of the second charge receiving layer. In response to the application of the second input voltage, at least a portion of the lowest energy state of the second charge receiving layer may have an energy lower than the Fermi energy of the second charge receiving layer. Accordingly, mobile charge carriers may flow from the charge reservoir layer to the second charge receiving layer in response to the application of the second input voltage.

[0064] Accordingly, the second charge receiving layer may become occupied in response to the application of the second input voltage. Accordingly, the second charge receiving layer may provide a low resistance to the flow of current in response to the application of the second input voltage. Accordingly, the second charge receiving layer may become conductive in response to the application of the second input voltage.

[0065] Accordingly, the number of mobile charge carriers in the charge reservoir layer can decrease in response to the application of the first applied input voltage. Accordingly, the charge reservoir layer can become unoccupied by mobile charge carriers in response to the application of the second applied input voltage.

[0066] In response to the application of the second applied input voltage, the lowest energy state of the charge reservoir layer can have an energy lower than the lowest energy state of the first charge receiving layer. In response to the application of the second applied input voltage, the lowest energy state of the first charge receiving layer can have an energy higher than the Fermi energy of the first charge receiving layer.

[0067] Accordingly, the first charge receiving layer may remain without mobile charge carriers, i.e., mobile charge carriers may not flow from the charge reservoir layer to the first charge receiving layer in response to the application of the second applied input voltage. Accordingly, the first charge receiving layer can remain unoccupied by mobile charge carriers in response to the application of the second applied input voltage. Accordingly, the first charge receiving layer can continue to provide a high resistance to the flow of current in response to the application of the second applied input voltage. Accordingly, the first charge receiving layer can remain non-conductive, i.e., insulating, in response to the application of the second applied input voltage.

[0068] The mobile charge carriers may be electrons or holes. When the mobile charge carriers are electrons, the first applied input voltage may be a positive applied input voltage, and the second applied input voltage may be a negative applied input voltage. Alternatively, the first applied input voltage may be a positive applied input voltage, and the second applied input voltage may be a less positive applied input voltage. This can be the case, for example, when a positive input voltage is applied in the stationary state to form a potential well in the charge reservoir layer. Further alternatively, the second applied input voltage may be a negative applied input voltage, and the first applied input voltage may be a less negative applied input voltage. This can be the case, for example, when a negative input voltage is applied in the stationary state to form a potential well in the charge reservoir layer.

[0069] When the mobile charge carrier is a hole, the first applied input voltage may be a negative applied input voltage, and the second applied input voltage may be a positive applied input voltage. Alternatively, the first applied input voltage may be a negative applied input voltage, and the second applied bias may be a smaller negative applied input voltage. This can be the case, for example, when a negative input voltage is applied in the stationary state to form a potential well in the charge reservoir layer. Further alternatively, the second applied input voltage may be a positive applied input voltage, and the first applied input voltage may be a smaller positive applied input voltage. This can be the case, for example, when a positive input voltage is applied in the stationary state to form a potential well in the charge reservoir layer.

[0070] The semiconductor device may comprise a planar layer. Any or all of the first charge receiving layer, the second charge receiving layer, the charge reservoir layer, and the charge barrier layer may comprise a substantially flat layer. Thus, the semiconductor structure may have a planar layer arrangement, i.e., the semiconductor layer and / or the charge barrier layer may be substantially planar. Alternatively, the semiconductor device may be arranged such that the semiconductor device layer and / or the charge barrier layer extend at least partially around each other, for example in the form of nanowires. Thus, each of the individual semiconductor device layers and / or the charge barrier layer may be substantially cylindrical.

[0071] When the above layers are substantially planar, the plane of each layer may be substantially parallel to the layer growth and / or substantially parallel to the plane of the substrate. That is, the layer may grow perpendicular to the substrate, i.e., in a direction perpendicular to the plane of the substrate and / or in a direction parallel to the normal of the plane of the substrate. In contrast, the different terminal regions of a conventional CMOS gate (i.e., the "p-n-p" or "n-p-n" doped regions) are arranged laterally on the substrate. Thus, the above feature may be advantageous in that the vertical growth of the layer makes the gate more scalable. The absence of lateral doping can also eliminate the problem of the "short channel effect".

[0072] The logic gate can operate as an inverter. Thus, according to a further aspect of the present invention, an inverter comprising a logic gate as described above is provided.

[0073] The logic gate may form part of an array or sequence of logic gates configured to operate as a logic device or digital circuit. For example, as described above, the logic gate according to the present invention effectively functions as a conventional CMOS NOT gate. Correspondingly, since conventional CMOS logic always comprises pairs of nMOS and pMOS, i.e., an equal number of nMOS and pMOS transistors, one or more of the above logic gates may be configured to form a logic device such as a NAND gate, a NOR gate, an OR gate, or an AND gate. Thus, according to a further aspect of the present invention, a logic device or digital circuit comprising one or more logic gates as described above is provided. The logic device may be a NAND gate, a NOR gate, an OR gate, or an AND gate.

[0074] Here, possible embodiments of the present invention will be described by way of example only with reference to the accompanying drawings.

Brief Description of the Drawings

[0075]

Figure 1

Figure 2a

Figure 2b

Figure 2c

Figure 3a

Figure 3b

Figure 4

Figure 5a

Figure 5b

Figure 5c

Figure 6

Figure 7a

Figure 7b

Figure 7c

Figure 8a

Figure 8b

DETAILED DESCRIPTION OF THE INVENTION

[0076] Figures 2a - 2c show the movement of charge carriers across the logic device 100 depending on the application of a voltage bias to the logic device 100.

[0077] Figure 2a shows a cross-sectional view of the logic device 100. The logic device 100 includes a charge reservoir 110, a first channel layer 120 (referred to as the "first charge-accepting layer" as defined above in the present invention), and a second channel layer 130 (referred to as the "second charge-accepting layer" as defined above in the present invention). When no bias is applied, the charge carriers 140 of the logic device 100 are present within the charge reservoir 110. When layers 120 and 130 are described as "channel" layers, it means that these layers can accept mobile charge carriers and thus can make them conductive and function as conventional channel layers during use.

[0078] Figure 2b shows the same logic device 100 with a positive voltage bias applied. In response to the application of the positive bias, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 to the first channel layer 120.

[0079] Figure 2c shows the same logic device 100 with a negative bias applied. In response to the application of the negative bias, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 to the second channel layer 130.

[0080] In the examples of FIGS. 2a - 2c, the charge carriers 140 are electrons. However, it is expected that the charge carriers 140 could alternatively be holes, in which case the logic device would operate in the reverse manner. That is, when the charge carriers 140 are holes, in response to the application of a positive bias, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 to the second channel layer 130, and in response to the application of a negative bias, the charge carriers 140 of the logic device 100 move from the charge reservoir 110 to the first channel layer 120.

[0081] FIGS. 3a and 3b show examples of the conduction band minimum energy level diagrams of the logic device 100 that achieve the behavior described in relation to FIGS. 2a - 2c.

[0082] FIG. 3a shows a first example of a logic device 100 in which the charge reservoir 110 is made of a first material having a relatively low conduction band edge energy, and the first and second channel layers 120, 130 are made of different materials having relatively high conduction band edge energy levels. Relatively low means that the conduction band edge energy of the charge reservoir 110 is lower than the conduction band edge energies of both the first and second channel layers 120, 130. Relatively high means that the conduction band edge energies of both the first and second channel layers 120, 130 are higher than the conduction band edge energy of the charge reservoir 110. As a result of the described differences in conduction band edge energy, the first and second channels 120, 130 define potential barriers on both sides of the charge reservoir 110 such that a potential well is formed by the charge reservoir 110.

[0083] Thus, when no bias is applied, the charge reservoir 110 provides an energy state 150 in which the existing charge carriers 140 are at a lower energy than the first and second channel layers 120, 130, and the charge carriers 140 remain within the charge reservoir 110.

[0084] When a positive bias is applied, the conduction band edge is distorted in one direction, whereby the first channel layer 120 provides an energy state in which the existing charge carriers 140 are at a lower energy than the charge reservoir 110 and the second channel layer 130, and as a result, the charge carriers 140 move from the charge reservoir to the first channel layer 120.

[0085] When a negative bias is applied, the conduction band edge is distorted in the opposite direction, whereby the second channel layer 130 provides an energy state in which the existing charge carriers 140 are at a lower energy than the charge reservoir 110 and the first channel layer 120, and as a result, the charge carriers 140 move from the charge reservoir to the second channel layer 130.

[0086] Figure 3b shows a second example in which quantum wells are formed in each of the charge reservoir 110, the first channel layer 120, and the second channel layer 130 due to the presence of the charge barrier, where the quantum well in the charge reservoir 110 is much wider than the quantum wells in the first channel layer 120 and the second channel layer 130.

[0087] Thus, when no bias is applied, the charge reservoir 110 provides an energy state 150 that is lower than the energy states 160, 170 provided by the first and second channel layers 120, 130, and the charge carriers 140 remain within the charge reservoir 110.

[0088] When a positive bias is applied, the conduction band edge is distorted in one direction, and the lowest energy state 160 of the first channel layer 120 becomes lower than the energy states 150, 170 of the charge reservoir 110 and the second channel layer 130, respectively. As a result, the charge carriers 140 move from the charge reservoir to the first channel layer 120.

[0089] When a negative bias is applied, the conduction band edge is distorted in the opposite direction, and the lowest energy state 170 of the second channel layer 130 becomes lower than the energy states 150, 160 of the charge reservoir 110 and the first channel layer 120, respectively. As a result, the charge carriers 140 move from the charge reservoir to the second channel layer 130.

[0090] This provision of energy states and band edge distortions is described in more detail in connection with FIGS. 5a - 5c, and the conduction and valence band edge energies across the logic device 100 are simulated at 300K in a one - dimensional model (through the device vertically) using a Schrödinger - Poisson solver in the effective mass approximation.

[0091] In the energy diagrams of FIGS. 5a - 5c, the logic device 100 is formed according to the layered arrangement shown in FIG. 4. In FIG. 4, the charge reservoir 110 is formed from a 80 - nm thick gallium arsenide (GaAs) layer, and the first and second channel layers 120, 130 are formed from 30 - nm thick aluminum gallium arsenide (Al 0.18 Ga 0.82 As) layers on both sides of the charge reservoir 110.

[0092] The reason for choosing this arrangement is that GaAs / AlGaAs is the most mature and well - understood compound semiconductor system. When the Al fraction of the AlGaAs layer is changed, the bandgap, conduction band edge, and valence band edge change with respect to the GaAs layer, but the change in lattice constant is minimal. This enables the conduction band edge and valence band edge to be manipulated with high quality and with little or no strain while growing the multilayer GaAs / Al x Ga 1-x As heterostructure material as needed. However, it is expected that other semiconductor materials, including other III - V semiconductor materials, may be used.

[0093] An insulating layer 180 is positioned outside the channel layers 120, 130, both of which are formed from 20 - nm thick aluminum arsenide (AlAs) layers. Finally, a gate 190 is placed outside the insulating layer 180, and a bias can be applied across the device 100 during use. The entire device 100 can also be constructed on a substrate.

[0094] In FIGS. 5a - 5c, the x - axis represents the thickness of the logic device 100 (i.e., perpendicular from top to bottom along the x - axis passing through the device 100 as shown in FIG. 4), and the y - axis represents the energy of the band edge.

[0095] Figure 5a shows a simulated schematic band energy diagram of the proposed logic device 100 when no bias is applied. From Figure 5a, for the charge reservoir 110 (at least at the ends) and the channel layers 120, 130, the Fermi level is within the bandgap (i.e., between the conduction band edge and the valence band edge), which means that the electrons 140 remain in the central part of the charge reservoir 110, and as a result, there are no mobile electrons in the channel layers 120 and 130 as described above. Therefore, no current can flow through the channel layers 120 and 130 of the logic device 100, and the device 100 is in the "off" state.

[0096] Figure 5b shows a simulated schematic band energy diagram of the proposed logic device 100 when a +3V bias is applied. As a result of the applied bias, the conduction band edge and the valence band edge are vertically distorted, such that the electron Fermi level exceeds the minimum value of the conduction band edge within the first channel layer 120. Although this is not immediately obvious in Figure 5b, upon closer inspection, it can be seen that the electron Fermi level exceeds the minimum value of the conduction band edge at the outer periphery of the first channel layer 120. Therefore, the electrons 140 of the logic device 100 move from the charge reservoir 110 to the first channel layer 120, making the first channel layer 120 highly conductive.

[0097] In contrast, the Fermi level remains within the bandgaps of both the charge reservoir 110 (at least at the ends) and the second channel layer 130, which means that no current can flow into the second channel layer 130. It is also important that the hole Fermi level remains within the bandgaps across the charge reservoir 110 and the channel layers 120, 130 to prevent hole transport during operation.

[0098] Figure 5c shows a simulated schematic band energy diagram of the proposed logic device 100 when a -3V bias is applied. As a result of the applied bias, the conduction band edge and valence band edge are vertically distorted, such that the electron Fermi level exceeds the conduction band edge minimum in the second channel layer 130. This is not immediately apparent in Figure 5c, but upon closer inspection, it can be seen that the electron Fermi level exceeds the conduction band edge minimum at the outer perimeter of the second channel layer 130. Thus, the electrons 140 in the logic device 100 move from the charge reservoir 110 to the first channel layer 130, making the first channel layer 130 highly conductive.

[0099] In contrast, the Fermi level remains within the band gaps of both the charge reservoir 110 (at least at the ends) and the first channel layer 120, which means that current cannot flow into the second channel layer 120. It is important that the hole Fermi level remains within the band gaps across the charge reservoir 110 and the channel layers 120, 130 to prevent hole transport during operation.

[0100] It should also be noted that due to the vertical symmetry of the layers (ignoring any substrate on which the device 100 is grown), the application of equal and opposite biases to the top gate 190 has equal and opposite effects on the operation of the device 100.

[0101] Figure 6 shows this movement of electrons depending on the bias applied across the device 100. In Figure 6, the x-axis represents the bias applied across the device, and the y-axis represents the integrated electron density in each of the first and second channel layers 120, 130 as a result of the bias applied across the device 100.

[0102] When a negative bias is applied, the second channel layer 130 has a high integrated electron density so as to be highly conductive, and the first channel layer 120 has a very low integrated electron density so as to be non-conductive. When a positive bias is applied, the second channel layer 130 has a very low integrated electron density so as to be non-conductive, and the first channel layer 120 has a high integrated electron density so as to be highly conductive.

[0103] In the presence of zero applied bias and negative applied bias, a small electron density exists in the first channel layer 120, and in the presence of zero applied bias and positive applied bias, a small electron density exists in the second channel layer 130, which is a result of the simulation conditions. In an actual device of finite size typical of modern electronic devices, the number of mobile electrons in those channels under such conditions is less than 1 and thus does not affect the operation of the device.

[0104] FIG. 7a shows a first embodiment in which the logic device 100 described herein can be used as part of an inverter 200. The inverter 200 of FIG. 7a comprises a planar layered arrangement in which a charge reservoir 110 is sandwiched between first and second channel layers 120, 130, and this arrangement itself is sandwiched between insulating layers 180. Gates 190 are applied on both sides of the insulating layer 190, and an input voltage V IN is provided to the upper gate 190. The lower gate 190 is connected to ground. Also, source and drain terminals are provided on both the first channel layer 120 and the second channel layer 130. A drive voltage V DD is provided to the first channel layer 120 via the drain terminal, and the drain terminal of the second channel layer 130 is connected to ground. An output voltage V OUT is provided via the source terminals of the first and second channel layers 120, 130.

[0105] FIG. 7b shows cross-sectional views of two further possible embodiments in which the logic device 100 described herein can be used as part of an inverter 300, where the inverters are provided in the form of "FINFET" devices and nanowires, respectively. Since both forms have the same cross-section, both embodiments will be described in relation to FIG. 7b.

[0106] In a second embodiment, the inverter 300 of FIG. 7b operates in the same manner as the inverter 200 of FIG. 7a, but is provided in the form of a "FinFET" device where the plane of the layer enters the page. The "FinFET" device may be considered more advantageous as a gate than a conventional planar device, and thus, the gate voltage can be applied to three sides of the device rather than one. In this regard, the inverter 300 comprises a layered arrangement in which the inner gate 190 is surrounded by an insulating layer 180, which is in turn surrounded by a second channel layer 130, which is in turn surrounded by a charge reservoir 110, which is surrounded by a first channel layer 120, which is in turn surrounded by an insulating layer 180, and the entire arrangement is surrounded by an outer gate 190. The source and drain terminals are provided in the first and second channel layers 120, 130 as in the embodiment of FIG. 7a, the terminals are connected to ground, and an input voltage V IN , a drive voltage V DD and an output voltage V OUT are provided.

[0107] In the third embodiment, the inverter 300 of FIG. 7b is provided in the form of a nanowire. Similar to a "FinFET", such a nanowire device may be considered advantageous over a conventional planar device as a gate, and thus an electric field can be applied around the device. In this regard, the inverter 300 comprises a cylindrical layered arrangement in which the inner gate 190 is surrounded by an insulating layer 180, which is in turn surrounded by a second channel layer 130, which is in turn surrounded by a charge reservoir 110, which is surrounded by a first channel layer 120, which is in turn surrounded by an insulating layer 180, the whole arrangement being surrounded by an outer gate 190. The source and drain terminals are provided in the first and second channel layers 120, 130 as in the embodiment of FIG. 7a, the terminals are connected to ground, and an input voltage V IN , a drive voltage V DD and an output voltage V OUT are provided.

[0108] FIG. 7c shows a fourth embodiment of the logic device 100 described herein that can be used as part of the inverter 300. The inverter 300 of FIG. 7c operates in the same manner as the inverter 200 of FIG. 7a, but an alternative shape of the upper gate 190 is provided with two separate upper gates 190. This allows the voltage V IN to be applied simultaneously to the first charge receiving layer 120 (via the arrangement on the left side of FIG. 7c) and to the charge reservoir layer 110 (via the arrangement on the right side of FIG. 7c). This can be advantageous for the operation of the logic device 100, especially when the logic device 100 forms part of a larger logic device or digital circuit.

[0109] FIGS. 8a and 8b show the inverter 200 of FIG. 7a in use. A positive voltage is applied to the upper gate 190 (V INIn FIG. 8a, which is applied across device 200 via (0), electrons move from charge reservoir 110 to the first channel layer 120 as described above with respect to the associated band edge energy diagram. As a result, the source and drain terminals of the first channel layer 120 are in a low resistance state, and the source and drain terminals of the second channel layer 130 are in a relatively high resistance state. This allows current to flow across the first channel layer 120 with low resistance so that any voltage applied to device 200 at V DD is output via V OUT .

[0110] In contrast, in FIG. 8b, where a negative voltage is applied across device 200 via the upper gate 190 (V IN ), electrons move from charge reservoir 110 to the second channel layer 130 as described above with respect to the associated band edge energy diagram. As a result, the source and drain terminals of the second channel layer 130 are in a low resistance state, and the source and drain terminals of the first channel layer 120 are in a relatively high resistance state. This prevents current from flowing across the first channel layer 120 so that the voltage output at V OUT is grounded, and allows current to flow across the second channel layer 130 with low resistance.

[0111] In this regard, inverter device 200 functions in the same manner as a conventional CMOS logic device, i.e., the first channel layer 120 acts as a pMOS layer and the second channel layer 130 acts as an nMOS layer. Similar to conventional CMOS logic devices, devices according to the present invention may be combined to form other digital logic gates such as AND, NAND, OR, or NOR logic gates.

[0112] It is also contemplated that a highly doped semiconductor that acts as effectively as a metal gate may be used instead of the metal gate 190 in the configurations of FIGS. 7a, 7b, 8a, and 8b.

Claims

1. A logic gate comprising a semiconductor device, wherein the semiconductor device includes a charge reservoir layer disposed between a first charge receiving layer and a second charge receiving layer, the first charge receiving layer defining a first current flow path connected to a common output contact at one end and a drive contact at the other end, the second charge receiving layer defining a current flow path connected to the common output contact at one end and a ground contact at the other end, the charge reservoir layer having a potential well with a minimum energy state of mobile charge carriers at an energy lower than the minimum energy state of mobile charge carriers in both the first and second charge receiving layers, the logic gate further comprising a control gate and a ground electrode separated from the charge receiving layer by a non-conductive layer, the control gate and the ground electrode being configured to apply an input voltage across the semiconductor device, such that mobile charge carriers confined within the charge reservoir layer move to the first charge receiving layer at a first applied input voltage and to the second charge receiving layer at a second applied input voltage.

2. The logic gate according to claim 1, wherein the first charge receiving layer and / or the second charge receiving layer is non-conductive in the absence of an applied input voltage.

3. The logic gate according to claim 2, wherein the first charge receiving layer remains non-conductive in response to the application of the second applied input voltage.

4. The logic gate according to claim 2, wherein the second charge receiving layer remains non-conductive in response to the application of the first applied input voltage.

5. The logic gate according to any one of the preceding claims, wherein the mobile charge carriers are electrons.

6. The logic gate according to claim 5, wherein the first applied input voltage is a positive input voltage and the second applied bias is a negative input voltage.

7. The logic gate according to any one of the preceding claims, wherein the semiconductor device has a planar layer arrangement.

8. The logic gate according to claim 7, wherein the logic gate further comprises a substrate layer, and the plane of each layer is substantially parallel to the plane of the substrate.

9. The logic gate according to any one of the preceding claims, wherein the semiconductor device has a heterostructure.

10. The logic gate according to any one of the preceding claims, wherein the charge reservoir layer includes a quantum well defined between the first charge receiving layer and the second semiconductor layer. **Claim 11** The logic gate according to claim 9 or claim 10, wherein the quantum well of the charge reservoir layer has discrete internal energy levels for accommodating mobile charge carriers within the charge reservoir layer. **Claim 12** The logic gate according to any one of the preceding claims, wherein the lowest energy state of the mobile charge carriers in the conduction band of the first charge receiving layer and the conduction band of the second charge receiving layer has an energy higher than the lowest energy state of the charge reservoir layer. **Claim 13** The logic gate according to any one of the preceding claims, wherein in response to the application of the first applied input voltage, at least a portion of the lowest energy state of the charge reservoir layer has an energy higher than at least a portion of the conduction band energy of the first charge receiving layer. **Claim 14** The logic gate according to any one of the preceding claims, wherein in response to the application of the first applied input voltage, at least a portion of the conduction band energy of the first charge receiving layer has an energy lower than the Fermi energy of the first charge receiving layer. **Claim 15** The logic gate according to any one of the preceding claims, wherein in response to the application of the first applied input voltage, the lowest energy state of the charge reservoir layer has an energy lower than the conduction band energy of the second charge receiving layer. **Claim 16** The logic gate according to any one of the preceding claims, wherein in response to the application of the first applied input voltage, the conduction band energy of the second charge receiving layer has an energy higher than the Fermi energy of the second charge receiving layer. **Claim 17** The logic gate according to any one of the preceding claims, wherein in response to the application of the second applied input voltage, at least a portion of the lowest energy state of the charge reservoir layer has an energy higher than at least a portion of the conduction band energy of the second charge receiving layer. **Claim 18** The logic gate according to any one of the preceding claims, wherein in response to the application of the second applied input voltage, at least a portion of the conduction band of the second charge receiving layer has an energy lower than the Fermi energy of the second charge receiving layer. **Claim 19** The logic gate according to any one of the preceding claims, wherein in response to the application of the second applied input voltage, the lowest energy state of the charge reservoir layer has an energy lower than the conduction band energy of the first charge receiving layer.

20. The logic gate according to any one of the preceding claims, wherein in response to the application of the second applied input voltage, the conduction band energy of the first charge receiving layer has an energy higher than the Fermi energy of the first charge receiving layer.

21. The logic gate according to any one of claims 1 to 11, wherein the first charge receiving layer includes a potential well defined between a first external charge barrier and a first internal charge barrier, and the second charge receiving layer includes a potential well defined between a second external charge barrier and a second internal charge barrier.

22. The logic gate according to claim 21, wherein the potential well of the first semiconductor layer and / or the potential well of the second semiconductor layer is a quantum well having discrete internal energy levels for accommodating charge carriers in those layers.

23. The logic gate according to claim 22, wherein the lowest energy state of the first charge receiving layer and / or the lowest energy state of the second charge receiving layer has an energy higher than the lowest energy state of the charge reservoir layer.

24. The logic gate according to claim 22 or claim 23, wherein in response to the application of the first applied input voltage, the lowest energy state of the charge reservoir layer has an energy higher than the lowest energy state of the first charge receiving layer.

25. The logic gate according to any one of claims 22 to 24, wherein in response to the application of the first applied input voltage, the lowest energy state of at least a part of the first charge receiving layer has an energy lower than the Fermi energy of the first charge receiving layer.

26. The logic gate according to any one of claims 22 to 25, wherein in response to the application of the first applied input voltage, the lowest energy state of the charge reservoir layer has an energy lower than the lowest energy state of the second charge receiving layer.

27. The logic gate according to any one of claims 22 to 26, wherein in response to the application of the first input voltage for imprinting, the lowest energy state of the second charge receiving layer has an energy higher than the Fermi energy of the second charge receiving layer.

28. The logic gate according to any one of claims 22 to 27, wherein in response to the application of the second input voltage for imprinting, the lowest energy state of the charge reservoir layer has an energy higher than the lowest energy state of the second charge receiving layer.

29. The logic gate according to any one of claims 22 to 28, wherein in response to the application of the second input voltage for imprinting, at least a part of the lowest confined internal state of the second charge receiving layer has an energy lower than the Fermi energy of the second charge receiving layer.

30. The logic gate according to any one of claims 22 to 29, wherein in response to the application of the second input voltage for imprinting, the lowest energy state of the charge reservoir layer has an energy lower than the lowest energy state of the first charge receiving layer.

31. The logic gate according to any one of claims 22 to 30, wherein in response to the application of the second input voltage for imprinting, the lowest energy state of the first charge receiving layer has an energy higher than the Fermi energy of the first charge receiving layer.

32. A logic device or digital circuit comprising one or more logic gates according to any of the preceding claims.

Images