Thin film transistor and method of manufacturing the same

Abstract

The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor. The method for manufacturing a thin film transistor according to an embodiment may include: forming a diffusion path layer on a substrate; forming one or more trenches in the diffusion path layer; forming a diffusion barrier layer inside the trenches; forming an active layer on the diffusion path layer and the diffusion barrier layer; forming a source and a drain on the active layer; forming a gate insulating layer between the source and the drain; forming a gate on the gate insulating layer; and performing a heat treatment.

Description

Technical Field

[0001] The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly, to an oxide thin film transistor and a method for manufacturing the same.

Background Art

[0002] A thin film transistor (TFT) is a type of field effect transistor (FET) manufactured by laminating a semiconductor thin film on an insulating substrate. A TFT includes three electrodes (e.g., source, drain, gate) and a thin film-like active layer (or channel layer) disposed between both electrodes. When a voltage is applied to the gate electrode, holes gather between the source electrode and the drain electrode, and a channel is formed, whereby current flows from the source electrode to the drain electrode. TFTs are used in display devices such as LCDs and OLEDs.

[0003] Examples of substances constituting the active layer of a TFT include amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and oxide. A TFT whose active layer is made of an oxide is referred to as an oxide TFT. Examples of oxides used in oxide TFTs include indium-gallium-zinc-oxide (IGZO). In recent years, various technologies have been studied to improve the electrical characteristics of oxide TFTs and enhance the performance and reliability of oxide TFTs.

[0004] In related prior art, there are Korean Patent Publication No. 10-2016-0131339 and Korean Patent Publication No. 10-2022-004795.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The object of the present specification is to provide a thin film transistor having improved electrical characteristics, performance, and reliability compared to the prior art, and a method for manufacturing the thin film transistor.

[0006] The object of the present specification is not limited to the objects mentioned above, and other objects and advantages of the present specification not mentioned can be more clearly understood from the embodiments of the present specification described below. Also, the objects and advantages of the present specification can be realized by the components described in the claims and combinations thereof.

Means for Solving the Problems

[0007] A thin film transistor according to one embodiment may include a substrate, a diffusion path layer disposed on the substrate, an active layer disposed on the diffusion path layer, a source and a drain disposed on the active layer, a gate insulating layer disposed between the source and the drain, a gate disposed on the gate insulating layer, and a diffusion barrier layer formed at positions corresponding to the source and the drain in the diffusion path layer.

[0008] A method for manufacturing a thin film transistor according to one embodiment may include a step of forming a diffusion path layer on a substrate, a step of forming one or more trenches in the diffusion path layer, a step of forming a diffusion barrier layer inside the trenches, a step of forming an active layer on the diffusion path layer and the diffusion barrier layer, a step of forming a source and a drain on the active layer, a step of forming a gate insulating layer between the source and the drain, a step of forming a gate on the gate insulating layer, and a step of performing heat treatment.

Effects of the Invention

[0009] According to the embodiment, by restrictively supplying oxygen to the active layer by the diffusion barrier layer and the diffusion path layer during the manufacturing process of the thin film transistor, oxygen vacancies that cause defects in the active layer are reduced, and thus the reliability of the thin film transistor is improved.

[0010] According to the embodiment, since a diffusion barrier layer having different density distributions is formed in the manufacturing process of the thin film transistor, there is an advantage that the transmittance of the reactants contained in the reaction gas can be selectively adjusted.

[0011] According to the embodiment, by forming a passivation layer on the active layer in the manufacturing process of the thin film transistor, there is an advantage that the thermal budget can be lowered and the charge mobility can be stably improved without generating thermal damage.

[0012] According to the embodiment, since the charge traps present in the passivation layer of the active layer are passivated by hydrogen in the manufacturing process of the thin film transistor, there is an advantage that the charge density of the passivation layer is reduced and the charge mobility is improved.

[0013] According to the embodiment, since a high-pressure heat treatment process is performed in a low-temperature environment in the manufacturing process of the thin film transistor, there is an advantage that deterioration of heat-sensitive parts can be prevented and the product yield can be improved.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0015] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the embodiments described herein and can be embodied in other forms. On the contrary, the embodiments introduced here are provided so that the disclosed content is thorough and complete, and to fully convey the idea of the present invention to ordinary technicians.

[0016] In this specification, when a component is referred to as being on another component, it means that it may be directly formed on the other component or a third component may be interposed therebetween. Also, in the drawings, the shape and size may be exaggerated for an effective explanation of the technical content.

[0017] Also, in various embodiments of this specification, although terms such as first, second, third, etc. are used to describe various components, these components should not be limited by these terms. These terms are merely used to distinguish one component from another. Thus, what is referred to as the first component in one embodiment can be referred to as the second component in another embodiment. Each embodiment described and illustrated herein includes its complementary embodiments. Also, “and / or” in this specification is used in the sense of including at least one of the components listed before and after.

[0018] The singular expressions in the specification include plural expressions unless the context clearly indicates otherwise. Also, terms such as “including” or “having” are intended to specify the presence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the presence or possibility of addition of one or more other features, numbers, steps, components, or combinations thereof. Also, “connected” in this specification is used in the sense of including both those that indirectly connect a plurality of components and those that directly connect them.

[0019] Also, in explaining the present invention below, when it is determined that a detailed description of related known functions or configurations obscures the gist of the present invention, the detailed description thereof will be omitted.

[0020] Hereinafter, for convenience of explanation, the first direction refers to the X-axis of the orthogonal coordinate system, and the second direction refers to the Z-axis of the orthogonal coordinate system. At this time, the first direction is orthogonal to the second direction.

[0021] FIG. 1 shows the structure of a thin film transistor according to the first embodiment. FIG. 2 shows the movement path of ions in a reaction gas by heat treatment during the manufacturing process of the thin film transistor according to the first embodiment.

[0022] The thin film transistor 10 according to the first embodiment may include substrates 110, 120, a diffusion path layer 200, a metal oxide active layer 300, a source 400, a drain 500, a gate insulating layer 600, a gate 700, and a diffusion barrier layer 800.

[0023] The substrates 110, 120 may include a base substrate layer 110 and a buffer substrate layer 120.

[0024] The base substrate layer 110 may be a single crystal substrate. A single crystal semiconductor layer may be formed on at least one surface of the base substrate layer 110. The single crystal semiconductor layer may be made of any one of Si, Ge, SiGe, GeSn, InSb, GaAs (III-V semiconductor), GaP, InAlAs, InGaAs, GaSbP, GaAsSb, and InP, but the constituent material of the single crystal semiconductor layer is not limited thereto.

[0025] The buffer substrate layer 120 may have a lattice constant different from that of the base substrate layer 110 in order to minimize lattice stress. In other embodiments, the lattice constant and / or crystal structure of the buffer substrate layer 120 may be the same as or similar to the lattice constant and / or crystal structure of the base substrate layer 110.

[0026] The buffer substrate layer 120 may be crystalline formed by epitaxial growth on the base substrate layer 110. The buffer substrate layer 120 may be formed by doping the base substrate layer 110 with impurities of a material different from that of the base substrate layer 110. In one embodiment, the buffer substrate layer 120 may be relatively over-doped compared to the base substrate layer 110 as the layer position goes higher.

[0027] The buffer substrate layer 120 may have different lattice constants for different layer positions. For example, the lattice constant of the buffer substrate layer 120 may gradually increase from a lower layer position to a higher layer position.

[0028] The diffusion path layer 200 may be disposed on the substrates 110 and 120. The diffusion path layer 200 can also be referred to as a diffusion layer.

[0029] The diffusion path layer 200 can serve as a path for the ionized reaction gas provided during the heat treatment of the active layer 300. That is, when the heat treatment is performed, the ions generated from the reaction gas can pass through the diffusion path layer 200. The ionized reaction gas according to one embodiment may contain at least one of oxygen ions, hydrogen ions, fluorine ions, and nitrogen ions, but the type of the ionized reaction gas is not limited thereto.

[0030] The diffusion path layer 200 may be made of an oxide such as SiO2, but the type of the material constituting the diffusion path layer 200 is not limited thereto.

[0031] The diffusion path layer 200 may be disposed between the substrates 110 and 120 and the active layer 300. The diffusion path layer 200 can allow the ionized reaction gas supplied from the outside to pass through.

[0032] The diffusion path layer 200 may be an oxide. Also, the diffusion path layer 200 may be a low dielectric. The diffusion path layer 200 in one embodiment may be SiO2, but the type of the diffusion path layer 200 is not limited thereto.

[0033] In one embodiment, the diffusion path layer 200 may have a thickness of 20 nm to 50 nm.

[0034] In one embodiment, oxygen (O2) or ozone (O3) can be provided as a reaction gas during the heat treatment. In this case, the diffusion passage layer 200 can serve as a tunnel through which oxygen ions pass.

[0035] In one embodiment, hydrogen (H2) or deuterium (D2) can be provided as a reaction gas during the heat treatment. In this case, the diffusion passage layer 200 can serve as a tunnel through which hydrogen ions pass.

[0036] In other embodiments, a gas containing fluorine (F x ) or nitrogen (N x ) can be provided as a reaction gas during the heat treatment. In this case, the diffusion passage layer 200 can serve as a tunnel through which fluorine ions or nitrogen ions pass.

[0037] The active layer 300 may be arranged to be in direct contact with the source 400 and the drain 500. The active layer 300 can be electrically connected to the source 400 and the drain 500 respectively.

[0038] The active layer 300 may be a channel region that is a movement path of carriers such as holes or electrons. Thus, the active layer 300 can also be referred to as a channel layer.

[0039] When a voltage is applied to the gate 700, in order to prevent the carriers in the active layer 300 from entering the gate 700 through the gate insulating layer 600, the active layer 300 may be made of a thin film having a high dielectric constant.

[0040] In one embodiment, the active layer 300 may be made of a zinc oxide (ZnO)-based oxide semiconductor material.

[0041] In one embodiment, the active layer 300 may further contain at least In, Ga, Sn, or Al in addition to Zn. For example, the active layer 300 may contain at least one of indium-gallium-zinc-oxide (In-Ga-Zn-O, IGZO), indium-tin-zinc-oxide (In-Sn-Zn-O, ISZO), indium-aluminum-zinc-oxide (In-Al-Zn-O, IAZO), tin-aluminum-zinc-oxide (Sn-Al-Zn-O, SAZO), and tin-zinc-oxide (Sn-Zn-O, SZO).

[0042] In one embodiment, the active layer 300 may have a thickness of 8 nm to 12 nm. Preferably, the active layer 300 may have a thickness of 10 nm.

[0043] In one embodiment, the active layer 300 may be formed by a vacuum deposition process or a solution process. For example, the active layer 300 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), or a solution process such as the sol-gel method or the colloidal particle method.

[0044] A passivation layer 310 may be formed on one side of the active layer 300.

[0045] As shown in FIG. 2, when a diffusion barrier layer 800 is formed in a part of the region of the diffusion passage layer 200, a tunnel through which ions contained in the reaction gas can pass may be formed in the diffusion passage layer 200. For example, the region of the diffusion passage layer 200 between the two diffusion barrier layers 800 in FIG. 2 can be defined as a tunnel. The passivation layer 310 may be formed by performing heat treatment in a reaction gas atmosphere with a tunnel formed in the diffusion passage layer 200 for ion movement.

[0046] In one embodiment, the reactive gas may contain at least one component of oxygen, hydrogen, fluorine, and nitrogen.

[0047] In one embodiment, the passivation layer 310 may be formed by heat treatment performed in a high-pressure oxygen atmosphere. In other embodiments, the passivation layer 310 may be formed by heat treatment under a high-pressure hydrogen atmosphere. In still another embodiment, the passivation layer 310 may be formed by performing a secondary heat treatment in a high-pressure hydrogen atmosphere after performing a primary heat treatment in a high-pressure oxygen atmosphere.

[0048] When heat treatment is performed in an oxygen atmosphere, oxygen vacancies existing in the active layer 300, that is, defects, are reduced.

[0049] In one embodiment, when heat treatment is performed in an oxygen atmosphere, the pressure of oxygen may be from 2 atmospheres to 50 atmospheres. In other embodiments, when heat treatment is performed in an oxygen atmosphere, the pressure of oxygen may be from 5 atmospheres to 20 atmospheres.

[0050] In one embodiment, the heat treatment performed in an oxygen atmosphere can be carried out in a temperature range of 100°C to 600°C. In other embodiments, the heat treatment performed in an oxygen atmosphere can be carried out in a temperature range of 200°C to 400°C.

[0051] When heat treatment is performed in a hydrogen atmosphere, oxygen vacancies and charge traps existing in the active layer 300 and / or the passivation layer 310 can be passivated by hydrogen ions. As a result, the charge density of the oxide TFT 10 decreases and the charge mobility improves.

[0052] In one embodiment, when heat treatment is performed in a hydrogen atmosphere, the pressure of hydrogen may be from 2 atmospheres to 50 atmospheres. In other embodiments, when heat treatment is performed in a hydrogen atmosphere, the pressure of hydrogen may be from 5 atmospheres to 20 atmospheres.

[0053] In one embodiment, the heat treatment performed in a hydrogen atmosphere can be carried out in a temperature range of 100°C to 600°C. In other embodiments, the heat treatment performed in a hydrogen atmosphere can be carried out in a temperature range of 200°C to 400°C.

[0054] When the passivation layer 310 is formed, the oxygen vacancies in the active layer 300 can be reduced. When the oxygen vacancies are reduced, the charge mobility increases, so the threshold voltage (Vth) of the oxide TFT 10 can be lowered.

[0055] The passivation layer 310 may be locally formed in a region of the active layer 300. The formation region of the passivation layer 310 may be determined by the arrangement relationship between the diffusion path layer 200 and the diffusion barrier layer 800. For example, the position and area of the passivation layer 310 may vary depending on the ratio occupied by the diffusion barrier layer 800 in the diffusion path layer 200, the position, cross-sectional area, or volume of the diffusion barrier layer 800.

[0056] The active layer 300 can be divided into a source region (S), a gate region (G), and a drain region (D). The source region (S) is the region in contact with the source 400, the gate region (G) is the region in contact with the gate insulating layer 600, and the drain region (D) is the region in contact with the drain 500.

[0057] The crystal structures of the active layer 300 in the source region (S), the drain region (D), and the gate region (G) can be different from each other. The bond of the material constituting the gate region (G) can be relatively more stable than the material constituting the source region (S) or the drain region (D). Also, the closer the source region (S) or the drain region (D) is to the gate region (G), the relatively more stable the bond of the material constituting the source region (S) or the drain region (D) can be.

[0058] When the active layer 300 is formed by the manufacturing method of the thin film transistor 10 according to one embodiment, the blinking ratio (I on / I off ) of the thin film transistor 10 can be higher than that of the prior art.

[0059] The source 400 and the drain 500 may be formed on the active layer 300 respectively. The source 400 and the drain 500 can be in direct contact with the active layer 300 respectively.

[0060] The source 400 and the drain 500 may be arranged separately from each other. The source 400 and the drain 500 may be arranged to face each other in the first direction. The source 400 can act as a source electrode. The drain 500 can act as a drain electrode.

[0061] The source 400 and the drain 500 can electrically connect each end of the active layer 300. Depending on the embodiment, the positions or functions of the source 400 and the drain 500 can be interchanged with each other.

[0062] The gate insulating layer 600 may be arranged between the source 400 and the drain 500. The gate insulating layer 600 can insulate the gate 700 from the active layer 300, the source 400 and the drain 500. The gate insulating layer 600 can prevent parasitic coupling of the substrates 110, 120 by the gate 700. The gate insulating layer 600 can prevent an undesirable conductive channel from being formed in the substrates 110, 120 during conduction of the thin film transistor 10.

[0063] In one embodiment, the gate insulating layer 600 may be made of Al2O3, but the type of material constituting the gate insulating layer 600 is not limited thereto.

[0064] The gate insulating layer 600 may be formed by a vapor deposition process. In one embodiment, the gate insulating layer 600 may have a thickness of 10 nm to 20 nm, preferably 15 nm.

[0065] The gate 700 may be disposed within the gate insulating layer 600. The gate 700 can function as a gate electrode that controls the flow of current passing through the active layer 300. In the gate region (G), the gate 700 can face the active layer 300.

[0066] The gate 700 may be insulated from the source 400, the drain 500, and the active layer 300 by the gate insulating layer 600.

[0067] The gate 700 may be disposed between the source 400 and the drain 500. In one embodiment, the gate 700 may be made of a metallic substance. For example, the gate 700 may include at least one of TiN and W.

[0068] The gate 700 may be formed by a vapor deposition process. The length of the gate 700 may be determined by the thickness of the gate insulating layer 600 and the lengths of the source 400 and the drain 500.

[0069] The diffusion barrier layer 800 can face the source 400 and the drain 500 in the second direction. The diffusion barrier layer 800 may be disposed below the active layer 300. The diffusion barrier layer 800 may be disposed corresponding to the source region (S) and the drain region (D), respectively.

[0070] The diffusion barrier layer 800 may be made of a material with a denser structure and higher hardness than the diffusion channel layer 200. For example, the diffusion barrier layer 800 is silicon nitride (Silicon Nitride, Si x N y) may be composed of this. At this time, 1 ≦ x ≦ 3 and 1 ≦ y ≦ 4 may hold. For example, the diffusion barrier layer 800 may be made of Si3N4. If the diffusion barrier layer 800 is made of Si3N4 with a dense structure and high hardness, ions generated from the reaction gas may not be able to pass through the diffusion barrier layer 800. By arranging the diffusion barrier layer 800 at positions corresponding to the source region (S) and the drain region (D) respectively, it is possible to prevent ions generated from the reaction gas from being implanted into the source 400 and the drain 500.

[0071] As a result, during the heat treatment, ions generated from the reaction gas (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) may not be able to pass through the diffusion barrier layer 800. Depending on the embodiment, some of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may also be able to pass through the diffusion barrier layer 800.

[0072] In one embodiment, when the heat treatment is performed together with the reaction gas, the amount of ions directly implanted into the active layer 300 through the tunnel formed in the diffusion passage layer 200 may be larger than the amount of ions implanted into the active layer 300 through the diffusion barrier layer 800.

[0073] That is, when the heat treatment is performed together with the reaction gas, the diffusion path of the ions contained in the reaction gas, the amount of ions implanted into the active layer 300, and the ion implantation position can be adjusted by the diffusion barrier layer 800.

[0074] FIG. 3 shows the structure of the thin film transistor according to the second embodiment. FIG. 4 is an enlarged view of A shown in FIG. 3. FIG. 5 shows the movement path of ions in the reaction gas by heat treatment during the manufacturing process of the thin film transistor according to the second embodiment.

[0075] The thin-film transistor 10 according to the second embodiment may include substrates 110 and 120, a diffusion path layer 200, a metal oxide active layer 300, a source 400, a drain 500, a gate insulating layer 600, a gate 700, and a diffusion barrier layer 800. The structure of the thin-film transistor 10 according to the second embodiment is the same as that of the thin-film transistor 10 according to the first embodiment except for the diffusion barrier layer 800. Therefore, hereinafter, the description of other components except for the diffusion barrier layer 800 will be omitted.

[0076] The diffusion barrier layer 800 can face the source 400 and the drain 500 in the second direction. The diffusion barrier layer 800 may be disposed below the active layer 300. The diffusion barrier layer 800 may be disposed so as to correspond to the source region (S) and the drain region (D), respectively.

[0077] The diffusion barrier layer 800 may be made of a material having a denser structure and higher hardness than the diffusion path layer 200. As a result, during heat treatment, ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may not be able to pass through the diffusion barrier layer 800. Depending on the embodiment, some of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may also be able to pass through the diffusion barrier layer 800.

[0078] The diffusion barrier layer 800 in the first embodiment described above is composed of a single layer. However, in other embodiments, the diffusion barrier layer 800 may be composed of a plurality of layers. For example, as shown in FIGS. 3 to 5, the diffusion barrier layer 800 according to the second embodiment may include a first diffusion barrier layer 810 and a second diffusion barrier layer 820.

[0079] The first diffusion barrier layer 810 and the second diffusion barrier layer 820 may be made of different substances. Depending on the embodiment, the first diffusion barrier layer 810 and the second diffusion barrier layer 820 may be made of the same kind of substance having different densities from each other.

[0080] The ion permeability of the first diffusion barrier layer 810 and the ion permeability of the second diffusion barrier layer 820 can be different from each other. In one embodiment, the ion permeability of the second diffusion barrier layer 820 may be relatively lower than the ion permeability of the first diffusion barrier layer 810.

[0081] Also, the density of the first diffusion barrier layer 810 and the density of the second diffusion barrier layer 820 can be different from each other. In one embodiment, the density of the second diffusion barrier layer 820 may be relatively higher than the density of the first diffusion barrier layer 810.

[0082] In one embodiment, the second diffusion barrier layer 820 may have a relatively denser structure compared to the first diffusion barrier layer 810. In one embodiment, the hardness of the second diffusion barrier layer 820 may be relatively higher than the hardness of the first diffusion barrier layer 810.

[0083] In one embodiment, the first diffusion barrier layer 810 may be made of a first material. The first material may be Silicon OxiNitride (Si x O y N z ). At this time, 1 ≦ x ≦ 3, 1 ≦ y ≦ 2, and 1 ≦ z ≦ 3 may be satisfied. For example, the first diffusion barrier layer 810 may be SiON or Si2ON2.

[0084] The first diffusion barrier layer 810 may be formed to surround the inner wall of the trench (T) (see FIG. 10). The first diffusion barrier layer 810 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or by a solution process such as the sol-gel method or the colloidal particle method. The first diffusion barrier layer 810 may be formed by low-pressure chemical vapor deposition (LPCVD).

[0085] In one embodiment, the second diffusion barrier layer 820 may be made of a second material. The second material may be silicon nitride (Si x N y ). At this time, 1 ≦ x ≦ 3 and 1 ≦ y ≦ 4 may be satisfied. For example, the second diffusion barrier layer 820 may be Si3N4.

[0086] The second diffusion barrier layer 820 may be formed to fill a trench-shaped space formed inside the first diffusion barrier layer 810. The second diffusion barrier layer 820 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metalorganic chemical vapor deposition (MOCVD), or a solution process such as sol-gel method or colloidal particle method. The second diffusion barrier layer 820 may be formed by low-pressure chemical vapor deposition (LPCVD).

[0087] Referring to FIG. 4, the diffusion barrier layer 800 can be divided into two regions (U a , U b ) in the first direction. The first region (U a ) is a region corresponding to the first diffusion barrier layer 810, and the second region (U b ) is a region corresponding to the second diffusion barrier layer 820 and the first diffusion barrier layer 810.

[0088] The ion permeability of the first region (U a ) and the ion permeability of the second region (U b ) can be different from each other. The density of the first region (U a ) and the density of the second region (U b ) can be different from each other.

[0089] In one embodiment, the diffusion barrier layer 800 may have different density distributions for different regions (U a , U b ). For example, the first region (U a ) in FIG. 4 is made of a single substance, while the second region (U bIn [case 0], two different substances can form a layer structure. More specifically, in the second region (U b ), a first diffusion barrier layer 810 and a second diffusion barrier layer 820 made of a substance with a higher density than the first diffusion barrier layer 810 can form a layer structure. In this case, the ion permeability of the first region (U a ) may be greater than the ion permeability of the second region (U b ).

[0090] In some embodiments, ions may pass through the first region (U a ), and ions may not pass through the second region (U b ).

[0091] FIG. 6 shows the structure of a thin film transistor according to a third embodiment. FIG. 7 is an enlarged view of B shown in FIG. 6. FIG. 8 shows the movement path of ions in the reaction gas during heat treatment in the manufacturing process of the thin film transistor according to the third embodiment.

[0092] The thin film transistor 10 according to the third embodiment may include substrates 110, 120, a diffusion passage layer 200, a metal oxide active layer 300, a source 400, a drain 500, a gate insulating layer 600, a gate 700, and a diffusion barrier layer 800. The structure of the thin film transistor 10 according to the third embodiment is the same as that of the thin film transistor 10 according to the first embodiment or the second embodiment except for the diffusion barrier layer 800. Therefore, the description of other components except for the diffusion barrier layer 800 will be omitted below.

[0093] The diffusion barrier layer 800 can face the source 400 and the drain 500 in the second direction. The diffusion barrier layer 800 may be disposed below the active layer 300. The diffusion barrier layer 800 may be disposed corresponding to the source region (S) and the drain region (D) respectively.

[0094] The diffusion barrier layer 800 may be made of a material with a denser structure and higher hardness than the diffusion path layer 200. As a result, during heat treatment, ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may not be able to pass through the diffusion barrier layer 800. Depending on the embodiment, some of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may also be able to pass through the diffusion barrier layer 800.

[0095] The diffusion barrier layer 800 in the first embodiment described above is composed of a single layer. However, in other embodiments, the diffusion barrier layer 800 may be composed of a plurality of layers. For example, as shown in FIGS. 6 to 8, the diffusion barrier layer 800 according to the third embodiment may include a first diffusion barrier layer 830, a second diffusion barrier layer 840, and a third diffusion barrier layer 850. Depending on the embodiment, the diffusion barrier layer 800 may be composed of four or more layers.

[0096] The first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may be made of different substances. Depending on the embodiment, the first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may be made of the same type of substance with different densities.

[0097] The ion permeability of the first diffusion barrier layer 830, the ion permeability of the second diffusion barrier layer 840, and the ion permeability of the third diffusion barrier layer 850 may be different from each other. For example, the ion permeability of the third diffusion barrier layer 850 may be relatively lower than the ion permeability of the first diffusion barrier layer 830 and the ion permeability of the second diffusion barrier layer 840, and the ion permeability of the second diffusion barrier layer 820 may be relatively lower than the ion permeability of the first diffusion barrier layer 810.

[0098] Further, the density of the first diffusion barrier layer 830, the density of the second diffusion barrier layer 840, and the density of the third diffusion barrier layer 850 may be different from each other. For example, the density of the third diffusion barrier layer 850 may be relatively higher than the density of the first diffusion barrier layer 830 and the density of the second diffusion barrier layer 840, and the density of the second diffusion barrier layer 840 may be relatively higher than the density of the first diffusion barrier layer 830.

[0099] In one embodiment, the third diffusion barrier layer 850 may have a relatively dense structure compared to the first diffusion barrier layer 830 and the second diffusion barrier layer 840, and the second diffusion barrier layer 840 may have a relatively dense structure compared to the first diffusion barrier layer 830.

[0100] In one embodiment, the hardness of the third diffusion barrier layer 850 may be relatively higher than the hardness of the first diffusion barrier layer 830 and the second diffusion barrier layer 840, and the hardness of the second diffusion barrier layer 840 may be relatively higher than the hardness of the first diffusion barrier layer 830.

[0101] In one embodiment, the first diffusion barrier layer 830 may be made of a first material. The first material may be Silicon OxiNitride (Si x O y N z ). At this time, 1 ≦ x ≦ 3, 1 ≦ y ≦ 2, and 1 ≦ z ≦ 3 may also be satisfied. For example, the first diffusion barrier layer 810 may be SiON or Si2ON2.

[0102] The first diffusion barrier layer 830 may be formed to surround the inner wall of a trench (T) (see FIG. 10). The first diffusion barrier layer 830 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or by a solution process such as the sol-gel method or the colloidal particle method. The first diffusion barrier layer 830 may be formed by low-pressure chemical vapor deposition (LPCVD).

[0103] In one embodiment, the second diffusion barrier layer 840 may be made of a second material. The second material may be silicon nitride (Si x N y ). At this time, 1 ≦ x ≦ 3 and 1 ≦ y ≦ 4 may also be satisfied. For example, the second diffusion barrier layer 840 may be Si3N4.

[0104] The second diffusion barrier layer 840 may be formed to surround the inner wall of the first diffusion barrier layer 830 having a trench shape. The second diffusion barrier layer 840 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or a solution process such as a sol-gel method or a colloidal particle method. The second diffusion barrier layer 840 may be formed by low-pressure chemical vapor deposition (LPCVD).

[0105] In one embodiment, the third diffusion barrier layer 850 may be made of a third material. The third material may be silicon nitride (Si x N y ). At this time, 1 ≦ x ≦ 2 and 1 ≦ y ≦ 2 may also be satisfied. For example, the third diffusion barrier layer 850 may be SiN or Si2N.

[0106] The third diffusion barrier layer 850 may be formed to fill the trench-shaped space formed inside the second diffusion barrier layer 840. The third diffusion barrier layer 850 may be formed by a deposition process such as physical vapor deposition (PVD) like sputtering, atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or a solution process such as a sol-gel method or a colloidal particle method. The third diffusion barrier layer 850 may be formed by low-pressure chemical vapor deposition (LPCVD).

[0107] Referring to FIG. 7, the diffusion barrier layer 800 can be divided into three regions (U a , U b , U c ) in the first direction. The first region (U a ) is the region corresponding to the first diffusion barrier layer 830, the second region (U b ) is the region corresponding to the second diffusion barrier layer 840 and the first diffusion barrier layer 830, and the third region (U c ) is the region corresponding to the third diffusion barrier layer 850, the second diffusion barrier layer 840 and the first diffusion barrier layer 830.

[0108] The ion transmittance of the first region (U a ), the ion transmittance of the second region (U b ), and the ion transmittance of the third region (U c ) can be different from each other. The density of the first region (U a ), the density of the second region (U b ), and the density of the third region (U c ) can be different from each other.

[0109] In one embodiment, the diffusion barrier layer 800 may have different density distributions for different regions (U a , U b , U c ). For example, the first region (U a ) in FIG. 4 is made of a single substance, but in the second region (U b ), two different substances can form layers, and in the third region (U c ), three different substances can form layers. More specifically, in the second region (U b ), the second diffusion barrier layer 840 made of a substance with a density greater than that of the first diffusion barrier layer 830 and the first diffusion barrier layer 830 can form layers, and in the third region (U c ), the first diffusion barrier layer 830, the second diffusion barrier layer 840 made of a substance with a density greater than that of the first diffusion barrier layer 830, and the third diffusion barrier layer 850 made of a substance with a density greater than that of the second diffusion barrier layer 840 can form layers. In this case, the first region (U a) has an ion transmittance in the second region (U b ) and the ion transmittance of the third region (U c ) is greater, and the ion transmittance of the second region (U b ) may be greater than the ion transmittance of the third region (U c ).

[0110] Depending on the embodiment, ions may pass through the first region (U a ), and may not pass through the second region (U b ) or the third region (U c ). In other embodiments, ions may pass through the first region (U a ) and the second region (U b ), and may not pass through the third region (U c ).

[0111] Figures 9 to 15 show the manufacturing process of a thin film transistor according to the third embodiment. Figure 16 is a flowchart showing a manufacturing method of a thin film transistor according to an embodiment.

[0112] First, referring to Figures 9 and 16, a diffusion path layer 200 is formed on substrates 110, 120 (S10). For example, the diffusion path layer 200 may be made of an oxide such as SiO2 and may be formed by vapor deposition.

[0113] Next, referring to Figures 10 and 16, one or more trenches (T) are formed by selectively removing an arbitrary region of the diffusion path layer 200 (S20). For example, the trenches (T) may be formed by selective etching.

[0114] Next, referring to FIGS. 11 and 16, a diffusion barrier layer 800 is formed inside a trench (T) formed in the diffusion path layer 200 (S30). FIG. 11 shows a diffusion barrier layer 800 including a first diffusion barrier layer 830, a second diffusion barrier layer 840, and a third diffusion barrier layer 850 according to the third embodiment. In this case, the first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may be sequentially formed inside the trench (T).

[0115] In the step of forming the diffusion barrier layer (S30), when the diffusion barrier layer 800 according to the second embodiment is formed, the first diffusion barrier layer 810 and the second diffusion barrier layer 820 may be sequentially formed inside the trench (T). In the step of forming the diffusion barrier layer (S30), when the diffusion barrier layer 800 according to the first embodiment is formed, the diffusion barrier layer 800 may be formed by filling a single substance inside the trench (T).

[0116] Next, referring to FIGS. 12 and 16, an active layer 300 is formed on the diffusion path layer 200 and the diffusion barrier layer 800 (S40). For example, the active layer 300 may be formed by a vacuum deposition process or a solution process.

[0117] Next, referring to FIGS. 13 and 16, a source 400 may be formed in a source region (S) on the active layer 300, and a drain 500 may be formed in a drain region (D) on the active layer 300 (S50). The formation order of the source 400 and the drain 500 may vary depending on the embodiment. On one side of the source 400 and the drain 500, substances similar to the diffusion path layer 200 (for example, SiO2) may be disposed respectively.

[0118] Also, a gate insulating layer 600 is formed in a gate region (G) on the active layer 300 (S60). The gate insulating layer 600 may be formed between the source 400 and the drain 500. The source 400 and the drain 500 may be arranged to be aligned with the gate insulating layer 600 in a first direction.

[0119] Further, a gate 700 is formed inside the gate insulating layer 600 (S70).

[0120] The source and drain formation step (S50), the gate insulating layer formation step (S60), and the gate formation step (S70) can be mutually replaced.

[0121] Next, referring to FIG. 16, heat treatment can be performed on the thin film transistor 10 (S80).

[0122] In one embodiment, the heat treatment step (S80) may include a first heat treatment step performed in an oxygen atmosphere and a second heat treatment step performed in a hydrogen atmosphere.

[0123] For example, as shown in FIG. 14, the first heat treatment step for the thin film transistor 10 may be performed first in an atmosphere of a reaction gas containing oxygen (e.g., oxygen (O2) or ozone (O3)). When the first heat treatment is performed, oxygen ions generated from the reaction gas can be injected into the thin film transistor 10 through the diffusion path layer 200.

[0124] The first heat treatment step can be performed in an atmosphere of 100% concentration of oxygen (O2) or ozone (O3). However, the concentration of the reaction gas containing oxygen may vary depending on the embodiment. For example, the first heat treatment step can also be performed using a reaction gas with a concentration of 50% or more or 100% concentration.

[0125] The first heat treatment step can be performed in a pressure range of 2 atmospheres to 50 atmospheres, preferably in a pressure range of 5 atmospheres to 20 atmospheres. The first heat treatment step can be performed under any condition or environment of wet, dry, or supercritical. The first heat treatment step can be performed in a temperature range of 100°C to 600°C, preferably in a temperature range of 200°C to 400°C.

[0126] When the first heat treatment is performed, oxygen ions can be injected into the active layer 300 through the tunnels formed in the diffusion passage layer 200. However, relatively few oxygen ions can pass through via the diffusion barrier layer 800. Depending on the embodiment, oxygen ions may not be able to pass through the diffusion barrier layer 800. Therefore, a relatively large amount of oxygen ions can be injected into the active layer 300 corresponding to the gate region (G), and a relatively small amount of oxygen ions can be injected into the active layer 300 corresponding to the source region (S) or the drain region (D).

[0127] As a result, in the active layer 300 corresponding to the gate region (G), relatively more oxygen vacancies can be reduced compared to the active layer 300 corresponding to the source region (S) or the drain region (D).

[0128] On the other hand, when the diffusion barrier layer 800 is composed of a plurality of layers and is divided into a number of regions as in the second or third embodiment, the oxygen ion transmittance can be different for each region. For example, as in the third embodiment, when the diffusion barrier layer 800 is divided into a first region (U a ), a second region (U b ), and a third region (U c ), the oxygen ion transmittance can decrease in the order of the first region (U a ), the second region (U b ), and the third region (U c ). As a result, the amount of reduction in oxygen vacancies can decrease from the first region (U a ) to the third region (U c ).

[0129] After the first heat treatment, a second heat treatment may be performed. For example, as shown in FIG. 15, a second heat treatment step for the thin film transistor 10 may be performed in an atmosphere of a reaction gas containing hydrogen (e.g., hydrogen (H2) or deuterium (D2)). When the second heat treatment is performed, hydrogen ions generated from the reaction gas can be injected into the thin film transistor 10 through the diffusion passage layer 200.

[0130] The second heat treatment stage can be carried out in an atmosphere of hydrogen (H2) or deuterium (D2) with a concentration of 3% to 10%, preferably 4%. However, the concentration of the reaction gas containing hydrogen may vary depending on the examples. For example, the second heat treatment stage can also be carried out using a reaction gas with a concentration of 50% or more or 100% concentration.

[0131] The second heat treatment stage can be carried out in a pressure range of 2 atmospheres to 50 atmospheres, preferably in a pressure range of 5 atmospheres to 20 atmospheres. The second heat treatment stage can be carried out under any condition or environment of wet, dry, or supercritical. The second heat treatment stage can be carried out in a temperature range of 100 °C to 600 °C, preferably in a temperature range of 200 °C to 400 °C.

[0132] When the second heat treatment is carried out, hydrogen ions can be injected into the active layer 300 through the tunnels formed in the diffusion passage layer 200. However, a relatively small amount of hydrogen ions can pass through via the diffusion barrier layer 800. Depending on the example, hydrogen ions may not be able to pass through the diffusion barrier layer 800. Therefore, a relatively large amount of hydrogen ions are injected into the active layer 300 corresponding to the gate region (G), and a relatively small amount of hydrogen ions can be injected into the active layer 300 corresponding to the source region (S) or the drain region (D).

[0133] On the other hand, when the diffusion barrier layer 800 is composed of multiple layers and divided into a number of regions, like in the second example or the third example, the hydrogen ion permeability can be different for each region. For example, as in the third example, when the diffusion barrier layer 800 is divided into the first region (U a ), the second region (U b ), and the third region (U c ), the hydrogen ion permeability can decrease in the order of the first region (U a ), the second region (U b ), and the third region (U c ).

[0134] A passivation layer 310 is formed in the active layer 300 corresponding to the gate region (G) by the second heat treatment. As a result, oxygen vacancies and charge traps present in the active layer 300 and / or the passivation layer 310 can be passivated by hydrogen ions. Thereby, the charge density of the oxide TFT 10 decreases and the charge mobility is improved.

[0135] Depending on the embodiment, only one of the first heat treatment step and the second heat treatment step described above can be selectively performed in the heat treatment step (S80).

[0136] FIG. 17 shows the drive current (I on ) and the off-current (I off ) of a thin film transistor manufactured according to the first embodiment and a thin film transistor from which heat treatment has been removed during the manufacturing process.

[0137] In FIG. 17, HPA is data showing the drive current (I on ) and the off-current (I off ) of a thin film transistor manufactured according to the first embodiment described above, and NHPA is the drive current (I on ) and the off-current (I off ) of a thin film transistor in which the heat treatment step (S80) described above has not been performed during the manufacturing process.

[0138] As shown in FIG. 17, when the heat treatment step (S80) is performed according to the first embodiment described above during the manufacturing process of the thin film transistor, the blinking ratio (I on / I off ) of the thin film transistor is represented as higher than when the heat treatment step (S80) is not performed.

[0139] Also, as shown in FIG. 17, when the heat treatment step (S80) is not performed during the manufacturing process of the thin film transistor, when the off-current (I off ) increases, a phenomenon occurs in which the drive current (I on ) greatly decreases. However, when the heat treatment step (S80) is performed according to the first embodiment described above during the manufacturing process of the thin film transistor, the off-current (I off) when it increases, the phenomenon that the drive current (I on ) becomes low is improved.

[0140] As described above, the embodiments have been described with reference to the exemplary drawings. However, the scope of the invention is not limited by the embodiments and drawings disclosed herein, and various modifications can be made by those of ordinary skill in the art. In addition, even if the effects due to the configuration of the invention are not explicitly described in the description of the embodiments, the effects predictable by the configuration should also be recognized.

Claims

1. A substrate, a diffusion path layer disposed on the substrate, an active layer disposed on the diffusion path layer, a source and a drain disposed on the active layer, a gate insulating layer disposed between the source and the drain, a gate disposed on the gate insulating layer, a diffusion barrier layer formed at positions corresponding to the source and the drain in the diffusion path layer, comprising a thin film transistor.

2. The diffusion barrier layer is made of a single substance, The thin film transistor according to Claim 1.

3. The diffusion barrier layer is composed of a plurality of layers made of a plurality of substances having different ion permeation rates from each other, The thin film transistor according to Claim 1.

4. The diffusion barrier layer is divided into a plurality of regions having different layer positions from each other, The thin film transistor according to Claim 1.

5. The ion permeation rate of each region is different from each other, The thin film transistor according to Claim 4.

6. The ion permeation rate of the diffusion barrier layer and the ion permeation rate of the diffusion path layer are different from each other, The thin film transistor according to Claim 1.

7. Further comprising a passivation layer formed in at least a part of the active layer region, The thin film transistor according to Claim 1.

8. A step of forming a diffusion path layer on a substrate, A step of forming one or more trenches in the diffusion path layer, A step of forming a diffusion barrier layer inside the trench, A step of forming an active layer on the diffusion path layer and the diffusion barrier layer, A step of forming a source and a drain on the active layer, A step of forming a gate insulating layer between the source and the drain, A step of forming a gate on the gate insulating layer, A step of performing heat treatment, comprising A method for manufacturing a thin film transistor.

9. The diffusion barrier layer is made of a single substance, The method for manufacturing a thin film transistor according to Claim 8.

10. The diffusion barrier layer is composed of a plurality of layers made of a plurality of substances having different ion permeation rates from each other, The method for manufacturing a thin film transistor according to Claim 8.

11. The diffusion barrier layer is divided into a plurality of regions having different layer positions from each other, The method for manufacturing a thin film transistor according to Claim 8.

12. The ion permeation rate of each region is different from each other, The method for manufacturing a thin film transistor according to Claim 11.

13. The step of performing the heat treatment is A step of performing a first heat treatment in an oxygen atmosphere, The step in which the second heat treatment is performed in a hydrogen atmosphere, and including The method for manufacturing a thin film transistor according to claim 8.

14. The first heat treatment or the second heat treatment is performed in a pressure range of 2 atmospheres to 50 atmospheres, The method for manufacturing a thin film transistor according to claim 13.

15. The first heat treatment or the second heat treatment is performed in a temperature range of 100°C to 600°C, The method for manufacturing a thin film transistor according to claim 13.

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