General Power FET Driver IC Architecture

Abstract

A gate driver circuit integrating a synchronous bootstrap circuit within an insulating well of an integrated circuit, wherein a synchronous bootstrap capacitor connected thereto (and to a corresponding switch node of a power converter) can be in a floating state with respect to the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrap capacitor is used to charge a synchronous bootstrap capacitor of another (higher-level) synchronous bootstrap circuit in a separate insulating well connected to a different switch node. As a result, all supply voltages for synchronous bootstrap circuits in different insulating wells can be supplied from a single ground-referenced power supply V dd from.

Description

Technical Field

[0001] The present disclosure relates to a power FET driver.

Background Art

[0002] Half-bridge integrated circuits generally use a high-side FET gate driver that implements a bootstrap circuit to supply a boosted voltage higher than the supply voltage to the gate terminal of the high-side field effect transistor (FET). In particular, the bootstrap circuit utilizes a bootstrap capacitor that charges while the high-side FET is off and the low-side FET of the half-bridge is on (when the SW terminal is shorted to ground). When the low-side FET is switched off and the high-side FET is switched on, the voltage stored in the bootstrap capacitor is applied to the gate terminal of the high-side FET. However, this architecture is not suitable for some power converter topologies, such as multi-level converters, because the upper-level SW node in the multi-level converter does not switch to ground. If the SW node does not conduct the low-side electrode of the bootstrap capacitor to ground, the bootstrap capacitor is not fully charged, and the gate terminal of the high-side FET does not reach a voltage higher than the supply voltage to keep the high-side FET on for the half-bridge circuit to function properly. Therefore, a power FET driver that can be used in multi-level power converter topologies is desired.

[0003] FIG. 1 is a conventional half-bridge integrated circuit (IC) design using a synchronous bootstrap high-side gate driver circuit. The half-bridge IC design 100 of FIG. 1 includes a high-side FET 102 and a low-side FET 112 that are controlled to supply power switched at the SW node to a load 116 connected to an inductor 118 and a capacitor 120 in a buck converter topology.

[0004] The high-side FET 102 is driven by the high-side gate driver 104, and both are formed within an isolation well 106. The high-side gate driver 104 receives a high-side input signal from a level shifter 108 controlled by a logic converter and a power-on reset (POR) circuit 110, and the logic converter and the power-on reset (POR) circuit 110 are controlled by a high-side input control signal "HSin" and a low-side input control signal "LSin". The low-side FET 112 is driven by a low-side gate driver 114 that receives a control signal from the logic converter and the POR circuit 110 based on the high-side signal "HSin" and the low-side signal "LSin".

[0005] In the half-bridge IC circuit of FIG. 1, the supply voltage for the high-side circuit elements including the level shifter 108 and the high-side gate driver 104 is supplied by a synchronous bootstrap circuit including a bootstrap capacitor 122 and a bootstrap diode 124. When the high-side input signal "HSin" is at logic level 0 and the high-side FET 102 is turned off, and the low-side input signal "LSin" is at logic level 1 and the low-side FET 112 is turned on, the bootstrap capacitor 122 is charged by the supply voltage V dd through the diode 124. Accordingly, the SW node is switched to ground, the bootstrap capacitor 122 is charged through the diode 124, and a voltage obtained by subtracting the diode voltage drop across the diode from the voltage V dd is ensured. This generates V ddF , and V ddF is a voltage obtained by subtracting the diode voltage drop from V dd and is higher than the voltage at the SW node. When "HSin" is at logic level 1, V ddF ensures that the gate-to-source voltage of the high-side FET 102 is high enough to turn on the transistor.

[0006] The half-bridge IC design 100 of FIG. 1 is not suitable for all power converter topologies. In particular, the half-bridge design 100 cannot be used in a multilevel power converter because the SW node does not always switch to ground in such topologies. As a result, the synchronous bootstrap capacitor 122 cannot be fully recharged by V dd and the half-bridge IC design 100 cannot function properly. Additionally, charging the synchronous bootstrap capacitor 122 through the diode 124 reduces V ddF due to the voltage drop associated with the diode 124. To address this latter problem, in the half-bridge IC design of FIG. 2, the diode 124 (FIG. 1) is replaced with a synchronous bootstrap FET 240 driven by a synchronous bootstrap driver 242 controlled by a logic converter and POR circuit 210.

[0007] In the synchronous bootstrap circuit of FIG. 2, the voltage drop associated with the diode 124 of FIG. 1 is removed as V ddF -V SW ≒V dd . However, like the circuit of FIG. 1, the synchronous bootstrap driver 242 must have an output logic 1 voltage higher than V dd to turn on the high-side FET 202. Thus, like the half-bridge IC design 100 shown in FIG. 1, the half-bridge IC design 200 shown in FIG. 2 cannot be implemented in a multilevel power converter.

[0008] FIG. 3 is a circuit diagram showing a synchronous bootstrap driver 300 suitable for GaN technology. The synchronous bootstrap driver 300 disclosed in U.S. Patent No. 9,667,245 includes an FET 304 and a capacitor 306. When the low-side gate driver 314 is at logic level 0 (0V), the capacitor 306 is charged to approximately V dd -V th where V this the threshold voltage of FET304. When the low-side gate driver 314 is at the logic level 1 (V dd ), the synchronous bootstrap voltage V SB at the gate of the synchronous bootstrap FET 320 is about 2V dd -V th . Therefore, the gate of the synchronous bootstrap FET 320 is turned on by the gate-source voltage of V dd -V th . However, since the threshold voltage V th of the synchronous bootstrap FET 310 can vary by a relatively large amount, the gate-source voltage of V dd -V th may be insufficient to turn on the synchronous bootstrap FET 320.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0010] Therefore, it is desirable to provide a power FET driver that overcomes the disadvantages of the prior art described above and can be universally implemented without the above-mentioned disadvantages. In particular, it is desirable to provide a power FET driver IC that can be universally implemented for driving a power FET in any power FET driver topology.

Means for Solving the Problems

[0011] The present invention achieves the object described above by overcoming the disadvantages and providing a power FET driver architecture that can be universally implemented in any power FET driver topology.

[0012] More specifically, the present invention described herein is a gate driver circuit that integrates a synchronous bootstrap circuit within an isolation well of an integrated circuit, whereby a synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of a power converter) can be in a floating state with respect to the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrap capacitor can be used to charge the synchronous bootstrap capacitor of another (higher-level) synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground referenced supply V dd from. Thus, the present invention can be used to implement various power converter topologies including multilevel converters.

[0013] Additional features and advantages of the present invention will be described in the following specification, will become somewhat apparent from the specification, or may be learned by practice of the present invention. The features and advantages of the present invention can be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by practice of the invention as described hereinafter.

[0014] The advantages and features of the present invention will become apparent when the following description of the preferred embodiments of the present invention is read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015]

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DETAILED DESCRIPTION OF THE INVENTION

[0016] It should be understood that the drawings and descriptions of the present invention may be simplified to show only appropriate elements for a clear understanding of this embodiment. Those skilled in the art will recognize that other elements may be desirable and / or necessary for implementing this embodiment. It should also be understood that the drawings included in this specification provide only a schematic representation of the presently preferred embodiments of the present invention. Next, drawings in which similar structures are given similar reference numerals are referred to.

[0017] Figure 4 shows the basic architecture of the universal power FET driver IC of the present invention. The universal power FET driver IC 400 includes a power FET gate driver circuit 401 of the present invention provided in an insulating well and controlled by a logic converter and a power-on reset circuit 414, and a level shifter 412 (whose receiver is disposed in the insulating well). The insulating well is formed from a known process and provides electrical insulation from other semiconductor circuit elements within the IC. Circuit elements of the gate driver of the present invention, namely, a synchronous bootstrap FET 402, a power FET 404, a gate driver 406 for driving the power FET 404, a synchronous bootstrap gate driver 408 for driving the synchronous bootstrap FET 402, a NAND gate 410, and the receiver of the level shifter 412 are all integrated within a single insulating well. In a preferred embodiment of the present invention, the synchronous bootstrap gate driver of the present invention is implemented with GaN technology.

[0018] In the operation of the power FET driver IC of the present invention, the logic converter / power-on reset circuit 414 receives an input control signal "in" and creates a corresponding control signal to the level shifter 412. The level shifter 412 creates either a level-shifted logic 0 output or a level-shifted logic 1 output based on the input control signal "in". The logic 0 output or the logic 1 output of the level shifter 412 is supplied as an input to the logic gate 410 and the gate driver 406.

[0019] When the level shifter 412 creates a logic 1, the FET 404 is turned on and V H is shorted to V L In the basic circuit shown in FIG. 4, V L is grounded, and thus by turning on the FET 404, V His connected to ground. Both inputs of NAND gate 410 also receive a logic 1, whereby NAND gate 410 creates a logic 0 which is an input to synchronous bootstrap gate driver 408, whereby gate driver 408 creates a logic 1 for the gate of FET402. As a result, FET402 is turned on and synchronous bootstrap capacitor C SB is charged from supply voltage V ddF .

[0020] When level shifter 412 creates a logic 0, FET404 is turned off and V H is disconnected from V L . Both inputs of NAND gate 410 also receive a logic 0, whereby the NAND gate creates a logic 1 which is an input to synchronous bootstrap gate driver 408, which creates a logic 0 for the gate of FET402. As a result, FET402 is turned off and the voltage V SB stored on synchronous bootstrap capacitor C ddF can be used to power a similar gate drive circuit in a different isolation well as shown in FIGS. 5 and 7. This feature of the circuit of FIG. 4 enables this circuit to be commonly used in architectures suitable for implementing power converters having many different topologies including multilevel converters.

[0021] NAND gate 410 is provided to cause the turn-off of synchronous bootstrap gate driver 408 to precede the turn-off of power FET404 and to delay the turn-on of synchronous bootstrap gate driver 408 until after power FET404 is turned on. Thereby, the NAND gate prevents overcharging of the synchronous bootstrap capacitor during the dead time of the power converter.

[0022] FIG. 5 shows synchronous bootstrap capacitor C SB1This is an implementation of a half-bridge buck converter using two universal power FET driver integrated circuits of FIG. 4. The low-side power FET driver integrated circuit 500a (bottom) includes a low-side power FET 504a and receives a low-side input control signal "LSin". The high-side power FET driver integrated circuit (top) includes a high-side power FET 504b and receives a high-side input control signal "HSin". A low-side synchronous gate driver circuit 501a including a synchronous bootstrap FET 502a, a synchronous bootstrap gate driver 508a, and a power FET 504a is provided in an isolation well 1 and is powered by a supply voltage V dd . A high-side synchronous gate driver circuit 501b including a synchronous bootstrap FET 502b, a synchronous bootstrap gate driver 508b, and a power FET 504b is provided in an isolation well 2 and is powered by the voltage on the synchronous bootstrap capacitor rather than V dd V F1 . Therefore, the voltage stored on the synchronous bootstrap capacitor in isolation well 2 is charged by the voltage stored on the synchronous bootstrap capacitor in isolation well 1.

[0023] FIG. 6 is a timing diagram for the power converter of FIG. 5. At condition c1, when a logic 1 is supplied as the low-side input signal "LSin" and a logic 0 is supplied as the high-side input signal "HSin", both the synchronous bootstrap FET 502a and the low-side power FET 504a turn on, and the synchronous bootstrap capacitor C SB1 is charged up to V dd .

[0024] At condition c2, the control input switches such that a logic 0 is supplied as the low-side input signal "LSin" and a logic 1 is supplied as the high-side input signal "HSin". Both the low-side synchronous bootstrap FET 502a and the low-side power FET 504a turn off, but both the high-side synchronous bootstrap FET 502b and the high-side power FET 504b turn on, and Vin Short-circuit it to the switch node SW to drive the load. The bootstrap capacitor C SB1 The voltage across, i.e., V F1 is the input voltage V in and the stored supply voltage V that supplies power to the gate driver circuit 506b within the insulating well 2, including an additional combination with dd

[0025] Condition c3 is substantially the same as condition c1, and the synchronous bootstrap capacitor C SB1 is charged again by V dd and this cycle repeats.

[0026] FIG. 7 shows a three-level buck power converter 700 including four of the power FET driver circuits 400 of FIG. 4 and three synchronous bootstrap capacitors C SB1 , C SB2 and C SB3 and capacitor C M FIG. 7 shows four power FET driver circuits 400 to form a three-level converter, but any plurality of N of the power FET driver circuits 400 shown in FIG. 4 may be implemented as shown in FIG. 7 to form an (N - 1)-level converter.

[0027] As shown in FIG. 7, the voltages across the synchronous bootstrap capacitors C SB1 , C SB2 and C SB3 are respectively arranged in the insulating wells 2, 3, and 4 and supply supply voltages to the synchronous gate driver circuits 701b, 701c, and 701d that drive the corresponding power FETs 704b, 704c, and 704d. Capacitor C M connected on one side to the drain of FET 704a and the source of FET 704b and on the other side to the drain of FET 704c and the source of FET 704d supplies a three-level voltage level of approximately V in / 2 within the three-level power converter.

[0028] ​Figures 8A and 8B are timing diagrams showing the charging of the three bootstrap capacitors C SB1 , C SB2 and C SB3 in the three-level converter of FIG. 7 for a duty cycle of less than 50% (FIG. 8A) and a duty cycle of greater than 50% (FIG. 8B), the respective charging voltages V F1 , V F2 and V F3 and the switch node voltages SW1, SW2, and SW3.

[0029] In FIG. 8A, for the conditions in the first column, both in1 and in2 are on. Therefore, the outputs of drivers 708a and 708b are logic 1. As a result, C SB1 is charged by V dd through FET702a, and C SB2 is charged by V F1 through FET702b. For the conditions in the second column, only in2 is on. Therefore, only the output of driver 708b is logic 1. As a result, C SB2 is charged by V F1 through FET702b. For the conditions in the third column, similar to the conditions for the first column, both in1 and in2 are on. Therefore, the outputs of drivers 708a and 708b are logic 1. As a result, C SB1 is charged by V dd through FET702a, and C SB2 is charged by V F1 through FET702b. For the conditions in the fourth column, in1 and in3 are on. Therefore, the outputs of drivers 708a and 708c are logic 1. As a result, C SB1 is charged by V dd through FET702a, and C SB3 is charged by V F2 through FET702c. The conditions in the fifth column are substantially the same as the conditions in the first column, and the cycle repeats.

[0030] In FIG. 8B, in the case of the condition in the first column, in3 is on. Therefore, the output of driver 708c is logic 1. As a result, C SB3 is charged by V F2 through FET702c. In the case of the condition in the second column, in2 is on. Therefore, the output of driver 708b is logic 1. As a result, C SB2 is charged by V F1 through FET702b. In the case of the condition in the second column, similar to the condition in the first column, in3 is on. Therefore, the output of driver 708c is logic 1. As a result, C SB3 is charged by V F2 through FET702c. In the case of the condition in the fourth column, in1 and in3 are on. Therefore, the outputs of drivers 708a and 708c are logic 1. As a result, C SB1 is charged by V dd through FET702a, and C SB3 is charged by V F2 through FET702c. The condition in the fifth column is substantially the same as the condition in the first column, and the cycle repeats.

[0031] FIG. 9 shows a cascaded active bootstrap topology 900 for a synchronous bootstrap driver circuit of the universal power FET driver of the present invention. The cascaded active bootstrap gate driver circuit 901 that drives the gate of the bootstrap FET 902 through the capacitor C D can be used for the synchronous bootstrap gate driver 408 (in FIG. 4), the synchronous bootstrap gate drivers 508a and 508b (in FIG. 5), and the synchronous bootstrap gate drivers 708a, 708b, 708c, and 708d (in FIG. 7).

[0032] The active bootstrap gate driver topology of FIG. 9 combines the active bootstrap gate driver circuit disclosed in U.S. Patent Application Publication No. 2023 / 0179203 and the cascaded bootstrap gate driver circuit disclosed in U.S. Patent No. 10,790,811. When the input "in" is a logic 1 equal to V ddF -V L , capacitor C D charges the gates of FETs 903a through 903n to approximately V ddF -V L through FET 903. Note that capacitor C1 recharges FET 903 to approximately V ddF -V L when the input "in" is logic 0, and voltage V ddF -V L becomes approximately equal to 2·(V D1 -V ddF -V L ).

[0033] When the input "in" is logic 0, the output of the cascaded bootstrap gate driver at the drain of FET 907a is a logic 1 equal to approximately V ddF -V L , and gate voltage V SB is approximately 2·(V ddF -V L ). Thus, the gate-source voltage V GS of synchronous bootstrap FET 902 is approximately V ddF -V L . Since the difference between V ddF and V L is equivalent to V dd , synchronous bootstrap FET 902 can drive V F to approximately V ddF .

[0034] FIG. 10 is similar to the synchronous bootstrap driver circuit 900 of FIG. 9, but combines bootstrap capacitors C B1 and C D into a single bootstrap capacitor CMERGE shows a synchronous bootstrap driver circuit 1000 that is modified to integrate the FETs 903 and 903a into a single FET 1003. The integration of the above capacitors and FETs in the circuit of FIG. 9 is possible. Because D1 and V SB are both driven by the same cascade of bootstrap driver outputs through the bootstrap capacitors C B1 and C D , V D1 and V SB are approximately the same. As a result, the synchronous bootstrap FET 1002 can be directly driven by the cascade of bootstrap drivers shown.

[0035] FIG. 11 shows a modified form of the integrated synchronous bootstrap driver circuit of FIG. 10 having a wide switching range. The integrated synchronous bootstrap driver circuit 1100 of FIG. 11 is similar to the synchronous bootstrap driver circuit 1000 of FIG. 10, except that the gate of the synchronous bootstrap FET 1102 is connected to the gate of the FET 1104.

[0036] In some cases, the switch node SW n may swing several volts below V L during the dead time period of the power converter. In such cases, the synchronous bootstrap FET 1102 may need to be shut down before the dead time period begins, and the gate terminal voltage V SB should also have a turn-off voltage close to V SBn to prevent overcharging of the synchronous bootstrap capacitor C L during the dead time period. By connecting the gate of the synchronous bootstrap FET 1102 to the gate of the FET 1104, the voltage swing with respect to the gate terminal voltage V SB is about 2·(V ddF - V L) and becomes between 0V (V L with respect to). Therefore, the possibility of turning on the synchronous bootstrap FET 1102 during the dead time period is minimized by the circuit of FIG. 11.

[0037] In summary, the universal power FET driver IC of the present invention integrates a synchronous bootstrap circuit within the isolation well of the driver IC. The architecture of the present invention enables the synchronous bootstrap capacitor connected to the synchronous bootstrap circuit (and to the corresponding switch node of the power converter) to be in a floating state with respect to the corresponding switch node. Due to this feature, the voltage on one synchronous bootstrap capacitor can be used to charge the synchronous bootstrap capacitors of another synchronous bootstrap circuit in a separate isolation well connected to a different switch node. As a result, the supply voltages for the synchronous bootstrap circuits in different isolation wells can all be supplied from a single ground-referenced power source. This enables the universal power FET driver IC architecture of the present invention to be used to implement various power converter topologies including multilevel converters, where not all of the switch nodes of the power converter are necessarily switched to ground.

[0038] To reduce the voltage drop of the supply voltage for the synchronous gate driver circuit within the isolation well, a cascaded active bootstrap driver topology can be used to drive the synchronous bootstrap FET.

[0039] The synchronous bootstrap driver of the present invention is particularly suitable for implementation in GaN technology using GaN FETs.

[0040] The present invention can be embodied in other specific forms without departing from its main idea or essential characteristics. The embodiments described are to be considered in all respects only as illustrative and not restrictive. Therefore, the scope of the present invention is indicated not by the foregoing description but by the appended claims. All modifications that come within the meaning and range of equivalents of the claims are to be embraced within their scope.

Explanation of Signs

[0041] 100 Half - bridge IC design 102 High - side FET 104 High - side gate driver 106 Insulated well 108 Level shifter 110 Logic converter and power - on reset (POR) circuit 112 Low - side FET 114 Low - side gate driver 116 Load 118 Inductor 120 Capacitor 122 Bootstrap capacitor 124 Bootstrap diode, diode 200 Half - bridge IC design 202 High - side FET 210 Logic converter and POR circuit 240 Synchronous bootstrap FET 242 Synchronous bootstrap driver 300 Synchronous bootstrap driver 304 FET 306 Capacitor 314 Low - side gate driver 320 Synchronous bootstrap FET 400 Power FET driver IC, power FET driver circuit 401 Power FET gate driver circuit 402 Synchronous bootstrap FET, FET 404 Power FET, FET 406 Gate Driver 408 Synchronous Bootstrap Gate Driver 410 NAND Gate, Logic Gate 412 Level Shifter 414 Power - on Reset Circuit 500a Low - side Power FET Driver Integrated Circuit 501a Low - side Synchronous Gate Driver Circuit 501b High - side Synchronous Gate Driver Circuit 502a Synchronous Bootstrap FET 502b Synchronous Bootstrap FET 504a Low - side Power FET 504b High - side Power FET 506b Gate Driver 508a Synchronous Bootstrap Gate Driver 508b Synchronous Bootstrap Gate Driver 700 3 - level Step - down Power Converter 701b Synchronous Gate Driver Circuit 701c Synchronous Gate Driver Circuit 701d Synchronous Gate Driver Circuit 702a FET 702b FET 702c FET 704a FET 704b Power FET 704c Power FET 704d Power FET 708a Synchronous Bootstrap Gate Driver 708b Synchronous Bootstrap Gate Driver 708c Synchronous Bootstrap Gate Driver 708d Synchronous Bootstrap Gate Driver 900 Cascade Active Bootstrap Topology, Synchronous Bootstrap Driver Circuit 901 Cascade Active Bootstrap Gate Driver Circuit 902 Bootstrap FET, synchronous bootstrap FET 903 FET 903a FET 903b FET 903n FET 907a FET 1000 Synchronous bootstrap driver circuit 1002 Synchronous bootstrap FET 1003 FET 1100 Synchronous bootstrap driver circuit 1102 Synchronous bootstrap FET 1104 FET

Claims

1. A gate driver integrated circuit, comprising a synchronous bootstrap circuit integrated within an insulating well of the gate driver integrated circuit, whereby a synchronous bootstrap capacitor connected to the synchronous bootstrap circuit can be in a floating state with respect to a corresponding switch node of a power converter.

2. The synchronous bootstrap circuit integrated within the insulating well includes a synchronous bootstrap gate driver and a synchronous bootstrap FET driven by the synchronous bootstrap driver, and the synchronous bootstrap FET is configured to charge the synchronous bootstrap capacitor. The gate driver integrated circuit according to Claim 1.

3. The synchronous bootstrap gate driver is driven by a NAND gate within the insulating well, and the NAND gate receives (i) an output of a gate driver for driving a power FET and (ii) a level shifter for level shifting an input logic signal. The gate driver integrated circuit according to Claim 2.

4. The gate driver integrated circuit according to Claim 1 implemented in GaN technology.

5. Further comprising a logic converter and a power-on reset (POR) circuit, wherein the level shifter receives an input signal from the logic converter and the POR circuit and outputs a level-shifted input signal to the synchronous bootstrap circuit. The gate driver integrated circuit according to Claim 3.

6. The synchronous bootstrap circuit includes a cascaded synchronous bootstrap gate driver circuit. The gate driver integrated circuit according to Claim 1.

7. A power integrated circuit including a plurality of synchronous bootstrap circuits according to Claim 1, wherein each of the plurality of synchronous bootstrap circuits is integrated within a separate insulating well, and a voltage stored on a synchronous bootstrap capacitor connected to a synchronous bootstrap circuit within one insulating well charges another synchronous bootstrap capacitor connected to another synchronous bootstrap circuit within a different insulating well.

8. The two synchronous bootstrap circuits of claim 1 are included in separate isolation wells, one of the two synchronous bootstrap circuits is a low-side synchronous bootstrap circuit, another one of the two synchronous bootstrap circuits is a high-side synchronous bootstrap circuit, the low-side synchronous bootstrap circuit receives a low-side signal for controlling a low-side power FET of a half-bridge circuit, the high-side synchronous bootstrap circuit receives a high-side signal for controlling a high-side power FET of the half-bridge circuit, a synchronous bootstrap capacitor connected to the corresponding switch node in the low-side synchronous bootstrap circuit and in a power converter can be in a floating state with respect to the corresponding switch node, whereby the voltage stored on the synchronous bootstrap capacitor can be used to supply power to the high-side synchronous bootstrap circuit, the power integrated circuit according to claim 7.

9. The power integrated circuit according to claim 7, implemented in GaN technology.

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