Inclined superlattice structure of gate-all-around device

Abstract

A silicon germanium (SiGe) / silicon-containing superlattice structure and a method for forming the same are provided. In various embodiments, SiGe layers are utilized within the SiGe / Si superlattice structure. This SiGe layer realizes a superlattice with reduced or no dislocations by varying the germanium concentration throughout the layer. For example, in some embodiments, each SiGe layer has a core SiGe film with a low Ge content and two thinner SiGe layers, i.e., cladding layers, disposed on both sides of the core SiGe film. In that case, the SiGe cladding layer has a higher Ge content than the core SiGe film. Various embodiments provide a SiGe layer having a germanium depth profile on which a strained SiGe superlattice can be deposited on a Si{110} substrate.

Description

Technical Field

[0001]

[0001] This disclosure relates to transistor devices and methods for manufacturing transistor devices. More particularly, this disclosure relates to superlattice structures that can be used in gate-all-around (GAA) transistor devices and methods for manufacturing such superlattice structures.

Background Art

[0002]

[0002] In the electronics industry, there has been an increasing demand for smaller and faster electronic devices, which are at the same time required to be more complex, sophisticated, and support more functions. Accordingly, in the semiconductor industry, there has been a continuing trend to manufacture integrated circuits (ICs) with low cost, high performance, and low power consumption. Conventionally, these objectives have been achieved mainly by reducing semiconductor IC dimensions (such as the minimum feature size, etc.) and thereby improving production efficiency and suppressing related costs. However, such miniaturization has brought greater complexity to the semiconductor manufacturing process. Therefore, in order to realize continuous progress in semiconductor ICs and devices, similar progress is also required in semiconductor manufacturing processes and technologies.

[0003]

[0003] In recent years, multi-gate devices have been introduced to improve gate control by enhancing gate-channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). One such multi-gate device that has been introduced is the gate-all-around transistor (GAA). In a GAA device, all sides of the channel region are surrounded by a gate electrode, which in the channel region has more depletion, a steeper subthreshold current swing, and a smaller drain induced barrier lowering (DIBL), resulting in less short channel effect.

[0004]

[0004] As transistor dimensions are scaled down to smaller technology nodes, further improvements in GAA design and manufacturing are needed.

Summary of the Invention

[0005]

[0005] The present disclosure relates to a transistor device and a method for manufacturing a transistor device. More particularly, the present disclosure relates to a superlattice structure that can be used in a GAA transistor device and a method for manufacturing the superlattice structure.

[0006]

[0006] In one aspect, a device structure is provided. The device structure includes a substrate. The device structure further includes a superlattice structure formed on the substrate. The superlattice structure includes one or more superlattice stacks. The one or more superlattice stacks include a silicon material layer, a first silicon germanium cladding layer having a first germanium concentration and a first thickness, a silicon germanium core layer having a second germanium concentration and a second thickness, and a second silicon germanium cladding layer having a third germanium concentration and a third thickness. The silicon material layer, the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer are arranged in a stacked configuration. The silicon germanium core layer is disposed between the first silicon germanium cladding layer and the second silicon germanium cladding layer. The first germanium concentration and the third germanium concentration are higher than the second germanium concentration, and the first thickness and the third thickness are thinner than the second thickness.

[0007]

[0007] Embodiments may include one or more of the following. The surface of the first silicon germanium cladding layer is in contact with the surface of the substrate, and the surface of the second silicon germanium cladding layer is in contact with the surface of the silicon material layer. At least one of the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer further includes carbon or boron. The first germanium concentration ranges from about 10% to about 50%. The first germanium concentration ranges from about 20% to about 50%. The first germanium concentration ranges from about 20% to about 40%. The first germanium concentration ranges from about 30% to about 40%. The first thickness and the third thickness are each independently in the range of about 1 nanometer to about 10 nanometers. The first thickness and the third thickness are each independently thicker than 0 nanometers and 3 nanometers or less. The first thickness, the second thickness, and the third thickness have a total thickness in the range of about 5 nanometers to about 20 nanometers. The first thickness, the second thickness, and the third thickness have a total thickness of about 10 nanometers or less. The silicon material layer has a thickness in the range of about 5 nanometers to about 20 nanometers. The silicon material layer has a thickness of about 10 nanometers or less. The superlattice structure includes a superlattice stack between two and five. The substrate includes silicon {110}.

[0008]

[0008] In another aspect, a method of forming a device structure is provided. The method includes forming a superlattice structure on a substrate. Forming the superlattice structure includes forming a first superlattice stack on the substrate. Forming the first superlattice stack includes forming a first silicon germanium structure by a first deposition process using a first precursor material and a second precursor material. Forming the first silicon germanium structure includes forming a first silicon germanium cladding layer having a first germanium concentration and a first thickness, forming a silicon germanium core layer having a second germanium concentration and a second thickness on the first silicon germanium cladding layer, and forming a second silicon germanium cladding layer having a third germanium concentration and a third thickness on the silicon germanium core layer. Forming the first superlattice stack further includes forming a first silicon layer by a second deposition process using a third precursor material. The first germanium concentration and the third germanium concentration are higher than the second germanium concentration, and the first thickness and the third thickness are thinner than the second thickness.

[0009]

[0009] Embodiments may include one or more of the following. The first deposition process and the second deposition process are epitaxial deposition processes. The first deposition process and the second deposition process are performed in the same process chamber. The first deposition process is performed at a temperature in the range of about 400°C to about 850°C and at a pressure in the range of approximately ultra-high vacuum (e.g., less than 1 Torr) to approximately atmospheric pressure. The first deposition process is performed at a temperature in the range of about 600°C to about 680°C and at a pressure in the range of about 1 Torr to about 10 Torr. The first precursor material is dichlorosilane, the second precursor material is germanium, and the third precursor material is disilane. The first deposition process is performed using a fourth precursor material that is a carbon-containing precursor material. Forming a silicon germanium core layer on the first silicon germanium clad layer includes creating a germanium concentration gradient within the silicon germanium core layer by decreasing the flow rate of a second precursor material and then increasing the flow rate of the second precursor material. The germanium concentration gradient is a gradient in which the germanium concentration decreases as the distance from a heterogeneous material increases.

[0010]

[0010] In yet another aspect, a method of forming a device structure is provided. Forming a device structure includes forming a superlattice structure on a substrate. The substrate includes silicon having a <110> crystal orientation. The substrate includes silicon {110}. Forming a superlattice structure includes forming a plurality of superlattice stacks on the substrate. Forming a plurality of superlattice stacks includes forming a first silicon germanium structure by a first deposition process using a first silicon-containing precursor material and a second germanium-containing precursor material. Forming the first silicon germanium structure includes forming a first silicon germanium clad layer having a first thickness, forming a silicon germanium core layer having a second thickness on the first silicon germanium clad layer, and forming a second silicon germanium clad layer on the silicon germanium core layer. The second silicon germanium clad layer has a third thickness. The silicon germanium stack has a germanium concentration gradient in which the germanium concentration decreases as the distance from a heterogeneous material increases. Forming a plurality of superlattice stacks further includes forming a first silicon layer on the first silicon germanium structure by a second deposition process using a second silicon-containing precursor material. The first thickness and the third thickness are thinner than the second thickness.

[0011]

[0011] Embodiments may include one or more of the following. Forming the device structure further includes forming a gate-all-around transistor from a substrate and a superlattice structure.

[0012]

[0012] In another aspect, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the steps of the above apparatus and / or method.

[0013]

[0013] To understand the above features of the present disclosure in detail, a more detailed description of this aspect, briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that since the present disclosure may admit other equally effective embodiments, the accompanying drawings show only typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present invention.

Brief Description of the Drawings

[0014]

Figure 1

[0014] A flowchart showing a method for manufacturing a superlattice structure according to one or more embodiments of the present disclosure is shown.

Figure 2A

[0015] Cross-sectional views of various stages of manufacturing a superlattice structure according to one or more embodiments of the present disclosure are shown.

Figure 2B

Figure 3

[0016] A cross-sectional view of a part of a superlattice structure according to one or more embodiments of the present disclosure is shown.

Figure 4A

[0017] A germanium concentration diagram of a part of a superlattice structure according to one or more embodiments of the present disclosure is shown.

Figure 4B

Figure 5

[0018] Shows a flowchart regarding a method for manufacturing a transistor device structure incorporating a superlattice structure according to one or more embodiments of the present disclosure.

Figure 6A

[0019] Shows cross-sectional views of various stages of manufacturing a transistor device structure incorporating a superlattice structure according to one or more embodiments of the present disclosure.

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0020] For ease of understanding, the same reference numbers are used as much as possible to indicate the same elements common to multiple drawings. It is assumed that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further description.

[0016]

[0021] The abruptness and uniformity of the interface in a heterostructure are key to controlling electronic and optical properties. To speed up the device, it is also desirable to use a material with high hole mobility.

[0017]

[0022] Scaling down silicon metal-oxide-semiconductor (MOS) devices has become a major challenge in the semiconductor industry. One problem with scaling down conventional planar devices is the short-channel effect, which is beginning to dominate device performance. One solution to this problem is the emergence of multi-gate devices with three-dimensional architectures, such as fin-type semiconductor devices, i.e., finFET devices, and gate-all-around (GAA) devices. In a finFET, a gate is wrapped around a thin semiconductor fin, and in a GAA, all sides of the channel region are surrounded by gate electrodes. With either of these three-dimensional architectures, it is possible to improve gate control over the channel (and thus reduce the short-channel effect) by using multiple gates.

[0018]

[0023] However, the introduction of these multi-gate devices has brought further challenges. For example, insufficient carrier mobility within the device is one problem. The development of high-mobility semiconductors is desirable for further improving the device performance of electronic devices. Therefore, in order to realize faster electronic devices, it is desirable to develop multi-gate devices with improved hole mobility. Crystalline silicon such as an Si{110} substrate is a type of crystalline silicon substrate that brings about an improvement in hole mobility.

[0019]

[0024] Superlattice structures can be used in the manufacture of devices for forming integrated circuits. These superlattice structures incorporate films with various properties depending on the specific application in which the films are deposited, such as silicon and silicon germanium films. One key property for controlling specific applications is the film stress. For example, in some applications, it is desirable to form a silicon germanium film having a high stress (compared to the underlying silicon substrate) to improve the mobility of electrons through the silicon. This improved electron mobility increases the speed of the device structure.

[0020]

[0025] In other applications, for example, to minimize the dislocation of the layer from the underlying substrate or to minimize the formation of dislocations in the substrate itself, it is desirable to form a silicon germanium film having a low stress (compared to the underlying silicon substrate). Such dislocations are harmful to the device function. This is because these dislocations scatter the movement of electrons / holes and / or promote diffusion in undesirable locations.

[0021]

[0026] Various embodiments provide an improved SiGe / Si superlattice structure that can be used with, for example, a silicon substrate that exhibits improved hole mobility, such as a Si{110} substrate. The SiGe layers of the SiGe / Si superlattice structure can be formed using a chlorosilane gas source. These chlorosilane gas sources provide a process with a high growth rate due to chlorine surface termination, resulting in excellent interface abruptness. This interface abruptness improves the etching selectivity between the SiGe layer and the Si layer in the superlattice structure. Various embodiments also provide an improved SiGe / Si superlattice structure having a low stress (compared to the underlying silicon substrate) to minimize, for example, the dislocation of the SiGe layer from the underlying substrate or to minimize the formation of dislocations in the substrate itself. These dislocations can be harmful to device function. This is because these dislocations scatter the movement of electrons / holes and / or promote diffusion in undesirable locations.

[0022]

[0027] Various embodiments use SiGe layers in a SiGe / Si superlattice structure. The SiGe layers include varying the germanium concentration throughout the layer to achieve a superlattice with reduced or no dislocations. For example, in some embodiments, each SiGe layer has a core SiGe film with a low Ge content and two thinner SiGe layers, i.e., cladding layers, disposed on both sides of the core SiGe film. In that case, the SiGe cladding layers have a higher Ge content than the core SiGe film. Various embodiments provide a SiGe layer having a germanium depth profile that enables strained SiGe superlattice deposition on a Si{110} substrate. The SiGe layer can be doped with atoms having a smaller atomic radius. For example, in some embodiments, the SiGe layer can be doped with carbon and / or boron to further reduce strain. As a result, superlattice structures on crystalline silicon, such as, for example, a Si / SiGe:C / Si{110} structure, are less prone to misfit dislocations compared to conventional superlattice designs.

[0023]

[0028] FIG. 1 shows a flowchart of a method 100 for manufacturing a superlattice structure according to one or more embodiments of the present disclosure. Method 100 can be part of a multi-step manufacturing process of a semiconductor device, such as, for example, a GAA transistor.

[0024]

[0029] In step 110, a substrate is provided. In some embodiments, the substrate is a bulk semiconductor substrate. The term bulk semiconductor substrate refers to a substrate that is entirely composed of a semiconductor material. The bulk semiconductor substrate includes any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may include one or more materials such as crystalline silicon (e.g., Si{100}, Si{110}, or Si{111}, etc.), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrates, patterned or unpatterned substrates, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon. In other embodiments, the semiconductor material is a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In certain embodiments, the semiconductor material is Si{110}. Si{110} improves hole mobility, which can lead to an improvement in the overall device speed.

[0025]

[0030] In step 120 of method 100, in some embodiments, the substrate is subjected to an optional pre-cleaning or surface treatment process. The substrate undergoes surface treatment to improve mobility and bias temperature instability (BTI). In some embodiments, the surface treatment includes annealing the substrate in an atmosphere of hydrogen (H2). The annealing process can be any suitable annealing process known to those skilled in the art. In some embodiments, the annealing is rapid thermal processing (RTP) annealing. In some embodiments, the annealing process is performed at a temperature in the range of about 500°C to about 900°C, or in the range of about 600°C to about 900°C, or in the range of about 600°C to about 800°C. In some embodiments, the annealing process is performed at a pressure in the range of about 5 Torr to about 20 Torr.

[0026]

[0031] In step 130 of method 100, a superlattice structure is formed on the substrate. As used herein, the term "superlattice" generally refers to a stack of material layers, where the stack of material layers consists of lattice-matched materials, but the selective removal process can be performed on the superlattice structure to a sufficient extent that the compositions are sufficiently different. More generally, the compositions of the various material layers within the stack can be specific to one or more of the material layers within the stack. In one example, the superlattice structure includes one or more layers of a silicon-containing material (e.g., Si) and a silicon-germanium-containing material (e.g., SiGe). In some embodiments, the superlattice structure includes a first material layer and a second material layer. In some embodiments, the superlattice structure includes a first material layer, a second material layer, a third material layer, and a fourth material layer. In this embodiment, the second material layer, the third material layer, and the fourth material layer are formed from the same compound material, but may have different material properties.

[0027]

[0032] Forming the superlattice structure in step 130 includes forming the first material layer in step 140 and forming the second material layer on top of the first material layer in step 150. Steps 140 and 150 can be repeated until the superlattice structure achieves the desired thickness and / or number of layers. The first material layer and the second material layer can be alternately arranged as a stacked pair. The superlattice structure can include a plurality of first material layers and corresponding second material layers alternately arranged as a plurality of stacked pairs. In one embodiment, the plurality of first layers are formed from a silicon-containing material, and the plurality of second layers are formed from at least a silicon-containing material and a germanium-containing material. Thus, the first material layer and the second material layer are different materials. In some embodiments, the plurality of first layers and the corresponding plurality of second layers are lattice-matched materials having sufficiently different compositions to allow selective layer removal to be continuously performed.

[0028]

[0033] In some embodiments, the plurality of first layers comprise a Group IV material such as silicon (e.g., Si). The plurality of second layers comprise a Group IV material such as silicon and germanium (e.g., SiGe). In some embodiments, the concentration (atomic percent) of germanium in the silicon germanium layer may have a gradient. For example, the concentration of germanium may be highest near the interface (e.g., the top and bottom surfaces of the silicon germanium layer) and may decrease from the interface towards the center of the silicon germanium layer.

[0029]

[0034] In some embodiments, the silicon germanium layer has a silicon:germanium molar ratio between about 1:1 and about 5:1. In some embodiments, the silicon germanium layer has a germanium content in the range of about 10% to about 50%, or about 20% to about 50%, or about 20% to about 40%, or about 30% to about 40%. The silicon content can be in the range of about 50% to about 90%, or about 50% to about 80%, or about 60% to about 80%, or about 60% to about 70%. In other embodiments, the silicon germanium layer has a germanium content in the range of about 20% to about 90%, or about 50% to about 80%. The silicon content can be in the range of about 10% to about 80%, or about 20% to about 50%.

[0030]

[0035] In some embodiments, the silicon germanium layer comprises a plurality of layers with different concentrations. For example, in some embodiments, the silicon germanium layer comprises a first silicon germanium layer or cladding layer having a first germanium concentration, a second silicon germanium layer or core layer having a second germanium concentration, and a third silicon germanium layer or cladding layer having a third germanium concentration. The second silicon germanium layer can be disposed between or sandwiched between the first silicon germanium layer and the third silicon germanium layer. The first germanium concentration and the third germanium concentration may be higher than the second germanium concentration. In some embodiments, the first germanium concentration and the third germanium concentration are each independently 10% or more germanium (e.g., in the range of about 10% to about 80%, or in the range of about 20% to about 50%, or in the range of about 30% to about 40%, etc.), and the second germanium concentration is less than or equal to the first germanium concentration and the third germanium concentration. For example, the second germanium concentration is 20% or less germanium, e.g., in the range of about 1% to about 20%, or in the range of about 5% to about 15%, or in the range of about 5% to about 10%. In some embodiments, the second germanium concentration is 50% or less, or 40% or less, or 30% or less, or 20% or less, or 10% or less, e.g., in the range of about 1% to about 50%, about 1% to about 40%, or about 1% to about 30%, or about 1% to about 20%, about 1% to about 10%, or about 1% to about 5%, or in the range of about 5% to about 10%.

[0031]

[0036] In some embodiments, at least one of the plurality of first material layers and the plurality of second material layers is doped with carbon, e.g., Si:C or SiGe:C.

[0032]

[0037] In some embodiments, the first material layer and the second material layer are formed through an epitaxial chemical vapor deposition process. As a result, the interface between different atomic species can be controlled, and the superlattice structure can be advantageously controlled during subsequent selective etching or modification processes. In some embodiments, the epitaxial deposition process includes loading a substrate into a process chamber and adjusting the conditions in the process chamber to a target temperature and pressure. Next, a deposition process is initiated to form one or more epitaxial layers on the single-crystal surface of the substrate. The deposition process then ends. The thickness of the epitaxial layer is then measured. When a predetermined thickness of the epitaxial layer is achieved, the epitaxial process ends. However, if the predetermined thickness is not achieved, the deposition and purge steps are repeated as a cycle until the predetermined thickness is achieved. Further details of this exemplary process are described below.

[0033]

[0038] After loading the substrate into the process chamber, the conditions inside the process chamber are adjusted to a predetermined temperature and pressure. The temperature is adjusted according to the specific process being executed. The temperature appropriate for performing the epitaxial process may depend on the specific precursors used to deposit silicon-containing materials and silicon-germanium-containing materials. In some embodiments, the process chamber is maintained at a temperature in the range of about 450°C to about 750°C, or in the range of about 550°C to about 650°C, or in the range of about 500°C to about 650°C during the epitaxial deposition process. In some embodiments, the process chamber is maintained at a pressure in the range of about 0.1 Torr to about 50 Torr, in the range of about 1 Torr to about 20 Torr, or in the range of about 5 Torr to about 10 Torr during the epitaxial deposition process. The pressure may vary during each processing step and between steps, but is generally maintained constant.

[0034]

[0039] During the epitaxial deposition process, the substrate is exposed to a deposition gas to form a first material layer and a second material layer. In some embodiments, the substrate is exposed to the deposition gas for a time in the range of about 0.5 seconds to about 30 seconds, or in the range of about 1 second to about 20 seconds, or in the range of about 5 seconds to about 10 seconds. In certain embodiments, the deposition step lasts for about 10 to 11 seconds. The specific exposure time during the epitaxial deposition process generally relates to the specific precursors and temperature used in the epitaxial deposition process. Generally, the substrate is exposed to the deposition gas for a sufficient time until the target thickness of the epitaxial layer within the superlattice structure is formed.

[0035]

[0040] In some embodiments, the deposition gas may include at least a silicon source, a carrier gas, and / or at least one secondary elemental source (e.g., a germanium source and / or a carbon source).

[0036]

[0041] In some embodiments, the silicon source is typically provided to the process chamber at a flow rate in the range of about 5 sccm to about 500 sccm, or in the range of about 10 sccm to about 300 sccm, or in the range of about 50 sccm to about 200 sccm, such as a flow rate of about 100 sccm. Silicon sources useful for the deposition gas to deposit silicon-containing compounds include silane, halogenated silanes, and organosilanes. Silane includes silane (SiH4), as well as higher-order silanes having the empirical formula SixH(2x + 2) such as disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), and neopentasilane. Halogenated silanes include compounds having the empirical formula X’ySixH(2x + 2 - y), where X’ is F, Cl, Br, or I, such as hexachlorodisilane (Si2Cl6), tetrachlorosilane (SiCl4), dichlorosilane (Cl2SiH2), and trichlorosilane (Cl3SiH). Organosilanes include compounds having the empirical formula RySixH(2x + 2 - y), where R is methyl, ethyl, propyl, or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH 2) Ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), and hexamethyldisilane ((CH3)6Si2) are included. The organosilane compound has been found to be an advantageous silicon source as well as a carbon source in embodiments where carbon is incorporated into the deposited silicon-containing compound.

[0037]

[0042] In some embodiments where the silicon source is provided with a carrier gas, the carrier gas has a flow rate in the range of about 1 slm (standard liters per minute) to about 100 slm, or in the range of about 5 slm to about 75 slm, or in the range of about 10 slm to about 50 slm, or in the range of about 10 slm to about 20 slm. The carrier gas may include nitrogen (N2), hydrogen (H2), argon, helium, or a combination thereof. In some embodiments, an inert carrier gas is preferred and is selected from nitrogen, argon, helium, or a combination thereof. The carrier gas may be selected based on the precursors used and / or the processing temperature during the epitaxial process.

[0038]

[0043] In certain embodiments, the epitaxial layer is a silicon layer and the deposition gas includes disilane.

[0039]

[0044] In some embodiments, the deposition gas utilized also includes at least one secondary elemental source such as a germanium source and / or a carbon source. The germanium source may be added to the process chamber with the silicon source and optionally a carrier gas to form a silicon-containing compound such as a silicon germanium material layer. In some embodiments, the germanium source is provided to the process chamber at a flow rate in the range of about 0.1 sccm to about 20 sccm (e.g., in the range of about 0.5 sccm to about 10 sccm, or in the range of about 1 sccm to about 5 sccm). Useful germanium sources for depositing silicon-containing compounds include germane (GeH4), higher-order germanes, and organogermaniums. Higher-order germanes include, for example, compounds having the empirical formula GexH(2x + 2) such as digermane (Ge2H6), trigermane (Ge3H8), tetragermane (Ge4H 10 ), etc., and others. Organogermaniums include compounds such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2H5), dimethyldigermane ((CH3)2Ge2H4), and hexamethyldigermane ((CH3)6Ge2). Germanium compounds and organogermanium compounds have been found to be advantageous germanium sources and carbon sources in embodiments where they are incorporated into silicon-containing compounds in which germanium and carbon are deposited, i.e., SiGe compounds and SiGe:C compounds. In some embodiments, the germanium concentration in the epitaxial layer ranges from about 1 atomic % to about 30 atomic % (e.g., about 20 atomic %). In some embodiments, as described herein, the germanium concentration may have a gradient within the epitaxial layer.

[0040]

[0045] The carbon source can be added to the process chamber during deposition, along with a silicon source and / or a germanium source and optionally a carrier gas, to form a silicon-containing compound such as a silicon carbon material (e.g., Si:C) or a silicon germanium carbon material (e.g., SiGe:C). In some embodiments, the carbon source is provided to the process chamber at a flow rate in the range of about 0.1 sccm to about 40 sccm, or in the range of about 3 sccm to about 25 sccm, or in the range of about 5 sccm to about 25 sccm. The carbon source can be diluted to 5% with argon gas or nitrogen gas and flowed at a flow rate of 750 sccm. Carbon sources useful for depositing silicon-containing compounds include organosilanes, ethyl, propyl, and butyl, including alkyls, alkenes, and alkynes. Such carbon sources include methylsilane (CH3SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane (CH3CH2SiH3), methane (CH4), ethylene (C2H4), acetylene (C2H2), propane (C3H8), propene (C3H6), butyne (C4H6), and others. In some embodiments, the carbon concentration in the epitaxial layer ranges from about 200 ppm to about 5 atomic %, or from about 1 atomic % to about 3 atomic %. In some embodiments, the carbon concentration may have a gradient within the epitaxial layer, preferably having a gradient such that the carbon concentration in the first portion of the epitaxial layer is lower than that in the last portion of the epitaxial layer. Alternatively, both the germanium source and the carbon source can be added into the process chamber together with the silicon source and the carrier gas during deposition to form a silicon-containing compound such as a silicon carbon or silicon germanium carbon material.

[0041]

[0046] In certain embodiments, a first epitaxial layer that is a silicon layer is formed using disilane, and a second epitaxial layer that is a silicon germanium layer is formed using dichlorosilane and germanium. By providing a process with a high growth rate due to chlorine surface termination using dichlorosilane, excellent interface abruptness is achieved. This interface abruptness contributes to an improvement in the etching selectivity of the silicon and germanium-containing layers with respect to the silicon layer.

[0042]

[0047] In some embodiments, after the deposition process is completed, the process chamber can be cleaned with a purge gas or a carrier gas and / or the process chamber can be evacuated with a vacuum pump. The purge and / or evacuation process removes excess deposition gases, reaction by-products, and other contaminants. In some embodiments, the process chamber can be purged between the deposition of the first layer and the second layer. In one embodiment, by flowing a carrier gas at a flow rate of about 5 slm, the process chamber can be purged for about 10 seconds. The deposition and purge cycles can be repeated many times.

[0043]

[0048] Referring to FIGS. 2A, 2B, and 3, cross-sectional views of some embodiments of a device structure for a semiconductor device at various manufacturing stages are provided to illustrate the method of FIG. 1. Although FIGS. 2A, 2B, and 3 are described in connection with method 100, it will be understood that the structures disclosed in FIGS. 2A, 2B, and 3 are not limited to method 100 and can rather stand on their own as structures independent of method 100. Similarly, although method 100 is described in connection with FIGS. 2A, 2B, and 3, it will be understood that method 100 is not limited to the structures disclosed in FIGS. 2A, 2B, and 3 and can rather stand on its own independently of the structures disclosed in FIGS. 2A, 2B, and 3.

[0044]

[0049] FIG. 2A shows a cross-sectional view of a semiconductor device structure 200 at an intermediate stage of manufacturing corresponding to steps 110 and 120 of method 100, according to some embodiments. The semiconductor device structure 200 includes a substrate 210. The substrate 210 can be the substrate described in step 110. The substrate 210 has a front side 210f (also referred to as the front surface) and a back side 210b (also referred to as the back surface) opposite the front side 210f. The substrate 210 can be exposed to a pre-cleaning process as described in step 120. Next, as shown in FIG. 2B, a superlattice structure 220 described herein is formed on the front side 210f of the substrate 210.

[0045]

[0050] FIG. 2B shows a cross-sectional view of a semiconductor device structure 200 at an intermediate stage of manufacturing corresponding to step 130, according to some embodiments. The superlattice structure 220 includes a plurality of first material layers 224a - c and corresponding second material layers 226a - c that are alternately arranged as a plurality of stacked pairs. In one embodiment, the plurality of first material layers 224a - c are formed from at least a silicon - containing material and a germanium - containing material. In one embodiment, the plurality of second material layers 226a - c are formed from at least a silicon - containing material. Thus, the first material layers 224a - c and the second material layers 226a - c are different materials. In some embodiments, the plurality of first material layers 224 and corresponding second material layers 226 are lattice - matched materials having compositions different enough that selective layer removal or layer modification can be successively performed.

[0046]

[0051] In some embodiments, the plurality of first material layers 224a - c and corresponding second material layers 226a - c can be any number of lattice - matched material pairs suitable for forming the superlattice structure 220. For example, the plurality of first material layers 224a - c and corresponding second material layers 226a - c include between about 2 and about 5 pairs of lattice - matched materials (e.g., 3 pairs of lattice - matched materials as shown in FIG. 2B).

[0047]

[0052] The material layers of the superlattice structure 220 can have a controlled thickness to provide a substantially defect - free crystallographic profile of various materials. In some embodiments, the layers of the superlattice structure 220 have a total thickness in the range of about 3 nm to about 50 nm, or in the range of about 5 nm to about 40 nm, or in the range of about 5 nm to about 30 nm, or in the range of about 5 nm to about 20 nm. In some embodiments, the layers of the superlattice structure 220 have a thickness in the range of about 3 nm to about 50 nm. For example, the plurality of first material layers 224a - c can have a thickness 225 in the range of about 1 nm to about 20 nm, or in the range of about 1 nm to about 10 nm, or in the range of about 3 nm to about 10 nm, or in the range of about 5 nm to about 7 nm (e.g., about 6 nm). The plurality of second material layers 226a-c may have a thickness 227 in the range of about 1 nm to about 20 nm, or in the range of about 5 nm to about 15 nm, or in the range of about 7 nm to about 10 nm (e.g., about 8 nm).

[0048]

[0053] FIG. 3 shows a cross-sectional view of a part of a semiconductor device structure 200 at an intermediate stage of manufacturing corresponding to step 130, according to some embodiments. In some embodiments, as shown in FIG. 3, the first material layer 224 is a multilayer structure 230. The multilayer structure 230 may include a first silicon germanium layer 232 or a first silicon germanium cladding layer having a back interface 232b and a front interface 232f, a second silicon germanium layer 234 or a core layer having a back interface 234b and a front interface 234f, and a third silicon germanium layer 236 or a second silicon germanium cladding layer having a back interface 236b and a front interface 236f. The first silicon germanium layer 232 has a first germanium concentration and a first thickness 233, the second silicon germanium layer 234 has a second germanium concentration and a second thickness 235, and the third silicon germanium layer 236 has a third germanium concentration and a third thickness 237. As shown in FIG. 3, in some embodiments, the second silicon germanium layer 234 may be disposed between or sandwiched between the first silicon germanium layer 232 and the third silicon germanium layer 236. In some embodiments, the first germanium concentration and the third germanium concentration may be higher than the second germanium concentration, and the first thickness and the third thickness may be thinner than the second thickness.

[0049]

[0054] In some embodiments, a germanium concentration gradient is formed within the first material layer 224. The germanium concentration gradient may be continuous or stepwise. The germanium concentration gradient may be formed in a direction perpendicular to the front interface 236f of the third silicon germanium layer 236. The germanium concentration gradient can change unidirectionally from high concentration to low concentration or vice versa. In some embodiments, the germanium concentration gradient may change unidirectionally from high concentration to low concentration and then return to high concentration, or vice versa. In some embodiments described herein, one or more regions of the first material layer may include a more complex gradient of germanium, such as high / low / high, or low / high / low germanium. In some embodiments, the concentration gradient is set to decrease as the distance from a different material (e.g., a different material in either the second material layer 226 or the substrate 210) increases. In some embodiments, referring to FIG. 3, for example, the germanium concentration may be highest at the front interface 236f and the back interface 232b. By maximizing the germanium concentration at the interface in contact with the material layer of a different material, the etching selectivity between the first material layer 224 and the second material layers 226a - c is improved. For example, having a higher germanium concentration at the front interface 236f that may be in contact with one of the second material layers 226a - c and a higher germanium concentration at the back interface 232b that is in contact with either one of the second material layers 226a - c or the front side 210f of the substrate 210 results in improved etching selectivity when removing the first material layers 224a - c.

[0050]

[0055] In some embodiments, the germanium concentration gradient is formed in at least one of the first silicon germanium layer 232, the second silicon germanium layer 234, and the third silicon germanium layer 236. For example, referring to FIG. 3, in some embodiments, the first silicon germanium layer 232 and the third silicon germanium layer 236 have an overall homogeneous germanium concentration, and the second silicon germanium layer has a germanium concentration gradient. The germanium concentration gradient in the second silicon germanium layer 234 may decrease from the back interface 234b towards the central region of the second silicon germanium layer 234, and may increase again from the central region of the second silicon germanium layer 234 towards the front interface 234.

[0051]

[0056] Figure 4A shows a germanium concentration diagram 400 for manufacturing a superlattice structure according to one or more embodiments of the present disclosure. The X-axis of the germanium concentration diagram 400 represents time, and the Y-axis represents the germanium concentration in the deposited layer. In some embodiments, as shown in Figure 4A, the first material layers 224a-c are silicon germanium layers, and the second material layers 226a-c are silicon layers. The germanium concentration diagram 400 shows the following example. That is, the germanium concentration varies within the first material layers 224a-c, but is highest at the interface between the first material layers 224a-c and the second material layers 226a-c.

[0052]

[0057] Figure 4B shows another germanium concentration diagram 410 for manufacturing a superlattice structure according to one or more embodiments of the present disclosure. The germanium concentration diagram 410 is similar to the germanium concentration diagram 400 shown in Figure 4A, but is different in the following points. That is, the germanium concentration shown in the germanium concentration diagram 410 varies within the second silicon germanium layer 234. That is, it decreases from the interface between the front interface 232f and the back interface 234b into the second silicon germanium layer 234, but then increases towards the interface between the front interface 234f and the back interface 236b.

[0053]

[0058] Figure 5 shows a flowchart of a method 500 for manufacturing a transistor device structure incorporating a superlattice structure according to one or more embodiments of the present disclosure. Figures 6A to 6F show cross-sectional views of various stages of manufacturing a transistor device structure incorporating a superlattice structure according to one or more embodiments of the present disclosure. The transistor device can be a GAA device. Figures 6A through 6F are shown in connection with method 500, but it should be understood that the structures disclosed in Figures 6A through 6F are not limited to method 500 and may rather exist independently as structures separate from method 500. Similarly, method 500 is shown in connection with Figures 6A through 6F, but it should be understood that method 500 is not limited to the structures disclosed in Figures 6A through 6F and may rather exist independently separate from the structures disclosed in Figures 6A through 6F.

[0054]

[0059] In step 510 of method 500, a superlattice structure is formed on a substrate, such as the superlattice structure 220 formed on the substrate 210 shown in Figure 2B, for example.

[0055]

[0060] Figure 6A shows a partial cross-sectional view of a semiconductor device structure 600 at a manufacturing intermediate stage corresponding to step 520 according to some embodiments. In step 520, after a hard mask layer 614 is deposited on the top surface of the superlattice structure 220, a patterning and etching process 610 is performed to form trenches 612a - c in the superlattice structure 220. In some embodiments, photolithography techniques are used to pattern the hard mask layer 614. Generally, a photoresist material (not shown) is deposited on the hard mask layer 614. The photoresist material is irradiated (exposed) with radiation such as light through a patterned reticle to cause a reaction in the portion of the photoresist material exposed to the energy. The photoresist material is developed to remove a portion of the photoresist material, and the remaining photoresist material protects the underlying material from subsequent processing steps such as etching.

[0056]

[0061] As shown in FIG. 6A, after the etching process is performed on the superlattice structure 220, the remaining regions of the superlattice structure 220 and the substrate 210 thereunder form fins such as a first fin 616a and a second fin 616b (collectively referred to as fin 616). As seen in FIG. 6A, the fin 616 includes portions of the superlattice structure 220 (e.g., portions of the first material layer 224' (e.g., SiGe layer) and the second material layer 226' (e.g., silicon layer)), as well as a portion of the substrate 210. Two fins, namely, a first fin 616a and a second fin 616b are shown in FIG. 6A, but it should be understood that any suitable number and type of fins may be used.

[0057]

[0062] FIG. 6B shows a cross-sectional view of a part of a semiconductor device structure 600 at a manufacturing intermediate stage corresponding to step 530 according to some embodiments. In step 530, shallow trench isolations (STIs) 622a - c are formed according to some embodiments. In step 530, to form the STIs 622a - c, a deposition process 620 may be performed to deposit a dielectric insulating material in trenches 612a - c between adjacent fins 616. The STIs 622a - c can be made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectrics such as carbon-doped oxide, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, and combinations thereof. In some embodiments, any acceptable process may be used, but the deposition process 620 is a process such as CVD, fluidized CVD (FCVD), or a spin-on glass process. Subsequently, STI 622a - c may undergo one or more hard mask removal processes and a process for removing the portions of STI 622a - c that extend over the upper surfaces of fins 616a - b, using, for example, an etching process, chemical mechanical polishing (CMP), etc.

[0058]

[0063] FIG. 6C shows a cross - sectional view of a part of a semiconductor device structure 600 at an intermediate stage of manufacturing corresponding to step 540, according to some embodiments. In step 540, by recessing STI 622a - c to form recessed STI 622a' - c', the sidewalls of fins 616a - b can be exposed. In some embodiments, using fins 616a - b as an etching mask, STI 622a - c is recessed by one or more selective etching processes 630. For example, STI 622a - c is recessed using one or more etching processes. The depth of recessed STI 622a' - c' can be determined by the height of the superlattice structure 220. In some embodiments, the recess extends to a depth such that the lowermost first material layer 224a' is exposed. Alternatively, the lowermost first material layer 224a' (e.g., SiGe layer) may remain under the upper surface of recessed STI 622a' - c'.

[0059]

[0064] FIG. 6D shows a cross - sectional view of a part of a semiconductor device structure 600 at an intermediate stage of manufacturing corresponding to step 550, according to some embodiments. In step 550, a dummy gate oxide layer 642 is formed over the exposed fins 616a - b. In some embodiments, the dummy gate oxide layer 642 can be formed by a deposition process 640 such as, for example, thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming a dummy gate oxide layer 642. In some embodiments, the dummy gate oxide layer 642 can be formed of the same material as the STIs 622a-c. In other embodiments, the dummy gate oxide layer 642 can be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, polymers such as polyimide, and combinations thereof. In other embodiments, the dummy gate oxide layer 642 includes, for example, a dielectric material having a high dielectric constant (k value) greater than 3.9. The material can include silicon nitride, oxynitride, metal oxides (e.g., HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx), combinations thereof, multilayers thereof, and the like.

[0060]

[0065] FIG. 6E shows a partial view of a semiconductor device structure 600 at an intermediate stage of manufacturing corresponding to step 560, according to some embodiments. In step 560, a dummy metal layer 652 can be deposited on the dummy gate oxide layer 642 (shown in FIG. 6D). In one embodiment, the dummy metal layer 652 is a conductive material and can be selected from the group including polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. In one embodiment, the dummy metal layer 652 can be deposited by a deposition process 650 such as, for example, PVD, CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. Other conductive and non-conductive materials can also be used. The upper surface of the dummy metal layer 652 can be planarized after deposition.

[0061]

[0066] In some embodiments, a first hard mask layer 654 is deposited on the dummy metal layer 652 via a deposition process such as, for example, CVD or a spin-on glass process, although any acceptable process can be used. In certain embodiments, the first hard mask layer 654 may be an oxide layer (e.g., silicon oxide) and may have a thickness in the range of about 10 Å to about 50 Å. Next, the second hard mask layer 656 is deposited over the first hard mask layer 654 via a process such as a CVD or spin-on glass process, although any acceptable process may be used. In certain embodiments, the second hard mask layer 656 may be a nitride (e.g., silicon nitride). The second hard mask layer 656 may have a thickness in the range of about 150 Å to about 850 Å. The first hard mask layer 654 and the second hard mask layer 656 may be patterned over the dummy metal layer 652 to form a dummy gate hard mask layer stack (not shown). In certain embodiments, a polysilicon etching and dummy oxide removal process is performed using the dummy gate hard mask layer stack to pattern the dummy metal layer 652 and the dummy gate oxide layer 642. During patterning, portions of the dummy metal layer 652 and the dummy gate oxide layer 642 are removed from the source / drain regions of the fins 616a - b, and portions of the dummy metal layer 652 and the dummy gate oxide layer 642 remain over the channel regions of the fins 616a - b to form a dummy metal gate electrode (not shown). The dummy metal gate electrode may include the patterned dummy metal layer and the patterned dummy gate oxide layer disposed under the patterned dummy metal layer. The dummy metal gate electrode and the dummy gate hard mask layer stack collectively form a dummy gate stack (not shown).

[0062]

[0067] The dummy metal gate stack can then be utilized to define and form the source / drain regions from the exposed portions of fins 616a - b. The dummy metal gate stack can then be removed to enable processing for defining and forming the channel region from the central portions of fins 616a - b (not shown).

[0063]

[0068] FIG. 6F shows a cross - sectional view of a portion of a semiconductor device structure 600 at an intermediate stage of manufacturing corresponding to step 570, according to some embodiments. In step 570, a removal process of the first material layers 224a - c (e.g., SiGe layers) is performed. After removing the first material layers 224a - c (shown by dashed lines in FIG. 6F), the second material layers 226a - c remain on fins 616a - b. In a particular embodiment where the first material layers 224a - c are formed of silicon germanium (SiGe) and the second material layers 226a - c are formed of silicon (Si), the first material layers 224a - c can be removed, for example, by a removal process 660. In some embodiments, the removal process 660 can use an etchant that etches silicon germanium faster than silicon, such as NH4OH:H2O2:H2O (ammonia peroxide mixture, APM), H2SO4 + H2O2 (sulfuric acid peroxide mixture, SPM), etc. Other suitable processes and materials may be used. This etching process removes the first material layers 224a - c. Thus, the first nanowires 662a - c or nanosheets are formed from fins 616a - b for n - type devices. In some embodiments, after etching, the lowermost first layer 224a (e.g., SiGe layer) can remain under the upper surface of the recessed STI 622a’ - c’ as a stress layer within the first fin 616a and the second fin 616b to introduce a certain amount of strain or relaxation in the fin material.

[0064]

[0069] After operation 570, the semiconductor device structure 600 may undergo additional processing in operation 580 to form a final device structure, such as, for example, a GAA device.

[0065]

[0070] The summary of the invention, the modes for carrying out the invention, the claims, and the accompanying drawings refer to specific features of the present disclosure (including method steps). It should be understood that the disclosure herein includes all possible combinations of such specific features. For example, if a specific feature is disclosed in the context of a particular aspect, embodiment, example, or particular claim of the present disclosure, that feature may also be combined, to the extent possible, with other particular aspects and embodiments of the present disclosure, and / or used in that context and throughout the present disclosure.

[0066]

[0071] All of the embodiments and functional operations described in this specification can be implemented in digital electronic circuitry, in computer software, firmware, or hardware (including the structural means disclosed herein and their structural equivalents), or in combinations of these. The embodiments described in this specification can be implemented as one or more non-transitory computer program products (i.e., one or more computer programs tangibly embodied in a machine-readable storage device) for execution by, or to control the operation of, a data processing apparatus (e.g., a programmable processor, a computer, or multiple processors or computers).

[0067]

[0072] The processes and logical flows described in this specification can be performed by one or more programmable processors that execute one or more computer programs to perform functions by operating on input data and generating output. The processes and logical flows may be implemented by special-purpose logic circuitry, such as, for example, an FPGA (field programmable gate array) or an ASIC (application specific circuitry), and the apparatus may be implemented as such special-purpose logic circuitry.

[0068]

[0073] The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including, by way of example, one programmable processor, computer, or a plurality of processors or computers. In addition to hardware, the apparatus can include code that creates an execution environment for the computer program in question (for example, processor firmware, protocol stack, database management system, operating system, or code constituting one or more combinations thereof). Processors suitable for executing a computer program include, by way of example, any one or more of both general-purpose and special-purpose microprocessors, and any kind of digital computer.

[0069]

[0074] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including by way of example semiconductor memory devices (such as EPROM, EEPROM, and flash memory devices), magnetic disks (such as internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special-purpose logic circuitry.

[0070]

[0075] In this book, the term "comprise" and its grammatical equivalents are used to mean that other components, elements, steps, etc. may optionally be present. For example, an article "comprising" or "including" components A, B, and C may consist of components A, B, and C (i.e., may contain only those), or may contain not only components A, B, and C but also one or more other components. In addition, when a transitional phrase such as "comprising", "including" or its grammatical equivalent precedes a composition, element or group of elements, the same composition or group of elements preceded by a transitional phrase such as "consisting essentially of", "consisting of", "selected from the group consisting of", or "is" may also be considered, and vice versa.

[0071]

[0076] When introducing elements of the present disclosure, or exemplary aspects or (one or more) embodiments thereof, the articles "a" and "the" are intended to mean the presence of one or more elements.

[0072]

[0077] The foregoing description is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, which is defined by the following claims.

Claims

1. A device structure comprising: a substrate; and a superlattice structure formed on the substrate, wherein the superlattice structure comprises: one or more superlattice stacks, and the one or more superlattice stacks comprise: a silicon material layer; a first silicon germanium cladding layer having a first germanium concentration and a first thickness; a silicon germanium core layer having a second germanium concentration and a second thickness; and a second silicon germanium cladding layer having a third germanium concentration and a third thickness; the silicon material layer, the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer are arranged in a stacked configuration; the silicon germanium core layer is disposed between the first silicon germanium cladding layer and the second silicon germanium cladding layer; the first germanium concentration and the third germanium concentration are higher than the second germanium concentration, and the first thickness and the third thickness are thinner than the second thickness; A device structure.

2. The surface of the first silicon germanium cladding layer is in contact with the surface of the substrate, and the surface of the second silicon germanium cladding layer is in contact with the surface of the silicon material layer. The device structure according to claim 1.

3. At least one of the first silicon germanium cladding layer, the silicon germanium core layer, and the second silicon germanium cladding layer further comprises carbon or boron. The device structure according to claim 1.

4. The first germanium concentration ranges from about 10% to about 50%. The device structure according to claim 1.

5. The first germanium concentration ranges from about 20% to about 40%. The device structure according to claim 1.

6. The first thickness and the third thickness are each independently in the range of about 1 nm to about 10 nm. The device structure according to claim 1.

7. The first thickness, the second thickness, and the third thickness have a total thickness in the range of about 5 nm to about 20 nm. The device structure according to claim 6.

8. The silicon material layer has a thickness in the range of about 5 nm to about 20 nm. The device structure according to claim 7.

9. The superlattice structure comprises between 2 and 5 superlattice stacks. The device structure according to claim 1.

10. The device structure according to claim 1, wherein the substrate comprises silicon {110}.

11. A method of forming a device structure, comprising: forming a superlattice structure on a substrate, wherein forming the superlattice structure comprises: forming a first superlattice stack on the substrate, wherein forming the first superlattice stack comprises: forming a first silicon germanium structure by a first deposition process using a first precursor material and a second precursor material, wherein forming the first silicon germanium structure comprises: forming a first silicon germanium cladding layer having a first germanium concentration and a first thickness; forming a silicon germanium core layer having a second germanium concentration and a second thickness on the first silicon germanium cladding layer; forming a second silicon germanium cladding layer having a third germanium concentration and a third thickness on the silicon germanium core layer; forming the first superlattice stack further comprises: forming a first silicon layer by a second deposition process using a third precursor material; wherein the first germanium concentration and the third germanium concentration are higher than the second germanium concentration, and the first thickness and the third thickness are thinner than the second thickness; Method.

12. The first deposition process and the second deposition process are epitaxial deposition processes, the method according to claim 11. The method according to claim 11.

13. The first deposition process and the second deposition process are performed in the same processing chamber, the method according to claim 12. The method according to claim 12.

14. The first deposition process is performed at a temperature in the range of about 600 °C to about 680 °C and a pressure in the range of about 1 Torr to about 10 Torr, the method according to claim 12. The method according to claim 12.

15. The first precursor material is dichlorosilane, the second precursor material is germanium, and the third precursor material is disilane, the method according to claim 11. The method according to claim 11.

16. The first deposition process is performed using a fourth precursor material which is a carbon-containing precursor material, the method according to claim 11. The method according to claim 11.

17. Forming the silicon germanium core layer on the first silicon germanium clad layer includes creating a germanium concentration gradient in the silicon germanium core layer by decreasing the flow rate of the second precursor material and then increasing the flow rate of the second precursor material. The method according to claim 11.

18. The germanium concentration gradient is a gradient in which the germanium concentration decreases as the distance from the heterogeneous material increases. The method according to claim 17.

19. A method of forming a device structure, comprising: forming a superlattice structure on a substrate, the substrate including silicon {110}, and forming the superlattice structure includes: forming a plurality of superlattice stacks on the substrate, and forming the plurality of superlattice stacks includes: forming a first silicon germanium structure by a first deposition process using a first silicon-containing precursor material and a second germanium-containing precursor material, and forming the first silicon germanium structure includes: forming a first silicon germanium clad layer having a first thickness; forming a silicon germanium core layer having a second thickness on the first silicon germanium clad layer; forming a second silicon germanium clad layer having a third thickness on the silicon germanium core layer, the silicon germanium stack having a germanium concentration gradient in which the germanium concentration decreases as the distance from the heterogeneous material increases, forming the superlattice stack further includes: forming a first silicon layer on the first silicon germanium structure by a second deposition process using a second silicon-containing precursor material, the first thickness and the third thickness being thinner than the second thickness, Method.

20. further comprising forming a gate all-around transistor from the substrate and the superlattice structure. The method according to claim 19.

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