Method for manufacturing a three-dimensional NAND flash memory array

Abstract

According to an embodiment of the present invention, a method for manufacturing a three-dimensional NAND flash memory array including a vertical NAND channel in which polysilicon extends vertically on a substrate may include a metal film forming step of injecting a metal to form a metal film along sidewalls of the polysilicon, a crystal phase growth step of irradiating microwaves to grow crystal phase silicon between the metal and the polysilicon, and a crystal phase transport step of irradiating microwaves to transport the crystal phase silicon in a bottom surface direction of the vertical NAND channel.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to a method for manufacturing a three-dimensional NAND flash memory array.

Background Art

[0002] With the technological development and increasing demand for mobile devices such as smartphones and tablets, the demand for storage devices with higher integration has also been rapidly increasing. Storage devices have also shifted from existing HDDs (hard disk drives) to SSDs (solid state memories) in order to increase the integration density within a small area, and in particular, the demand for non-volatile memory devices among SSDs has been rapidly increasing. As non-volatile memory devices, NAND flash memory devices with increased integration density and reduced costs have been widely used.

[0003] Three-dimensional NAND flash memory devices are manufactured by stacking cells, which are basic storage units, vertically. At this time, as the number of stacked layers increases, the bit density improves, and the cost per bit can be reduced.

[0004] Currently, three-dimensional NAND flash memory devices have about 100 or more stacked layers, and as the capacity is increasing, an expansion of the number of stacked layers of four digits or more is expected.

[0005] In addition, in three-dimensional NAND flash memory devices, cost reduction is achieved by using polysilicon as a channel material.

[0006] When a channel is formed of polysilicon, the resistance increases during the read operation, and the read current in the cell becomes smaller than the minimum size of the current that can be sensed by the sensing circuit, which causes difficulty in the read operation, or when the number of stacked layers is high, there is a problem that the electric field mobility in the channel relatively decreases.

[0007] The limitations of polysilicon act as obstacles that restrict the long-term expansion of 3D NAND flash memory devices.

[0008] To improve the device characteristics of these amorphous polysilicons, crystallization techniques are used. In crystallization techniques, there are solid phase crystallization (SPC) where the temperature is raised above the melting point of silicon and recrystallized, excimer laser crystallization (ELC) which targets only amorphous polysilicon and enables crystallization in a local area, and metal induced lateral crystallization (MILC) which crystallizes at a low temperature.

[0009] Since solid phase crystallization (SPC) is performed at a high temperature, it is quite difficult to carry out the process. Although excimer laser crystallization (ELC) enables crystallization in a local area and has fewer process constraints, it requires the installation of laser equipment, resulting in increased costs and a problem of low yield of crystallized polysilicon.

[0010] The crystallization of amorphous polysilicon by metal induced lateral crystallization (MILC) undergoes a series of process steps such as forming polysilicon, injecting metal, and growing NiSi2 crystals, followed by the transport of NiSi2.

[0011] Korean Patent Publication No. 10-2021-0117522 (Publication Date: September 29, 2021) discloses a first semiconductor pattern crystallized by metal induced lateral crystallization (MILC) as described above. However, these metal induced lateral crystallization (MILC) also have problems such as requiring a long process time and having a high heat load due to the process being carried out at a high temperature.

Summary of the Invention

Problems to be Solved by the Invention

[0012] This specification aims to provide a method for manufacturing a three-dimensional NAND flash memory array that can improve the reduction of read current even when increasing the number of cells for higher integration density.

Means for Solving the Problem

[0013] To solve the above technical problem, the present invention provides a method for manufacturing a three-dimensional NAND flash memory array.

[0014] According to an embodiment of the present invention, a method for manufacturing a three-dimensional NAND flash memory array including a vertical NAND channel in which polysilicon extends vertically on a substrate may include a metal film forming step of injecting metal to form a metal film along the sidewalls of the polysilicon, a crystal phase growth step of irradiating a first microwave to grow crystalline silicon between the metal and the polysilicon, and a crystal phase transport step of irradiating a second microwave to transport the crystalline silicon in the direction of the bottom surface of the vertical NAND channel.

[0015] According to an embodiment, the method for manufacturing a three-dimensional NAND flash memory array may further include a polysilicon pretreatment step of irradiating a third microwave to pretreat the polysilicon before the metal film forming step.

[0016] According to an embodiment, after the crystal phase transport step, it may further include a defect removal step of annealing in a hydrogen atmosphere to remove defects in the crystalline silicon phase.

[0017] According to an embodiment, the defect removal step can be performed in a pressure range of 2 atmospheres to 50 atmospheres.

[0018] According to an embodiment, the defect removal step can be performed in a temperature range of 200°C to 800°C.

[0019] According to an embodiment, the first microwave may be output at 1 KW to 10 KW.

[0020] According to one embodiment, the first microwave can be irradiated in a frequency band range of 2.4 GHz to 2.5 GHz.

[0021] According to one embodiment, the crystal phase growth stage can be performed in a temperature range of 200°C to 600°C.

[0022] According to one embodiment, the metal may be any one selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co), and aluminum (Al).

Advantages of the Invention

[0023] According to an embodiment of the present invention, by combining microwave annealing and hydrogen annealing to perform metal-induced lateral crystallization (MILC) at a relatively low temperature, there is an advantage of reducing the heat load in the manufacturing process of a 3D NAND flash memory array.

[0024] According to an embodiment of the present invention, by combining microwave annealing and hydrogen annealing to perform metal-induced lateral crystallization (MILC) at a relatively low temperature, there is an advantage of improving the reduction of the read current of a 3D NAND flash memory array.

[0025] According to another embodiment of the present invention, by irradiating a first microwave on the metal film in the crystal phase growth stage to induce resistive conduction absorption of the metal and enabling the metal atoms to quickly penetrate at the interface of polysilicon, there is an advantage of shortening the manufacturing process time of a 3D NAND flash memory array.

[0026] According to still another embodiment of the present invention, by irradiating a second microwave on the vertical NAND channel in the crystal phase transport stage to provide kinetic energy, there is an advantage of quickly transporting the crystal phase silicon to the bottom surface of the vertical NAND channel and shortening the manufacturing process time of a 3D NAND flash memory array.

[0027] According to still another embodiment of the present invention, by irradiating polysilicon with a third microwave in the polysilicon pretreatment stage to pretreat the polysilicon, impurities in the polysilicon are removed, and there is an advantage of improving the bonding stability of the metal film formed on the interface of the polysilicon.

[0028] According to still another embodiment of the present invention, by irradiating polysilicon with a third microwave in the polysilicon pretreatment stage to pretreat the polysilicon, the pretreatment is performed at a relatively low temperature, and there is an advantage of minimizing the thermal deformation of the polysilicon.

[0029] According to still another embodiment of the present invention, by removing defects on the crystalline phase silicon by high-pressure heat treatment in a hydrogen atmosphere in the defect removal stage, there is an advantage of reducing the defects of the crystalline phase silicon in the entire region of the vertical NAND channel.

Brief Description of the Drawings

[0030]

Figure 1

Figure 2

Figure 3

Figure 4

Modes for Carrying Out the Invention

[0031] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical idea of the present invention is not limited to the embodiments described herein and can be embodied in other forms. On the contrary, the embodiments introduced here are provided so that the disclosed content is thorough and complete, and that the idea of the present invention is sufficiently conveyed to those of ordinary skill in the art.

[0032] In this specification, when a component is referred to as being on another component, it may mean that it is directly formed on the other component or that a third component may intervene therebetween. Also, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical content.

[0033] Also, in various embodiments of this specification, although terms such as first, second, and third are used to describe various components, these components should not be limited by these terms. These terms are merely used to distinguish one component from another. Thus, a component referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment illustrated and described herein includes its complementary embodiment. Also, "and / or" as used in this specification is used to mean including at least one of the components listed before and after.

[0034] The singular expressions in the specification include plural expressions unless the context clearly indicates otherwise. Also, terms such as "including" or "having" are intended to specify the presence of the features, numbers, steps, components, or combinations thereof described in the specification, and are not to be understood as excluding the presence or possibility of addition of one or more other features, numbers, steps, components, or combinations thereof. Also, "connected" as used in this specification is used to mean including both indirectly connecting and directly connecting a plurality of components.

[0035] Also, when explaining the present invention as follows, if it is determined that a detailed description of related known functions or configurations obscures the gist of the present invention, the detailed description thereof will be omitted.

[0036] FIG. 1 is a cross-sectional perspective view schematically showing a three-dimensional NAND flash memory array 10 according to an embodiment of the present invention, and FIG. 2 is an enlarged front cross-sectional view of A in FIG. 1.

[0037] The three-dimensional NAND flash memory array 10 according to an embodiment of the present invention may include a vertical NAND channel 300.

[0038] Referring to FIGS. 1 and 2, the vertical NAND channel 300 may extend vertically on the substrate 100 in the Z-axis direction on the XYZ orthogonal coordinate system. The vertical NAND channel 300 may be a path through which carriers such as holes or electrons flow.

[0039] The vertical NAND channel 300 may include polysilicon 310 and an oxide film 320. The vertical NAND channel 300 may have a macaroni structure in which the polysilicon 310 forms a body and the inside is filled with the oxide film 320. That is, the oxide film 320 may be filled in the central portion of the polysilicon 310.

[0040] Since the vertical NAND channel 300 has a macaroni structure, the thickness of the cross section (the cross section on the X-Y plane) of the vertical NAND channel 300 may be reduced. When the thickness of the cross section of the vertical NAND channel 300 is reduced, the leakage current (Off Current Leakage Current or Subthreshold Leakage Current) is reduced, and the swing characteristic (SS, subthreshold swing) can be improved.

[0041] On the X-Y plane of FIG. 1, the polysilicon 310 may have a ring-shaped cross section with the oxide film 320 present in the central portion.

[0042] According to the method for manufacturing a three-dimensional NAND flash memory array described later, the amorphous silicon 312 constituting the polysilicon 310 may be crystallized and changed to crystalline phase silicon 311.

[0043] Referring further to FIGS. 1 and 2, the substrate 100 may have a circumferential surface in a horizontal plane. The horizontal plane may face the XY plane.

[0044] The polygate 200 may include a plurality of gates 210 stacked alternately and in multiple layers, and a gate insulating layer 220. The polygate 200 may have a horizontal plane facing the substrate 100. The polygate 200 may surround at least a part of the vertical NAND channel 300.

[0045] The gate insulating layer 220 may be provided between the gates 210 and may be stacked alternately with the gates 210.

[0046] FIGS. 3(a) to 3(e) are diagrams schematically showing the crystallization (MILC) process of a vertical NAND channel according to an embodiment of the present invention, and FIG. 4 is a flowchart showing a method of manufacturing a 3D NAND flash memory array according to an embodiment of the present invention.

[0047] Hereinafter, a method of manufacturing a 3D NAND flash memory array according to an embodiment of the present invention will be described in detail in chronological order.

[0048] Referring to FIGS. 3(a) to 3(e) and FIG. 4, the method of manufacturing a 3D NAND flash memory array may include a metal film formation step (S20), a crystal phase growth step (S30), and a crystal phase transport step (S40). In other embodiments, the method of manufacturing a 3D NAND flash memory array may further include a polysilicon pretreatment step (S10) and a defect removal step (S50).

[0049] In a polygate formation step (not shown), gates and a gate insulating layer may be alternately stacked on a substrate to form a polygate stack.

[0050] In the opening formation stage (not shown), openings can be formed to form vertical NAND channels. The openings can correspond to regions where polysilicon described later is to be formed. In the opening formation stage (not shown), at least one or more openings can be formed in an arbitrary region of the polygate.

[0051] In the polysilicon formation stage (not shown), polysilicon can be formed by depositing silicon (Si) and an oxide filler in the openings. More specifically, in the polysilicon formation stage (not shown), after depositing silicon (Si) with a certain thickness in the openings, the oxide filler can be sequentially filled in the hollow part inside the silicon (Si).

[0052] The oxide filler may be an insulating material such as silicon oxide (Si x O y , where x and y are positive constants). For example, the oxide filler may be SiO2.

[0053] In the polysilicon formation stage (not shown), by depositing silicon (Si) and the oxide filler, ring-shaped polysilicon surrounded by an oxide film can vertically grow in the openings. The polysilicon formed in the polysilicon formation stage (not shown) may be amorphous silicon (a-Si). The oxide film may be provided to reduce the thickness of the polysilicon. The oxide film may be an insulating material such as silicon oxide (Si x O y , where x and y are positive constants). For example, the oxide film may be SiO2.

[0054] Referring to FIGS. 3(a) and 4, in the polysilicon pretreatment stage (S10), polysilicon (amorphous silicon) can be pretreated. In the polysilicon pretreatment stage (S10), by irradiating with a third microwave, incomplete bonds such as SiOH, non-bonded molecules, dangling bonds, and oxygen vacancies on the polysilicon (amorphous silicon) can be removed.

[0055] In the polysilicon pretreatment step (S10), before forming a metal film (see 313 in (b) of FIG. 3) in the subsequent metal film formation step (S20), polysilicon (amorphous silicon) can be pretreated. The fluidity of carriers in the polysilicon (amorphous silicon) can be improved by the polysilicon pretreatment step (S10).

[0056] In the polysilicon pretreatment step (S10), a third microwave can be locally irradiated to the end portion of the vertical NAND channel. More specifically, in the polysilicon pretreatment step (S10), electromagnetic wave energy by irradiation of a third microwave can be injected into the polysilicon (amorphous silicon) to induce resistive conduction absorption in the polysilicon.

[0057] The polysilicon pretreatment step (S10) can be performed in a temperature range of 200°C to 600°C.

[0058] The third microwave according to one embodiment may have an output value of 1 KW to 10 KW, preferably an output value of 4 KW.

[0059] The third microwave according to one embodiment may have a frequency band of 2.4 GHz to 2.5 GHz, preferably a frequency band of 2.45 GHz. The third microwave according to still another embodiment may have a frequency band of 5.8 GHz to 5.9 GHz, preferably a frequency band of 5.85 GHz.

[0060] Referring to (b) of FIG. 3 and FIG. 4, in the metal film formation step (S20), metal can be injected into the upper end region of the vertical NAND channel to form a metal film 313. In the metal film formation step (S20), a thin metal film can be formed along the sidewall of the polysilicon (amorphous silicon) constituting the vertical NAND channel. The metal film can be formed in a film shape between the polysilicon (amorphous silicon) and the oxide film.

[0061] In the metal film formation step (S20) according to an embodiment, an external electric field can be applied to accelerate the application of metal atoms inside the vertical NAND channel.

[0062] According to an embodiment, the metal constituting the metal film 313 may be any selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co), and aluminum (Al). According to an embodiment, when nickel (Ni) is implanted, after crystallization, the crystal structure of the vertical NAND channel can be densified. In FIG. 3(b), it is assumed that nickel (Ni) is implanted, which corresponds to an embodiment, and the type of metal is not limited thereto.

[0063] Referring to FIG. 3(c) and FIG. 4, in the crystal phase growth step (S30), crystal phase silicon can be grown in the upper end region of the vertical NAND channel. In the crystal phase growth step (S30), the metal and polysilicon (amorphous silicon) may be bonded to each other to form crystal phase silicon. In the crystal phase growth step (S30), the polysilicon (amorphous silicon) located in the upper end region of the vertical NAND channel begins to crystallize into crystal phase silicon at the interface between the polysilicon (amorphous silicon) and the metal film. In the crystal phase growth step (S30), the crystallized silicon can grow in the internal direction of the polysilicon in the Z - direction at the interface of the polysilicon in the end region of the vertical NAND channel. In the crystal phase growth step (S30), the first microwave can be irradiated. When the first microwave is irradiated, the metal atoms and silicon (Si) atoms can be bonded to grow crystal phase silicon. According to an embodiment, when the metal is nickel (Ni), the crystal phase silicon may be nickel silicide (NiSi2).

[0064] In the crystal phase growth stage (S30), the end of the local vertical NAND channel can be irradiated with the first microwave. More specifically, in the crystal phase growth stage (S30), electromagnetic wave energy by irradiating the first microwave is injected into the metal film to induce resistive conduction absorption, thereby accelerating the rate at which metal atoms in the metal film penetrate into the polysilicon at the interface between the metal film and the polysilicon.

[0065] In other embodiments, in the crystal phase growth stage (S30), the crystal phase silicon can also be grown by applying heat to the 3D NAND flash memory array. For example, by applying heat to the 3D NAND flash memory array for 720 minutes, the crystal phase silicon can be grown. Preferably, by applying heat to the 3D NAND flash memory array for 30 to 120 minutes, the crystal phase silicon can be grown.

[0066] When the crystal phase growth stage (S30) is performed at a low temperature, the damage applied to the polysilicon and the metal film can be minimized. When heat of about 700 °C is applied to the 3D NAND flash memory array in the crystal phase growth stage (S30), a high heat load can be brought about. To reduce the heat load, in the crystal phase growth stage (S30), the 3D NAND flash memory array can be irradiated with the first microwave in a temperature range of 200 °C to 600 °C. In the crystal phase growth stage (S30), the first microwave may have an output value of 1 KW to 10 KW, preferably an output value of 4 KW.

[0067] In the crystal phase growth stage (S30), the first microwave may have a frequency band of 2.4 GHz to 2.5 GHz, preferably a frequency band of 2.45 GHz. The first microwave according to still other embodiments may have a frequency band of 5.8 GHz to 5.9 GHz, preferably a frequency band of 5.85 GHz.

[0068] Referring to (d) of FIG. 3 and FIG. 4, in the crystal phase transport stage (S40), the second microwave is irradiated at the end of the vertical NAND channel, and the crystal phase silicon can be transported to the bottom surface of the vertical NAND channel having a certain thickness. In the crystal phase transport stage (S40), polysilicon can crystallize into crystal phase silicon up to the bottom surface of the vertical NAND channel by reacting with metal. In the crystal phase transport stage (S40), the second microwave can be irradiated in the Z - direction toward the bottom surface of the vertical NAND channel. In the crystal phase transport stage (S40), the second microwave is irradiated to provide kinetic energy, and the crystal phase silicon can be transported to the bottom surface of the vertical NAND channel.

[0069] In the crystal phase transport stage (S40), by irradiating the second microwave, the crystal phase silicon can be transported to the bottom layer of the vertical NAND channel in a relatively short time.

[0070] More specifically, in the crystal phase transport stage (S40), electromagnetic wave - like kinetic energy by the second microwave is provided to the crystal phase silicon, and the crystal phase silicon can be transported to the entire region of the vertical NAND channel.

[0071] The step of irradiating the second microwave in the crystal phase transport stage (S40) can be performed in a relatively short process time compared to the method of applying heat to the 3 - D NAND flash memory array.

[0072] In one embodiment, heat at 500 °C can be applied to the 3 - D NAND flash memory array for 720 minutes to transport the crystal phase silicon. Thus, when the 3 - D NAND flash memory array is exposed to high temperature for a long time, a high heat load of the vertical NAND channel can be brought about.

[0073] Therefore, in order to minimize damage to the polysilicon and metal, the crystal phase transport stage (S40) can be performed in a temperature range of 200 °C to 400 °C.

[0074] Preferably, the crystal phase transport step (S40) can be performed for 30 minutes to 120 minutes.

[0075] At this time, the second microwave may have an output value of 1 KW to 10 KW, preferably an output value of 4 KW. In the crystal phase transport step (S40), the second microwave can be locally irradiated to the end of the vertical NAND channel.

[0076] The second microwave (WM) according to one embodiment may have a frequency band of 2.4 GHz to 2.5 GHz, preferably a frequency band of 2.45 GHz. Further, the second microwave according to another embodiment may have a frequency band of 5.8 GHz to 5.9 GHz, preferably a frequency band of 5.85 GHz.

[0077] Referring to FIGS. 3(e) and 4, in the defect removal step (S50), the three-dimensional NAND flash memory array can be annealed in a hydrogen atmosphere to remove defects on the crystalline silicon phase.

[0078] When some of the metals forming the crystalline silicon phase do not bond and remain as metal atoms, they can act on the defects of the vertical NAND channel itself. In the defect removal step (S50), in order to remove defects such as unbonded metal atoms in the crystalline silicon phase, the three-dimensional NAND flash memory array can be annealed in a hydrogen atmosphere.

[0079] The defect removal step (S50) can be performed in a relatively short time. Preferably, the defect removal step (S50) can be performed for 10 minutes to 60 minutes.

[0080] In the defect removal step (S50), annealing can be performed with 3% to 10% hydrogen (H2) or deuterium (D2) as the reaction gas. The gas other than the reaction gas may be nitrogen (N2). In particular, although the explosion risk may increase in a flammable environment when the hydrogen (H2) concentration is 10% or more, it can be used if the explosion risk is controlled in terms of the design of the annealing apparatus. Therefore, the use of hydrogen (H2) or deuterium (D2) at a concentration higher than that (for example, 10% or more or 100%) is not excluded. Depending on the embodiment, a reaction gas containing oxygen (O), fluorine (F), or nitrogen (N) can also be provided in the defect removal step (S50).

[0081] In the defect removal step (S50), annealing can be performed in a pressure range of 2 atmospheres to 50 atmospheres, preferably in a pressure range of 2 atmospheres to 20 atmospheres.

[0082] In the defect removal step (S50), annealing can be performed in a temperature range of 200°C to 800°C, preferably in a temperature range of 200°C to 600°C, more preferably in a temperature range of 350°C to 450°C.

[0083] As described above, the present invention has been described in detail with preferred embodiments. However, the scope of the present invention is not limited to specific embodiments and should be interpreted by the appended claims. Also, those having ordinary knowledge in this technical field should understand that various modifications and variations can be made without departing from the scope of the present invention.

Claims

1. In a method for manufacturing a three-dimensional NAND flash memory array including vertical NAND channels in which polysilicon extends vertically on a substrate, a metal film forming step of injecting a metal to form a metal film along sidewalls of the polysilicon; a crystal phase growth step of irradiating a first microwave to grow crystal phase silicon between the metal and the polysilicon; a crystal phase transport step of irradiating a second microwave to transport the crystal phase silicon in a bottom direction of the vertical NAND channel; comprising: A method for manufacturing a three-dimensional NAND flash memory array.

2. Further comprising a polysilicon pretreatment step of irradiating a third microwave to pretreat the polysilicon before the metal film forming step, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

3. After the crystal phase transport step, further comprising a defect removal step of annealing in a hydrogen atmosphere to remove defects on the crystal phase silicon, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

4. The defect removal step is performed in a pressure range of 2 atmospheres to 50 atmospheres, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 3.

5. The defect removal step is performed in a temperature range of 200°C to 800°C, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 3.

6. The first microwave is output at 1 KW to 10 KW, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

7. The first microwave is irradiated in a frequency band range of 2.4 GHz to 2.5 GHz, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

8. The crystal phase growth step is performed in a temperature range of 200°C to 600°C, The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

9. The metal is any one selected from nickel (Ni), titanium (Ti), molybdenum (Mo), cobalt (Co), and aluminum (Al), The method for manufacturing a three-dimensional NAND flash memory array according to Claim 1.

Images