Display panel and method for manufacturing the same

Abstract

In an embodiment of the present invention, a display panel and a manufacturing method thereof are disclosed. The display panel includes a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition portions that cover edges of the anodes and expose a part of the anodes. Here, one of the pixel definition portions is arranged to surround one of the anodes, and adjacent pixel definition portions are spaced apart. The pixel definition portion includes a first side surface far from the anode in a direction parallel to the substrate. The first side surface forms a first included angle with the substrate, with the side closer to the substrate, and the first included angle is 35° or more and 45° or less.

Description

Technical Field

[0001] This application relates to the display field, and particularly to a display panel and a manufacturing method thereof.

Background Art

[0002] With the development of display technology, OLED (Organic Light-Emitting Diode) display panels have been widely applied because they have advantages such as high brightness, low power consumption, fast response, high resolution, and high luminous efficiency.

[0003] However, an OLED display panel forms a light-emitting element in an opening by forming an opening in a pixel definition layer formed over the entire layer. Therefore, since it is difficult to remove stress from the pixel definition layer, there is a technical problem of affecting the quality of the display panel.

[0004] Therefore, in order to solve the above technical problem, a display panel and a manufacturing method thereof are desired.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a display panel and a manufacturing method thereof, and can solve the technical problem that since a pixel definition layer is formed over the entire layer of the current display panel, it becomes difficult to remove stress, which affects the quality of the display panel.

Means for Solving the Problems

[0006] In order to solve the above problems, the technical solution provided by this application is as follows.

[0007] The present invention provides a display panel, which includes a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition parts that cover the edges of the anodes and expose a part of the anodes. Here, one of the pixel definition parts is arranged to surround one of the anodes, and adjacent pixel definition parts are arranged at intervals. The pixel definition part includes a first side surface far from the anode in a direction parallel to the substrate. The first side surface forms a first included angle with the substrate on the side close to the substrate, and the first included angle is 35° or more and 45° or less.

[0008] Preferably, the display panel further includes a first metal layer, the first metal layer is sandwiched between the anode and the substrate, the display panel further includes a first insulating layer, the first insulating layer is sandwiched between the first metal layer and the anode, the first insulating layer includes a first via hole, the anode includes a first connection part located in the first via hole, the first connection part is connected to the first metal layer, and the pixel definition part covers the first connection part.

[0009] Preferably, the display panel further includes an active layer, the active layer is sandwiched between the first metal layer and the substrate, the active layer includes a channel part, a first conductor sub - part and a second conductor sub - part located on both opposite sides of the channel part respectively. The first metal layer includes a source and a drain, the source is located in the first conductor sub - part, the drain is located in the second conductor sub - part. Here, at least a part of the source is in contact with the first conductor sub - part on the side close to the active layer, and at least a part of the drain is in contact with the second conductor sub - part on the side close to the active layer.

[0010] Preferably, the display panel further includes a gate, the gate is sandwiched between the source and the drain, the orthographic projection of the gate on the active layer covers the channel part, the display panel further includes a gate insulating layer, and the gate insulating layer is sandwiched between at least the gate and the channel part.

[0011] Preferably, the gate is located in the first metal layer, the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart from each other, the first insulating portion is sandwiched between the channel portion and the gate, the second insulating portion is sandwiched between a part of the source and the first conductor sub-portion, the third insulating portion is sandwiched between a part of the drain and the second conductor sub-portion, an end portion of the source close to the gate is in contact with the first conductor sub-portion, and an end portion of the drain close to the gate is in contact with the second conductor sub-portion.

[0012] Preferably, the gate is located on the side of the first metal layer far from the substrate, there is no insulating layer between the source and the first conductor sub-portion, and there is no insulating layer between the drain and the second conductor sub-portion.

[0013] Preferably, in a plane parallel to the substrate, in a direction from the channel portion toward the first conductor sub-portion, an edge of the source far from the gate extends beyond an edge of the first conductor sub-portion far from the channel portion. In a plane parallel to the substrate, in a direction from the channel portion toward the second conductor sub-portion, an edge of the drain far from the gate extends beyond an edge of the second conductor sub-portion far from the channel portion.

[0014] Preferably, the display panel further includes a second metal layer, the second metal layer is sandwiched between the active layer and the substrate, the second metal layer includes a first light-shielding portion, and a front projection of the active layer on the substrate is located within a front projection of the first light-shielding portion on the substrate. The display panel further includes a buffer layer, the buffer layer is located on the side of the active layer close to the substrate, and the buffer layer covers the second metal layer.

[0015] Preferably, the first insulating layer includes a passivation layer on the side close to the substrate, the buffer layer is sandwiched between the second metal layer and the active layer, a side of the buffer layer far from the substrate is in direct contact with the active layer and the passivation layer, and a side of the buffer layer close to the substrate is in direct contact with the second metal layer and the substrate.

[0016] Preferably, when the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart from each other, an end of the second insulating portion that is far from the first insulating portion contacts the buffer layer, and an end of the third insulating portion that is far from the first insulating portion contacts the buffer layer.

[0017] Preferably, the first insulating layer further includes a second via hole, and the second via hole is located on one side of the active layer. The buffer layer includes a third via hole, the third via hole communicates with the second via hole, and the anode is connected to the first light-shielding portion through the second via hole and the third via hole. The anode includes a second connection portion, and a front projection of the pixel defining portion on the substrate covers a front projection of the second connection portion on the substrate.

[0018] Preferably, the gate insulating layer includes a fourth via hole, the fourth via hole is located on a side of the second insulating portion that is far from the active layer, the buffer layer includes a fifth via hole, the fourth via hole communicates with the fifth via hole, and the source is connected to the first light-shielding portion through the fourth via hole and the fifth via hole.

[0019] Preferably, the gate insulating layer includes a sixth via hole, the sixth via hole is located on a side of the third insulating portion that is far from the active layer, the buffer layer includes a seventh via hole, the sixth via hole communicates with the seventh via hole, and the drain is connected to the first light-shielding portion through the sixth via hole and the seventh via hole.

[0020] Preferably, the display panel includes a display area and a non-display area located on at least one side of the display area, the display panel further includes a terminal located in the non-display area, and the terminal is located in the first metal layer. Here, the terminal includes a first type of terminal, and the first type of terminal is connected to the second metal layer.

[0021] Preferably, when the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart from each other, the gate insulating layer further includes a fourth insulating portion sandwiched between the terminal and the buffer layer, the gate insulating layer further includes an eighth via hole, the eighth via hole penetrates the fourth insulating portion, the buffer layer includes a ninth via hole, the ninth via hole penetrates the buffer layer sandwiched between the wiring of the second metal layer and the fourth insulating portion, and a front projection of the eighth via hole on the substrate covers a front projection of the ninth via hole on the substrate. The first type of terminal includes a first type of terminal connection portion, the first type of terminal connection portion is located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the wiring of the second metal layer, and the first type of terminal connection portion contacts the wiring of the second metal layer.

[0022] Preferably, the pixel defining portion has an overlapping portion with the anode, and a width of a front projection of the overlapping portion on the substrate is 2 μm or more.

[0023] Preferably, the display panel further includes an organic layer located on a side of the anode far from the substrate, and the organic layer includes a light emitting layer. The pixel defining portion includes a second side surface close to the anode in a direction parallel to the substrate, and a front projection of the anode on the substrate and a front projection of the second side surface on the substrate both cover a front projection of the light emitting layer on the substrate.

[0024] Preferably, a side of the second side surface close to the anode forms a second included angle of 35° or more with the anode, and the second included angle is 35° or more and 45° or less.

[0025] The present invention further provides a method for manufacturing a display panel, and the method for manufacturing the display panel includes: providing a substrate; forming an anode material layer on the substrate; forming a pixel defining material layer on the anode material layer; Forming the anode material layer and the pixel defining material layer into a plurality of anodes and a plurality of pixel defining portions respectively by a first patterning process, Here, the pixel defining portion covers an edge of the anode and exposes a part of the anode. One of the pixel defining portions is arranged to surround one of the anodes, and adjacent pixel defining portions are arranged at intervals.

[0026] Preferably, before forming the anode material layer on the substrate, Forming a semiconductor material layer on the substrate, Forming the first metal material layer on the semiconductor material layer such that the first metal material layer is in direct contact with the semiconductor material layer, Further including forming the semiconductor material layer and the first metal material layer into a semiconductor layer and a first metal layer respectively by a second patterning process, Here, the first metal layer includes a source and a drain, and the source and the drain are located on opposite sides of the semiconductor layer respectively.

Advantages of the Invention

[0027] In the present invention, by arranging the pixel defining portions in a one-to-one correspondence with the anodes, adjacent pixel defining portions are arranged at intervals, reducing the stress received by the pixel defining portions, making the gradient of the first side surface of the pixel defining portion gentler, increasing the contact area between the pixel defining portion and the adjacent film layer, strengthening the robustness of the bond between the pixel defining portion and the adjacent film layer, and improving the product quality of the display panel.

Brief Description of the Drawings

[0028]

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Embodiments for Carrying Out the Invention

[0029] This application provides a display module. To make the objectives, technical solutions, and effects of this application clearer, the following describes the application in more detail by way of examples with reference to the accompanying drawings. It should be understood that the embodiments described in this specification are only for explaining this application and are not intended to limit this application.

[0030] Conventionally, since the pixel definition layer in the display panel is formed throughout the entire layer, it is difficult to remove the stress of the pixel definition layer, which causes a technical problem of affecting the quality of the display panel.

[0031] Referring to FIGS. 1 and 2, an embodiment of the present invention provides a display panel 100, and the display panel 100 includes: a substrate 101, a plurality of anodes 102 located on the substrate 101, and a plurality of pixel definition parts 103 that cover the edges of the anodes 102 and expose a part of the anodes 102. Here, one of the pixel definition parts 103 is arranged to surround one of the anodes 102, and adjacent pixel definition parts 103 are arranged at intervals.

[0032] The pixel definition part 103 includes a first side surface 103a far from the anode 102 in a direction parallel to the substrate 101. The side of the first side surface 103a close to the substrate 101 forms a first included angle α with the substrate 101, and the first included angle α is 35° or more and 45° or less.

[0033] The embodiment of the present invention arranges the pixel definition parts 103 in a one-to-one correspondence with the anodes 102, so that adjacent pixel definition parts 103 are arranged at intervals, reducing the stress received by the pixel definition parts 103, making the gradient of the first side surface 103a of the pixel definition parts 103 gentler, increasing the contact area between the pixel definition parts 103 and adjacent film layers, strengthening the robustness of the bond between the pixel definition parts 103 and adjacent film layers, and improving the product quality of the display panel 100.

[0034] The technical solution of the present invention will be described below in conjunction with specific embodiments.

[0035] Referring to FIGS. 1 and 2, in this embodiment, the display panel 100 further includes a first metal layer 104, and the first metal layer 104 is sandwiched between the anode 102 and the substrate 101.

[0036] The display panel 100 further includes a first insulating layer, the first insulating layer is sandwiched between the first metal layer 104 and the anode 102, the first insulating layer includes a first via hole H1, the anode 102 includes a first connection portion located in the first via hole H1, the first connection portion is connected to the first metal layer 104, and the pixel defining portion 103 covers the first connection portion.

[0037] In some embodiments, the first metal layer 104 may be a plurality of layers or a single layer made of a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy containing these metals. For example, the first metal layer 104 may be a molybdenum-titanium alloy, a molybdenum-titanium alloy / copper / molybdenum-titanium alloy (MoTi / Cu / MoTi) three-layer laminated structure composed of copper.

[0038] When the first metal layer 104 is a MoTi / Cu / MoTi three-layer laminated structure composed of a MoTi layer, a Cu layer, and a MoTi layer, the thickness of the MoTi layer on the side close to the substrate 101 is 250 Å to 350 Å, the thickness of the Cu layer is 4200 Å to 6500 Å, and the thickness of the MoTi layer on the side far from the substrate 101 is 400 Å to 500 Å.

[0039] In some embodiments, the anode 102 comprises a material having a high work function. The anode 102 comprises any one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc., which are transparent conductive materials having a relatively high work function. In addition to the conductive materials described above, the anode 102 may further comprise a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof. The anode 102 may be composed of a single layer or a multilayer of transparent conductive materials and / or reflective conductive materials. For example, the anode 102 may have a three-layer stacked structure of IZO / Ag / IZO composed of IZO and Ag. At this time, the thickness of the IZO layer closer to the substrate 101 is 100 Å to 200 Å, the thickness of the Ag layer is 1000 Å to 1500 Å, and the thickness of the IZO layer farther from the substrate 101 is 700 Å to 1000 Å.

[0040] Referring to FIGS. 1 and 2, in this embodiment, the pixel defining portion 103 is disposed to surround the anode 102 and has a pixel defining opening for exposing the anode 102.

[0041] In some embodiments, the material of the pixel defining portion 103 is selected from organic materials such as positive photoresist materials or negative photoresist materials. The material of the pixel defining portion 103 can be used as a photoresist. The pixel defining portion 103 and the anode 102 are formed by the same patterning process, enabling production with a smaller number of steps and reducing the process cost. The thickness of the pixel defining portion 103 may be 2.8 μm to 3.7 μm, for example, 3 μm, 3.2 μm, 3.4 μm, 3.5 μm, 3.6 μm, etc., so as to form a pixel defining opening with sufficient depth.

[0042] In some embodiments, the first insulating layer includes a passivation layer 112 closer to the substrate 101 and a planarization layer 113 farther from the substrate 101. The passivation layer 112 covers at least the first metal layer 104, and the planarization layer 113 serves to provide a flat surface for forming the anode 102. The anode 102 can be directly formed on the side of the planarization layer 113 and farther from the buffer layer 111. Further, the first insulating layer may be composed of the passivation layer 112 and the planarization layer 113.

[0043] The material of the passivation layer 112 is selected from inorganic materials such as silicon nitride compounds or silicon oxide compounds. The material of the planarization layer 113 may be selected from organic materials such as positive photoresist materials or negative photoresist materials. Thereby, the passivation layer 112 and the planarization layer 113 are formed by the same patterning process, enabling manufacturing with a smaller number of steps and reducing the process cost.

[0044] To completely cover the first metal layer 104, the thickness of the passivation layer 112 is 3500 Å to 5000 Å, and may be, for example, 3600 Å, 3800 Å, 4000 Å, 4200 Å, 4500 Å, 4800 Å, etc. To provide a flat surface, the thickness of the planarization layer 113 is 3500 Å to 5000 Å, and may be, for example, 3600 Å, 3800 Å, 4000 Å, 4200 Å, 4500 Å, 4800 Å, etc.

[0045] The first via hole H1 exposes the first metal layer 104. The anode 102 includes a first connection portion located in the first via hole H1. The first connection portion contacts the first metal layer 104 within the first via hole H1, thereby realizing the connection between the anode 102 and the first metal layer 104. Since the first connection portion is filled in the first via hole H1 to be connected to the first metal layer 104, the pixel defining portion 103 covers the first via hole H1 so that an organic layer (e.g., a light-emitting layer) formed on the anode 102 does not fall into the first via hole H1.

[0046] When the first insulating layer is composed of the passivation layer 112 and the planarization layer 113, the first via hole H1 includes a first sub-via hole located in the passivation layer 112 and a second sub-via hole located in the planarization layer 113.

[0047] In some embodiments, the substrate 101 may be a rigid substrate or a flexible substrate. When the substrate 101 is a rigid substrate, the substrate 101 may be a glass substrate. When the substrate 101 is a flexible substrate, the material of the substrate 101 may be polyimide.

[0048] Referring to FIGS. 1 and 2, in this embodiment, the first metal layer 104 includes a source 106 and a drain 107. The first via hole H1 exposes the source 106, and the first connection portion contacts the source 106. Alternatively, the first metal layer 104 exposes the drain 107, and the first connection portion contacts the drain 107.

[0049] Referring to FIGS. 1 and 2, in this embodiment, the display panel 100 further includes an active layer 105. The active layer 105 is sandwiched between the first metal layer 104 and the substrate 101. The active layer 105 includes a channel portion 105a, and a first conductor sub-portion 105b and a second conductor sub-portion 105c respectively located on opposite sides of the channel portion 105a.

[0050] The source 106 is located in the first conductor sub-portion 105b, and the drain 107 is located in the second conductor sub-portion 105c.

[0051] Here, at least a part of the source 106 has the side close to the active layer 105 in contact with the first conductor sub-portion 105b, and at least a part of the drain 107 has the side close to the active layer 105 in contact with the second conductor sub-portion 105c.

[0052] In some embodiments, the material of the active layer 105 may be selected from conductive oxide materials such as indium gallium zinc oxide (IGZO). In the process of forming the active layer 105, the conductorization of the first conductor sub - part 105b and the second conductor sub - part 105c can be completed by means such as ion implantation or ion bombardment. When the means of ion implantation is used, the doped specific elements or particles include, but are not limited to, H, He, B, Al, N, F, P, Ar, S, etc. When the means of conductorization by plasma bombardment is used, defects (oxygen defects) are formed by bombarding the surface of the material of the active layer 105 with high - energy particles. These oxygen defects generate carriers and increase the conductive characteristics, thereby realizing the conductorization of the first conductor sub - part 105b and the second conductor sub - part 105c.

[0053] In some embodiments, the material of the active layer 105 may be selected from polysilicon.

[0054] In this embodiment, the thickness of the active layer 105 may be 200 Å to 500 Å, and for example, it may be 250 Å, 300 Å, 350 Å, 400 Å, 450 Å, etc.

[0055] Referring to FIGS. 1 and 2, in this embodiment, the display panel 100 further includes a gate 108. The gate 108 is located on the side of the active layer 105 far from the buffer layer 111. The gate 108 is sandwiched between the source 106 and the drain 107, and the orthographic projection of the gate 108 on the active layer 105 covers the channel portion 105a.

[0056] In this embodiment, the display panel 100 further includes a gate insulating layer 109. The gate insulating layer 109 is located on the side of the gate 108 close to the active layer 105, and the gate insulating layer 109 is at least sandwiched between the gate 108 and the channel portion 105a. The planarization layer 113 covers the gate insulating layer 109, the first metal layer 104, and / or the gate 108.

[0057] In some embodiments, the material of the gate 108 may be selected from low-resistance materials such as Al, Ti, Mo, Cu, Ni, or alloys containing these metals, and the gate 108 may have a single-layer or multi-layer structure composed of the above metals or alloys.

[0058] Referring to FIG. 1, in some embodiments, the gate 108 is located in the first metal layer 104, and the source 106, the drain 107, and the gate 108 can be formed using the same material in the same process, enabling manufacturing with a small number of processes and reducing the process cost.

[0059] In some embodiments, the material of the gate insulating film 109 may be selected from at least one of silicon nitride and silicon oxy compounds. The gate insulating film 109 may be composed of a single layer or multiple layers of silicon nitride or silicon oxy compounds. For example, the gate insulating film 109 may have a single-layer structure composed of silicon oxide.

[0060] The thickness of the gate insulating film 109 is 1000 Å to 2000 Å, and may be, for example, 1200 Å, 1500 Å, 1800 Å, etc.

[0061] In some embodiments, the gate 109 includes a first insulating portion, a second insulating portion, and a third insulating portion arranged at intervals. The first insulating portion is sandwiched between the channel portion 105a and the gate 108, the second insulating portion is sandwiched between a part of the source 106 and the first conductor sub-portion 105b, and the third insulating portion is sandwiched between a part of the drain 107 and the second conductor sub-portion 105c.

[0062] The first insulating portion, the second insulating portion, and the third insulating portion are arranged separately, that is, their orthographic projections on the substrate 101 are separated from each other. The space between the first insulating portion and the second insulating portion is cut off, and the space between the first insulating portion and the third insulating portion is cut off. The gate insulating layer 109 includes a first opening sandwiched between the first insulating portion and the second insulating portion, and the gate insulating layer 109 includes a second opening sandwiched between the first insulating portion and the third insulating portion.

[0063] The first insulating portion is sandwiched between the channel portion 105a and the gate 108, that is, in the direction from the substrate 101 toward the first metal layer 104, the channel portion 105a and the gate 108 are respectively located on both sides of the first insulating portion. The side of the gate 108 close to the first insulating portion is in direct contact with the first insulating portion, and the side of the first insulating portion close to the active layer 105 is in direct contact with the channel portion 105a. The orthographic projection of the gate 108 on the substrate 101 is located within the orthographic projection of the first insulating portion on the buffer layer 111, and the orthographic projection of the channel portion 105a on the substrate 101 is located within the orthographic projection of the first insulating portion on the buffer layer 111.

[0064] The second insulating portion is sandwiched between a part of the source 106 and the first conductor sub - portion 105b. The side of the second insulating portion close to the buffer layer 111 is in direct contact with the end of the first conductor portion 105b far from the channel portion 105a. The second insulating portion covers at least a part of the end of the first conductor sub - portion 105b far from the channel portion 105a. The end of the source 106 close to the gate 108 is in contact with the first conductor sub - portion 105b through the first opening, and the end of the source 106 close to the gate 108 covers the end of the second insulating portion close to the first insulating portion.

[0065] The third insulating portion is sandwiched between a part of the source 106 and the second conductor sub-portion 105c. The side of the third insulating portion closer to the buffer layer 111 is in direct contact with the end portion of the second conductor sub-portion 105c far from the channel portion 105a. The third insulating portion covers at least a part of the end portion of the second conductor sub-portion 105c far from the channel portion 105a. The end portion of the drain 107 close to the gate 108 is in contact with the second conductor sub-portion 105c through the second opening, and the end portion of the drain 107 close to the gate 108 covers the end portion of the third insulating portion close to the first insulating portion.

[0066] Referring to FIG. 2, in some embodiments, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c. That is, the source 106 is directly located on the first conductor sub-portion 105b, and the drain 107 is directly located on the second conductor sub-portion 105c. Thereby, it is advantageous that the first metal layer 104 and the active layer 105 are formed by a single patterning process, which simplifies the process and reduces the process cost.

[0067] When there is no insulating layer between the source 106 and the first conductor sub - part 105b, and no insulating layer between the drain 107 and the second conductor sub - part 105c, the gate 108 is located on the side of the first metal layer 104 far from the buffer layer 111, and the gate insulating layer 109 is sandwiched between the channel part 105a and the gate 108. The orthographic projection of the gate 108 on the buffer layer 111 is located within the orthographic projection of the gate insulating layer 109 on the buffer layer 111, and the orthographic projection of the channel part 105a on the buffer layer 111 is located within the orthographic projection of the gate insulating layer 109 on the buffer layer 111. At this time, the material of the gate 108 may have a two - layer structure composed of a Cu layer and a MoTi alloy layer. Here, the Cu layer is located on the side of the gate 108 far from the buffer layer 111. The thickness of the Cu layer is 1800 Å - 4200 Å, and for example, it may be 1900 Å, 2500 Å, 3000 Å, 3500 Å, 4000 Å, etc. The thickness of the MoTi alloy layer is 250 Å - 350 Å, and for example, it may be 280 Å, 300 Å, 320 Å, 340 Å, etc.

[0068] When there is no insulating layer between the source 106 and the first conductor sub - part 105b, and no insulating layer between the drain 107 and the second conductor sub - part 105c, in a plane parallel to the substrate 101, along the direction from the channel part 105a to the first conductor sub - part 105b, the edge of the source 106 far from the gate 108 exceeds the edge of the first conductor sub - part 105b far from the channel part 105a. In the direction from the channel part 105a to the second conductor sub - part 105c, in a plane parallel to the substrate 101, the edge of the drain 107 far from the gate 108 exceeds the edge of the second conductor sub - part 105c far from the channel part 105a.

[0069] In this embodiment, the thin - film transistor device of the display panel 100 is composed of the gate 108, the source 106, the drain 107, and the active layer 105.

[0070] Referring to FIGS. 1 and 2, in this embodiment, the display panel 100 further includes a second metal layer 110, the second metal layer 110 is sandwiched between the active layer 105 and the substrate 101, the second metal layer 110 includes a first light-shielding portion 110a, and the orthographic projection of the active layer 105 on the buffer layer 111 is located within the orthographic projection of the first light-shielding portion 110a on the buffer layer 111. The arrangement of the first light-shielding portion 110a is advantageous for preventing light from the substrate 101 from irradiating the active layer 105 and affecting the operating performance of the active layer 105.

[0071] In some embodiments, the material of the second metal layer 110 may be selected from metal materials such as Al, Ti, Mo, Cu, Ni, or alloys containing these. The second metal layer 110 may be a single layer or multiple layers composed of these metal materials or alloys containing these metal materials. For example, the second metal layer 110 may have a double-layer structure of MoTi / Cu composed of a Cu layer and a MoTi alloy layer. The MoTi alloy layer is located on the side closer to the substrate 101, and the Cu layer is located on the side farther from the substrate 101. Arranging the second metal layer 110 as MoTi / Cu and combining the light-shielding performance of MoTi and the conductivity performance of Cu is advantageous for achieving light shielding while maintaining the conductivity of the wiring in the second metal layer 110. Preferably, the thickness of the MoTi alloy layer is 250 Å to 350 Å, and may be, for example, 280 Å, 300 Å, 320 Å, 340 Å, etc. The thickness of the Cu layer is 2800 Å to 8000 Å, and may be, for example, 2900 Å, 3000 Å, 3500 Å, 4000 Å, 4500 Å, 5000 Å, 5500 Å, 6000 Å, 6500 Å, 7000 Å, 7500 Å, etc.

[0072] The display panel 100 further includes a buffer layer 111, the buffer layer 111 is located on the side closer to the active layer 105, and the buffer layer 111 covers the second metal layer 110.

[0073] The buffer layer 111 is sandwiched between the second metal layer 110 and the active layer 105. The side of the buffer layer 111 far from the substrate 101 is in direct contact with the active layer 105, and the side of the buffer layer 111 far from the substrate 101 is in direct contact with the passivation layer 112.

[0074] In some embodiments, the side of the buffer layer 111 close to the substrate 101 is in direct contact with the second metal layer 110, and the side of the buffer layer 111 close to the substrate 101 is in direct contact with the substrate 101.

[0075] In some embodiments, the material of the buffer layer 111 is selected from at least one of a silicon nitride compound and a silicon oxy compound. The buffer layer 111 may be a single layer or a laminate composed of a silicon nitride compound or a silicon oxy compound. For example, the buffer layer 111 includes a first buffer sublayer and a second buffer sublayer. The material of the first buffer sublayer is a silicon nitride compound, the material of the second buffer sublayer is a silicon oxy compound, the first buffer sublayer is located on the side of the buffer layer 111 close to the substrate 101, and the second buffer sublayer is located on the side of the buffer layer 111 far from the substrate 101. The thickness of the first buffer sublayer is 500 Å to 2000 Å, and may be, for example, 800 Å, 1000 Å, 1200 Å, 1500 Å, 1800 Å, etc. The thickness of the second buffer sublayer is 2000 Å to 3000 Å, and may be, for example, 2200 Å, 2500 Å, 2600 Å, 2800 Å, etc.

[0076] When the first insulating portion, the second insulating portion, and the third insulating portion in which the gate insulating layer 109 is spaced apart are included, the end of the second insulating portion far from the first insulating portion is in contact with the buffer layer 111, and the end of the third insulating portion far from the first insulating portion is in contact with the buffer layer 111.

[0077] In some embodiments, the first light-shielding portion 110a is connected to the source 106, or the first light-shielding portion 110a is connected to the drain 107. The connection between the first light-shielding portion 110a and the source 106 or the drain 107 avoids the electrical drift of the thin-film transistor device caused by the first light-shielding portion 110a, and thus improves the operating performance of the thin-film transistor device.

[0078] Referring to FIG. 2, when the gate 108 is located on the side of the first metal layer 104 far from the buffer layer 111, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the source 106 and the first light-shielding portion 110a are connected via the anode 102, or the drain 107 and the first light-shielding portion 110a are connected via the anode 102. At this time, the first insulating layer further includes a second via hole, the second via hole is located on one side of the active layer 105, the buffer layer 111 includes a third via hole of the buffer layer 111, the third via hole communicates with the second via hole, and the anode 102 is connected to the first light-shielding portion 110a via the second via hole and the third via hole. The anode 102 includes the second connection portion, and the orthographic projection of the pixel defining portion 103 on the substrate 101 covers the orthographic projection of the second connection portion on the substrate 101. Specifically, the buffer layer 111 includes a buffer portion covering the first light-shielding portion 110a, the second via hole penetrates the first insulating layer, the third via hole penetrates the buffer portion of the buffer layer 111, and the orthographic projection of the second via hole on the substrate 101 covers the orthographic projection of the third via hole on the substrate 101. The second via hole and the third via hole expose the first light-shielding portion 110a, and the second connection portion contacts the first light-shielding portion 110a. When the anode 102 is connected to the source 106, the source 106 is connected to the first light-shielding portion 110a via the anode 102. When the anode 102 is connected to the drain 107, the drain 107 is connected to the first light-shielding portion 110a via the anode 102.

[0079] When the first insulating portion, the second insulating portion, and the third insulating portion in which the gate insulating layer 109 is disposed apart from each other are included, the gate insulating layer 109 includes a fourth via hole, the fourth via hole is located on a side far from the active layer 105 of the second insulating portion, the buffer layer 111 includes a fifth via hole, the fifth via hole is located in the buffer layer 111, the fourth via hole communicates with the fifth via hole, and the source 106 is connected to the first light-shielding portion 110a through the fourth via hole and the fifth via hole. Specifically, the buffer layer 111 includes a buffer portion covering the first light-shielding portion 110a, the fourth via hole penetrates the side far from the active layer 105 of the second insulating portion, the fifth via hole penetrates the buffer portion, and the orthographic projection of the fourth via hole on the substrate 101 covers the orthographic projection of the fifth via hole on the substrate 101. The source 106 includes a source 106 connection portion, the source 106 connection portion is located in the fourth via hole and the fifth via hole, the fourth via hole and the fifth via hole expose the first light-shielding portion 110a, and the source 106 connection portion contacts the first light-shielding portion 110a to realize the connection between the source 106 and the first light-shielding portion 110a.

[0080] Preferably, referring to FIG. 1, when the gate insulating layer 109 includes the first insulating portion, the second insulating portion, and the third insulating portion that are spaced apart from each other, the gate insulating layer 109 includes a sixth via hole that penetrates the side of the third insulating portion far from the active layer 105, the buffer layer 111 includes a seventh via hole that penetrates the buffer layer 111, the sixth via hole communicates with the seventh via hole, and the drain 107 is connected to the first light-shielding portion 110a through the sixth via hole and the seventh via hole. Specifically, the sixth via hole penetrates the side of the third insulating layer far from the active layer 105, the seventh via hole penetrates the buffer portion, and the orthographic projection of the sixth via hole on the substrate 101 covers the orthographic projection of the seventh via hole on the substrate 101. The drain 107 includes a drain 107 connection portion, the drain 107 connection portion is located in the sixth via hole and the seventh via hole, the sixth via hole and the seventh via hole expose the first light-shielding portion 110a, and the drain 107 connection portion contacts the first light-shielding portion 110a to realize the connection between the drain 107 and the first light-shielding portion 110a.

[0081] In this embodiment, the display panel 100 includes a display area and a non-display area located on at least one side of the display area, the display panel 100 further includes a terminal located in the non-display area, and the terminal is located in the first metal layer 104.

[0082] The non-display area has a plurality of terminals including a first type of terminal connected to the second metal layer 110. The second metal layer 110 further includes wirings of the second metal layer, and the first type of terminal is connected to the wirings of the second metal layer.

[0083] When including the first insulating portion, the second insulating portion, and the third insulating portion where the gate insulating layer 109 is disposed in a spaced-apart manner, the gate insulating layer 109 further includes a fourth insulating portion sandwiched between the terminal and the buffer layer 111. The gate insulating layer 109 further includes an eighth via hole penetrating the fourth insulating portion. The buffer layer 111 includes a ninth via hole penetrating the buffer layer 111 between the wiring of the second metal layer and the fourth insulating portion. A front projection of the eighth via hole on the substrate 101 covers a front projection of the ninth via hole on the substrate 101. The first type of terminal includes a first type of terminal connection portion. The first type of terminal connection portion is located in the eighth via hole and the ninth via hole. The eighth via hole and the ninth via hole expose the wiring of the second metal layer. The first type of terminal connection portion is in contact with the wiring of the second metal layer.

[0084] When the gate 108 is located on a side of the buffer layer 111 of the first metal layer 104 far away, there is no insulating layer between the source 106 and the first conductor sub-portion 105b, and there is no insulating layer between the drain 107 and the second conductor sub-portion 105c, the buffer layer 111 includes a tenth via hole. The tenth via hole penetrates the buffer layer 111 between the wiring of the second metal layer and the first type of terminal. The first type of terminal includes a first type of terminal connection portion. The first type of terminal connection portion is located in the tenth via hole. The tenth via hole exposes the wiring of the second metal layer. The first type of terminal connection portion is in contact with the wiring of the second metal layer.

[0085] In some embodiments, the pixel definition portion 103 has an overlapping portion with the anode 102. The width of the orthographic projection of the overlapping portion on the substrate 101 is 2 μm or more, so that the exposure of the edge of the anode 102 due to process errors can be avoided, and the first connection portion and / or the second connection portion can be easily covered. The anode 102 has a central portion not covered by the pixel definition portion 103 and a peripheral portion covered by the pixel definition portion 103. The orthographic projection of the peripheral portion on the substrate 101 overlaps with the orthographic projection of the overlapping portion on the substrate 101. The overlapping portion includes a first side close to the central portion and a second side far from the central portion. The width of the orthographic projection of the overlapping portion on the substrate 101 is 2 μm or more, that is, the minimum distance between the first side and the second side is 2 μm or more.

[0086] In some embodiments, the distance between adjacent anodes 102 is 7 μm or more, so that a sufficient distance can be provided between the pixel definition portions 103 while ensuring sufficient resolution. Thereby, the stress received by the pixel definition portion 103 can be relieved, and the light emission rate of the display panel 100 can be improved.

[0087] Referring to FIGS. 1 and 2, in this embodiment, the flat layer 113 is parallel to the substrate 101, the pixel definition portion 103 is in direct contact with the flat layer 113, and the first included angle α is equal to the included angle between the first side surface 103a and the flat layer 113. The first included angle α is 35° or more and the first included angle α is 45° or less. For example, the first included angle α may be 36°, 37°, 38°, 39°, 40°, 41°, 42°, 43°, 44°, etc. Since the included angle value of the first included angle α is within the above range, the gradient of the first side surface 103a is made gentler, and while the height remains unchanged, the total surface area of the pixel definition portion 103 is increased, which is advantageous for increasing the contact area between the pixel definition portion 103 and the adjacent film layer, strengthening the robustness of the bond between the pixel definition portion 103 and the adjacent film layer, making it difficult for the film layer to separate when the display panel 100 is applied to a bending scenario, and improving the product quality of the display panel 100.

[0088] Referring to FIGS. 1 and 2, in this embodiment, the display panel 100 further includes an organic layer 119 located on the side far from the buffer layer 111 of the anode 102, and the organic layer 119 includes a light-emitting layer 120. The pixel defining portion 103 includes a second side surface 103b adjacent to the anode 102 in a direction parallel to the substrate 101, and the orthographic projection of the anode 102 on the substrate 101 and the orthographic projection of the second side surface 103b on the substrate 101 both cover the orthographic projection of the light-emitting layer 120 on the substrate 101. That is, the light-emitting layer 120 is disposed within the pixel defining opening, and the edge of the light-emitting layer 120 does not extend beyond the second side surface 103b. By the orthographic projection of the anode 102 on the buffer layer 111 and the orthographic projection of the second side surface 103b on the buffer layer 111 both covering the orthographic projection of the light-emitting layer 120 on the buffer layer 111, it is advantageous to avoid light-emitting layers having different emission colors (for example, red, green, blue) from mixing outside the pixel defining portion 103 and affecting the display quality of the display panel 100.

[0089] Referring to FIGS. 1 and 2, in some embodiments, the side of the second side surface 103b close to the anode 102 forms a second included angle β of 35° or more with the anode 102, and the second included angle β is 45° or less. For example, the second included angle β may be 36°, 37°, 38°, 39°, 40°, 41°, 42°, 43°, 44°, etc. When the second included angle β is within the above range, the second side surface 103b is gentler, which is advantageous for forming the light-emitting layer 120 so as not to extend beyond the second side surface 103b.

[0090] In this embodiment, the organic layer 119 includes a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer located within the pixel defining opening. The hole injection layer is located on the side far from the buffer layer 111 of the anode 102, and the hole injection layer, the hole transport layer, the light-emitting layer, the electron transport layer, and the electron injection layer are sequentially stacked and arranged.

[0091] In this embodiment, the display panel 100 further includes a cathode, and the cathode covers at least the side of the substrate 101 far from the organic layer 119.

[0092] The anode 102, the cathode, and the organic layer 119 constitute a light-emitting element.

[0093] In the embodiment of the present invention, by arranging the pixel definition part 103 in a one-to-one correspondence with the anode 102, the distance between adjacent pixel definition parts 103 reduces the stress received by the pixel definition part 103, makes the gradient of the first side surface 103a of the pixel definition part 103 gentler, increases the contact area between the pixel definition part 103 and an adjacent film layer, strengthens the robustness of the bond between the pixel definition part 103 and an adjacent film layer, and improves the product quality of the display panel 100.

[0094] Referring to FIGS. 1 to 3 and FIGS. 4a to 4m, the embodiment of the present invention further provides a manufacturing method of the display panel 100. The manufacturing method of the display panel 100 includes: S100, providing the substrate 101; S200, forming an anode material layer on the substrate 101; S300, forming a pixel definition material layer on the anode material layer; S400, forming the anode material layer and the pixel definition material layer into a plurality of anodes 102 and a plurality of pixel definition parts 103 respectively by a first patterning process.

[0095] Here, the pixel definition part 103 covers the edge of the anode 102 and exposes a part of the anode 102. One pixel definition part 103 is arranged to surround one anode 102, and adjacent pixel definition parts 103 are arranged at intervals.

[0096] The pixel definition part 103 includes a first side surface 103a far from the anode 102 in a direction parallel to the substrate 101, and a side closer to the substrate 101 of the first side surface 103a forms a first included angle α with the substrate 101, where the first included angle α is not less than 35° and not more than 45°. The pixel definition part 103 includes a first side surface 103a far from the anode 102 in a direction parallel to the substrate 101, and a side closer to the substrate 101 of the first side surface 103a forms a first included angle α with the substrate 101, where the first included angle α is not less than 35° and not more than 45°.

[0097] In this embodiment, the material of the substrate 101 has been described in detail in the aforementioned display panel 100, so it will not be described here.

[0098] In this embodiment, the anode material layer includes a material with a high work function. The anode material layer is a transparent conductive substance with a relatively high work function, and includes any one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc. In addition to the above-mentioned conductive materials, the anode material layer may include a reflective material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a combination thereof. The anode material layer may be composed of a single-layer or multi-layer transparent conductive material and / or reflective conductive material. For example, the anode material layer may have a three-layer laminated structure of IZO / Ag / IZO composed of IZO and Ag. The anode material layer can be formed by physical vapor deposition or chemical vapor deposition. The anode material layer may be formed by physical vapor deposition or chemical vapor deposition.

[0099] In this embodiment, the material of the pixel definition material layer is selected from organic materials, such as positive photoresist materials or negative photoresist materials. The pixel definition material layer can be used as a photoresist. The pixel definition portion 103 and the anode 102 are formed by the same patterning process, enabling manufacturing with a small number of process steps and reducing the process cost.

[0100] In some embodiments, step S400 includes the following.

[0101] S410, exposing the pixel definition material layer using a first mask.

[0102] The first mask may be a halftone mask.

[0103] S420, after the pixel definition material layer is developed, a first photoresist region, a second photoresist region, and a first photoresist-free region are formed.

[0104] Here, the thickness of the pixel definition material layer in the first photoresist region is greater than the thickness of the pixel definition material layer in the second photoresist region.

[0105] S430, to form the anode 102, a first etching process is used to remove the anode material layer corresponding to the first photoresist-free region.

[0106] The first etching process is a wet etching process. When the anode material layer is a three-layer stacked structure of an IZO material layer / Ag material layer / IZO material layer formed of an IZO material layer and an Ag material layer, a first etching agent is used in the first etching process. The first etching agent includes phosphoric acid, nitric acid, etc., and is used to etch the Ag material layer and the IZO material layer.

[0107] S440. Remove the pixel definition material layer within the second photoresist region, retain the pixel definition material layer within the first photoresist region, and form it on the pixel definition portion 103.

[0108] The pixel definition material layer within the second photoresist region can be removed by an ashing process.

[0109] In some embodiments, step S400 further includes the following.

[0110] S450. Clean the pixel definition portion 103 and the anode 102.

[0111] S460. Perform a heat treatment on the pixel definition portion 103.

[0112] The materials, thickness, and structure of the anode 102 and the pixel definition portion 103 have been described in detail in the aforementioned display panel 100, so they will not be described here.

[0113] In this embodiment, before step S200, it includes the following.

[0114] Referring to S500 in FIG. 4b, a second metal layer 110 is formed on the substrate 101.

[0115] In this embodiment, the materials, thickness, and structure of the second metal layer 110 have been described in detail in the aforementioned display panel 100, so they will not be described here.

[0116] Referring to S600 in FIG. 4c, a buffer material layer 115 is formed on the second metal layer 110.

[0117] The buffer material layer 115 covers the second metal layer 110 and the substrate 101.

[0118] S700. Form a thin film transistor layer on the buffer material layer 115.

[0119] S800. Form a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0120] In this embodiment, since the materials, thicknesses, structures, etc. of the passivation layer 112 and the planarization layer 113 have been described in detail in the aforementioned display panel 100, they will not be described here.

[0121] The passivation material layer covers the thin film transistor layer, and the planarization material layer covers the passivation material layer. The material of the planarization material layer is a positive photoresist material or a negative photoresist material.

[0122] Referring to FIGS. 4d to 4h, in some embodiments, step S700 includes the following.

[0123] S710. Form a semiconductor layer 114 and a first metal layer 104 on the buffer layer 111.

[0124] Step S710 includes the following.

[0125] S711. Form a semiconductor material layer 116 on the substrate 101.

[0126] S712. Form a first metal material layer 117 on the semiconductor material layer 116, and the first metal material layer 117 is in direct contact with the semiconductor material layer 116.

[0127] S713. Form the semiconductor material layer 116 and the first metal material layer 117 into a semiconductor layer 114 and a first metal layer 104 respectively by a second patterning process.

[0128] Here, the first metal layer 104 includes a source 106 and a drain 107, and the source 106 and the drain 107 are located on opposite sides of the semiconductor layer 114 respectively.

[0129] There is no insulating layer between the source 106 and the first conductor sub - part 105b, and there is no insulating layer between the drain 107 and the second conductor sub - part 105c.

[0130] Step S713 includes the following.

[0131] S713a: Form a first photoresist material layer 118 on the first metal material layer.

[0132] S713b: Expose the first photoresist material layer 118 using a second mask.

[0133] The second mask may be a halftone mask.

[0134] S713c: After the first photoresist material layer 118 is developed, a third photoresist region, a fourth photoresist region, and a second photoresist - free region are formed.

[0135] Here, the thickness of the first photoresist material layer 118 in the third photoresist region is greater than the thickness of the first photoresist material layer 118 in the fourth photoresist region.

[0136] S713d: To form the semiconductor layer 114, use a second etching process to remove the semiconductor material layer 116 and the first metal material layer 117 corresponding to the second photoresist - free region.

[0137] The second etching process may be a wet etching process.

[0138] S713e: Use an ashing process to remove the first photoresist material layer 118 in the fourth photoresist region.

[0139] Step S713f: To form the first metal layer 104, use a third etching process to remove the first metal material layer 117 corresponding to the fourth photoresist region.

[0140] The third etching step may be a wet etching step. When the first metal material layer has a three-layer laminated structure of MoTi / Cu / MoTi composed of a MoTi layer, a Cu layer, and a MoTi layer, a second etchant is used in the third etching step. The second etchant does not contain a fluorine element so as to avoid damage to the semiconductor layer 114. The second etchant is used for the first metal material layer and contains components such as hydrogen peroxide.

[0141] S713g, Remove the first photoresist material layer 118.

[0142] S720, Form a gate insulating layer 109 and a gate 108 between the source 106 and the drain 107.

[0143] Step S720 includes the following.

[0144] S721, Form a gate insulating material layer on the first metal layer 104.

[0145] S722, Form a gate material layer on the gate insulating material layer.

[0146] S723, Form the gate insulating material layer and the gate material layer into the gate insulating layer 109 and the gate 108 respectively by a third patterning process.

[0147] Step S723 includes the following.

[0148] S723a, Form a second photoresist material layer on the gate material layer.

[0149] S723b, Expose the second photoresist material layer using a third mask.

[0150] S723c, After the second photoresist material layer is developed, a fifth photoresist region and a third photoresist-free region are formed.

[0151] S723d. To form the gate 108, remove the gate material layer corresponding to the third photoresist-free region using a fourth etching process.

[0152] The fourth etching process may be a wet etching process.

[0153] S723e. To form the gate insulating film 109, remove the gate insulating material layer corresponding to the third photoresist stress region using a fifth etching process.

[0154] The fifth etching process may be a dry etching process.

[0155] S723f. Remove the second photoresist material layer.

[0156] S730. To form the active layer 105, conductify the semiconductor layer 114.

[0157] The conductification process may be means such as ion implantation or ion bombardment to form the active layer 105, and the active layer 105 includes a channel portion 105a, and a first conductor sub-portion 105b and a second conductor sub-portion 105c respectively located on both opposite sides of the channel portion 105a.

[0158] In this embodiment, the materials, thicknesses, and structures of the gate insulating film 109, the first metal layer 104, and the active layer 105 have been described in detail in the aforementioned display panel 100, so they will not be described here.

[0159] Referring to FIG. 4i, when forming the thin film transistor layer in steps S710 to S730, step S800 includes the following.

[0160] S810. Form the passivation layer 112 and the buffer layer 111.

[0161] Step S810 includes the following.

[0162] S811. Form a third photoresist material layer on the passivation material layer.

[0163] S812. Expose the third photoresist material layer using a fourth mask.

[0164] S813. After the third photoresist material layer is developed, a sixth photoresist region and a fourth photoresist-free region are formed.

[0165] The fourth photoresist-free region includes a first photoresist-free sub-region and a second photoresist-free sub-region.

[0166] S814. To form the passivation layer 112 and the buffer layer 111, use a sixth etching process to remove the passivation material layer corresponding to the first photoresist-free sub-region, and remove the passivation material layer corresponding to the second photoresist-free sub-region and the buffer material layer 115.

[0167] The sixth etching process may be a dry etching process.

[0168] S815. Remove the third photoresist material layer.

[0169] S820. Form a planarization layer 113.

[0170] Step S820 includes the following.

[0171] S821. Expose the planarization material layer using a fifth mask.

[0172] S822. After the planarization material layer is developed, via holes of the first planarization layer 113 and via holes of the second planarization layer 113 are formed.

[0173] The flat layer 113 and the passivation layer 112 constitute a first insulating layer. What is formed by removing the via hole of the first flat layer 113 and the passivation material layer corresponding to the first photoresist-free sub-region is formed in the first via hole H1 of the first insulating layer, and the anode 102 is connected to the source 106 or the drain 107 through the first via hole H1. What is formed by removing the via hole of the second flat layer 113 and the passivation material layer corresponding to the second photoresist-free sub-region is formed in the second via hole of the first insulating layer. What is formed by removing the buffer material layer 115 corresponding to the second photoresist-free sub-region is formed in the third via hole, and the third via hole communicates with the second via hole. The anode 102 is connected to the first light-shielding portion 110a in the second metal layer 110 through the second via hole.

[0174] By removing the passivation material layer corresponding to the first photoresist-free sub-region, the source 106 or the drain 107 is exposed, and while removing the passivation material layer corresponding to the first photoresist-free sub-region, the passivation material layer corresponding to the second photoresist-free sub-region and the buffer material layer 115 are removed, so that the source 106 or the drain 107 is over-etched. Since using dry etching can avoid damage to the metal material, it is preferable that the passivation layer 112 and the buffer layer 111 are formed by the same etching process, and the process cost can be reduced.

[0175] Referring to FIGS. 4j to 4l, in some embodiments, step S700 includes the following.

[0176] S740, forming a semiconductor layer 114 on the buffer layer 111.

[0177] In some embodiments, step S740 includes the following.

[0178] S741. Form a semiconductor material layer on the buffer layer 111.

[0179] S742. Form the semiconductor layer 114 from the semiconductor material layer by a fourth patterning process.

[0180] Step S742 includes the following.

[0181] S742a. Form a fourth photoresist material layer on the semiconductor material layer.

[0182] S742b. Expose the fourth photoresist material layer using a sixth mask.

[0183] S742c. After the fourth photoresist material layer is developed, a seventh photoresist region and a fifth photoresist-free region are formed.

[0184] S742d. To form the semiconductor layer 114, remove the semiconductor material layer corresponding to the fifth photoresist-free region using a seventh etching process.

[0185] The seventh etching process may be a wet etching process.

[0186] S742e. Remove the fourth photoresist material layer.

[0187] S750. Form the gate insulating film 109 and the buffer layer 111.

[0188] Step S750 includes the following.

[0189] S751. Form a gate insulating material layer on the semiconductor layer 114, and the gate insulating material layer covers the semiconductor layer 114 and the buffer material layer 115.

[0190] S752. The gate insulating material layer forms the semiconductor layer 114 by a fifth patterning process.

[0191] Step S752 includes the following:

[0192] S752a. Form a fifth photoresist material layer on the gate insulating material layer.

[0193] S752b. Expose the fifth photoresist material layer using a seventh mask.

[0194] S752c. After the fifth photoresist material is developed, an eighth photoresist region and a sixth photoresist-free region are formed.

[0195] The sixth photoresist-free region includes a third photoresist-free sub-region, a fourth photoresist-free sub-region, and a fifth photoresist-free sub-region.

[0196] S752d. Using an eighth etching process, remove the gate insulating material layer corresponding to the third photoresist-free sub-region and the fourth photoresist-free sub-region, the gate insulating material layer corresponding to the fifth photoresist-free sub-region, and the buffer material layer 115 to form the gate insulating layer 109 and the buffer layer 111.

[0197] The eighth etching process may be a dry etching process.

[0198] The gate insulating layer 109 includes a first insulating portion, a second insulating portion, and a third insulating portion. Remove the gate insulating material layer and the buffer layer 111 corresponding to the third photoresist sub-region, the fourth photoresist sub-region, and the fifth photoresist sub-region to form a first opening, a second opening, and a fourth via hole or a sixth via hole of the gate insulating layer 109, and a fifth via hole or a seventh via hole of the buffer layer 111, respectively.

[0199] The fourth via hole is located on the side far from the active layer 105 of the second insulating portion. The buffer layer 111 includes a fifth via hole. The fourth via hole communicates with the fifth via hole. The source 106 and the first light-shielding portion 110a of the second metal layer 110 are connected through the fourth via hole and the fifth via hole. Alternatively, the sixth via hole is located on the side far from the active layer 105 of the third insulating portion. The buffer layer 111 includes a seventh via hole. The sixth via hole communicates with the seventh via hole. The drain 107 and the first light-shielding portion 110a are connected through the sixth via hole and the seventh via hole.

[0200] S760. Form the active layer 105 in the semiconductor layer 114.

[0201] Using the first opening and the second opening, the semiconductor layer 114 forms the active layer 105 by conductivity treatment.

[0202] The conductivity treatment may be in a manner such as ion implantation or ion bombardment.

[0203] Step S770. Form the first metal layer 104 on the gate insulating film 109.

[0204] The first metal layer 104 includes a source 106, a drain 107, and a gate 108.

[0205] Step S770 includes the following.

[0206] S771. Form a first metal material layer on the gate insulating layer 109.

[0207] S772. Form the first metal layer 104 from the first metal material layer by a sixth patterning process.

[0208] Step S772 includes the following.

[0209] S772a. Form a sixth photoresist material layer on the first metal material layer.

[0210] S772b. Expose the sixth photoresist material layer using the eighth mask.

[0211] S772c. After the sixth photoresist material layer is developed, a ninth photoresist region and a seventh photoresist-free region are formed.

[0212] The ninth photoresist region includes a first photoresist sub-region, a second photoresist sub-region, and a third photoresist sub-region.

[0213] Step S772d. To form the first metal layer 104, remove the first metal material layer corresponding to the seventh photoresist-free region using a ninth etching process.

[0214] The first metal material layers corresponding to the first photoresist sub-region, the second photoresist sub-region, and the third photoresist sub-region are respectively formed on the source 106, the drain 107, and the gate 108.

[0215] The ninth etching process may be a wet etching process.

[0216] S772e. Remove the sixth photoresist material layer.

[0217] In this embodiment, the materials, thicknesses, and structures of the gate insulating film 109, the first metal layer 104, and the active layer 105 have been described in detail in the aforementioned display panel 100, so they will not be described here.

[0218] Referring to FIG. 4m, when forming the thin film transistor layer in steps S740 to S770, step S800 includes the following.

[0219] S830. Form a passivation layer 112 and a planarization layer 113 on the thin film transistor layer.

[0220] Step S830 includes the following.

[0221] S831. Form a passivation material layer on the thin film transistor layer.

[0222] S832. Form a planarizing material layer on the passivation material layer.

[0223] The material of the planarizing material layer is selected from a positive photoresist material or a negative photoresist material.

[0224] S834. Form the passivation layer 112 and the planarization layer 113 on the passivation material layer and the planarizing material layer respectively by a seventh patterning process.

[0225] Step S834 includes the following.

[0226] S834a. Expose the planarizing material layer using an eighth mask.

[0227] S834b. After the planarizing material layer is developed to form a tenth photoresist region and an eighth photoresist-free region in order to form the planarization layer 113.

[0228] S834c. Remove the passivation material layer corresponding to the eighth photoresist-free region using a tenth etching process in order to form the passivation layer 112.

[0229] The tenth etching process may be a dry etching process.

[0230] The via hole of the planarization layer 113 and the passivation layer 112 constitute a first insulating layer. What is formed by removing the eighth photoresist-free region and the passivation material layer corresponding to the eighth photoresist-free region is formed in the first via hole H1 of the first insulating layer, and the anode 102 is connected to the first metal material layer through the first via hole H1.

[0231] In this embodiment, step S500 further includes the following.

[0232] S510. Form a second metal material layer on the substrate 101.

[0233] S520. Form the second metal material layer into the second metal layer 110 by an eighth patterning process.

[0234] Step S520 includes the following.

[0235] S520a. Form a seventh photoresist material layer on the second metal material layer.

[0236] S520b. Expose the seventh photoresist material layer using a tenth mask.

[0237] S520c. After the seventh photoresist material is developed, an eleventh photoresist region and a ninth non-photoresist region are formed.

[0238] S520d. To form the second metal layer 110, remove the second metal material layer corresponding to the ninth non-photoresist region using an eleventh etching process.

[0239] The eleventh etching process may be a wet etching process.

[0240] S520e. Remove the seventh photoresist material layer.

[0241] In the method for manufacturing a display panel provided by an embodiment of the present invention, since the manufacturing of the film layer between the substrate 101 and the pixel definition portion 103 only requires 6 patterning processes, the process cost can be reduced and the process efficiency can be improved. Further, the pixel definition portion 103 is arranged in a one-to-one correspondence with the anode 102, and adjacent pixel definition portions 103 are arranged at intervals, reducing the stress received by the pixel definition portion 103, and making the gradient of the first side surface 103a of the pixel definition portion 103 gentler, increasing the contact area between the pixel definition portion 103 and the adjacent film layer, improving the robustness of the bond between the pixel definition portion 103 and the adjacent film layer, and improving the product quality of the manufactured display panel.

[0242] An embodiment of the present invention discloses a display panel and a method for manufacturing the same. The display panel includes a substrate, a plurality of anodes located on the substrate, and a plurality of pixel definition portions that cover the edges of the anodes and expose a part of the anodes. Here, one of the pixel definition portions is arranged to surround one of the anodes, and adjacent pixel definition portions are arranged at intervals. The pixel definition portion includes a first side surface far from the anode in a direction parallel to the substrate. The first side surface forms a first included angle with the substrate on the side close to the substrate, and the first included angle is 35° or more and 45° or less. By arranging the pixel definition portions in a one-to-one correspondence with the anodes, the present invention enables adjacent pixel definition portions to be arranged at intervals, reduces the stress received by the pixel definition portions, makes the gradient of the first side surface of the pixel definition portions gentler, increases the contact area between the pixel definition portions and the adjacent film layers, strengthens the robustness of the bond between the pixel definition portions and the adjacent film layers, and improves the product quality of the display panel.

[0243] Those skilled in the art should understand that equivalent substitutions or modifications can be made based on the technical idea described in the claims and the technical idea, and such modifications or changes belong to the technical scope of the claims.

Claims

1. A substrate, a plurality of anodes located on the substrate, and a plurality of pixel defining parts covering edges of the anodes and exposing a part of the anodes, wherein one of the pixel defining parts is disposed to surround one of the anodes, and adjacent pixel defining parts are spaced apart from each other, the pixel defining part includes a first side surface far from the anode in a direction parallel to the substrate, and the first side surface forms a first included angle with the substrate on the side close to the substrate, and the first included angle is 35° or more and 45° or less, a display panel.

2. The display panel further includes a first metal layer, and the first metal layer is sandwiched between the anode and the substrate, the display panel further includes a first insulating layer, the first insulating layer is sandwiched between the first metal layer and the anode, the first insulating layer includes a first via hole, the anode includes a first connection part located in the first via hole, the first connection part is connected to the first metal layer, and the pixel defining part covers the first connection part, The display panel according to Claim 1.

3. The display panel further includes an active layer, the active layer is sandwiched between the first metal layer and the substrate, and the active layer includes a channel part, and a first conductor sub-part and a second conductor sub-part respectively located on both opposite sides of the channel part, the first metal layer includes a source and a drain, the source is located in the first conductor sub-part, and the drain is located in the second conductor sub-part, wherein at least a part of the source is in contact with the first conductor sub-part on the side close to the active layer, and at least a part of the drain is in contact with the second conductor sub-part on the side close to the active layer, The display panel according to Claim 2.

4. The display panel further includes a gate, the gate is sandwiched between the source and the drain, and a positive projection of the gate on the active layer covers the channel part, The display panel further includes a gate insulating layer, and the gate insulating layer is sandwiched between at least the gate and the channel part, The display panel according to Claim 3.

5. The gate is located in the first metal layer, and the gate insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion that are spaced apart. The first insulating portion is sandwiched between the channel portion and the gate. The second insulating portion is sandwiched between a part of the source and the first conductor sub-portion. The third insulating portion is sandwiched between a part of the drain and the second conductor sub-portion. The end of the source close to the gate is in contact with the first conductor sub-portion, and the end of the drain close to the gate is in contact with the second conductor sub-portion. The display panel according to claim 4.

6. The gate is located on the side of the first metal layer far from the substrate, there is no insulating layer between the source and the first conductor sub-portion, and there is no insulating layer between the drain and the second conductor sub-portion. The display panel according to claim 4.

7. In a plane parallel to the substrate, in the direction from the channel portion toward the first conductor sub-portion, the edge of the source far from the gate extends beyond the edge of the first conductor sub-portion far from the channel portion. In a plane parallel to the substrate, in the direction from the channel portion toward the second conductor sub-portion, the edge of the drain far from the gate extends beyond the edge of the second conductor sub-portion far from the channel portion. The display panel according to claim 6.

8. The display panel further includes a second metal layer. The second metal layer is sandwiched between the active layer and the substrate. The second metal layer includes a first light-shielding portion. The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first light-shielding portion on the substrate. The display panel further includes a buffer layer. The buffer layer is located on the side of the active layer close to the substrate. The buffer layer covers the second metal layer. The display panel according to claim 3.

9. The first insulating layer includes a passivation layer on the side close to the substrate. The buffer layer is sandwiched between the second metal layer and the active layer. The side of the buffer layer far from the substrate is in direct contact with the active layer and the passivation layer. The side of the buffer layer close to the substrate is in direct contact with the second metal layer and the substrate. The display panel according to claim 8.

10. When including a first insulating portion, a second insulating portion, and a third insulating portion in which the gate insulating layer is disposed at intervals, a distal end of the second insulating portion away from the first insulating portion contacts the buffer layer, and a distal end of the third insulating portion away from the first insulating portion contacts the buffer layer. The display panel according to claim 9.

11. The first insulating layer further includes a second via hole, and the second via hole is located on one side of the active layer. The buffer layer includes a third via hole, the third via hole communicates with the second via hole, and the anode is connected to the first light-shielding portion through the second via hole and the third via hole. The anode includes a second connection portion, and a positive projection of the pixel defining portion on the substrate covers a positive projection of the second connection portion on the substrate. The display panel according to claim 8.

12. The gate insulating layer includes a fourth via hole, the fourth via hole is located on a side of the second insulating portion away from the active layer, the buffer layer includes a fifth via hole, the fourth via hole communicates with the fifth via hole, and the source is connected to the first light-shielding portion through the fourth via hole and the fifth via hole. The display panel according to claim 8.

13. The gate insulating layer includes a sixth via hole, the sixth via hole is located on a side of the third insulating portion away from the active layer, the buffer layer includes a seventh via hole, the sixth via hole communicates with the seventh via hole, and the drain is connected to the first light-shielding portion through the sixth via hole and the seventh via hole. The display panel according to claim 8.

14. The display panel includes a display area and a non-display area located on at least one side of the display area, the display panel further includes a terminal located in the non-display area, and the terminal is located in the first metal layer. Here, the terminal includes a first type of terminal, and the first type of terminal is connected to a second metal layer. The display panel according to claim 2.

15. When including a first insulating portion, a second insulating portion, and a third insulating portion in which the gate insulating layer is disposed at intervals, the gate insulating layer further includes a fourth insulating portion sandwiched between the terminal and the buffer layer, the gate insulating layer further includes an eighth via hole, the eighth via hole penetrates the fourth insulating portion, the buffer layer includes a ninth via hole, the ninth via hole penetrates the buffer layer sandwiched between the wiring of the second metal layer and the fourth insulating portion, and the orthographic projection of the eighth via hole on the substrate covers the orthographic projection of the ninth via hole on the substrate. The first type of terminal includes a first type of terminal connection portion, the first type of terminal connection portion is located in the eighth via hole and the ninth via hole, the eighth via hole and the ninth via hole expose the wiring of the second metal layer, and the first type of terminal connection portion contacts the wiring of the second metal layer. The display panel according to claim 14.

16. The pixel defining portion has an overlapping portion with the anode, and the width of the orthographic projection of the overlapping portion on the substrate is 2 μm or more. The display device according to any one of claims 1 to 15.

17. The display panel further includes an organic layer located on the side of the substrate far from the anode, and the organic layer includes a light emitting layer. The pixel defining portion includes a second side surface close to the anode in a direction parallel to the substrate, and the orthographic projection of the anode on the substrate and the orthographic projection of the second side surface on the substrate both cover the orthographic projection of the light emitting layer on the substrate. The display panel according to claim 16.

18. The side of the second side surface close to the anode forms a second included angle of 35° or more with the anode, and the second included angle is 35° or more and 45° or less. The display panel according to claim 17.

19. Providing a substrate; Forming an anode material layer on the substrate; Forming a pixel defining material layer on the anode material layer; Including forming the anode material layer and the pixel defining material layer into a plurality of anodes and a plurality of pixel defining portions respectively by a first patterning process. Here, the pixel defining portion covers the edge of the anode and exposes a part of the anode, one pixel defining portion is arranged to surround one anode, and adjacent pixel defining portions are arranged at intervals. The pixel definition part includes a first side surface far from the anode in a direction parallel to the substrate, and on the first side surface, the side close to the substrate forms a first included angle with the substrate, the first included angle is not less than 35° and not more than 45°. A method for manufacturing a display panel.

20. Before forming an anode material layer on the substrate, forming a semiconductor material layer on the substrate; forming the first metal material layer on the semiconductor material layer so that the first metal material layer is in direct contact with the semiconductor material layer; further comprising forming the semiconductor material layer and the first metal material layer into a semiconductor layer and a first metal layer respectively by a second patterning process, wherein the first metal layer includes a source and a drain, and the source and the drain are respectively located on opposite sides of the semiconductor layer; The method for manufacturing a display panel according to claim 19.

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