LTH and SVLC Hybrid Core Architecture for Lower Cost Component Embedding into Package Substrates

Abstract

Provided are an apparatus and a method for efficiently transferring information as signals through a silicon package substrate. A semiconductor manufacturing process (or process) begins with a relatively thin package substrate core layer and uses a laser to generate an opening in the package substrate at the location of a signal path. The use of each of the relatively thin core layer and the laser enables a reduction in the pitch of the signal path. This process uses a stacked via from one side of the package substrate to the opposite side of the package substrate to generate a signal path within the opening. Additionally, the process forms a package substrate having a plurality of embedded passive components having different thicknesses in different layers of the package substrate. The embedded passive components are used to improve the integrity of the signals of the signal path.

Description

Background Art

[0001] (Description of Related Art) There is an increasing demand for semiconductor packages that provide communication between one or more integrated circuits within a chip package and external components on a motherboard located outside the chip package. Electronic products associated with mobile computing, wearable electronics, and the Internet of Things (IoT) are driving the demand for small packages that utilize vertical signal interconnects. Examples of chip packages used in these products include ball grid array (BGA), chip scale package (CSP), and System in Package (SiP).

[0002] Also, the demand for SiP and more signal interconnects between integrated circuits and printed circuit boards (PCBs) increases the demand for semiconductor package substrates (or package substrates). The package substrate is part of a chip package that provides a mechanical base support and an electrical interface for signal interconnects. Vertical silicon through vias (TSVs) are formed in a silicon package substrate that has connections to a printed circuit board using bump pads. A group of TSVs that form a through-silicon bus is used as an interconnect between a base die, one or more additional integrated circuits, and routing on a printed circuit board (PCB) such as a motherboard or card.

[0003] When transferring information between a transmitter and a receiver, usually, electrical signals are transmitted on a plurality of parallel metal traces. The transmitter transmits an electrical signal across the parallel metal traces. The receiver receives the electrical signal. The metal traces have transmission line effects such as distributed inductance, capacitance, and resistance over their entire length. In modern integrated circuits, the interconnect capacitance reduces signal integrity and signal transfer speed more than the gate capacitance of semiconductor devices. The interconnect capacitance per unit length includes both sidewall fringing capacitance and cross-coupling capacitance. For example, the electromagnetic field for a metal trace conducting a signal and the return current on the ground plane generate electrical interference on adjacent metal traces and adjacent devices.

[0004] To reduce the distortion caused by many spurious sources (transmission line effects), designers provide multiple signal integrity components within or near the metal signal path. These components typically include passive elements arranged in a specific way to prevent noise sources from affecting the shape and amplitude of the electrical signal transmitted across the metal signal path. Examples of passive elements include resistors, inductors, capacitors, etc. Placing these passive elements on the side of the silicon package substrate where the integrated circuit is located does not allow the passive elements to be fully utilized for noise reduction. Furthermore, the passive elements consume area on the silicon package substrate and reduce the density of the signal path.

[0005] In view of the above, an efficient method and system for transferring information as signals through a silicon package substrate are desired.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0007] While the present invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description thereof are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.

[0008] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It should be recognized, however, that the present invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail in order to avoid obscuring the present invention. Furthermore, it should be understood that the elements shown in the figures are not necessarily drawn to scale for the sake of simplicity and clarity of the description. For example, the dimensions of some of the elements are exaggerated relative to other elements.

[0009] An apparatus and method for efficiently transferring information as signals through a silicon package substrate are contemplated. A semiconductor manufacturing process (or process) forms a package substrate having one or more signal paths using laminated vias from one side of the package substrate to the opposite side of the package substrate. Thus, these one or more signal paths refrain from using plated through holes (PTHs). These signal paths have a smaller pitch than signal paths using plated through holes. This process forms a package substrate having a plurality of embedded passive components with different thicknesses in different layers of the package substrate. To do so, the process starts with a relatively thin package substrate core layer and uses a laser to generate openings in the package substrate at the locations of the signal paths. The use of each of the relatively thin core layer and the laser enables reduction of the pitch of the signal paths. In contrast, using a relatively thick package substrate core and mechanical drilling increases the pitch of the signal paths. The relatively large openings generated by mechanical drilling reduce the reliability of subsequently forming a plurality of embedded passive components with different thicknesses in different layers of the package substrate.

[0010] Examples of embedded passive components include resistors, inductors, capacitors, etc. Embedded passive components are used to improve the integrity of signals on signal paths that transfer data within the package substrate. For example, embedded passive components perform impedance matching to minimize signal reflection, reduce signal skew by precisely matching the lengths of signal paths, reduce crosstalk, minimize overshoot and undershoot of electrical signals, and reduce electromigration interference, and are arranged in layers of the package substrate in a specific manner.

[0011] This process places a first side of a package substrate on a plurality of interconnects of a motherboard. This process places an integrated circuit on a second side different from the first side of the package substrate. This process completes the connection of a chip package that can be any of a ball grid array (BGA) surface mount package, a chip scale package (CSP), or a system in package (SiP). A potential such as at least one power supply voltage is applied to one or more nodes of the chip package in addition to components on the motherboard. When the package substrate receives data being transferred, the package substrate conveys the data from the first side of the package substrate where the data was received to a second side opposite the first side of the package substrate. A plurality of embedded passive components having different thicknesses in different layers of the package substrate enhance the signal integrity of the electrical signals being transferred.

[0012] In the following description, a plurality of package substrates including a plurality of embedded passive components having different thicknesses in different layers of the package substrate are shown in FIG. 1. FIG. 2 shows a package substrate that relies on mechanical drilling to form openings having a large pitch for plated through holes. Relatively large and widely spaced plated through holes limit the number and type of embedded passive components that can be placed within the package substrate. FIG. 3 shows a semiconductor chip package. FIGS. 4-10 show manufacturing steps for generating a package substrate having a plurality of embedded passive components having different thicknesses in different layers of the package substrate. FIGS. 11-12 provide steps of a method performed to generate a package substrate having a plurality of embedded passive components having different thicknesses in different layers of the package substrate. An example of a manufactured chip package including a package substrate having a plurality of embedded passive components disposed within a computing system is shown in FIG. 13.

[0013] Referring to FIG. 1, a generalized block diagram of a package substrate 100 having a plurality of embedded passive components located within a plurality of layers is shown. As illustrated, the package substrate 100 includes a core layer 102 having a relatively thin thickness 120. The thickness 120 of the core layer 102 is measured along the dimension of the package substrate 100 that is aligned with the direction of the signal path for transferring data as an electrical signal through the package substrate 100. The signal path uses metal layers 106 and stacked vias rather than plated through holes (PTHs). Although not shown for ease of explanation, one surface of the package substrate 100, such as the bottom surface of FIG. 1 of the package substrate 100, can be and is contemplated to be placed on a plurality of interconnects of a mother board. The other side of the package substrate 100 has one or more integrated circuits disposed on another side, such as the upper side of FIG. 1 of the package substrate 100. The core layer 102 includes passive components such as an inductor 110 having a thickness smaller than the thickness 120 of the core layer 102. Also, the package substrate 100 includes another passive component such as a capacitor 112 in a layer different from the inductor 110. Thus, the package substrate 100 includes a plurality of embedded passive components (passive components 110 and 112) located within a plurality of layers of the package substrate 100.

[0014] Also, the package substrate 100 includes a plurality of layers of dielectric 104, and one or more of these layers have a thickness and composition different from the other dielectric layers 104 of the package substrate 100. Note that in various embodiments, the thickness of the capacitor 112 is different from the thickness of the inductor 110. Thus, the package substrate 100 includes a plurality of embedded passive components having different thicknesses.

[0015] In various embodiments, the metal layer 106 comprises copper or an alloy of copper and other metals such as aluminum mixed with copper. Similar to other printed circuit boards such as motherboards, expansion cards, network cards, and video cards, the core layer 102 utilizes a glass-reinforced epoxy laminate material. This material provides relatively high mechanical strength while providing electrical insulation between the interconnects and the semiconductor chips. An example of a glass-reinforced epoxy laminate material is FR-4 (or FR4) glass epoxy. The core layer 102 includes one or more signal paths embedded in and extending through the FR-4 material. Another example is glass bismaleimide triazine (BT) epoxy.

[0016] In various embodiments, the dielectric layer 104 includes various types of packaging dielectric layers. For example, various prepreg resin materials are used. A prepreg is a reinforcing cloth pre-impregnated with a resin such as epoxy that already contains a curing agent. Thus, the prepreg is ready to be placed in the corresponding mold with more resin added. The laminate is cured using a combination of heat and pressure. The heat softens and causes the prepreg material to flow, surround the metal layer 106, bond the multiple different layers together, and then fully cure. The dielectric layer 104 protects the metal layer 106 and passive components such as the inductor 110 and the capacitor 112 from physical, chemical, and electrical damage by insulating them.

[0017] Note that the core layer 102 is not mechanically drilled after the formation of the dielectric layer 104. Rather, the core layer 102 has openings generated by a laser prior to the formation of the dielectric layer 104 in order to increase the pitch density of the stacked vias used to create signal paths. In one embodiment, the thickness 120 of the core layer 102 is 250 micrometers. The thickness of each of the inductor 110 and the capacitor 112 is less than the thickness of the core layer 102. A laser is used for the relatively thin core layer 102 to form openings in the core layer 102. In contrast, mechanical drilling is used to create openings in a core layer having a relatively high thickness of 1,000 micrometers (or 1 millimeter). The use of the relatively thin core layer 102 and the use of a laser to create openings for signal paths enables a reduction in the pitch of the signal paths (an increase in pitch density).

[0018] Data can be transferred through via stacks generated within the package substrate 100 using the metal layer 106, which is contemplated. The process uses stacked vias including the metal layer 106 to create signal paths within the openings generated by the laser. The stacked vias using the metal layer 106 create signal paths from one side of the package substrate 100 to the opposite side of the package substrate 100. Thus, in various embodiments, the package substrate 100 foregoes the use of plated through holes (PTHs) for signal paths.

[0019] Examples of embedded passive components disposed within the package substrate 100 include resistors, inductors, capacitors, and the like. Although a single inductor 110 and a single capacitor 112 are shown, in other embodiments, the package substrate 100 includes a different number of passive components disposed in different layers of the package substrate 100. Embedded passive components are used to improve signal integrity on signal paths that transfer data within the package substrate 100. For example, embedded passive components such as inductor 110 and capacitor 112 perform impedance matching to minimize signal reflection, reduce signal skew by precisely matching the lengths of signal paths, reduce crosstalk, minimize overshoot and undershoot of electrical signals, and reduce electromigration interference, and are disposed within the layers of the package substrate 100 in a specific manner.

[0020] When the package substrate 100 receives data to be transferred, the package substrate 100 conveys the data from a first side of the package substrate 100, such as the top of the package substrate 100 where the data was received, to a second side opposite the first side of the package substrate 100. A plurality of embedded passive components, at least such as inductor 110 and capacitor 112, having different thicknesses in different layers of the package substrate 100 enhance the signal integrity of the electrical signals being transferred.

[0021] Referring to FIG. 2, a generalized block diagram of a cross-sectional view of the package substrate 200 being formed is shown. The same reference numerals are assigned to the materials, layers, and components described previously. Note that the core layer 102 is not mechanically drilled after the formation of the dielectric layer 104. Rather, the core layer 102 has openings generated by a laser prior to the formation of the dielectric layer 104 in order to increase the pitch density of the stacked vias used to generate signal paths. The core layer 102 has a relatively thin thickness 120 and uses a laser to form through-holes at positions for the stacked vias generated in the metal layer 106. The laser-formed through-holes are electrically filled and patterned with copper or another metal mixture using existing standard processes.

[0022] The cavity 210 is formed to later embed passive components such as the inductor 110. A laminate temporary tape 220 is formed for component embedding. Thereafter, passive components such as the inductor 110 are disposed within the cavity 210. The inductor 110 is shown as being disposed within the cavity 210, but in other embodiments, other types of passive components are disposed within the cavity 210. Note that the width of the cavity 210, measured in a direction aligned with the pitch of the signal path, is relatively small. The relatively small width of the cavity 210 makes subsequent cavity filling easier to manage and increases the yield. Note that the thickness of passive components such as the inductor 110 is smaller than the thickness 120 of the core layer 102. After disposing the passive components within the cavity 210, a copper (Cu) adhesion promotion (AP) treatment step is performed.

[0023] Figures 3 to 8 show subsequent processing steps for forming a package substrate having a plurality of embedded passive components located within a plurality of layers. In Figures 3 to 9, the materials, layers, and components described above are assigned the same reference numerals. Figure 3 shows a generalized block diagram of the package substrate 300 after a dielectric lamination step for filling the cavity 210, with the tape 220 removed. Another dielectric lamination step is performed, followed by a curing step, and openings are generated by a laser at positions for the stacked vias. Thereafter, a smear removal (desmear) process is performed. Figure 4 shows a generalized block diagram of the package substrate 400 after electroless plating technology is used to perform copper seed layer deposition.

[0024] FIG. 5 shows a generalized block diagram of a package substrate 500 after a dry film photoresist (DFR) lamination process followed by an exposure step, a development step, an etching step, and a stripping step. FIG. 6 shows a package substrate 600 after a copper (Cu) adhesion promotion (AP) treatment step and dielectric lamination. FIG. 7 shows a generalized block diagram of a package substrate 700 after a laser has generated an opening, a smear removal (desmear) step has been performed, and a copper seed layer deposition has been performed using electroless plating technology. Thereafter, the DFR lamination process is executed, followed by an exposure step, a development step, an etching step, and a stripping step. Thereafter, passive components such as capacitor 112 are placed.

[0025] In various embodiments, capacitor 112 has a thickness different from that of inductor 110, and each of the thicknesses of inductor 110 and capacitor 112 is less than the thickness 120 of core layer 102. Further, capacitor 112 is disposed in a dielectric layer 104 different from core layer 102 in which inductor 110 is disposed. FIG. 8 shows a generalized block diagram of a package substrate 800 after a copper (Cu) adhesion promotion (AP) treatment step and dielectric lamination.

[0026] FIG. 9 shows a generalized block diagram of a semiconductor chip package 900. As shown, the semiconductor chip package 900 (or chip package 900) uses various types of interconnections. One example is a controlled collapse chip connection (C4) interconnection 910, also referred to as a flip chip interconnection. Another example is a solder ball 960. The solder ball 960 provides a connection between multiple layers of the package substrate and a motherboard (not shown). The solder resist 940 is an insulating ink that covers the surface of the printed wiring board and protects the circuit pattern. The underfill 930 is a composite material composed of an epoxy polymer used to compensate for the thermal expansion of the material between the integrated circuit (IC) 920 and the package substrate. The integrated circuit 920 can be any of various types of integrated circuits. The package substrate shown has plated through holes (PTHs) with a corresponding resin 950, and thus consumes more area than the signal paths shown in FIGS. 1-8 and has a lower pitch density of signal paths. Note that replacing the method of generating PTHs with the method previously described with respect to FIGS. 1-8 provides a thinner core layer 102 and a higher pitch density for the signal paths and enables the placement of multiple embedded passive components located within multiple layers of the package substrate. Further, these embedded passive components have various thicknesses compared to each other, and the thickness is smaller than the thickness of the core layer 102.

[0027] Referring to FIG. 10, a generalized block diagram of a method 1000 for efficiently generating a silicon package substrate having multiple layers of embedded passive components is shown. For the sake of explanation, the steps of this embodiment (and FIG. 11) are shown in order. However, in other embodiments, some steps occur in a different order than the order shown, some steps are executed simultaneously, some steps are combined with other steps, and some steps do not exist.

[0028] The semiconductor manufacturing process forms an opening in the core layer of a package substrate having a first thickness by using a laser (block 1002). The process fills the opening with metal (block 1004). The process forms a cavity in the core layer (block 1006). The process places passive components in the cavity (block 1008). The process deposits a dielectric in the cavity (block 1010). The process deposits a dielectric on both the top and bottom surfaces of the core layer (block 1012). The process forms an opening using a laser and fills the opening with metal to create stacked vias on the passive components and through-holes (block 1014).

[0029] The process etches away excess metal and deposits a dielectric on both the top and bottom surfaces of the package substrate (block 1016). The process optionally places one or more other passive components on the metal layer or dielectric layer (block 1018). The process deposits a dielectric on both the top and bottom surfaces of the package substrate (block 1020). If the desired customizable thickness of the package substrate has not yet been reached (conditional block 1022: "No"), the control flow of method 1200 returns to block 1014 and the process forms an opening using a laser and fills the opening with metal to create stacked vias on the passive components and through-holes. If the desired customizable thickness of the package substrate has been reached (conditional block 1022: "Yes"), the process is complete (block 1024). The package substrate is ready to be placed within a chip package.

[0030] Referring to FIG. 11, a generalized block diagram of a method 1100 for efficiently generating a chip package having a silicon package substrate with multiple layers of embedded passive components is shown. A semiconductor manufacturing process (or process) forms a package substrate having multiple signal paths using via stacks from one side of the package substrate to the opposite side of the package substrate (block 1102). The process forms a package substrate having multiple embedded passive components with different thicknesses in different layers of the package substrate (block 1104). In various embodiments, the package substrate includes the materials, layers, and multiple passive components of the package substrates 100-800 (of FIGS. 1-8).

[0031] The process places the first side of the package substrate on multiple interconnects of a motherboard (block 1106). The process places an integrated circuit on a second side different from the first side of the package substrate (block 1108). This process completes the connection of a chip package, which can be any of a ball grid array (BGA) surface mount package, a chip scale package (CSP), or a system in package (SiP). A potential such as at least one power supply voltage is applied to one or more nodes of the chip package in addition to components on the motherboard. If the package substrate does not receive the data being transferred (conditional block 1110: "no"), the package substrate waits for the data (block 1112). However, if the package substrate receives the data being transferred (conditional block 1110: "yes"), the package substrate conveys the data from the first side of the package substrate where the data was received to the second side opposite the first side of the package substrate (block 1114).

[0032] Referring to FIG. 12, an embodiment of a computing system 1200 that utilizes a plurality of embedded passive components located within a plurality of layers of a package substrate is shown. The computing system 1200 utilizes a chip package 1240 that includes a package substrate 1220. The package substrate 1220 has a plurality of embedded passive components located within a plurality of layers. In various embodiments, the package substrate 1220 includes the materials, layers, and plurality of passive components of the package substrates 100 - 800 (of FIGS. 1 - 8). The chip package 1240 uses any one of a ball grid array (BGA) surface mount package, a chip scale package (CSP), and a system in package (SiP). The chip package 1240 communicates with other components on a motherboard (or printed circuit board). In one embodiment, the computing system 1200 includes a processor 1210 and a memory 1230 within the chip package 1240.

[0033] In another embodiment, only one of the processor 1210 and the memory 1230 is included in the chip package 1240. Although a single processor is shown, in other embodiments, the chip package 1240 includes a different number of processors and various other types of integrated circuits (ICs). The number and type of ICs located within the chip package 1240 are based on design requirements. A memory controller, interfaces such as buses and communication fabrics, one or more phase - locked loops (PLLs) and other clock generation circuits, a power management unit, etc. are not shown for ease of illustration. Further, in the illustrated embodiment, the chip package 1240 is connected to a disk memory 1254 via a memory bus 1250 and an input / output (I / O) controller and bus 1252.

[0034] In other embodiments, it should be understood that the computing system 1200 includes one or more peripheral devices, a network interface, one or more other memory devices, and the like. In some embodiments, the functionality of the computing system 1200 is incorporated on a system-on-chip (SoC). In other embodiments, the functionality of the computing system 1200 is incorporated on a peripheral card inserted into a motherboard. The computing system 1200 is used in any of a variety of computing devices such as desktop computers, server computers, tablet computers, laptops, smartphones, smartwatches, game consoles, personal assistant devices, and the like.

[0035] The processor 1210 includes hardware such as circuitry. In various embodiments, the processor 1210 includes one or more processing units. In some embodiments, each of the processing units includes one or more processor cores capable of general-purpose data processing and an associated cache memory subsystem. In such embodiments, the processor 1210 is a central processing unit (CPU). In another embodiment, the processing core is a computing unit, and each of the computing units has a highly parallel data microarchitecture with a plurality of parallel execution lanes and an associated data storage buffer. In such embodiments, the processor 1210 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0036] In some embodiments, memory 1230 includes any of various types of dynamic random access memory (DRAM). Memory 1230 stores at least a portion of operating system (OS) 1232, one or more applications represented by code 1234, and at least source data 1236. In various embodiments, memory 1230 stores copies of these software components 1232, 1234, 1236 that have an original copy stored in disk memory 1254. Further, memory 1230 can store intermediate result data and final result data generated by processor 1210 when executing a particular application of code 1234.

[0037] In various embodiments, off-chip disk memory 1254 includes one or more hard disk drives (HDDs) and solid state disks (SSDs) comprising banks of flash memory. I / O controller and bus 1252 supports communication protocols with off-chip disk memory 1254. Although a single instance of operating system 1232, code 1234, and source data 1236 is shown, in other embodiments, a different number of these software components are stored in memory 1230 and disk memory 1254. Operating system 1232 includes instructions for starting up processor 1210, assigning tasks to hardware circuits, managing resources of computing system 1200, and hosting one or more virtual environments.

[0038] Note that one or more of the above-described embodiments may include software. In such embodiments, program instructions for implementing the method and / or mechanism are carried or stored on a computer-readable storage medium. A number of types of media configured to store program instructions are available, including hard disks, floppy (registered trademark) disks, CD-ROMs, DVDs, flash memories, programmable ROMs (Programmable ROM, PROM), random access memories (random access memory, RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or storage media such as Blu-Ray (registered trademark). Storage media further include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (synchronous dynamic RAM, SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (SRAM), etc.), ROM, flash memory, etc., and non-volatile memory (e.g., flash memory) accessible via a peripheral interface such as a Universal Serial Bus (USB) interface. Storage media include microelectromechanical systems (microelectromechanical system, MEMS), as well as storage media accessible via communication media such as networks and / or wireless links.

[0039] Additionally, in various embodiments, the program instructions include an operational level description or register-transfer level (RTL) description of the hardware functionality in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII stream format (GDS II). In some cases, the description is read by synthesis tools that synthesize the description to produce a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including the system. The netlist can then be placed and routed to produce a dataset that describes the geometric shapes to be applied to the mask. The mask can then be used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuitry corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are, optionally, a netlist (with or without a synthesis library) or a dataset. Additionally, the instructions are utilized for emulation by hardware-based types of emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0040] While the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art upon a full understanding of the above disclosure. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

1. An apparatus, comprising: one or more integrated circuits (ICs); a plurality of interconnections to a motherboard; a package substrate configured to transfer data via a plurality of signal paths between a predetermined one of the one or more ICs and the plurality of interconnections; wherein one or more of the plurality of signal paths comprise stack vias from one side of the package substrate to an opposite side of the package substrate; the apparatus.

2. The apparatus of claim 1, wherein the package substrate comprises a plurality of embedded passive components having at least two passive components with two different thicknesses. The apparatus of claim 1.

3. The apparatus of claim 1, wherein the package substrate comprises a plurality of embedded passive components having at least two passive components disposed in two different layers of the package substrate. The apparatus of claim 1.

4. The apparatus of claim 1, wherein one or more of the plurality of signal paths comprise an embedded passive component having a first thickness that is less than a second thickness of a core layer of the package substrate. The apparatus of claim 1.

5. The apparatus of claim 1, wherein a pitch of the plurality of signal paths is independent of an area consumable by passive components between the predetermined IC and the package substrate. The apparatus of claim 1.

6. The apparatus of claim 5, wherein the pitch is set by a granularity of a laser used during manufacture of the package substrate. The apparatus of claim 5.

7. The apparatus of claim 1, wherein the plurality of signal paths do not use plated through holes. The apparatus of claim 1.

8. A method, comprising: forming, by a semiconductor manufacturing process, a package substrate including a plurality of signal paths, wherein one or more of the plurality of signal paths include stack vias from one side of the package substrate to an opposite side of the package substrate; placing, by the semiconductor manufacturing process, a first side of the package substrate on the plurality of interconnections; placing, by the semiconductor manufacturing process, a predetermined one of one or more integrated circuits (ICs) on a second side of the package substrate different from the first side of the package substrate; transferring, by the plurality of signal paths, data to an opposite side of the package substrate different from the predetermined side of the package substrate in response to receiving the data at a predetermined side of the first side and the second side of the package substrate; the method.

9. Forming a plurality of embedded passive components within the package substrate such that, by the semiconductor manufacturing process, at least two passive components have two different thicknesses. The method of claim 8. **Claim 10** Forming a plurality of embedded passive components within the package substrate such that, by the semiconductor manufacturing process, at least two passive components are located within two different layers of the package substrate. The method of claim 8. **Claim 11** Forming one or more of the plurality of signal paths having an embedded passive component having a first thickness that is less than a second thickness of a core layer of the package substrate. The method of claim 8. **Claim 12** Forming the plurality of signal paths such that, by the semiconductor manufacturing process, a pitch of the plurality of signal paths does not depend on an area consumable by passive components between the predetermined IC and the package substrate. The method of claim 9. **Claim 13** The pitch is set by a granularity of a laser used during manufacture of the package substrate. The method of claim 12. **Claim 14** Forming the plurality of signal paths such that, by the semiconductor manufacturing process, the plurality of signal paths do not use plated through holes. The method of claim 8. **Claim 15** A computing system comprising: A memory configured to store one or more applications of a workload; A chip package; The chip package comprising: One or more integrated circuits (ICs); A plurality of interconnects to a motherboard; A package substrate configured to transfer data between a predetermined IC of the one or more ICs and the plurality of interconnects via a plurality of signal paths; One or more of the plurality of signal paths comprising a stack via from one side of the package substrate to an opposite side of the package substrate. A computing system. **Claim 16** The package substrate comprises a plurality of embedded passive components having at least two passive components having two different thicknesses. The computing system of claim 15. **Claim 17** The package substrate comprises a plurality of embedded passive components having at least two passive components disposed in two different layers of the package substrate. The computing system of claim 15. **Claim 18** One or more of the plurality of signal paths comprise an embedded passive component having a first thickness that is less than a second thickness of a core layer of the package substrate. The computing system of claim 15. **Claim 19** The pitch of the plurality of signal paths is independent of the area that can be consumed by passive components between the given IC and the package substrate. The computing system of claim 15. **Claim 20** The pitch is set by the granularity of a laser used during manufacture of the package substrate. The computing system of claim 19.

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