Optoelectronic semiconductor component and method for manufacturing at least one optoelectronic semiconductor component

Abstract

An optoelectronic semiconductor component and a method for manufacturing at least one optoelectronic semiconductor component, comprising: a semiconductor layer stack (2), at least one recess (19), a first contact structure (11), and a second contact structure (21), wherein the semiconductor layer stack (2) comprises a first semiconductor region (4), a second semiconductor region (6), and an active region (5) arranged between the first and second semiconductor regions (4, 6), the second semiconductor region (6) comprising a first semiconductor layer (7) and a second semiconductor layer (8), the second semiconductor layer (8) being arranged on an opposite side of the first semiconductor layer (7) from the active region (5), the at least one recess (19) extending from a first main surface (2A) of the semiconductor layer stack (2) to the second semiconductor layer (8), through the first semiconductor region (4) and the active region (5), The first contact structure (11) is a structure for making electrical contact with the first semiconductor region (4) and is arranged in at least a portion of the first main surface (2A), the second contact structure (21) is a structure for making electrical contact with the second semiconductor region (6) and is arranged in a portion of the first main surface (2A) and in at least one of the recesses (19), the first semiconductor layer (7) is made of a first compound semiconductor material, and the second semiconductor layer (8) is made of a second compound semiconductor material, the first compound semiconductor material having a higher aluminum content than the second compound semiconductor material, an optoelectronic semiconductor component (1), and a method for manufacturing such an optoelectronic semiconductor component (1) are also provided.

Description

[Technical Field]

[0001] An optoelectronic semiconductor component and a method for manufacturing at least one optoelectronic semiconductor component are provided. For example, the optoelectronic semiconductor component is an InGaAlP-based semiconductor component. The optoelectronic semiconductor component may be intended to generate or emit electromagnetic radiation. [Background technology]

[0002] For example, in the case of a radiation-emitting semiconductor component based on InGaAlP compound semiconductor material, various electrical contacts are possible. For example, a first electrode of a first polarity, such as a p-electrode, can be located at the rear, and a second electrode of a second polarity, such as an n-electrode, can be located at the front. However, if the second electrode for emitting radiation is located at the front, absorption losses can occur there. An alternative solution is to provide a via that extends completely through the semiconductor chip and toward the front. In this case, the second electrode, although small in size, is again located at the front, which can result in absorption losses. It is also possible to electrically contact the semiconductor regions located at the rear and forward by one or more vias that penetrate the semiconductor chip. However, due to relatively high tolerances in the manufacturing of the recesses in which the vias are created, the semiconductor layers contacted by the vias must be as thick as possible. This, combined with their thickness and sometimes high doping, results in relatively high absorption losses. Summary of the Invention

[0003] It is an object of the present disclosure to provide a more efficient optoelectronic semiconductor component. A further object of the present disclosure is, in particular, to provide a more efficient method for manufacturing at least one optoelectronic semiconductor component.

[0004] These objects are achieved in particular by a method for manufacturing at least one optoelectronic semiconductor component having the features of the independent claims.

[0005] Further advantages and configurations of the optoelectronic semiconductor component and the method for manufacturing the optoelectronic semiconductor component are the subject of dependent claims.

[0006] According to at least one embodiment, an optoelectronic semiconductor component comprises a semiconductor layer stack having a first semiconductor region, a second semiconductor region, and an active region, the active region being disposed between the first and second semiconductor regions. The active region may be configured to generate or emit electromagnetic radiation, for example, in the visible to infrared spectral range.

[0007] Furthermore, the active region may comprise a sequence of individual layers that may form a quantum well structure, in particular a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.

[0008] The first semiconductor region may have a first conductivity type, e.g., p-conductivity. Furthermore, the second semiconductor region may have a second conductivity type, e.g., n-conductivity. However, the second semiconductor region may be a p-conductivity semiconductor region and the first semiconductor region may be an n-conductivity semiconductor region. The first and second semiconductor regions may each comprise a sequence of individual layers, some of which may be undoped or lightly doped. The individual layers may be epitaxially grown on a growth substrate.

[0009] According to at least one embodiment, the second semiconductor region comprises a first semiconductor layer made of a first compound semiconductor material and a second semiconductor layer made of a second compound semiconductor material different from the first compound semiconductor material. The first compound semiconductor material may have a higher aluminum content than the second compound semiconductor material. By selecting an appropriate etchant with sufficient selectivity, the higher aluminum content in the first semiconductor layer will be etched at a higher rate than in the second semiconductor layer. As a result, the etching process can be stopped at the second semiconductor layer. This allows for particularly precise setting of the etching depth and for determining the vertical extent of the recesses to be generated with relatively high accuracy.

[0010] According to at least one embodiment, the second semiconductor layer is disposed on the opposite side of the first semiconductor layer from the active region.

[0011] According to at least one embodiment, the optoelectronic semiconductor component comprises at least one recess extending from a first main surface of the semiconductor layer stack to the second semiconductor layer through the first semiconductor region and the active region, the first main surface being a surface of the semiconductor layer stack that delimits a rearward-facing side of the optoelectronic semiconductor component.

[0012] According to at least one embodiment, an optoelectronic semiconductor component comprises a first contact structure for electrically contacting a first semiconductor region and a second contact structure for electrically contacting a second semiconductor region. The first contact structure can be arranged on at least a partial region of the first main surface. Furthermore, the second contact structure can be arranged on a partial region of the first main surface and in at least one recess. The first and second contact structures allow the optoelectronic semiconductor component to be electrically connected to the outside only on one side of the semiconductor component, for example, on a side surface. The first and second contact structures enable uniform current distribution in the semiconductor layer stack and also allow for larger semiconductor components.

[0013] According to at least one embodiment, an optoelectronic semiconductor component includes a semiconductor layer stack; at least one recess; a first contact structure; a second contact structure; the semiconductor layer stack includes a first semiconductor region, a second semiconductor region, and an active region disposed between the first and second semiconductor regions; the second semiconductor region includes a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is disposed on an opposite side of the first semiconductor layer from the active region; the at least one recess extends from the first major surface of the semiconductor layer stack to the second semiconductor layer through the first semiconductor region and the active region; the first contact structure is a structure for making electrical contact with the first semiconductor region and is disposed in at least a part of the first main surface; the second contact structure is a structure for making electrical contact with the second semiconductor region, and is arranged in a partial region of the first main surface and in at least one of the recesses; the first semiconductor layer is made of a first compound semiconductor material; the second semiconductor layer is made of a second compound semiconductor material; The first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0014] For example, the contact region of the second contact structure disposed in at least one recess or recess may have a three-dimensional shape with a constant cross-section, such as a cylindrical or rectangular parallelepiped shape. However, the contact region of the at least one recess or recess may have a three-dimensional shape with a varying cross-section, such as a truncated cone or a truncated pyramid shape. The cross-section may decrease in the depth direction. For example, the shape and size of the contact region are determined by the shape and size of the recess. The shape and size of the contact region may be at least substantially the same as the shape and size of the recess.

[0015] Where multiple recesses or contact regions are present, their size and / or spacing may be varied, for example, to compensate for contact resistance and / or surface resistance in the second semiconductor region.

[0016] According to at least one embodiment or configuration, the first compound semiconductor material is a phosphorus compound semiconductor material, i.e., a phosphorus-containing semiconductor material. Furthermore, the second compound semiconductor material may be a phosphorus compound semiconductor material. The first and second phosphorus compound semiconductor materials may be InGaAlP.

[0017] According to at least one embodiment or configuration, the first compound semiconductor material is Al n Ga m In 1-n-mIt contains P, where 0.3 ≤ n ≤ 0.6, 0 ≤ m ≤ 0.2, and 0.4 ≤ n + m ≤ 0.6. The first semiconductor layer may have a function as a buffer layer. An appropriate lattice constant can be achieved with an indium content between 40% and 60%.

[0018] According to at least one embodiment or configuration, the second compound semiconductor material is Al n Ga m In 1-n-m It contains P, where 0 < n < 0.6, 0 < m < 0.6, and 0.4 ≤ n + m ≤ 0.6. The second semiconductor layer may have a function as, for example, a contact layer or a contact layer兼current diffusion layer. The second semiconductor layer may be formed thinner than the first semiconductor layer. For example, the second semiconductor layer may have a thickness of 10 nm to 500 nm, particularly 20 nm to 100 nm, and the manufacturing tolerance may be ±10%. By making the thickness relatively thin, the absorption loss in the second semiconductor layer or contact layer becomes relatively small.

[0019] According to at least one embodiment or configuration, the second semiconductor region has a third semiconductor layer disposed on the side of the second semiconductor layer opposite to the first semiconductor layer. For the third semiconductor layer, a phosphorus compound semiconductor material, particularly InGaAlP, is suitable as with the first and second semiconductor layers. The compound semiconductor materials of the second and third semiconductor layers may have different gallium contents and / or doping levels. For example, as described above, the second semiconductor layer may be a contact layer, and the third semiconductor layer may be a current diffusion layer.

[0020] According to at least one embodiment or configuration, the second main surface opposite to the first main surface of the semiconductor layer stack does not have the first and second contact structures. The second main surface may be located in front of the optoelectronic semiconductor component that emits radiation. Most of the emitted radiation passes through the second main surface and may be partially absorbed in the contact structure disposed on the second main surface. This can be advantageously prevented by disposing the contact structure outside the second main surface.

[0021] According to at least one embodiment or configuration, the at least one recess has a widening region between the active region and the second semiconductor layer, which widening region can be considered to be indicative of a two-stage etching process for fabricating the at least one recess, as described in more detail below in connection with the fabrication method.

[0022] For example, the widened region may have a depth or vertical extension that corresponds to at least about 25% of the thickness of the first semiconductor layer, and at most the thickness of the first semiconductor layer. The vertical extension may be, for example, along a vertical direction antiparallel to the growth direction in which the semiconductor regions are stacked one on top of the other. The widened region may also have a lateral extension at the bottom of the recess that deviates by about 10%, with a tolerance of ±10%, from the lateral extension that would have occurred if the original shape of the recess had continued. For example, the lateral extension of the widened region may be a value between 5.5 μm and 7.5 μm, with a tolerance of ±10%.

[0023] According to at least one embodiment or configuration, the second contact structure comprises a connection layer. The connection layer can cover one or more surfaces of the semiconductor layer stack that delimit the at least one recess. Metallic material compounds and / or layer stacks are suitable for the connection layer. For example, Au or Pd are suitable for the connection layer. The connection layer may also comprise a dopant, such as Ge.

[0024] According to at least one embodiment or configuration, a cavity is provided in the widened region of at least one recess between the semiconductor layer stack and the second contact structure. The cavity may be filled with a gas or may be substantially empty and evacuated. For example, the connection layer and other layers applied to the semiconductor layer stack in the widened region may be formed to conform to the original shape of the recess if the widened region is not provided. Therefore, the second contact structure or the connection layer and other layers may not be applied conformally to the semiconductor layer stack in the widened region of the recess, which may result in the formation of a cavity.

[0025] According to at least one embodiment or configuration, the optoelectronic semiconductor component comprises an insulating layer disposed between the semiconductor layer stack and the connection layer. The insulating layer may comprise or consist of an electrically insulating material such as silicon oxide or silicon nitride. For example, the insulating layer may be disposed on one or more surfaces of the semiconductor layer stack that laterally delimit a recess. The bottom surface of the recess may not be covered by the insulating layer so that a second contact structure or a connection layer can contact the second semiconductor layer.

[0026] According to at least one embodiment or configuration, the optoelectronic semiconductor component comprises a carrier on which a semiconductor layer stack is arranged. A first semiconductor region may be arranged on the carrier side of an active region and a second semiconductor region may be arranged on the opposite side of the active region from the carrier. The carrier may comprise or consist of a semiconductor material such as Ge or Si, or a ceramic material such as SiN.

[0027] The method described below is suitable for the manufacture of at least one optoelectronic semiconductor component as described above, and therefore features described with respect to the semiconductor component are also applicable to the method and vice versa.

[0028] According to at least one embodiment or configuration of a method for manufacturing at least one optoelectronic semiconductor component, the method comprises the following steps, for example in the following order: According to at least one embodiment or configuration of a method for manufacturing at least one optoelectronic semiconductor component, the method comprises the following steps, for example in the following order: Providing a semiconductor layer sequence for producing at least one semiconductor layer stack, comprising: the semiconductor layer sequence comprises a first semiconductor region, a second semiconductor region, an active region disposed between the first and second semiconductor regions, and a first main surface; the second semiconductor region includes a first semiconductor layer and a second semiconductor layer; the second semiconductor layer is disposed on an opposite side of the first semiconductor layer from the active region; forming a first contact structure on the first major surface; creating at least one recess extending from the first major surface through the first semiconductor region and the active region to the second semiconductor layer; forming a second contact structure disposed in a partial region of the first main surface and in the at least one recess; The at least one recess is produced by a two-stage etching process, whereby the semiconductor layer sequence is etched down to the first semiconductor layer in a first etching step and down to the second semiconductor layer in a second etching step.

[0029] Compared to the two-step etching process described herein, in a single-step etching process, the semiconductor layer used to stop the etching must be relatively thick. In contrast, in a two-step etching process, the second semiconductor layer can be relatively thin, e.g., between 10 nm and 500 nm, particularly between 20 nm and 100 nm, with a typical manufacturing tolerance of ±10%. Meanwhile, the first semiconductor layer, which is the end point of the first etching step, can be thicker than the second semiconductor layer. For example, the thickness of the first semiconductor layer can be in the range of 0.4 μm to 0.6 μm, with a tolerance of ±10%. The thickness of the first semiconductor layer is determined, for example, taking into account variations in thickness and etching rate that occur during the first etching step.

[0030] The semiconductor layer sequence corresponds to the semiconductor layer stack to be manufactured, for example, with respect to its layer structure and material composition, and therefore the details apply equally to the semiconductor layer sequence. Preferably, a first semiconductor region of at least one semiconductor layer stack is formed from the first semiconductor region of the semiconductor layer sequence, an active region of the at least one semiconductor layer stack is formed from the active region of the semiconductor layer sequence, and a second semiconductor region of the at least one semiconductor layer stack is formed from the second semiconductor region of the semiconductor layer sequence. In particular, the first semiconductor layer of the second semiconductor region is formed from a first compound semiconductor material, for example InAlP, and the second semiconductor layer is formed from a second compound semiconductor material, for example InGaAlP, where the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material.

[0031] The semiconductor layer sequence may be provided on a substrate formed, for example, by epitaxial growth.

[0032] Furthermore, the first and second contact structures formed on the semiconductor layer sequence are designed to enable the production of first and second contact structures for at least one optoelectronic semiconductor component. Therefore, details of the structure and suitable materials for the first and second contact structures of the optoelectronic semiconductor component apply analogously. That is, the second contact structure may comprise a connecting layer provided for generating the connecting layer of the second contact structure of the at least one semiconductor component. The connecting layer may cover one or more surfaces of the semiconductor layer sequence that delimit the at least one recess.

[0033] According to at least one embodiment or configuration, the first etching step includes a dry etching process. Furthermore, the second etching step may include a wet chemical etching process. In particular, the second etching step or the wet chemical etching process uses an etchant with sufficient selectivity to etch a first semiconductor layer having a higher aluminum content than a second semiconductor layer having a lower aluminum content. For example, the etching rate in the second semiconductor layer may be one or more orders of magnitude lower than the etching rate in the first semiconductor layer. This allows the etching process to be terminated precisely at the second semiconductor layer. In this way, the desired etching depth can be set as intended.

[0034] Aqueous solutions such as dilute hydrochloric acid or dilute sulfuric acid can be used as the etchant.

[0035] According to at least one embodiment or configuration, a widened region of the at least one recess is generated by a second etching step, the widened region being created by under-etching in the first semiconductor layer, with reference to the description of the optoelectronic semiconductor component above for the size of the widened region.

[0036] According to at least one embodiment or configuration, an insulating layer is formed between the semiconductor layer sequence and the connection layer, which is provided to generate an insulating layer in at least one semiconductor component. Therefore, for example, details regarding the structure and suitable materials of the insulating layer of an optoelectronic semiconductor component apply analogously. For example, the insulating layer may be provided as a closed layer on the semiconductor layer sequence so that the first partial region of the recess or the surface that bounds the recess is completely covered. The insulating layer may then be partially removed to expose the bottom of the recess or the surface of the semiconductor layer sequence arranged in the first partial region of the recess.

[0037] According to at least one embodiment or configuration, the insulating layer is applied before the second etching step is performed, in which case the insulating layer may be under-etched during the second etching step and may be spaced apart from the semiconductor layer sequence. However, the insulating layer may also be applied after the second etching step, in which case the insulating layer may be closer to the semiconductor layer sequence.

[0038] According to at least one embodiment or configuration, the active region has a quantum well structure, and hybridization of the quantum well structure is performed in a portion of the active region adjacent to the recess. In this process, the quantum well and the barrier layer are hybridized to create a higher bandgap, resulting in reduced charge carriers and reduced surface recombination. This hybridization process may, for example, apply an insulating layer or a connecting layer to the semiconductor layer sequence within the recess. Hybridization may also be performed before the recess is created.

[0039] Optoelectronic semiconductor components are suitable for projection and lighting applications in the long wavelength spectral range, for example in the red to infrared region. [Brief explanation of the drawings]

[0040] Further advantages, advantageous embodiments and further variants will become apparent from the exemplary embodiments described below with reference to the figures. [Figure 1] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 2] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 3] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 4] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 5] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 6] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 7] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 8] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 9] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 10] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 11] 1A-1D show schematic cross-sectional views of steps in a method for manufacturing an optoelectronic semiconductor component according to an embodiment. [Figure 12] 1 shows a schematic cross-sectional view of an optoelectronic semiconductor component according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0041] In the present embodiment and drawings, identical elements, elements of the same kind, or elements having similar functions may be designated by the same or similar reference numerals, and these reference numerals may be distinguished by the presence or absence of an apostrophe. Note that the illustrated elements and their relative sizes are not necessarily faithfully reproduced to actual scale, and the size of each element may be exaggerated to improve visibility and understanding.

[0042] 1 to 11, an embodiment of a method or layer composite 100 suitable for manufacturing an optoelectronic semiconductor component 1 as described below, as well as possible variations of that embodiment, will be described, for example, in connection with Fig. 12. The dashed areas in the figures indicate further areas of the layer composite 100 that allow, for example, the manufacturing of multiple optoelectronic semiconductor components 1.

[0043] The method comprises providing a semiconductor layer sequence 2' for producing at least one semiconductor layer stack 2 (see FIG. 12), the semiconductor layer sequence 2' being provided on a substrate 3 (see FIG. 1). The semiconductor layer sequence 2' can be made of a semiconductor material based on a phosphide compound semiconductor. Furthermore, the substrate 3 can be made of a semiconductor material based on an arsenide compound semiconductor. For example, GaAs can be used for the substrate 3. In particular, the substrate 3 is a growth substrate on which the semiconductor layer sequence 2' is epitaxially grown.

[0044] The semiconductor layer sequence 2' comprises a first semiconductor region 4' of a first conductivity type, for example p-conductivity, a second semiconductor region 6' of a second conductivity type, for example n-conductivity, and an active region 5' arranged between the first and second semiconductor regions 4', 6'. The first semiconductor region 4' is located on the opposite side of the active region 5' from the substrate 3, and the second semiconductor region 6' is located between the substrate 3 and the active region 5'.

[0045] The first and second semiconductor regions 4', 6' may each comprise a sequence of individual layers. The individual layers may be doped, or in some cases undoped or lightly doped. For example, the first semiconductor region 4' may comprise a confinement layer near the active region 5' (not shown). Furthermore, the second semiconductor region 6' comprises a first semiconductor layer 7' and a second semiconductor layer 8' arranged on the opposite side of the first semiconductor layer 7' from the active region 5'. The second semiconductor layer 8' may be designed to function as a contact layer and a current spreading layer. However, it is also possible to realize different functions in separate layers. In an exemplary embodiment, the second semiconductor layer 8' functions as a contact layer. For its function as a current spreading layer, a third semiconductor layer 9' is located on the opposite side of the second semiconductor layer 8' from the first semiconductor layer 7'. Furthermore, the second semiconductor region 6' may comprise a radiation-emitting layer 10'. This radiation-emitting layer 10' is arranged on the substrate 3 side of the semiconductor layer sequence 2' and may have radiation-emitting structures that improve the radiation emission in the finished semiconductor component.

[0046] Furthermore, the active region 5' may include the sequences of individual layers. Each individual layer can form a quantum well structure, particularly a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.

[0047] The first semiconductor layer 7' of the second semiconductor region 6' may be formed from a first phosphorus compound semiconductor material, the second semiconductor layer 8' may be formed from a second phosphorus compound semiconductor material, and the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material. In particular, the first compound semiconductor material is Al n Ga m In 1-n-m P, where 0.3 ≤ n ≤ 0.6, 0 ≤ m ≤ 0.2, and 0.4 ≤ n + m ≤ 0.6. The first semiconductor layer 7' may function as a buffer layer. An indium content between 40% and 60% can achieve an appropriate lattice constant. Furthermore, the second compound semiconductor material may be Al n Ga m In 1-n-m P. Here, 0 < n < 0.6, 0 < m < 0.6, and 0.4 ≤ n + m ≤ 0.6. The third semiconductor layer 9' may be formed from a phosphorus compound semiconductor material, particularly InGaAlP, similar to the first and second semiconductor layers 7', 8'. The compound semiconductor materials of the second and third semiconductor layers 8', 9' have different gallium contents and / or doping levels.

[0048] The second semiconductor layer 8' may be formed thinner than the first semiconductor layer 7'. For example, the second semiconductor layer 8' may have a thickness d2 in the range of 10 nm to 500 nm, particularly 20 nm to 100 nm, and the normal manufacturing tolerance may be ±10%. Such a relatively low thickness d2 can reduce the absorption loss in the second semiconductor layer 8' or the contact layer. The thickness can represent, for example, the vertical extension along the vertical direction V parallel to the growth direction in which the semiconductor regions 6', 5', 4' are stacked on top of each other.

[0049] The method further includes forming a first contact structure 11' on the first main surface 2A' of the semiconductor layer sequence 2', which first main surface 2A' of the semiconductor layer sequence 2' defines the semiconductor layer sequence 2' on its outer side facing away from the substrate (see FIG. 1). The forming of the first contact structure 11' may include generating a first diffusion layer 12' on the first main surface 2A'. The first diffusion layer 12' may be provided in direct contact with the first semiconductor region 4'. The first diffusion layer 12' may be formed as a single layer or as a multilayer. The first diffusion layer 12' is suitably made of a TCO (transparent conductive oxide), such as ITO, ZnO, InZnO, or AlO.

[0050] Furthermore, forming the first contact structure 11' may include creating a second diffusion layer 14' arranged on the opposite side of the first diffusion layer 12' from the semiconductor layer sequence 2' and electrically conductively connected to the first diffusion layer 12'. The second diffusion layer 14' may cover a larger area of the first main surface 2A' than the first diffusion layer 12'. For example, the second diffusion layer 14'' is a metal layer that may be formed as a single layer or multiple layers.

[0051] Furthermore, forming the first contact structure 11' may include creating a mirror layer 13', for example made of Ag, between the first and second diffusion layers 12', 14'. During operation of the completed semiconductor component 1 (see FIG. 12), radiation emitted from the active regions 5', 5' can largely pass through the first diffusion layers 12', 12'. The mirror layers 13', 13' can deflect the radiation toward the second main surfaces 2B', 2B opposite the first main surfaces 2A', 2A, and can also shield the radiation to prevent absorption by the second diffusion layers 14', 14.

[0052] To achieve advantageous reflectivity at the back side of the finished semiconductor component, a reflective element 15' may be disposed on the first main surface 2A' (see FIG. 1). The reflective element 15' may comprise alternating high-refractive-index layers and low-refractive-index layers. The layers may be dielectric layers, preferably made of materials such as SiO, SiN, NbO, or HfO. For example, the reflective element 15' may comprise a Bragg mirror. The reflective element 15' may cover the first main surface 2A' and partially cover the first diffusing layer 12'. The reflective element 15' may comprise an opening 16 within which the second diffusing layer 14' and, optionally, the mirror layer 13' extend to the first diffusing layer 12'.

[0053] Additionally, an opening 17 may be formed in the second diffusing layer 14 ′ and possibly in the mirror layer 13 ′ at a location laterally spaced from the opening 16 .

[0054] An insulating layer 18′ may be provided on the side of the second diffusion layer 14′ opposite the semiconductor layer sequence 2′, covering at least most of the first main surface 2A′ and extending into the opening 17. The insulating layer 18′ is configured to electrically insulate the first contact structure 11′ and the second contact structure 21′ (see FIG. 10) on the first main surface 2A′.

[0055] 2 and 6, the method further comprises creating at least one recess 19 extending from the first main surface 2A' through the first semiconductor region 4' and the active region 5' to the second semiconductor layer 8'. The recess 19 may already extend from the insulating layer 18' through the opening 17.

[0056] The recess 19 is produced by a two-stage etching process. In a first etching step, the semiconductor layer sequence 2′ is etched towards the first semiconductor layer 7′. The first etching step comprises, for example, a dry etching process. A first region 19A of the recess 19 produced in this process is laterally delimited by one or more surfaces 2C′ of the semiconductor layer sequence 2′ and may extend in cross section at an angle of 90°<α<180°, in particular 95°<α<115°, relative to a surface 2D′ of the semiconductor layer sequence 2′ that delimits the first region 19A at its bottom (see FIG. 2 ). The first region 19A may have a truncated conical or pyramidal shape.

[0057] 3, the method may further include a step of hybridizing the quantum well structure of the active region 5′ in the recess 19 or in the region adjacent to the first region 19A of the recess 19. In this step, the quantum well and barrier layers are hybridized, for example, by heat treatment and, if necessary, by introducing impurities, to increase the bandgap, thereby reducing charge carriers and suppressing surface recombination. This step is particularly useful in the case where surface recombination is important in the recess 19. Hybridization can be performed at an early stage, for example, before the recess 19 is formed, allowing for higher processing temperatures.

[0058] Furthermore, the method may include a step of forming an insulating layer 20', which, as an example embodiment, is performed before the second etching step, although this step may also be performed after the second etching step.

[0059] 4, the insulating layer 20' is applied, for example, as a closed layer on the semiconductor layer sequence 2', completely covering the surfaces 2C', 2D' that delimit the first region 19A of the recess 19. The insulating layer 20' is then partially removed to expose the surface 2D' of the semiconductor layer sequence 2' located at the bottom of the first region 19A of the recess 19 (see FIG. 5).

[0060] The insulating layer 20' may be formed of an electrically insulating material such as silicon oxide or silicon nitride, or a combination thereof.

[0061] After structuring the insulating layer 20′, a second etching step is performed, as shown in FIG. 6, in which the semiconductor layer sequence 2′ is etched down to the second semiconductor layer 8′. For example, the second etching step comprises a wet-chemical etching process. For the second etching step or the wet-chemical etching process, an etching agent with sufficient selectivity is used, in particular, so that the etching rate in the first semiconductor layer 7′, which has a high aluminum content, is higher than the etching rate in the second semiconductor layer 8′, which has a low aluminum content. For example, the etching rate in the second semiconductor layer 8′ can be an order of magnitude lower than the etching rate in the first semiconductor layer 7′. This allows the etching process to be terminated precisely at the second semiconductor layer 8′ and the desired etching depth to be specifically set. For example, an aqueous solution of dilute hydrochloric acid or dilute sulfuric acid can be used as the etching agent.

[0062] In a low-precision single-step etching process, the contacting semiconductor layer must be formed relatively thick due to the large etching tolerance. In contrast, this method allows the second semiconductor layer 8' to be formed relatively thin. Specifically, the thickness d2 of the second semiconductor layer 8' can be in the range of 10 nm to 500 nm, particularly 20 nm to 100 nm, with a typical manufacturing tolerance of ±10%. Meanwhile, the first semiconductor layer 7' after the first etching step can be formed thicker than the second semiconductor layer 8'. For example, the thickness d1 of the first semiconductor layer 7' can be between 0.4 μm and 0.6 μm, with a tolerance of ±10%. The thickness d1 of the first semiconductor layer 7' is determined, for example, taking into account variations in thickness and etching rate that occur during the first etching step.

[0063] In the second etching step, widened regions 19B of the recess 19 are formed. The widened regions 19B are created by under-etching in the first semiconductor layer 7'. The insulating layer 20' is also under-etched in the second etching step, and is spaced apart from the semiconductor layer sequence 2'.

[0064] For example, the widened region 19B may have a depth or vertical extension h that is at least about 25% of the thickness d1 of the first semiconductor layer 7′, and at most corresponds to the thickness d1. The vertical extension h may refer to the extension along the vertical direction V.

[0065] Furthermore, the widened region 19B may have a lateral extension b at the bottom of the recess 19 that deviates by approximately 10%, with a tolerance of ±10%, from the lateral extension that would occur if the original shape of the recess 19 were continued or if the shape of the first region 19A of the recess 19 were continued while maintaining the angle α (see FIG. 2). For example, the lateral extension b of the widened region may be a value between 5.5 μm and 7.5 μm, with a tolerance of ±10%. The lateral extension b may indicate an extension along the lateral direction L. The lateral direction L may extend transversely, for example perpendicularly, to the direction V, for example.

[0066] The method further includes forming second contact structures 21' arranged in a partial area of the first main surface 2A' and in the recesses 19 (see FIGS. 7 to 9).

[0067] The step of forming the second contact structure 21' may also include a step of generating a connection layer 22' covering one or more surfaces 2C', 2D' of the semiconductor layer sequence 2' that delimits the recess 19 (see FIG. 7). For example, the connection layer 22' can cover only the surface 2D' arranged at the bottom of the recess 19, or it can additionally cover the surface 2C'. In particular, the connection layer 22' is provided so as to be electrically contactable with the second semiconductor layer 8'. The connection layer 22' can be produced from a stack of one or more material compounds and / or metal materials. For example, materials or material compounds containing Au or Pd and doped with Ge are suitable for the connection layer 22'. Surface oxides can be removed before applying the connection layer 22'. After applying the connection layer 22', a so-called annealing treatment can be performed.

[0068] 7, a cavity 23 is provided in the widened region 19B of the recess 19 between the semiconductor layer sequence 2′ and the insulating layer 20′ or the connecting layer 22′. The cavity 23 is, for example, filled with gas or is substantially empty and evacuated. This cavity can be formed by the insulating layer 20′ or the connecting layer 22′ in the widened region 19B according to the original shape of the recess 19 or the shape of the first region 19A of the recess 19.

[0069] As shown in FIG. 8 , forming the second contact structure 21′ may further include forming a solder barrier layer 24′ and a first solder layer 25′ such that the solder barrier layer 24′ is disposed between the semiconductor layer sequence 2 and the first solder layer 25′. The solder barrier layer 24′ is configured, for example, to prevent the solder material from diffusing into the layers 2′, 13′, 18′, and 20′. The solder barrier layer 24′ and the first solder layer 25′ can cover the first main surface 2A′ and fill the recess 19. Suitable materials for the solder barrier layer 24′ include, for example, WTi, Ti, or Ta. Suitable materials for the first solder layer 25′ include, for example, AuPt, Au, or Ni.

[0070] Furthermore, the step of forming the second contact structure 21' includes forming a second solder layer (not shown) on the first solder layer 25', which, when bonded to the carrier 27', bonds to the first solder layer 25' to form a bonding layer 26' (see FIG. 9). Suitable materials for the second solder layer include, for example, Sn and InSn. In this case, the bonding layer 26'' includes, for example, AuSn, AuInSn, NiSn, or NiInSn. The carrier 27' can be made of a semiconductor material such as Ge or Si, or a ceramic material such as SiN. The carrier 27' is provided on the side of the semiconductor layer sequence 2' opposite the substrate 3.

[0071] The method may further comprise the step of removing the substrate 3 (see FIG. 10). In this process, the second main surface 2B' of the semiconductor layer sequence 2' may be exposed. For example, the substrate 3 may be removed by wet chemical etching. Furthermore, the method may comprise the step of forming a radiation-emitting structure 28' in the radiation-emitting layer 10'. For example, the radiation-emitting structure 28' may be produced by roughening the surface of the radiation-emitting layer 10' facing away from the carrier 27' or by roughening the second semiconductor region 6' on the second main surface 2B'. The roughening may be carried out, for example, by lithography and a dry etching process.

[0072] The method may further comprise a step of structuring the semiconductor layer sequence 2′ (see FIG. 10). For example, the structuring can be carried out by dry etching. During the structuring, the edge regions of the semiconductor layer sequence 2′ are removed so that, for example, the second diffusion layer 14′ protrudes beyond the semiconductor layer sequence 2′ in at least some regions thereof and can be contacted in the protruding regions with contact pads 29 made, for example, of Au (see FIG. 11). The semiconductor layer sequence 2′ may be structured to have a mesa-like shape, such that the carrier 27′ protrudes beyond all sides of the semiconductor layer sequence 2′ when viewed from above.

[0073] An example embodiment of an optoelectronic semiconductor component 1 will now be described with reference to Figure 12. This optoelectronic semiconductor component 1 can be manufactured by the method described in relation to Figures 1 to 11, and after the steps shown in Figure 11, it is singulated by being separated from the layer structure 100 between the dashed lines. Therefore, the features and relationships described in relation to this method apply equally to the optoelectronic semiconductor component 11, and vice versa.

[0074] The optoelectronic semiconductor component 1 comprises a carrier 27 and a semiconductor layer stack 2 arranged thereon, the carrier 27 of the optoelectronic semiconductor component 1 being separated from the carrier 27' (see Figure 11) by a singulation process, and the semiconductor layer stack 2 corresponding to the structured semiconductor layer sequence 2' (see Figure 11).

[0075] Corresponding to the semiconductor layer sequence 2', the semiconductor layer stack 2 comprises a first semiconductor region 4, a second semiconductor region 6 and an active region 5 arranged between the first and second semiconductor regions 4, 6 and configured to generate or emit electromagnetic radiation, for example in the visible to infrared spectral range. This enables the optoelectronic semiconductor component 1 to emit electromagnetic radiation, for example in the visible to infrared spectral range, during operation. In this case, a large portion of the radiation can be emitted from a second main surface 2B of the semiconductor layer stack 2, which is arranged on the front side of the semiconductor component 1.

[0076] The absence of a contact structure on the second main surface 2B effectively prevents radiation loss due to light blocking on the second main surface 2B. The optoelectronic semiconductor component 1 includes a first contact structure 11 in electrical contact with the first semiconductor region 4, the first contact structure 11 being arranged on a partial region of the first main surface 2A of the semiconductor layer stack 2. As described in relation to FIG. 1 , the first contact structure 11 may include a first diffusion layer 12 arranged on the first main surface 2A and a second diffusion layer 14 arranged between the first diffusion layer 12 and the carrier 27. A mirror layer 13 may be arranged between the first and second diffusion layers 12, 14 and, if it has good electrical conductivity, forms part of the first contact structure 11.

[0077] Furthermore, the optoelectronic semiconductor component 1 includes a second contact structure 21 for making electrical contact with the second semiconductor region 6, the second contact structure 21 being arranged in a partial region of the first main surface 2A and in a recess 19 of the semiconductor layer stack 2. As described in detail in relation to Figures 7 to 10, the second contact structure 21 may include a connection layer 22 arranged in the recess 19, a bonding layer 26 adjacent to the carrier 27, and a solder barrier layer 24 arranged on the bonding layer 26 side of the semiconductor layer stack 2.

[0078] The first main surface 2A may be formed, for example, by the surface of the first semiconductor region 4 and is arranged on the side opposite to the second main surface 2B. The second main surface 2B may be formed, for example, by the surface of the second semiconductor region 6 and is arranged on the side of the semiconductor layer stack 2 facing the carrier 27. The first semiconductor region 4 may be, for example, a p-conductivity region and is arranged on the side of the active region 5 facing the carrier 27. The second semiconductor region 6 may be, for example, an n-conductivity region and is arranged on the side of the active region 5 opposite to the carrier 27.

[0079] As described in connection with FIG. 1 , the second semiconductor region 6 includes a first semiconductor layer 7 made of a first compound semiconductor material with a high aluminum content and a second semiconductor layer 8 made of a second compound semiconductor material different from the first compound semiconductor material with a low aluminum content. For example, the first and second compound semiconductor materials are each a phosphorus compound semiconductor material. The different aluminum contents of the first and second semiconductor layers 7 and 8 allow the two-step etching process for fabricating the recess 19 to be precisely controlled to stop at the second semiconductor layer 8, thereby electrically contacting the second semiconductor region 6. The precise two-step etching process allows for relatively low thicknesses d1 and d2 (see the discussion of FIGS. 1 and 6 ), which can result in a highly efficient semiconductor component 1 due to factors such as low absorption. The first semiconductor layer 7 is disposed between the active region 5 and the second semiconductor layer 8.

[0080] The recess 19, in which the second contact structure 21 is located in a partial region, extends from the first main surface 2A of the semiconductor layer stack 2 to the second semiconductor layer 8, through the first semiconductor region 4 and the active region 5. For example, the contact region 21A of the second contact structure 21 located in the recess 19 or the recess 19 may have a three-dimensional shape with a variable cross-section, such as a truncated cone or a truncated square pyramid. The cross-section may decrease with increasing depth, which may be set parallel to the vertical direction V in which the semiconductor regions 4, 5, and 6 are stacked in order from the carrier 27. For example, the shape and size of the contact region 21A are determined by the shape and size of the recess 19. The shape and size of the contact region 21 may be at least approximately the same as the shape and size of the recess 19. If the contact and / or surface resistance is too high, the semiconductor component 1 may have multiple recesses 19 or multiple contact regions 21A, and the multiple recesses 19 or contact regions 21A may have different sizes and / or spacings from one another.

[0081] The recess 19 comprises a widened region 19B between the active region 5 and the second semiconductor layer 8. The widened region 19B can be interpreted as indicating a two-stage etching process. The vertical extension h and lateral extension b of the widened region 19B will be explained with reference to FIG. 6.

[0082] In the widened region 19B, a cavity 23 is provided between the semiconductor layer stack 2 and the second contact structure 21, and the cavity 23 is, for example, filled with air or is substantially empty and evacuated. For example, the connection layer 22 and other layers (for example, the insulating layer 20) provided in the semiconductor layer stack 2 may extend in the widened region 19B along the original shape of the recess 19 that would be assumed if the widened region were not provided (see also the description of FIG. 2 ).

[0083] The first and second contact structures 11, 21 allow electrical connection of the optoelectronic semiconductor component 1 from the outside only from one side of the semiconductor component 1. For example, a first contact pad 29 of the first contact structure 11, which functions as a first electrode of the semiconductor component 1, and a second contact pad (not shown) of the second contact structure 21, which functions as a second electrode of the semiconductor component 1, may be arranged laterally of the semiconductor layer stack 2 in the protruding region of the carrier 27, for connection with contact means such as bonding wires.

[0084] The first contact pad 29 is arranged in an area of the reflective element 15 that is arranged in a partial region of the first main surface 2A and is not covered by the semiconductor layer stack 2, and extends through the opening of the reflective element 15 to the second diffusion layer 14 of the first contact structure 11. As described in detail in relation to Figure 1, the second diffusion layer 14, like the mirror layer 13, extends through the opening 16 of the reflective element 15 to the first diffusion layer 12.

[0085] The first contact structure 11 may be electrically isolated from the second contact structure 21 by an insulating layer 20 (see the description of Figures 4 to 6 in this regard) and an insulating layer 18 (see the description of Figure 1 in this regard).

[0086] The first and second contact structures 11, 21 allow for a uniform current distribution in the semiconductor layer stack 2, which allows for larger semiconductor components.

[0087] The scope of the carriers is not limited by the description based on the exemplary embodiments, but rather the invention includes any novel feature and any combination of features, and in particular any combination of features in the claims, even if that feature or combination itself is not explicitly recited in the claims or embodiments.

[0088] This patent application claims priority from German patent application 102022119108.7, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0089] 1. Optoelectronic semiconductor components 2. Semiconductor layer stack 2A 1st main surface 2B 2nd main surface 2C, 2D surface 2' Semiconductor layer sequence 2A' 1st main surface 2B' 2nd principal surface 2C', 2D' surface 2E, 2E' side 3. Circuit Board 4, 4' First semiconductor region 5, 5' active region 6, 6' Second semiconductor region 7, 7' First semiconductor layer 8, 8' Second semiconductor layer 9 Third semiconductor layer 10, 10' radiation emitting layer 11, 11' First contact structure 12, 12' First diffusion layer 13, 13' mirror layer 14, 14' Second diffusion layer 15, 15' reflective element 16, 17 aperture 18, 18' insulation layer 19 Recess 19A 1st area 19B Second widening area 20, 20' insulation layer 21, 21' Second contact structure 21A Contact Area 22, 22' connecting layer 23 Cavity 24, 24' solder barrier layer 25' 1st solder layer 26, 26' bonding layer 27, 27' career 28, 28' radiation emitting structure 29 First contact pad 100 layer composite α angle b Lateral extension d1, d2 thickness h depth, vertical extension V Vertical L Horizontal

Claims

1. A semiconductor layer stack (2), At least one recess (19); a first contact structure (11); a second contact structure (21); The semiconductor layer stack (2) is a first semiconductor region (4); a second semiconductor region (6); an active region (5) disposed between the first and second semiconductor regions (4, 6); The second semiconductor region (6) comprises a first semiconductor layer (7) and a second semiconductor layer (8), The second semiconductor layer (8) is disposed on the opposite side of the first semiconductor layer (7) from the active region (5), the at least one recess (19) extends from the first main surface (2A) of the semiconductor layer stack (2) to the second semiconductor layer (8) through the first semiconductor region (4) and the active region (5); the first contact structure (11) is a structure for making electrical contact with the first semiconductor region (4) and is arranged in at least a part of the first main surface (2A); the second contact structure (21) is a structure for electrically contacting the second semiconductor region (6), and is arranged in a partial region of the first main surface (2A) and in at least one of the recesses (19); The first semiconductor layer (7) is made of a first compound semiconductor material, the second semiconductor layer (8) is made of a second compound semiconductor material; the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material; Optoelectronic semiconductor components (1).

2. the first compound semiconductor material and the second compound semiconductor material are each a phosphorus compound semiconductor material; An optoelectronic semiconductor component (1) according to claim 1.

3. The first compound semiconductor material is Al ｎ Ga ｍ In １－ｎ－ｍ P, wherein 0.3≦n≦0.6, 0≦m≦0.2, and 0.4≦n+m≦0.6; An optoelectronic semiconductor component (1) according to claim 1 or 2.

4. The second compound semiconductor material is Al ｎ Ga ｍ In １－ｎ－ｍ P, wherein 0<n<0.6, 0<m<0.6, and 0.4≦n+m≦0.6; An optoelectronic semiconductor component (1) according to any one of claims 1 to 3.

5. The second semiconductor layer (8) is formed thinner than the first semiconductor layer (7). An optoelectronic semiconductor component (1) according to any one of claims 1 to 4.

6. The second semiconductor region (6) is disposed on the opposite side of the second semiconductor layer (8) from the first semiconductor layer (7) and includes a third semiconductor layer (9) containing InGaAlP; the compound semiconductor materials of the second and third semiconductor layers (8, 9) differ in their gallium content and / or doping level; An optoelectronic semiconductor component (1) according to any one of claims 1 to 5.

7. A second main surface (2B) opposite to the first main surface (2A) of the semiconductor layer stack (2) does not have the first and second contact structures (11, 21). An optoelectronic semiconductor component (1) according to any one of claims 1 to 6.

8. The recess (19) has a widened region (19B) between the active region (5) and the second semiconductor layer (8). An optoelectronic semiconductor component (1) according to any one of claims 1 to 7.

9. The second contact structure (21) comprises a connection layer (22), the connection layer (22) covers one or more surfaces (2C, 2D) of the semiconductor layer stack (2) that delimit the at least one recess (19); An optoelectronic semiconductor component (1) according to any one of claims 1 to 8.

10. A cavity (23) is provided in the widened region (19B) between the semiconductor layer stack (2) and the second contact structure (21). An optoelectronic semiconductor component (1) according to claim 8 or 9.

11. An insulating layer (20), The insulating layer (20) is disposed between the semiconductor layer stack (2) and the connection layer (22). An optoelectronic semiconductor component (1) according to claim 9 or 10.

12. A method for manufacturing at least one optoelectronic semiconductor component (1), said method comprising the steps of: Providing a semiconductor layer sequence (2') for producing at least one semiconductor layer stack (2), the semiconductor layer sequence (2') comprises a first semiconductor region (4'), a second semiconductor region (6'), an active region (5') arranged between the first and second semiconductor regions (4', 6'), and a first main surface (2A'), The second semiconductor region (6') comprises a first semiconductor layer (7') and a second semiconductor layer (8'); the second semiconductor layer (8') is disposed on the opposite side of the first semiconductor layer (7') from the active region (5'); forming a first contact structure (11') on the first main surface (2A'); creating at least one recess (19) extending from the first main surface (2A') through the first semiconductor region (4') and the active region (5') to the second semiconductor layer (8'); forming a second contact structure (21') disposed in a partial region of the first main surface (2A') and in the at least one recess (19); said at least one recess (19) is produced by a two-stage etching process, said semiconductor layer sequence (2') being etched in a first etching step down to said first semiconductor layer (7') and in a second etching step down to said second semiconductor layer (8'); method.

13. the first etching step comprises a dry etching process; The method of claim 12.

14. the second etching step comprises a wet chemical etching process; 14. The method according to claim 12 or 13.

15. The first semiconductor layer (7') is formed of a first compound semiconductor material, the second semiconductor layer (8') is formed of a second compound semiconductor material; the first compound semiconductor material has a higher aluminum content than the second compound semiconductor material; 15. The method according to any one of claims 12 to 14.

16. In the wet chemical etching process, an etching agent is used that has a higher etching rate for the first semiconductor layer (7') having a higher aluminum content than for the second semiconductor layer (8') having a lower aluminum content.

16. The method of claim 14 or 15.

17. the widened region (19B) of the at least one recess (19) is produced by the second etching step; The method according to any one of claims 12 to 16.

18. The active region (5') has a quantum well structure, The hybridization of the quantum well structure is performed in a portion of the active region (5') adjacent to the at least one recess (19). The method according to any one of claims 12 to 17.

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