High aspect ratio carbon etching by simulated Bosch process

Abstract

Various embodiments herein relate to methods and apparatus for etching a substrate. The substrate is typically a semiconductor substrate. In various implementations, the method involves receiving the substrate in a process chamber, the substrate including a carbon layer and a mask layer positioned over the carbon layer, the mask layer being patterned to define where features are to be etched in the carbon layer, and exposing the substrate to a plasma to etch features into the carbon layer of the substrate, the composition of the plasma being varied over time to perform at least a deposition step, a clearing step, and an etching step, and the deposition step, the clearing step, and the etching step are cycled through one another until the feature reaches its final depth.

Description

[Technical Field]

[0001] Incorporated by reference: A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] One process that may be used during the fabrication of semiconductor devices is the formation of recessed features in a dielectric material. Such features may be formed by etching using a patterned mask layer that defines where the features are to be etched in the dielectric material. One material that may be used for this mask layer is carbon. Exemplary situations in which such a process may occur include, but are not limited to, memory applications such as DRAM and 3D NAND structures.

[0003] As the semiconductor industry advances and device dimensions shrink, etching these recessed features becomes increasingly difficult.

[0004] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] In one aspect of the disclosed embodiment, there is provided a method of etching a feature into a substrate, the method including receiving a substrate in a process chamber, the substrate including a carbon layer and a mask layer positioned over the carbon layer, the mask layer being patterned to define where a feature is to be etched into the carbon layer; and exposing the substrate to a plasma to etch the feature into the substrate, wherein a composition of the plasma is varied over time to perform at least a deposition step, a clearing step, and an etching step, and the deposition step, clearing step, and etching step are cycled through one another until the feature reaches its final depth.

[0006] In various embodiments, during the deposition step, a plasma may be generated from a first plasma generating gas including a first oxygen source and a boron source, and exposing the substrate to the plasma during the deposition step forms boron oxide on the sidewalls of the feature. In some embodiments, during the clearing step, a plasma may be generated from a second plasma generating gas including a second oxygen source and a halogen source, and exposing the substrate to the plasma during the clearing step may remove boron oxide adjacent to an etch front within the feature. In some embodiments, during the etching step, a plasma is generated from a third plasma generating gas including a third oxygen source, and exposing the substrate to the plasma during the etching step etches the feature isotropically at an etch front within the feature.

[0007] In various embodiments, the deposition step, the clearing step, and the etching step may be cycled iteratively relative to one another, and the deposition step, the clearing step, and the etching step may be balanced differently relative to one another in different iterations. In some such embodiments, balancing the deposition step, the clearing step, and the etching step differently relative to one another in different iterations may result in an etch profile including at least a first portion and a second portion, the first portion and the second portion having different profile shapes selected from vertical, re-entrant, or tapered. In some embodiments, during a first iteration, the deposition step, the clearing step, and the etching step may be balanced relative to one another in a first balance, and during a second iteration, the deposition step, the clearing step, and the etching step may be balanced relative to one another in a second balance, the second iteration occurring after the first iteration, and the second balance prioritizing the deposition step over the etching step relative to the first balance, such that the etch profile formed at the etch front within the feature during the second iteration has a tapered shape. In some embodiments, during a first iteration, the deposition step, the clearing step, and the etching step may be balanced against each other in a first balance, and during a second iteration, the deposition step, the clearing step, and the etching step may be balanced against each other in a second balance, the second iteration occurring after the first iteration, the second balance prioritizing the etching step over the deposition step compared to the first balance, such that the etching profile formed at the etch front within the feature during the second iteration has a re-entrant shape.

[0008] In various embodiments, the plasma is generated sequentially so as not to be extinguished between the deposition step, the clearing step, and the etching step. The clearing step may occur immediately after either the deposition step or the etching step in various embodiments.

[0009] In another aspect of the disclosed embodiments, an apparatus is provided for etching features into a substrate, the apparatus including: a process chamber; a substrate holder positioned in the process chamber, the substrate holder configured to support a substrate, the substrate including a carbon layer and a mask layer positioned on the carbon layer, the mask layer being patterned to define locations where features are to be etched into the carbon layer; an inlet to the process chamber configured to provide a reactant to the process chamber; an outlet to the process chamber configured to remove material from the process chamber; a plasma generator configured to generate a plasma in the process chamber; and a controller configured to expose the substrate to the plasma to etch features into the substrate, the composition of the plasma being varied over time to perform at least a deposition step, a clearing step, and an etching step, and the deposition step, clearing step, and etching step are cycled through one another until the feature reaches its final depth.

[0010] In various embodiments, during the deposition step, the controller may be configured to generate a plasma from a first plasma generating gas comprising a first oxygen source and a boron source, whereby exposing the substrate to the plasma during the deposition step forms boron oxide on the sidewalls of the feature. In some embodiments, during the clearing step, the controller may be configured to generate a plasma from a second plasma generating gas comprising a second oxygen source and a halogen source, whereby exposing the substrate to the plasma during the clearing step removes boron oxide proximate an etch front within the feature. In some embodiments, during the etching step, the controller may be configured to generate a plasma from a third plasma generating gas comprising a third oxygen source, whereby exposing the substrate to the plasma during the etching step etches the feature isotropically at an etch front within the feature.

[0011] In various embodiments, the controller may be configured to cycle the deposition, clearing, and etching steps iteratively relative to one another, and the controller may be configured to balance the deposition, clearing, and etching steps differently in different iterations. In some embodiments, the controller may be configured to balance the deposition, clearing, and etching steps differently in different iterations, such that an etch profile including at least a first portion and a second portion is formed within the feature, the first portion and the second portion having different profile shapes selected from vertical, re-entrant, or tapered. In some embodiments, the controller may be configured to balance the deposition, clearing, and etching steps relative to one another in a first balance during a first iteration, and to balance the deposition, clearing, and etching steps relative to one another in a second balance during a second iteration, the second iteration occurring after the first iteration, and the second balance prioritizing the deposition step over the etch step relative to the first balance, such that an etch profile formed at an etch front within the feature during the second iteration has a tapered shape. In some embodiments, the controller may be configured to balance the deposition step, the clearing step, and the etching step against each other in a first balance during a first iteration, and to balance the deposition step, the clearing step, and the etching step against each other in a second balance during a second iteration, the second iteration occurring after the first iteration, and the second balance prioritizing the etching step over the deposition step compared to the first balance, such that an etching profile formed at an etch front within the feature during the second iteration has a re-entrant shape.

[0012] In various embodiments, the controller may be configured to generate the plasma sequentially such that the plasma is not extinguished between the deposition step, the clearing step, and the etching step, hi some embodiments, the controller may be configured to cause the clearing step to occur immediately after either the deposition step or the etching step.

[0013] These and other aspects are further described below with reference to the drawings. [Brief explanation of the drawings]

[0014] [Figure 1A] FIG. 1A is a diagram illustrating a feature that has been partially etched during a single etching iteration in a cyclic process with a deposition step. [Figure 1B] FIG. 1B is a diagram illustrating a feature that has been partially etched during a single etching iteration in a cyclic process with a clearing step. [Figure 1C] FIG. 1C is a diagram illustrating a feature that has been partially etched during a single etching iteration in a cyclic process involving etching steps.

[0015] [Figure 2] FIG. 2 is a diagram illustrating an example feature profile that may be achieved using the disclosed techniques.

[0016] [Figure 3] FIG. 3 is a diagram illustrating an apparatus configured for plasma processing in accordance with various embodiments herein.

[0017] [Figure 4] FIG. 4 is a diagram illustrating a cluster architecture configured for plasma processing in accordance with various embodiments herein.

[0018] [Figure 5]FIG. 5 shows experimental results illustrating various profile shapes that can be achieved using the techniques disclosed herein.

[0019] [Figure 6] FIG. 6 is a flowchart illustrating a method for etching a feature according to various embodiments herein. DETAILED DESCRIPTION OF THE INVENTION

[0020] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that the specific embodiments are not intended to limit the disclosed embodiments.

[0021] Semiconductor device manufacturing continues to push the boundaries with respect to increasing chip density and reducing cost per bit. One technique for achieving this in the case of 3D NAND is to increase the number of alternating layers in the mold stack (e.g., 90 or more NAND layers are frequently employed in current devices). As a result, the depth:width aspect ratio of features formed in the mold stack is increasing. This increase in aspect ratio creates significant challenges with respect to forming features with desired specifications (e.g., acceptable etch rate, etch profile, curvature, twist, roundness, uniformity, etc.).

[0022] In various embodiments herein, recessed features are formed in a carbon mask layer. After the features are formed in the carbon mask layer, that layer can be used as a mask to transfer the recessed features into an underlying material. The underlying material can be a 3D NAND mold stack including alternating layers of dielectric materials, such as silicon oxide and silicon nitride, or silicon oxide and polysilicon.

[0023] Carbon masks have shown promise, especially for high-aspect-ratio etching, where features have depth-to-width aspect ratios of approximately 50:1 or greater. However, carbon masks present particular challenges with respect to bowing, bottom critical dimension (CD) control, and profile challenges such as local CD uniformity and hole circularity. Poor profile and local CD uniformity when etching carbon masks can significantly impact subsequent memory hole formation, ultimately leading to electrical failure at the memory string level and compromising final device performance.

[0024] Typically, features are etched into the carbon mask using a process called reactive ion etching. A second mask layer, often silicon-based (e.g., SiON, SiO, SiN, SiOC, SiB, etc.), is applied over the carbon mask. The second mask layer is patterned to define where features will be etched into the carbon mask (and underlying material). The substrate is exposed to an oxygen-based plasma to transfer the features from the second mask layer into the carbon mask. During this etching process, profile curvature is common, typically due to ion angular distribution and ion scattering behavior resulting from mask shape variations (e.g., faceting, clogging, etc.). To provide sidewall protection, a sulfur-based passivation gas may be added to the oxygen-based plasma. However, excessive passivation gas can lead to non-circular hole shapes and reduced etch rates.

[0025] Another challenge in high aspect ratio memory hole etching is maintaining good local CD uniformity throughout the process. High aspect ratio etching tends to result in poor local CD uniformity due to the sputtering and redeposition behavior of the mask. For example, material from the silicon-based second mask layer can be sputtered and redeposited near the top of the feature, resulting in clogged features, non-circular features, or undesirable etch profiles. These issues are undesirable.

[0026] In embodiments herein, a new approach is used to etch a carbon mask. The new approach provides a cyclical etching method involving (1) a deposition step, (2) a clearing step, and (3) an etching step. These steps can be performed in any order and can be cycled through one another until the features reach their final depth in the carbon mask. The steps can be cycled sequentially to maximize throughput. Alternatively, the steps can be performed non-sequentially. The features are actively etched in all three steps. In other words, the features continue to deepen during the deposition and clearing steps.

[0027] FIG. 6 shows a flowchart illustrating a method for etching features in a substrate in accordance with various embodiments herein. The method begins in operation 601, where a substrate is received in a process chamber. The substrate includes a carbon layer and a mask layer positioned over the carbon layer. The mask layer is patterned to define where features are to be etched into the carbon layer. In operation 603, the substrate is exposed to a plasma. During operation 603, the composition of the plasma is varied over time to perform a deposition step 603a, a clearing step 603b, and / or an etching step 603c. Each of these steps is described further below. In operation 605, it is determined whether the feature has reached its final depth. Such a determination may be made based on one or more factors, including, but not limited to, processing time, reactant flow rates, plasma conditions, and / or metrology. The plasma may or may not be extinguished during operation 605. If the feature has reached its final depth in operation 605, the method is complete. If the feature has not yet reached its final depth in operation 605, the method returns to operation 603, and the substrate continues to be exposed to the plasma (or is exposed to the plasma at another time). Operation 603 (including deposition step 603a, clearing step 603b, and etching step 603c) is repeated until the feature reaches its final depth. In particular, as operation 603 is repeated, the balance between deposition step 603a, clearing step 603b, and etching step 603c can be varied in a controlled manner to result in a desired feature shape.

[0028] The new approach is similar to the Bosch process, a cyclic etching process designed to form high-aspect-ratio features in silicon. The process has been adapted and modified to etch carbon instead of silicon. Until now, such a process has not been applied to etching carbon-based materials.

[0029] One advantage of the disclosed technique is that the etch profile can be very carefully controlled to achieve the desired CD along the entire depth of the feature. This potentially enables arbitrary profile shapes within the etched carbon mask. This high degree of CD / profile control can be achieved by controlling the balance between different steps (e.g., deposition vs. clear vs. etch) during each iteration. The resulting profile in the etched carbon can be vertical, sloped, curved, tapered, re-entrant, bowed, or a combination thereof. The desired profile shape may vary depending on the specific application. The disclosed technique also offers numerous additional advantages. These include high throughput, good hole shape performance, and low cost compared to other expensive passivation schemes.

[0030] A related advantage of the disclosed techniques is that they can significantly shorten the development process for optimizing memory hole etching (or other applications), resulting in faster process development cycles. Conventional etching techniques, such as reactive ion etching, involve significant tradeoffs when optimizing different aspects of the etching process and resulting features. These tradeoffs include improving or degrading performance with respect to bottom hole shape, local CD uniformity, unopen performance, and the like. Often, techniques that improve one of these properties degrade another. Therefore, designing a process that achieves adequate performance with respect to all of these properties is extremely challenging. Recently, there have been numerous optimization requirements for memory hole etching to achieve the best performance. Due to the aforementioned difficulties, profile tuning in the case of reactive ion etching involves significant efforts over a long period of time to address various tradeoffs. In contrast, the techniques disclosed herein allow for significant profile flexibility by adjusting deposition, clearing, and etching steps during each iteration to control the CD and associated local profile shape at each etch depth. This is expected to significantly shorten process development cycles.

[0031] As previously mentioned, the disclosed etching technique involves three steps, including a deposition step, a clearing step, and an etching step. All three steps involve exposing the substrate to an oxygen-based plasma, with specific additional chemicals being provided during each step. The steps are cycled through one another until the feature is completely etched into the carbon mask.

[0032] The substrate to be etched includes at least a carbon layer, which can act as a mask layer when later transferring features to an underlying material, such as a dielectric material. The carbon layer can be amorphous and can be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The features are etched into the carbon layer. In many embodiments, the substrate further includes a mask layer over the carbon layer, which defines where the features are to be formed in the carbon layer. This mask layer may be a silicon-based material, as described above. In these or other embodiments, the substrate may further include an underlying material positioned below the carbon layer. The underlying material may include a dielectric material, for example, a mold stack for forming a 3D NAND device.

[0033] While the embodiments herein are presented in the context of memory applications such as 3D NAND, it is understood that the embodiments are not limited thereto. In general, the techniques herein can be applied to any embodiment in which features are etched into carbon, regardless of whether the carbon is subsequently used as a mask layer, and regardless of other materials that may be present on the substrate. Other specific applications in which the disclosed techniques may be used include, but are not limited to, DRAM and logic applications. In some such applications, the process conditions described below may be modified as appropriate for the particular application. For example, such applications may utilize lower power regimes and / or shorter plasma exposure durations than those listed below.

[0034] During the deposition step, a boron-based film (e.g., boron oxide) is deposited within the feature. The boron-based film is deposited conformally and protects the sidewalls from overetching. The boron-based passivation film has a low adhesion coefficient and is not prone to agglomeration. Ion bombardment causes the boron-based film to migrate from the top of the feature (where deposition begins) down along the feature's sidewalls. Boron oxide exhibits good etch resistance to oxygen-based plasmas, making it an excellent material for protecting the feature's sidewalls from overetching. This protection also allows the use of relatively aggressive plasma conditions that provide very high etch rates (e.g., during all steps) without compromising the feature profile. The feature is also aggressively etched during the deposition step. In fact, etching can occur very rapidly during the deposition step, with etch rates often ranging from about 100 nm / min to about 1000 nm / min. Aggressive plasma conditions (e.g., relatively high TCP power and high bias voltage, as shown below) contribute to the high etch rate. Etching during the deposition step is substantially vertical (rather than isotropic / lateral) due to the formation of a boron-based film that acts to protect the sidewalls. The deposition of the boron-based film, in conjunction with the clear and etch steps, provides a high degree of control over the shape of the etch profile.

[0035] To accomplish the deposition step, the substrate is exposed to a relatively aggressive plasma. The plasma is an oxygen-based plasma generated from a plasma generating gas including at least an oxygen source (e.g., O2, HO, CO2, CO, COS, O3, etc.) and a boron source (e.g., BCl3, B2H6, B(CH3)3, etc.). The plasma generating gas may further include an optional passivation chemical source (e.g., COS, SO2, N2, CO2, etc.), which may act in combination with the boron source to further passivate the feature sidewalls. The oxygen source may be provided at a minimum flow rate of about 100 sccm to a maximum flow rate of about 2000 sccm. The boron source may be provided at a minimum flow rate of about 5 sccm to a maximum flow rate of about 100 sccm. The passivation chemical source (if present) may be provided at a minimum flow rate of about 25 sccm to a maximum flow rate of about 500 sccm. In various embodiments, the passivation chemical source may be provided at a flow rate higher or lower than that of the boron source. Typically, the flow rate of the oxygen source is substantially higher than the combined flow rate of the boron source and the passivation chemical source. The plasma may also contain one or more inert / carrier gases, such as Ar, He, or Ne. The plasma is a transformer-coupled plasma (TCP) and is generated with a high TCP power and a high bias voltage. For example, the plasma may be generated with a minimum source TCP power of about 500 W. In these or other embodiments, the plasma may be generated with a maximum source TCP power of about 7500 W. The source TCP power may be provided at one or more frequencies, such as 13 MHz, 2 MHz, or a combination thereof. In addition, the substrate is heavily biased during the deposition step. For example, the substrate may be biased with a minimum bias power of about 50 W to a maximum bias power of about 8000 W (e.g., at a frequency of about 13 MHz to about 400 kHz). The plasma may be generated at a specific duty cycle during the deposition phase, for example, with a minimum duty cycle of about 5% to a maximum duty cycle of about 100%. These plasma generation conditions represent conditions suitable for processing a single 300 mm diameter semiconductor substrate and can be suitably scaled for additional substrates or substrates of other sizes.

[0036] During the deposition step, numerous other process conditions can be controlled. For example, the pressure in the process chamber can be from a minimum of about 10 mT to a maximum of about 50 mT. The temperature of the substrate can be controlled, for example, by controlling the temperature of the substrate support and / or associated hardware. In various embodiments, the substrate support temperature can be controlled from a minimum of about -40°C to a maximum of about 100°C.

[0037] The duration of the deposition step can be controlled during each iteration and may vary between different iterations. Generally, the duration of the deposition step may range from a minimum duration of about 3 seconds to a maximum duration of about 30 seconds. As explained further below, the ratio of the durations of the various steps (deposition, clear, and etch) during each iteration significantly affects the shape of the etch profile formed.

[0038] During the clear step, excess polymer buildup is removed from the etch front (e.g., the bottom of the feature). Additionally, etch by-products that are clogging or beginning to clog the feature (e.g., on the sidewalls of the mask) can be removed. Such etch by-products typically include SiO-based materials from the mask layer above the carbon layer. These by-products are problematic because they contribute to local depth and CD non-uniformities across the substrate. Features are also actively etched during the clear step. For example, the etch rate during the clear step can be from about 50 nm / min to about 1000 nm / min.

[0039] To accomplish the clearing step, the substrate is exposed to a relatively aggressive plasma generated from a combination of an oxygen source, a halogen source, and an optional passivating chemical source. Often, the halogen source is combined with a fluorine source (e.g., C x F y (e.g., CF4, C2F6, C4F6, C4F8, etc.), NF3, SF6, CH x F y(e.g., CHF3, CH2F2, CH3F), SiF4, etc.), or a chlorine source (e.g., Cl2, HCl, etc.). The passivation chemical source may include one or more of the passivation chemical sources listed above. The oxygen source may include one or more of the oxygen sources listed above. The oxygen source may be provided at a minimum flow rate of about 100 sccm to a maximum flow rate of about 2000 sccm. The halogen source may be provided at a minimum flow rate of about 3 sccm to a maximum flow rate of about 100 sccm. The passivation chemical source (if present) may be provided at a minimum flow rate of about 25 sccm to a maximum flow rate of about 500 sccm. In various embodiments, the passivation chemical source may be provided at a higher or lower flow rate than the halogen source. Typically, the flow rate of the oxygen source is substantially higher than the combined flow rate of the halogen source and the passivation chemical source. The plasma may also include one or more inert / carrier gases, such as Ar, He, or Ne. The plasma is a transformer-coupled plasma (TCP) and is generated with high TCP power and a high bias voltage. For example, the plasma may be generated at a minimum source TCP power of about 500 W. In these or other embodiments, the plasma may be generated at a maximum source TCP power of about 7500 W. The source TCP power may be provided at one or more frequencies, such as 13 MHz, 2 MHz, or a combination thereof. In addition, the substrate is heavily biased during the clearing step. For example, the substrate may be biased at a minimum bias power of about 50 W to a maximum bias power of about 8000 W (e.g., at a frequency of about 13 MHz to about 400 kHz). The plasma may be generated at a particular duty cycle during the clearing step, for example, at a minimum duty cycle of about 5% to a maximum duty cycle of about 100%. These plasma generation conditions represent conditions suitable for processing a single 300 mm diameter semiconductor substrate and can be appropriately scaled for additional substrates or substrates of other sizes.

[0040] During the clearing step, numerous other process conditions can be controlled. For example, the pressure in the process chamber can be from a minimum of about 10 mT to a maximum of about 50 mT. The temperature of the substrate can be controlled, for example, by controlling the temperature of the substrate support and / or associated hardware. In various embodiments, the substrate support temperature can be controlled from a minimum of about -40°C to a maximum of about 100°C.

[0041] The duration of the clear step can be controlled during each iteration and may vary between different iterations. Generally, the duration of the clear step may range from a minimum duration of about 1 second to a maximum duration of about 15 seconds. As explained further below, the ratio of the durations of the various steps (deposition, clear, and etch) during each iteration significantly affects the shape of the etch profile formed.

[0042] During the etching step, the features are isotropically etched (e.g., etched both vertically and laterally). Unlike conventional Bosch processes implemented to etch silicon, the disclosed etching process utilizes both radicals and ions to perform the etching step. For high-density carbon, the chemical etching rate is typically much slower (e.g., <200 nm / min at an aspect ratio of about 10:1) compared to the ion-assisted etching rate (e.g., >500 nm / min at an aspect ratio of about 10:1). Strong passivation at the pre-etched sidewall surface resulting from the deposition step causes ion scattering at the pre-etched sidewall, resulting in a curved, vertical, or tapered profile at the etch front. The resulting etch profile depends on the balance between etchant and polymer formation at the etch front, which is primarily a result of the balance between the deposition, clearing, and etching steps, including the flow provided during each step and the duration of each step.

[0043] To accomplish the etching step, the substrate is exposed to a relatively aggressive plasma generated from an oxygen source and an optional passivating chemical source. The passivating chemical source may include one or more of the passivating chemical sources listed above. The oxygen source may include one or more of the oxygen sources listed above. The oxygen source may be provided at a minimum flow rate of about 100 sccm to a maximum flow rate of about 2000 sccm. The passivating chemical source (if present) may be provided at a minimum flow rate of about 25 sccm to a maximum flow rate of about 500 sccm. Typically, the flow rate of the oxygen source is substantially higher than the flow rate of the passivating chemical source. The plasma may also include one or more inert / carrier gases, such as Ar, He, or Ne. The plasma is a transformer-coupled plasma (TCP) and is generated with a high TCP power and a high bias voltage. For example, the plasma may be generated at a minimum source TCP power of about 500 W. In these or other embodiments, the plasma may be generated at a maximum source TCP power of about 7500 W. The source TCP power may be provided at one or more frequencies, such as 13 MHz, 2 MHz, or a combination thereof. In addition, the substrate is heavily biased during the etching step. For example, the substrate may be biased at a minimum bias power of about 50 W to a maximum bias power of about 8000 W (e.g., at a frequency of about 13 MHz to about 400 kHz). The plasma may be generated at a specific duty cycle during the etching step, for example, at a minimum duty cycle of about 5% to a maximum duty cycle of about 100%. These plasma generation conditions represent conditions suitable for processing a single 300 mm diameter semiconductor substrate and can be appropriately scaled for additional substrates or substrates of other sizes.

[0044] During the etching step, numerous other process conditions can be controlled. For example, the pressure in the process chamber can be from a minimum of about 10 mT to a maximum of about 50 mT. The temperature of the substrate can be controlled, for example, by controlling the temperature of the substrate support and / or associated hardware. In various embodiments, the substrate support temperature can be controlled from a minimum of about -40°C to a maximum of about 100°C.

[0045] The duration of the etching step can be controlled during each iteration and may vary between different iterations. Generally, the duration of the etching step may be from a minimum duration of about 5 seconds to a maximum duration of about 50 seconds.

[0046] In various embodiments, the plasma generating gas used to form the plasma may be relatively low in polymerizing chemicals (e.g., compared to the deposition and / or clearing steps) to reduce the formation of polymers at the etch front. This strategy may improve the roundness of the etched features.

[0047] The combined total duration of the deposition, clear, and etch steps in a single iteration can be approximately 1 to 100 seconds. The total number of iterations can be approximately 10 to 10,000. Often, these steps are performed consecutively without extinguishing the plasma to maximize throughput. To switch between steps, the chemicals provided to the reaction chamber are controlled as described above. Fast switching hardware may be provided to enable rapid switching between different chemicals. In some cases, the hardware (e.g., valves and associated piping) may be similar to that commonly used for atomic layer deposition (ALD), which often provides fast switching times for different chemicals. This hardware may enable improved phase separation and enhanced etching performance.

[0048] Additionally, one or more other processing conditions may be varied between steps, including, but not limited to, pressure, substrate support temperature, TCP plasma source power, TCP plasma frequency, bias power, bias frequency, duty cycle, etc.

[0049] Generally speaking, the shape of the etch front can be controlled to achieve a desired etch profile by balancing the deposition, clearing, and etching steps. For example, a first iteration may result in a particular degree of deposition, clearing, and etching. A second iteration, which prioritizes deposition over clearing and / or etching, can result in a local etch profile that tapers at that depth (as used herein, a tapered local profile is wider at the top and narrower at the bottom). In contrast, if the second iteration prioritizes clearing and / or etching over deposition, the local etch profile formed at this depth may be a re-entrant angle. As used herein, a re-entrant local profile is narrow at the top and wide at the bottom. Similarly, if the second iteration provides balanced amounts of deposition, clearing, and etching (e.g., does not substantially favor any particular step), the local profile formed at the etch front will be substantially vertical. The deposition, clearing, and etching steps are repeated, and the balance between these steps during each iteration controls the shape of the etch profile formed.

[0050] The disclosed techniques offer a high degree of profile control flexibility, including the ability to achieve target CDs at desired depths. These factors significantly improve profile and performance control for subsequent memory hole etches or other etch processes where carbon is used as a mask.

[0051] The balance between the deposition, clear, and etch steps can be controlled in a number of ways. For example, the duration of each step can be controlled, and the ratio of these durations can be controlled. Alternatively or additionally, the flow rates provided during each step can be controlled, and the ratio of these flow rates between different steps can also be controlled. Alternatively or additionally, the plasma conditions and / or other processing conditions provided during each step can be controlled, and the ratio of such conditions between different steps can also be controlled. Exemplary conditions that can be controlled to affect the balance between each step during each iteration include, but are not limited to, duration, plasma power, duty cycle, bias voltage, chemistry, pressure, temperature, etc. As described throughout this application, the balance between the deposition, clear, and etch steps during each iteration controls the shape of the resulting etch profile. In various embodiments, the balance between these steps is varied between different iterations (e.g., by varying one or more processing conditions between different iterations as described herein) to achieve a desired etch profile. One or more of the processing conditions described herein can be varied between different iterations to achieve a desired balance between the deposition, clear, and etch steps for each iteration. The ratio of such process conditions between different iterations can be controlled, i.e., the various process conditions can be controlled, varied, and balanced with one another (1) within each step, (2) between steps in a given iteration, and / or (3) between different iterations.

[0052] While the deposition, clearing, and etching steps together form a single iteration, it is understood that one or more of these steps may be omitted or repeated within a single iteration. Such omissions and repetitions may vary over the course of various iterations of the etching process to achieve a desired etching profile. For example, a first iteration may involve a deposition step, a clearing step, and an etching step, a second iteration may involve a deposition step and an etching step, a third iteration may involve a deposition step and a clearing step, a fourth iteration may involve a clearing step and an etching step, and so on. These can be mixed and combined as desired for a particular application and desired etching profile. Similarly, while the deposition step, clearing step, and etching step are typically described in that order, it is understood that these steps may be performed in any order. For example, a clearing step may be performed after the deposition step and / or after the etching step to remove polymer buildup at different times. Furthermore, the order of these steps may vary between different iterations. In one example, the first iteration involves a deposition step, followed by a clearing step, followed by an etching step, and the second iteration involves a deposition step, followed by an etching step, followed by a clearing step. Many variations are possible.

[0053] 1A-1C together illustrate features partially etched into a substrate during a single etching iteration according to various embodiments herein. The substrate includes a carbon layer 102 and a mask layer 104. The carbon layer 102 may then be used as a mask layer for etching an underlying layer (e.g., to form memory holes in a dielectric material in various embodiments). The mask layer 104 is patterned to include a series of openings that define where features will be etched into the carbon layer 102. The mask layer 104 is a silicon-based mask material in various embodiments, although any suitable mask material may be used.

[0054] FIG. 1A shows the substrate after a deposition step. As previously described, during the deposition step, features are actively etched into the carbon layer 102, and a boron-based film 106 is simultaneously formed on the sidewalls and bottom of the partially etched features. FIG. 1B shows the substrate after a clearing step. During the clearing step, features are actively etched into the carbon layer 102, and the boron-based film 106 is removed from the bottom of the features. This acts to clear the etch front, allowing for more substantial etching, while maintaining a high degree of protection for the feature sidewalls where the boron-based film 106 is present. While FIG. 1B does not show a significant additional etch depth compared to FIG. 1A, it is understood that etching is occurring during this step. FIG. 1C shows the substrate after an etching step. During the etching step, features are actively etched into the carbon layer 102. As shown in FIG. 1C, during the etching step, the bottom of the feature is isotropically etched, meaning that etching occurs both vertically and laterally. Since the boron-based film 106 is not formed during the etching step, substantial lateral etching can be achieved at the etch front during this step, if desired.

[0055] Each step offers distinct advantages that combine to yield highly customizable, high-quality features: for example, the deposition step promotes low bowing, the clearing step promotes high local CD uniformity, the etching step (in combination with the other steps) promotes tunable profile and high feature roundness, and all three steps promote high etch rates.

[0056] FIG. 2 illustrates an exemplary feature profile that can be achieved using the disclosed techniques. This feature profile represents a profile achieved during a single iteration of the etching method described herein, e.g., a deposition step, a clearing step, and an etching step. While many different profile shapes can be formed, the shape illustrated in FIG. 2 is particularly advantageous for etching a carbon layer used as a masking layer for etching memory holes or other recessed features in a dielectric material positioned below the carbon layer. The feature profile includes an upper portion 202, a middle portion 204, and a lower portion 206. In various embodiments, the upper portion 202 is substantially formed during the deposition step, while the middle portion 204 and the lower portion 206 are substantially formed during the etching step. The clearing step can also contribute to the shape of each of these portions. In this example, the upper portion 202 includes a tapered profile, the middle portion 204 includes a curved / re-entrant profile, and the lower portion 206 includes a tapered profile. In a similar example, the upper portion 202 includes a substantially vertical profile. Each of these portions contributes to the etch profile and associated CD achieved at each depth.

[0057] Device The methods described herein can be performed by any suitable apparatus including at least a process chamber, a plasma generator configured to generate a plasma in the process chamber, and a controller configured to perform one or more of the methods described herein.

[0058] FIG. 3 schematically illustrates a cross-sectional view of an inductively coupled plasma etching apparatus 300 according to certain embodiments of the present disclosure. The Kiyo™ reactor manufactured by Lam Research, Inc. of Fremont, California, is an example of a suitable reactor that can be used to implement the techniques described herein. The inductively coupled plasma etching apparatus 300 includes an overall etching chamber structurally defined by chamber 301 walls and window 311. The chamber 301 walls can be fabricated from stainless steel or aluminum. The window 311 can be fabricated from quartz or other dielectric materials. An optional plasma grid 350 divides the overall etching chamber into upper and lower subchambers 302 and 303. The plasma grid 350 may include a single grid or multiple individual grids. In many embodiments, the plasma grid 350 can be removed, thereby utilizing the chamber space comprised of subchambers 302 and 303.

[0059] A chuck 317 (also referred to as a substrate support) is positioned within the lower subchamber 303 near the bottom inner surface. The chuck 317 is configured to receive and hold a wafer 319 (e.g., a semiconductor wafer) on which an etching process is performed. If present, the chuck 317 may be an electrostatic chuck for supporting the wafer 319. In some embodiments, an edge ring (not shown) surrounds the chuck 317 and, if present on the chuck 317, has an upper surface that is approximately planar with the upper surface of the wafer 319. The chuck 317 also includes an electrostatic electrode for chucking and dechucking the wafer. For this purpose, a filter and DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 319 from the chuck 317 may also be provided. The chuck 317 may be charged using an RF power supply 323. The RF power supply 323 is connected to a matching circuit 321 through connection 327. The matching circuit 321 is connected to the chuck 317 through connection 325. In this manner, RF power supply 323 is connected to chuck 317 .

[0060] A coil 333 is positioned over the window 311. The coil 333 is fabricated from a conductive material and includes at least one full turn. The coil 333 shown in FIG. 3 includes three turns. A cross section of the coil 333 is symbolized, with the coil marked with an "X" extending into the page and the coil marked with a "●" extending out of the page. An RF power source 341 is configured to provide RF power to the coil 333. Generally, the RF power source 341 is connected to a matching circuit 339 through connection 345. The matching circuit 339 is connected to the coil 333 through connection 343. In this manner, the RF power source 341 is connected to the coil 333. An optional Faraday shield 349 is positioned between the coil 333 and the window 311. The Faraday shield 349 is maintained in a spaced apart relationship relative to the coil 333. The Faraday shield 349 is positioned directly above the window 311. The coil 333, the Faraday shield 349, and the window 311 are each configured to be substantially parallel to one another. The Faraday shield can prevent metals or other species from depositing on the dielectric window of the plasma chamber.

[0061] Process gases may be supplied through a main injection port 360 (also referred to as a main inlet) positioned in the upper chamber and / or through a side injection port 370, which may also be referred to as an STG or side inlet. A vacuum pump, e.g., a single-stage or two-stage mechanical dry pump and / or a turbomolecular pump 340, may be used to draw process gases from the process chamber, and pressure within the plasma etcher 300 may be maintained during plasma processing operations by using a closed-loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown).

[0062] During operation of the apparatus, one or more reactant gases can be supplied through injection ports 360 and / or 370. In certain embodiments, gases can be supplied only through the main injection port 360 or only through the side injection port 370. In some cases, the injection ports can be replaced with showerheads. The Faraday shield 349 and / or the optional plasma grid 350 can include internal channels and holes that allow process gases to be delivered to the chamber. Either or both of the Faraday shield 349 and the optional plasma grid 350 can serve as showerheads for delivering process gases.

[0063] Radio frequency power is supplied from RF power supply 341 to coil 333, causing RF current to flow through coil 333. The RF current flowing through coil 333 generates an electromagnetic field around coil 333. The electromagnetic field generates an induced current within upper subchamber 302. Physical and chemical interactions of the various generated ions and radicals with wafer 319 selectively etch features on the wafer.

[0064] If a plasma grid 350 is used such that both the upper subchamber 302 and the lower subchamber 303 are present, induced currents act on the gas present in the upper subchamber 302, generating an electron-ion plasma in the upper subchamber 302. The optional plasma grid 350 (if present) may also act to limit the number of thermal electrons in the lower subchamber 303. In some embodiments, the apparatus is designed and operated such that the plasma present in the lower subchamber 303 is an ion-ion plasma. In other embodiments, the apparatus may be designed and operated such that the plasma present in the lower subchamber 303 is an electron-ion plasma. Internal plasma grids and ion-ion plasmas are further described in U.S. Patent Application No. 14 / 082,009, entitled "INTERNAL PLASMA GRID FOR SEMICONDUCTOR FABRICATION," filed November 15, 2013, and U.S. Patent No. 9,245,761, each of which is incorporated herein by reference in its entirety.

[0065] Volatile etch byproducts may be removed from the lower subchamber 303 through port 322 (also referred to as an outlet). The chuck 317 disclosed herein can operate at high temperatures ranging from about 30°C to about 250°C. In some cases, the chuck 317 can also operate at lower temperatures, for example, when the chuck 317 is actively cooled. In such cases, the chuck 317 can operate at substantially lower temperatures, as desired. The temperature depends on the etch process operation and the particular recipe. In some embodiments, the chamber 301 can operate at pressures ranging from about 1 mTorr to about 95 mTorr. In certain embodiments, the pressure can be higher.

[0066] Chamber 301 may be coupled to equipment (not shown) when installed in a clean room or fabrication facility. The equipment includes plumbing that provides process gases, vacuum, temperature control, and environmental particle control. These equipment are coupled to chamber 301 when installed in the target fabrication facility. Additionally, chamber 301 may be coupled to a transfer chamber that allows a robot to move semiconductor wafers in and out of chamber 301 using typical automated operations.

[0067] In some embodiments, a system controller 330 (which may include one or more physical or logical controllers) controls some or all of the operation of the etch chamber. The system controller 330 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the system controller 330 or may be provided over a network. In certain embodiments, the system controller 330 executes system control software.

[0068] In some cases, the system controller 330 controls gas concentrations, wafer movement, and / or power supplied to the coil 333 and / or chuck 317. The system controller 330 can control gas concentrations, for example, by opening and closing associated valves and generating one or more inlet gas flows that provide the required reactants at the appropriate concentrations. In various embodiments herein, the system controller 330 controls switching between deposition, clear, and etch steps by providing the appropriate chemicals to the process chamber at the start of each step (e.g., through appropriate valves, piping, etc.). Wafer movement can be controlled, for example, by moving a wafer positioning system as desired. The power supplied to the coil 333 and / or chuck 317 can be controlled to provide specific RF power levels. Similarly, if the optional plasma grid 350 is used, the RF power applied to the grid can be adjusted by the system controller 330.

[0069] The system controller 330 can control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, etc., reaches a certain threshold), timing of actions (e.g., opening a valve at a certain time during the process), or commands received from a user. Exemplary controllers are described further below.

[0070] FIG. 4 illustrates a semiconductor process cluster architecture with various modules interfacing with a vacuum transfer module 438 (VTM). The arrangement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. An airlock 430, also known as a load lock or transfer module, is shown in the VTM 438 along with four processing modules 420a-420d, which may be individually optimized to perform various fabrication processes. By way of example, processing modules 420a-420d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processes. One or more of the substrate etching processing modules (any of 420a-420d) may be implemented as disclosed herein. The airlock 430 and process modules 420 may be referred to as "stations." Each station has a facet 436 that interfaces the station to the VTM 438. Within each facet, sensors 1-18 are used to detect the passage of wafer 426 as it moves between the respective stations.

[0071] A robot 422 transfers wafers 426 between stations. In one embodiment, the robot 422 has one arm, and in another embodiment, the robot 422 has two arms, each arm having an end effector 424 for picking up wafers, such as wafers 426 for transfer. A front-end robot 432 in an atmospheric transfer module (ATM) 440 is used to transfer wafers 426 from cassettes or front-opening unified pods (FOUPs) 434 in a load port module (LPM) 442 to the airlock 430. A module center 428 in the process module 420 is one location for placing wafers 426. An aligner 444 in the ATM 440 is used to align the wafers.

[0072] In an exemplary processing method, a wafer is placed into one of the FOUPs 434 within the LPM 442. The front-end robot 432 transfers the wafer from the FOUP 434 to the aligner 444, which allows the wafer 426 to be properly centered before being etched or processed. After being aligned, the wafer 426 is moved into the airlock 430 by the front-end robot 432. Because the airlock module has the ability to match the environment between the ATM and the VTM, the wafer 426 can move between the two pressure environments without being damaged. From the airlock 430, the wafer 426 is moved by the robot 422 through the VTM 438 to one of the process modules 420a-420d. To accomplish this wafer transfer, the robot 422 uses end effectors 424 on each of its arms. Once processed, the wafer 426 is moved from the process modules 420a-420d to the airlock 430 by the robot 422. From here, the wafer 426 can be moved by the front-end robot 432 to one of the FOUPs 434 or to the aligner 444 .

[0073] It should be noted that the computer controlling the wafer movement may be local to the cluster architecture, or may be located external to the cluster architecture or at a remote location on the manufacturing floor and connected to the cluster architecture via a network.

[0074] In some embodiments, the controller is part of a system, and such a system may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. The controller may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or type of system. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from tools and other transfer tools connected or interfaced with a particular system, and / or wafer transfer to and from load locks.

[0075] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0076] In some embodiments, the controller may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the controller may be in the “cloud” or all or part of a fab host computer system. This allows for remote access of wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, configure processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. These instructions may change over the course of different iterations of the deposition, clear, and etch steps. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as noted above, the controller may be distributed, for example, by having one or more individual controllers networked together and working together toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0077] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0078] As noted above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0079] experiment Numerous experiments were conducted to demonstrate that the disclosed techniques can be used to create desired etching profiles for features etched into carbon layers, with a high degree of flexibility in profile shape and high-quality features. The results of one such experiment are shown in FIG. 5. In this experiment, a first substrate and a second substrate were etched using the techniques described herein. FIG. 5 shows the local critical dimensions of features etched into each substrate at various depth levels. The results associated with the first substrate are shown by line 501, and the results associated with the second substrate are shown by line 502. Each substrate was etched by repeating the deposition, clear, and etch steps described herein. The balance between the different steps was controlled during each iteration for each substrate. Furthermore, the balance between the different steps was controlled differently for each substrate. As a result, the etch profiles formed were different for the two substrates. As shown by line 501, the first substrate had a profile that included a slightly tapered or vertical upper portion, a substantially vertical middle portion, and a lower portion that was more tapered than the upper portion. As shown by line 502, the second substrate had a profile that included a vertical or slightly re-entrant upper portion, a substantially vertical middle portion, and a tapered lower portion.

[0080] While Figure 5 shows results associated with only two substrates, it is understood that the techniques described herein can be used to create essentially any desired etch profile shape, with tapered, vertical, or re-entrant profiles at any particular etch depth, which is a significant improvement over conventional carbon etching techniques.

[0081] conclusion Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Therefore, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein.

Claims

1. 1. A method of etching a feature into a substrate, comprising: receiving the substrate in a process chamber, the substrate comprising a carbon layer and a mask layer positioned over the carbon layer, the mask layer patterned to define where the features are to be etched into the carbon layer; exposing the substrate to a plasma to etch the feature into the carbon layer of the substrate, wherein a composition of the plasma is varied over time to perform at least a deposition step, a clearing step, and an etching step, and the deposition step, the clearing step, and the etching step are cycled through one another until the feature reaches its final depth. A method comprising:

2. 10. The method of claim 1, wherein during the depositing step, the plasma is generated from a first plasma generating gas comprising a first oxygen source and a boron source, and exposing the substrate to the plasma during the depositing step forms boron oxide on sidewalls of the feature.

3. 3. The method of claim 2, wherein during the clearing step, the plasma is generated from a second plasma generating gas comprising a second oxygen source and a halogen source, and exposing the substrate to the plasma during the clearing step removes boron oxide adjacent an etch front in the feature.

4. 4. The method of claim 3, during the etching step, the plasma is generated from a third plasma generating gas comprising a third oxygen source, and exposing the substrate to the plasma during the etching step etches the feature isotropically at the etch front within the feature.

5. 10. The method of claim 1, The method wherein the deposition step, the clearing step, and the etching step may be cycled iteratively around one another, the deposition step, the clearing step, and the etching step being balanced differently with respect to one another in different iterations.

6. 6. The method of claim 5, balancing the depositing step, the clearing step, and the etching step differently from one another in different iterations to result in an etching profile comprising at least a first portion and a second portion, the first portion and the second portion having different profile shapes selected from vertical, re-entrant, or tapered.

7. 6. The method of claim 5, during a first iteration, the deposition step, the clearing step, and the etching step are balanced against one another in a first balance, and during a second iteration, the deposition step, the clearing step, and the etching step are balanced against one another in a second balance, the second iteration occurring after the first iteration, the second balance prioritizing the deposition step over the etching step relative to the first balance, such that an etching profile formed at an etch front within the feature during the second iteration has a tapered shape.

8. 6. The method of claim 5, during a first iteration, the deposition step, the clearing step, and the etching step are balanced against one another in a first balance, and during a second iteration, the deposition step, the clearing step, and the etching step are balanced against one another in a second balance, the second iteration occurring after the first iteration, the second balance prioritizing the etching step over the deposition step relative to the first balance, such that an etching profile formed at an etch front within the feature during the second iteration has a re-entrant shape.

9. 10. The method of claim 1, The method, wherein the plasma is generated continuously so as not to be extinguished between the deposition step, the clearing step, and the etching step.

10. 10. The method of claim 1, A method wherein the clearing step occurs immediately after either the deposition step or the etching step.

11. 1. An apparatus for etching features into a substrate, comprising: a process chamber; a substrate holder positioned in the process chamber, the substrate holder configured to support the substrate, the substrate comprising a carbon layer and a mask layer positioned over the carbon layer, the mask layer patterned to define where the features are to be etched into the carbon layer; an inlet to the process chamber configured to provide a reactant to the process chamber; an outlet to the process chamber configured to remove material from the process chamber; a plasma generator configured to generate a plasma in the process chamber; The substrate is exposed to a plasma to etch the feature into the carbon layer of the substrate, the composition of the plasma being varied over time to perform at least a deposition step, a clearing step, and an etching step, and the deposition step, the clearing step, and the etching step are cycled through one another until the feature reaches its final depth. With a controller configured as An apparatus comprising:

12. 12. The apparatus of claim 11, and during the deposition step, the controller is configured to generate the plasma from a first plasma-generating gas comprising a first oxygen source and a boron source, whereby exposing the substrate to the plasma during the deposition step forms boron oxide on sidewalls of the feature.

13. 13. The apparatus of claim 12, During the clearing step, the controller is configured to generate the plasma from a second plasma-generating gas comprising a second oxygen source and a halogen source, whereby exposing the substrate to the plasma during the clearing step removes boron oxide proximate an etch front in the feature.

14. 14. The apparatus of claim 13, during the etching step, the controller is configured to generate the plasma from a third plasma generating gas comprising a third source of oxygen, whereby exposing the substrate to the plasma during the etching step etches the feature isotropically at the etch front within the feature.

15. 12. The apparatus of claim 11, the controller is configured to cycle the deposition step, the clearing step, and the etching step repeatedly through one another, and the controller is configured to balance the deposition step, the clearing step, and the etching step differently with respect to one another in different iterations.

16. 16. The apparatus of claim 15, the controller is configured to balance the depositing step, the clearing step, and the etching step in different manners relative to one another in different iterations, thereby forming an etching profile in the feature including at least a first portion and a second portion, the first portion and the second portion having different profile shapes selected from vertical, re-entrant, or tapered.

17. 16. The apparatus of claim 15, the controller is configured to balance the deposition step, the clearing step, and the etching step relative to one another in a first balance during a first iteration, and to balance the deposition step, the clearing step, and the etching step relative to one another in a second balance during the second iteration, the second iteration occurring after the first iteration, and the second balance prioritizing the deposition step over the etching step relative to the first balance, such that an etching profile formed at an etch front within the feature during the second iteration has a tapered shape.

18. 16. The apparatus of claim 15, the controller is configured to balance the deposition step, the clearing step, and the etching step relative to one another in a first balance during a first iteration, and to balance the deposition step, the clearing step, and the etching step relative to one another in a second balance during the second iteration, the second iteration occurring after the first iteration, and the second balance prioritizing the etching step over the deposition step relative to the first balance, such that an etching profile formed at an etch front within the feature during the second iteration has a re-entrant shape.

19. 12. The apparatus of claim 11, The apparatus, wherein the controller is configured to generate the plasma continuously such that the plasma is not extinguished between the deposition step, the clearing step, and the etching step.

20. 12. The apparatus of claim 11, The apparatus, wherein the controller is configured to cause the clearing step to occur immediately after either the depositing step or the etching step.

Images