Semiconductor Package

Abstract

The semiconductor package of the embodiment includes a photosensitive insulating layer, a first circuit pattern layer embedded in the photosensitive insulating layer, and a lower oxide layer disposed at the interface between the photosensitive insulating layer and the first circuit pattern layer.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board including a cavity and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a board with limited size are being proposed and researched.

[0003] A typical semiconductor package has a structure in which multiple chips are arranged. Recently, the size of semiconductor packages has increased due to the high specifications of products to which the semiconductor packages are applied and the adoption of multiple chips such as HBM (High Bandwidth Memory). Therefore, the semiconductor package includes an interposer for connecting multiple chips.

[0004] In addition, semiconductor packages used in products that provide the Internet of Things (IOT), autonomous vehicles, and high-performance servers are required to have high performance and reliability in response to the trend toward higher integration. Here, high performance includes the ability to transmit signals at high speeds, integration of the semiconductor package, and a high allowable current for transmittable signals.

[0005] At this time, the semiconductor package uses a substrate having a cavity for miniaturization and integration, which reduces the thickness of the substrate and thereby reduces the thickness of the semiconductor package.

[0006] (Patent Document 1) KR10-2021-0024840A Summary of the Invention [Problem to be solved by the invention]

[0007] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0008] Also, embodiments provide a circuit board including the cavity and a semiconductor package including the same.

[0009] Furthermore, the embodiments provide a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0010] Furthermore, the embodiments provide a circuit board having improved adhesion between insulating layers containing different insulating materials, and a semiconductor package including the same.

[0011] Furthermore, the embodiments provide a circuit board with improved adhesion between a plurality of adjacent layers, and a semiconductor package including the same.

[0012] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same that can solve the reliability problem caused by the exposed glass fibers of the prepreg.

[0013] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0014] The semiconductor package of the embodiment includes a photosensitive insulating layer, a first circuit pattern layer embedded in the photosensitive insulating layer, and a lower oxide layer disposed at the interface between the photosensitive insulating layer and the first circuit pattern layer.

[0015] The lower oxide layer is further provided on the lower surface of the photosensitive insulating layer, the lower oxide layer not overlapping the first circuit pattern layer in the vertical direction.

[0016] The semiconductor package further includes an additional insulating layer disposed on a lower surface of the photosensitive insulating layer, and a lower oxide layer provided on the lower surface of the photosensitive insulating layer contacts an upper surface of the additional insulating layer.

[0017] The additional insulating layer includes an insulating material different from the insulating material of the photosensitive insulating layer.

[0018] The additional insulating layer also includes reinforcing fibers.

[0019] The additional insulating layer is a thermosetting insulating layer.

[0020] The semiconductor package also includes a through electrode penetrating the photosensitive insulating layer and a second circuit pattern layer disposed on the photosensitive insulating layer, and the lower oxide layer includes an open area vertically overlapping the lower surface of the through electrode.

[0021] The semiconductor package further includes an upper oxide layer disposed on the photosensitive insulating layer.

[0022] At least one of the upper oxide layer and the lower oxide layer includes aluminum oxide.

[0023] The semiconductor package further includes a protective layer disposed on the upper oxide layer, and the upper oxide layer includes a first portion provided at an interface between the photosensitive insulating layer and the protective layer, and a second portion provided at an interface between the second circuit pattern layer and the protective layer.

[0024] Additionally, the protective layer includes an opening that vertically overlaps the second circuit pattern layer, and the second portion of the upper oxide layer includes an open area that vertically overlaps the opening in the protective layer.

[0025] The semiconductor package further includes a protective layer disposed on the upper oxide layer, the oxide layer including a first portion disposed at the interface between the photosensitive insulating layer and the protective layer, and a second portion disposed between the photosensitive insulating layer and the second circuit pattern layer.

[0026] The upper oxide layer further includes a third portion disposed between the through electrode and an inner wall of a through hole that penetrates the photosensitive insulating layer.

[0027] The photosensitive insulating layer further includes at least one cavity penetrating the upper and lower surfaces of the photosensitive insulating layer, and the upper oxide layer further includes a fourth portion disposed on an inner wall of the cavity of the photosensitive insulating layer.

[0028] The upper oxide layer or the lower oxide layer further includes a fifth portion disposed on the upper surface of the additional insulating layer corresponding to the bottom surface of the cavity.

[0029] Additionally, the first circuit pattern layer includes a pad that vertically overlaps the cavity, and the fifth portion of the upper oxide layer or the lower oxide layer includes an open area that vertically overlaps an upper surface of the pad.

[0030] The first circuit pattern layer also includes a circuit pattern that does not vertically overlap the cavity and is covered with the photosensitive insulating layer, a trace that directly connects the circuit pattern and the pad, the trace including a first part that directly contacts the pad and vertically overlaps the cavity, and a second part that is covered with the photosensitive insulating layer and directly contacts the circuit pattern, and the upper oxide layer or the lower oxide layer silver further includes a sixth part that is disposed on the top surface and side surface of the second part of the trace.

[0031] The semiconductor package further includes a connection member disposed on the pad.

[0032] The semiconductor package further includes a semiconductor element disposed on the connecting member.

[0033] The semiconductor package further includes a molding layer disposed in the cavity to mold the semiconductor device.

[0034] The upper oxide layer is disposed on the inner wall of the cavity and includes a portion in contact with the molding layer. [Effects of the Invention]

[0035] The circuit board of the embodiment can improve the adhesion between a plurality of layers.

[0036] Specifically, the circuit board of the embodiment includes a first insulating layer including a first insulating material, and a second insulating layer disposed on the first insulating layer and including a second insulating material different from the first insulating material.

[0037] In this case, the embodiment includes a buffer layer disposed between the first insulating layer and the second insulating layer. The buffer layer may function as an adhesive layer that improves adhesion between the first insulating layer and the second insulating layer. The buffer layer may be an oxide layer. For example, the buffer layer may include aluminum oxide.

[0038] Through this, the embodiment can improve the adhesion between the first insulating layer and the second insulating layer, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0039] Furthermore, the first insulating layer can include a thermosetting resin, and the second insulating layer can include a photocurable resin. In an embodiment, the second insulating layer includes a photocurable resin, which can improve the physical and electrical reliability of the circuit pattern layer and the through electrodes disposed on the second insulating layer. Furthermore, the second insulating layer includes a photocurable resin, which can reduce the size of the circuit pattern layer and the through electrodes disposed on the second insulating layer.

[0040] In this case, the photocurable resin contains a relatively high amount of ceramic particles and has a relatively high cure shrinkage rate, which may result in a decrease in adhesion between the photocurable resin and other layers.

[0041] In contrast, in the embodiment, the buffer layer is disposed on the surface of the photocurable resin, so that even if the second insulating layer contains the photocurable resin, the circuit pattern layer and the through electrodes can be miniaturized without affecting the adhesion.

[0042] Therefore, the embodiment can improve the circuit integration density of the circuit board, and can further improve the physical and / or electrical reliability of the circuit board.

[0043] On the other hand, the buffer layer in the embodiment is also disposed between the second insulating layer and the circuit pattern layer, thereby improving the adhesion between the second insulating layer and the circuit pattern layer.

[0044] In addition, the buffer layer in the embodiment is also disposed between the second insulating layer and the through electrode, thereby improving the adhesion between the second insulating layer and the through electrode.

[0045] In addition, the buffer layer in the embodiment is also disposed between the second insulating layer and the first protective layer, thereby improving the adhesion between the second insulating layer and the first protective layer.

[0046] In addition, the buffer layer in the embodiment is also disposed between the circuit pattern layer and the first protective layer, thereby improving the adhesion between the circuit pattern layer and the first protective layer.

[0047] In the embodiment, by forming a buffer layer having the structure described above, the adhesion between the multiple layers constituting the circuit board can be improved, thereby improving the reliability of the product.

[0048] Meanwhile, the second insulating layer includes a cavity. In this case, the buffer layer may also be disposed on the inner wall of the cavity of the second insulating layer. This allows the embodiment to omit a desmear process for removing debris remaining on the inner wall of the cavity. This simplifies the manufacturing process of the circuit board. Furthermore, by omitting the desmear process, the embodiment can prevent the size of the cavity from expanding due to the desmear process, thereby forming a cavity with an optimal size. Therefore, the embodiment can reduce the volume of the circuit board.

[0049] The buffer layer may also be disposed on the bottom surface of the cavity. When a desmear process is performed after the cavity is formed, the buffer layer disposed on the bottom surface of the cavity can function as a barrier layer. In the embodiment, the barrier layer can prevent the reinforcing fibers contained in the first insulating layer from being exposed during the desmear process. This can further improve the reliability of the product. [Brief explanation of the drawings]

[0050] [Figure 1a] FIG. 1 is a diagram illustrating a semiconductor package according to a first embodiment. [Figure 1b] FIG. 10 is a diagram illustrating a semiconductor package according to a second embodiment. [Figure 1c] FIG. 10 is a diagram showing a semiconductor package according to a third embodiment. [Figure 1d] FIG. 10 is a diagram showing a semiconductor package according to a fourth embodiment. [Figure 1e] FIG. 10 is a diagram showing a semiconductor package according to a fifth embodiment. [Figure 1f] FIG. 10 is a diagram showing a semiconductor package according to a sixth embodiment. [Figure 2] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3]FIG. 2 is a cross-sectional view illustrating the arrangement structure of a first buffer layer according to an embodiment. [Figure 4] FIG. 3 is a cross-sectional view illustrating the arrangement structure of the second buffer layer according to the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view illustrating the arrangement structure of a second buffer layer according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing a circuit board according to a second embodiment. [Figure 7a] FIG. 10 is a cross-sectional view showing a circuit board according to a third embodiment. [Figure 7b] FIG. 7b is a plan view of the circuit board of FIG. 7a. [Figure 8] FIG. 13 is a diagram illustrating a semiconductor package according to a seventh embodiment. [Figure 9] FIG. 13 is a diagram illustrating a semiconductor package according to an eighth embodiment. [Figure 10] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 11] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 12] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 13] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 14] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 15] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 16] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. [Figure 17] 1A to 1C are cross-sectional views for explaining a method for manufacturing a circuit board according to an embodiment in the order of steps. MODE FOR CARRYING OUT THE INVENTION

[0051] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0052] However, the technical concept of the present invention is not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0053] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings that can be commonly understood by a person of ordinary skill in the art to which the present invention belongs, and commonly used terms such as dictionary-defined terms may be interpreted in light of the contextual meaning of the relevant art. Furthermore, the terms used in the embodiments of the present invention are intended to explain the embodiments and are not intended to limit the present invention.

[0054] In this specification, unless otherwise specified, the singular can also include the plural, and when it is stated as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. Furthermore, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used.

[0055] Such terms are used merely to distinguish a component from other components, and do not limit the nature, order, or sequence of the components. Furthermore, when a component is described as being "connected," "coupled," or "connected" to another component, it includes not only the case where the component is directly connected, coupled, or connected to the other component, but also the case where the component is "connected," "coupled," or "connected" by another component between the other component and the component.

[0056] Furthermore, when it is stated that something is formed or placed "above or below" a component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or placed between the two components. Furthermore, when it is expressed as "above" or "below," it can mean not only the upper direction but also the lower direction based on one component.

[0057] -Electronic Devices-

[0058] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various chips may be mounted in the semiconductor package.

[0059] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0060] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0061] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0062] The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0063] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various package structures including the circuit board described below.

[0064] FIG. 1a is a diagram showing a semiconductor package according to a first embodiment.

[0065] Referring to FIG. 1 a, the semiconductor package of the first embodiment includes a first substrate 100 .

[0066] The first substrate 100 may refer to a package substrate. For example, the first substrate 100 may provide a space to which at least one external substrate is coupled. For example, the first substrate 100 may provide a space to which a main board included in an electronic device is coupled.

[0067] As described below, the first substrate 100 may include at least one insulating layer, a circuit pattern layer disposed on the at least one insulating layer, a through electrode penetrating the at least one insulating layer, and a protective layer that protects the insulating layer and the circuit pattern layer.

[0068] The first substrate 100 may include a plurality of pads. Here, the plurality of pads may refer to parts of a circuit pattern layer disposed on the outermost layer of the first substrate 100. For example, the pads may refer to parts of a circuit pattern layer disposed on the uppermost side of the first substrate 100. For example, the pads may refer to parts of a circuit pattern layer disposed on the lowermost side of the first substrate 100. The protective layer may include openings exposing surfaces (e.g., upper or lower surfaces) of the pads.

[0069] Meanwhile, the semiconductor package may include a plurality of connecting members.

[0070] For example, the first substrate 100 may include a plurality of pads, and the plurality of connection members may be disposed on the plurality of pads, respectively.

[0071] Specifically, the first substrate 100 may include a plurality of first pads, and the semiconductor package may include a first connection member 110 disposed on the plurality of first pads.

[0072] The first substrate 100 may also include a plurality of second pads, and the semiconductor package may also include a second connection member 140 disposed on the plurality of second pads.

[0073] The first substrate 100 may also include a plurality of third pads, and the semiconductor package may also include a third connection member 160 disposed on the plurality of third pads.

[0074] In this case, the first pad may be disposed on the upper surface of the first substrate 100, and the second and third pads may be disposed on the lower surface of the first substrate 100.

[0075] Meanwhile, a semiconductor package can include multiple semiconductor devices.

[0076] For example, the semiconductor package may include a first semiconductor device 120 disposed on the first connection member 110. In this case, the first pads of the first substrate 100 may be divided into a plurality of groups. The first connection member 110 may be disposed on each of the first pads of the plurality of groups. The first semiconductor devices 120 may be mounted on each of the first pads of the plurality of groups. Therefore, a plurality of the first semiconductor devices 120 may be mounted on the upper side of the first substrate 100 at regular intervals. In this case, the first semiconductor device 120 may refer to a semiconductor device mounted on the upper side of the first substrate 100. A plurality of first semiconductor devices may be disposed on the upper side of the first substrate 100, spaced apart from each other.

[0077] The semiconductor package may also include a second semiconductor device 140 disposed below the second connecting member 140. The second semiconductor device 140 may refer to a semiconductor device mounted below the first substrate 100 among the semiconductor devices included in the semiconductor package. A plurality of second semiconductor devices may be disposed below the first substrate 100, spaced apart from one another.

[0078] In this case, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a logic chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an application processor chip. For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include an analog-to-digital converter or an application-specific IC (ASIC). For example, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc.

[0079] In addition, at least one of the first semiconductor device 120 and the second semiconductor device 140 may include at least one of a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, an MLCC (Multilayer Ceramic Condenser) chip, a BGA (Ball Grid Array) chip, and a chip capacitor.

[0080] The semiconductor package may also include a third connecting member 160. The third connecting member 160 may be disposed under a third pad of the first substrate 100. The third connecting member 160 may connect the first substrate 100 to a main board of an electronic device. The third connecting member 160 may have a larger diameter than the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 10 to 200 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 20 to 180 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. For example, the diameter of the third connecting member 160 may be in the range of 40 to 150 times the diameter of at least one of the first connecting member 110 and the second connecting member 140. That is, the third connecting member 160 may be connected to a main board of an electronic device and have a diameter larger than the other connecting members so as to correspond to the width of a pad portion of the main board, and the first connecting member 110 and the second connecting member 140 may be connected to a semiconductor device and have a diameter smaller than the third connecting member 160 so as to correspond to the terminals of the semiconductor device.

[0081] The semiconductor package may include a molding layer.

[0082] For example, the semiconductor package may include a first molding layer 130 disposed on the first substrate 100. The first molding layer 130 may mold components disposed on the outermost layer of the first substrate 100. For example, the first molding layer 130 may mold a surface of a protective layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed on the uppermost side of the first substrate 100. The first molding layer 130 may also mold the first connecting member 110 and the first semiconductor element 120 disposed on the first substrate 100. In this case, the semiconductor package may further include an underfill (not shown) surrounding the periphery of the first connecting member 110 and the first semiconductor element 120. If the semiconductor package includes the underfill, the first molding layer 130 may mold the periphery of the underfill.

[0083] The semiconductor package may also include a second molding layer 170 disposed below the first substrate 100. The second molding layer 170 may mold a surface of a protective layer, a surface of a circuit pattern layer, and a surface of an insulating layer disposed on the bottom side of the first substrate 100. The second molding layer 170 may also mold a second connecting member 140 and a second semiconductor element 140 disposed below the first substrate 100. The second molding layer 170 may also mold the third connecting member 160.

[0084] In this case, the second molding layer 170 may expose at least a portion of the lower surface of the second semiconductor chip 140. For example, the lower surface of the second molding layer 170 may be positioned not lower than the lower surface of the second semiconductor chip 140. For example, the lower surface of the second molding layer 170 may be positioned on the same plane as the lower surface of the second semiconductor chip 140.

[0085] Furthermore, the second molding layer 170 may be positioned not lower than the lower surface of the third connecting member 160. For example, the lower surface of the second molding layer 170 may be flush with the lower surface of the third connecting member 160 or may be positioned higher than the lower surface of the third connecting member 160. Therefore, the lower surface of the third connecting member 160 may not be covered by the second molding layer 170. Furthermore, at least a portion of the third connecting member 160 may protrude downward from the second molding layer 170.

[0086] The first molding layer 130 and the second molding layer 170 may be, but are not limited to, EMC (Epoxy Mold Compound). The first molding layer 130 and the second molding layer 170 may have a low dielectric constant. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first molding layer 130 and the second molding layer 170 may be 0.8 to 5. Thus, in this embodiment, the first molding layer 130 and the second molding layer 170 have a low dielectric constant, thereby improving the heat dissipation characteristics of the heat generated in the first semiconductor element 120 and the second semiconductor element 140.

[0087] The semiconductor package of the first embodiment may have a double-sided molding structure as described above, that is, the semiconductor package of the first embodiment may have a structure in which at least one first semiconductor device 120 and at least one second semiconductor device 140 are mounted on the upper and lower sides of the first substrate 100, respectively.

[0088] FIG. 1b is a diagram showing a semiconductor package according to a second embodiment.

[0089] Referring to FIG. 1b, the semiconductor package according to the second embodiment may differ from the semiconductor package according to the first embodiment of FIG. 1a in that it has a one-side molding structure.

[0090] For example, the semiconductor package of the second embodiment may include a first substrate 100 , a first connecting member 110 , a first semiconductor element 120 , a first molding layer 130 , and a third connecting member 160 .

[0091] The semiconductor package of the second embodiment may have a structure in which a semiconductor element is mounted only on the upper side of the first substrate 100. Thus, the molding layer of the semiconductor package of the second embodiment may be disposed only on the upper side of the first substrate 100.

[0092] FIG. 1c is a diagram showing a semiconductor package according to a third embodiment.

[0093] Referring to FIG. 1c, the semiconductor package according to the third embodiment is different from the semiconductor package according to the second embodiment of FIG. 1b in that it further includes an additional package.

[0094] The semiconductor package of the third embodiment may further include a fourth pad disposed on the upper side of the first substrate 100. That is, a circuit pattern layer is disposed on the upper surface of the first substrate 100. A portion of the circuit pattern layer may function as a first pad on which the first semiconductor element 120 is mounted, and another portion may function as a fourth pad.

[0095] The semiconductor package of the third embodiment may further include a fourth connection member 180 disposed on the fourth pad.

[0096] The top surface of the fourth connection member 180 may not be covered by the first molding layer 130 .

[0097] The semiconductor package of the third embodiment may include a second substrate 200 disposed on the fourth connection member 180. The second substrate 200 may be, but is not limited to, a memory substrate.

[0098] The semiconductor package of the third embodiment may include a third semiconductor device 210 mounted on the second substrate 200. The third substrate 210 may be, but is not limited to, a memory substrate.

[0099] In addition, the semiconductor package of the third embodiment may further include a connecting member 220 connecting the second substrate 200 and the third semiconductor device 210. That is, the semiconductor package of the third embodiment of FIG. 1c may have a package-on-package structure.

[0100] FIG. 1d is a diagram showing a semiconductor package according to a fourth embodiment.

[0101] Referring to FIG. 1d, the semiconductor package of the fourth embodiment differs from the semiconductor package of the third embodiment of FIG. 1c in that the first semiconductor element 120 includes multiple logic chips and an additional third substrate 190 is disposed on the first substrate 100.

[0102] For example, a plurality of logic chips may be arranged on the first substrate 100. For example, a plurality of logic chips of the same type may be arranged on the first substrate 100, or alternatively, a plurality of logic chips of different types may be arranged on the first substrate 100.

[0103] In this case, a connecting member may be disposed on the first substrate 100 to connect the first semiconductor chips 120. The connecting member may refer to the third substrate 190.

[0104] The third substrate 190 may be a bridge substrate. The third substrate 190 may include a redistribution layer. The third substrate 190 is disposed on the first substrate 100. The third substrate 190 may electrically connect a plurality of first semiconductor devices 120 corresponding to a plurality of logic chips. Although the third substrate 190 is embedded in the first substrate 100 in the drawings, the present invention is not limited thereto. For example, the third substrate 190 may be disposed on the first substrate 100.

[0105] The third substrate 190 may be a silicon bridge substrate, or alternatively, the third substrate 190 may be an organic bridge substrate including an organic material.

[0106] FIG. 1e is a diagram showing a semiconductor package according to a fifth embodiment.

[0107] Referring to FIG. 1e, the semiconductor package according to the fifth embodiment differs from the semiconductor packages of the previous embodiments in that a fourth substrate 300 is disposed between the first substrate and the first semiconductor element.

[0108] The semiconductor package according to the fifth embodiment may include a fourth substrate 300 disposed on the first substrate 100 .

[0109] To this end, a first connection member 110 for connecting the first substrate 100 and the fourth substrate 300 may be disposed on the first substrate 100 .

[0110] The semiconductor package according to the fifth embodiment may also include a fifth connecting member 320 disposed on the fourth substrate 300. The semiconductor package according to the fifth embodiment may also include a semiconductor element 320 disposed on the fifth connecting member 320. The semiconductor element 320 may be one or, alternatively, may be configured to include a plurality of semiconductor elements 320.

[0111] Meanwhile, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may function to connect the first substrate 100 and the semiconductor device 320. In addition, the fourth substrate 300 may function to connect a plurality of semiconductor devices 320 to each other.

[0112] In this case, the fourth substrate 300 can be regarded as an interposer connecting the first substrate 100 and the semiconductor device 320 .

[0113] In one embodiment, the fourth substrate 300 may be an active interposer that functions as a semiconductor device. When the fourth substrate 300 functions as a semiconductor device, the package of the fifth embodiment may have a vertically stacked structure on the first substrate 100 and have multiple logic chips mounted thereon. A first logic chip among the logic chips that corresponds to the active interposer may perform a signal transmission function between the first substrate 100 and a second logic chip disposed thereon while performing the function of the logic chip.

[0114] According to another embodiment, the fourth substrate 300 may be a passive interposer. For example, the fourth substrate 300 may perform a signal relay function between the semiconductor device 320 and the first substrate 100. For example, the number of terminals on the semiconductor device 320 is gradually increasing due to factors such as 5G, Internet of Things (IoT), improved image quality, and increased communication speed. That is, as the number of terminals on the semiconductor device 320 increases, the width of the terminals and the spacing between the terminals are reduced. In this case, the first substrate 100 is connected to a main board of an electronic device. Therefore, in order for the pads on the first substrate 100 to have the width and spacing required for connection to the semiconductor device 320 and the main board, respectively, the thickness of the first substrate 100 increases or the layer structure of the first substrate 100 becomes complex. Therefore, the fourth substrate 300 may be disposed between the first substrate 100 and the semiconductor device 320. The fourth substrate 300 may include pads having fine widths and intervals corresponding to the terminals of the semiconductor devices 320 .

[0115] FIG. 1f is a diagram showing a semiconductor package according to a sixth embodiment.

[0116] Referring to FIG. 1F, the semiconductor package according to the sixth embodiment is different from the semiconductor package according to the fifth embodiment in that a fifth substrate 330 is further disposed on the fourth substrate 300.

[0117] The semiconductor devices 320 may be arranged on the fourth substrate 300 and spaced apart from one another in the horizontal direction. The semiconductor devices 320 may be active devices of the same type or different types. Exemplarily, the semiconductor devices 320 may represent AP chips of different types. Furthermore, one of the semiconductor devices 320 may be an AP chip and the other may be a memory chip.

[0118] The semiconductor package of the sixth embodiment further includes a fifth substrate 330. The fifth substrate 330 may be embedded in the fourth substrate 300, but is not limited to this. For example, the fifth substrate 330 may be disposed on the fourth substrate 300 and function to connect the semiconductor devices 320 together.

[0119] The fifth substrate 330 may include a redistribution layer. For example, the fifth substrate 330 may be a bridge. The fifth substrate 330 may include a silicon bridge. Alternatively, the fifth substrate 330 may be an organic bridge including an organic material.

[0120] On the other hand, each of the semiconductor packages of the first to sixth embodiments includes a connecting member as described above.

[0121] In this case, the connection member may be a member that electrically connects a plurality of components using at least one bonding method selected from the group consisting of wire bonding, solder bonding, and direct intermetal bonding.

[0122] In other words, since the connecting member has the function of electrically connecting multiple components, when using metal-to-metal direct bonding, the semiconductor package can be understood as the electrically connected part, rather than the solder or wire.

[0123] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material containing at least one of Sn, Ag, and Cu. The inter-metal direct bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using materials such as solder, wire, or conductive adhesive. The inter-metal direct bonding method may refer to a connecting member connecting a substrate and a semiconductor device. In this case, the connecting member in the direct bonding method may refer to a metal layer formed between the multiple components by the recrystallization.

[0124] Furthermore, at least one of the substrates included in the semiconductor package shown in FIGS. 1a to 1f may be provided with a cavity.

[0125] The cavities can be used for different purposes depending on the function of the substrate.

[0126] As an example, the cavity may be used in applications for placing semiconductor elements.

[0127] For example, if the first substrate 100 has a cavity, the cavity can be used to embed at least one of the semiconductor elements 120 and 140 .

[0128] Alternatively, if the second substrate 200 has a cavity, the cavity may be used to place a semiconductor device 210. Also, if the second substrate 200 has a cavity, the cavity may be used to accommodate at least a portion of the semiconductor device 120 placed on the first substrate 100. Here, "placement of the semiconductor device 210" may mean that the semiconductor device 210 is electrically connected to the substrate in the cavity. "accommodation of the semiconductor device 120" may mean that the semiconductor device 120 is not electrically connected to the substrate in the cavity, but that at least a portion of the semiconductor device 120 is positioned in a floating state within the cavity.

[0129] The cavity can also be used to place a bridge substrate.

[0130] For example, if the first substrate 100 has a cavity, the cavity can be used to place a third substrate 190 that connects a plurality of semiconductor elements.

[0131] For example, if the fourth substrate 300 has a cavity, the cavity can be used to place the fifth substrate 330 that connects multiple semiconductor elements.

[0132] The circuit board of the embodiment will be described below.

[0133] Before describing the circuit board of the embodiment, the circuit board described below may refer to any one of the substrates included in the semiconductor package.

[0134] Preferably, the circuit board of an embodiment described below may be any one of the first substrate 100, second substrate 200, third substrate 190, fourth substrate 300, and fifth substrate 330 included in the semiconductor package. Here, the circuit board of an embodiment may refer to an embodiment that does not include a cavity.

[0135] As another example, a circuit board in another embodiment described below may be any one of the first substrate 100, the second substrate 200, and the fourth substrate 300 included in the semiconductor package. Here, the circuit board in another embodiment may refer to an embodiment including a cavity. A semiconductor device may be mounted or housed in the cavity, and alternatively, a bridge substrate may be coupled to the cavity.

[0136] FIG. 2 is a cross-sectional view showing the circuit board according to the first embodiment.

[0137] Referring to FIG. 2, a circuit board 400 includes an insulating layer 410 .

[0138] The insulating layer 410 may include multiple layers, and preferably has a multi-layer structure.

[0139] The insulating layer 410 may include a first insulating layer 411 , a second insulating layer 412 , and a third insulating layer 413 .

[0140] The first insulating layer 411 may refer to, but is not limited to, an insulating layer disposed in the center of the vertical layer structure of the circuit board 400 .

[0141] The first insulating layer 411 includes a first insulating material, for example, a prepreg in which reinforcing fibers are impregnated in a resin.

[0142] For example, the prepreg of the first insulating layer 411 may include an epoxy resin impregnated into a fiber layer in the form of a fabric sheet such as a glass fabric woven with glass fiber yarn.

[0143] In this case, although the first insulating layer 411 including the first insulating material is illustrated as having a single layer structure in the drawings, the first insulating layer 411 is not limited thereto. For example, the first insulating layer 411 may have a multi-layer structure including two or more layers.

[0144] The second insulating layer 412 is disposed on the first insulating layer 411. And, the third insulating layer 413 is disposed below the first insulating layer 411.

[0145] The second insulating layer 412 includes a second insulating material that is different from the first insulating material of the first insulating layer 411. Preferably, the second insulating layer 412 does not include the reinforcing fibers included in the first insulating layer 411.

[0146] For example, the second insulating layer 412 may include at least one of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric resin (PID), BT, and Resin coated copper (RCC).

[0147] The third insulating layer 413 is disposed under the first insulating layer 411. The third insulating layer 413 may include the same second insulating material as the second insulating layer 412. For example, the third insulating layer 413 may not include reinforcing fibers. For example, the third insulating layer 413 may include at least one of Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imageable Dielectric resin (PID), BT, and Resin coated copper (RCC).

[0148] Meanwhile, although the second insulating layer 412 and the third insulating layer 413 are shown as each having a single-layer structure in the drawings, they are not limited thereto. For example, at least one of the second insulating layer 412 and the third insulating layer 413 may have a multi-layer structure of two or more layers.

[0149] The second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 10 μm to 60 μm. The second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 15 μm to 55 μm. More preferably, the second insulating layer 412 and the third insulating layer 413 may have a thickness in the range of 18 μm to 52 μm.

[0150] The thickness of each of the second insulating layer 412 and the third insulating layer 413 may refer to the vertical distance between a plurality of circuit pattern layers arranged adjacent to each other in the vertical direction.

[0151] If the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the warpage characteristics of the circuit board 400 may be reduced. For example, if the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the circuit pattern layers disposed on the surfaces of the second insulating layer 412 and the third insulating layer 413 may not be stably protected, which may result in problems with electrical reliability and / or physical reliability. Furthermore, if the thickness of the second insulating layer 412 and the third insulating layer 413 is less than 10 μm, the processability of forming the circuit pattern layers on the second insulating layer 412 and the third insulating layer 413 may be reduced.

[0152] Furthermore, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, the overall thickness of the circuit board 400 increases, which may result in an increase in the thickness of the semiconductor package. Furthermore, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, it may be difficult to miniaturize the circuit pattern layer. For example, if the thickness of the second insulating layer 412 and the third insulating layer 413 exceeds 60 μm, it may be difficult to form the width of the circuit pattern layer and the spacing between adjacent patterns to 12 μm or less, 10 μm or less, 8 μm or less, or 6 μm or less. Furthermore, if it is difficult to miniaturize the circuit pattern layer, the circuit integration density decreases, which increases the signal transmission distance and signal transmission loss.

[0153] The circuit board 400 includes a circuit pattern layer disposed on an insulating layer 410 .

[0154] For example, the circuit board 400 may include a first circuit pattern layer 421 disposed on a first insulating layer 411. The circuit board 400 may also include a second circuit pattern layer 422 disposed on the upper surface of a second insulating layer 412. The circuit board 400 may also include a third circuit pattern layer 423 disposed on the lower surface of the first insulating layer 411. The circuit board 400 may also include a fourth circuit pattern layer 424 disposed on the lower surface of the third insulating layer 413.

[0155] Each of the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may include multiple metal layers.

[0156] For example, the first circuit pattern layer 421 may include a plurality of metal layers. For example, the first circuit pattern layer 421 may include a first metal layer disposed on the upper surface of the first insulating layer 411 and a second metal layer disposed on the first metal layer. The first metal layer of the first circuit pattern layer 421 may serve as a seed layer for electrolytic plating of the second metal layer of the first circuit pattern layer 421. The thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.2 μm to 3.0 μm. Preferably, the thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.3 μm to 2.8 μm. More preferably, the thickness of the first metal layer of the first circuit pattern layer 421 may be in the range of 0.5 μm to 2.5 μm.

[0157] If the thickness of the first metal layer of the first circuit pattern layer 421 is less than 0.2 μm, the first metal layer of the first circuit pattern layer 421 may not function as a seed layer. If the thickness of the first metal layer of the first circuit pattern layer 421 is less than 0.2 μm, it may be difficult to form a uniform first metal layer on the upper surface of the first insulating layer 411. If the thickness of the first metal layer of the first circuit pattern layer 421 is more than 3.0 μm, the process time for forming the first metal layer of the first circuit pattern layer 421 may increase, thereby reducing yield. If the thickness of the first metal layer of the first circuit pattern layer 421 is more than 3.0 μm, the etching time for the first metal layer in the process of forming the first circuit pattern layer 421 may increase. If the thickness of the first metal layer of the first circuit pattern layer 421 is more than 3.0 μm, deformation of the second metal layer of the first circuit pattern layer 421 may occur during etching of the first metal layer of the first circuit pattern layer 421. Here, the deformation of the second metal layer of the first circuit pattern layer 421 may mean that the difference between the width of the upper surface and the width of the lower surface of the second metal layer increases because the side portions of the second metal layer are also etched when the first metal layer is etched. For example, the deformation of the second metal layer of the first circuit pattern layer 421 may mean that the shape of the vertical cross section of the second metal layer changes from a rectangular shape to a trapezoidal shape.

[0158] Furthermore, if the thickness of the first metal layer of the first circuit pattern layer 421 exceeds 3.0 μm, the etching depth in the etching process of the first metal layer increases, thereby increasing the depth of recesses (e.g., undercuts) formed on the sides of the first metal layer and the second metal layer. For example, if the etching depth in the etching process of the first metal layer increases, the difference between the width of the first metal layer and the width of the second metal layer may increase. If the difference between the width of the first metal layer and the width of the second metal layer increases, electrical characteristics may be degraded due to increased signal transmission loss. Furthermore, if the difference between the width of the first metal layer and the width of the second metal layer increases, dendrites may be formed due to electromigration, which may degrade the electrical and / or physical characteristics of the first circuit pattern layer 420.

[0159] The second metal layer of the first circuit pattern layer 421 may be an electroplated layer formed by electroplating using the first metal layer as a seed layer. The second metal layer of the first circuit pattern layer 421 may be formed to a certain thickness on the first metal layer. The second metal layer of the first circuit pattern layer 421 may include, but is not limited to, the same metal as the first metal layer of the first circuit pattern layer 421. For example, the first and second metal layers of the first circuit pattern layer 421 may each include copper.

[0160] The thickness of the second metal layer of the first circuit pattern layer 421 may be greater than the thickness of the first metal layer of the first circuit pattern layer 421 .

[0161] The thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 3.5 μm to 25 μm. Preferably, the thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 4.0 μm to 23 μm. More preferably, the thickness of the second metal layer of the first circuit pattern layer 421 may be in the range of 4.5 μm to 22 μm.

[0162] If the thickness of the second metal layer of the first circuit pattern layer 421 is less than 3.5 μm, the etching of the second metal layer may be performed simultaneously with the etching of the first metal layer. If the thickness of the second metal layer of the first circuit pattern layer 421 is less than 3.5 μm, the allowable current of signals transmitted through the first circuit pattern layer may decrease, resulting in degraded electrical characteristics. If the thickness of the second metal layer of the first circuit pattern layer 421 is more than 25 μm, it may be difficult to miniaturize the first circuit pattern layer 421. For example, if the thickness of the second metal layer of the first circuit pattern layer 421 is more than 25 μm, the width and spacing of the patterns constituting the first circuit pattern layer 421 may not meet the required conditions. This may result in a reduced circuit integration level or an increased volume of the circuit board and semiconductor package.

[0163] In addition, each of the second circuit pattern layer 422 , the third circuit pattern layer 423 , and the fourth circuit pattern layer 424 may include a first metal layer and a second metal layer corresponding to the first circuit pattern layer 421 .

[0164] Meanwhile, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 each include, but are not limited to, the first and second metal layers. For example, each of the first circuit pattern layer 421 and the third circuit pattern layer 423 may further include a third metal layer disposed between the insulating layer and the first metal layer. The third metal layer may refer to, but is not limited to, a copper foil layer.

[0165] The first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may include a conductive material. For example, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may include at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0166] Meanwhile, the first circuit pattern layer 421, the second circuit pattern layer 422, the third circuit pattern layer 423, and the fourth circuit pattern layer 424 can be formed using conventional circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed explanations thereof will be omitted here.

[0167] The circuit board 400 of the embodiment may include a through electrode, which may penetrate the insulating layer 410.

[0168] For example, the through electrodes may include a through electrode 431 that penetrates the first insulating layer 411 , a through electrode 432 that penetrates the second insulating layer 412 , and a through electrode 433 that penetrates the third insulating layer 413 .

[0169] The through electrodes 431 may electrically connect the first circuit pattern layer 421 and the third circuit pattern layer 423 .

[0170] In addition, the through electrodes 432 may electrically connect the first circuit pattern layer 421 and the second circuit pattern layer 422 .

[0171] In addition, the through electrodes 433 may electrically connect the third circuit pattern layer 423 and the fourth circuit pattern layer 424 .

[0172] The through electrodes 431, 432, and 433 may be formed by filling through holes penetrating the insulating layer 410 with a conductive material.

[0173] The through-holes may be formed by any one of mechanical, laser, and chemical processing. When the through-holes are formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the through-holes are formed by laser processing, UV or CO2 laser methods may be used. When the through-holes are formed by chemical processing, chemicals including aminosilanes, ketones, etc. may be used.

[0174] At this time, at least one of the through electrodes may be formed in a process different from that of at least the other through electrodes.

[0175] For example, the first insulating layer 411 includes a different insulating material than the second insulating layer 412 and the third insulating layer 413 .

[0176] That is, the first insulating layer 411 includes a thermosetting resin, and thus, through holes can be formed in the first insulating layer 411 by laser processing.

[0177] In contrast, the second insulating layer 412 and the third insulating layer 413 include a photo-curable resin, so that through-holes can be formed in the second insulating layer 412 and the third insulating layer 413 by a chemical processing method using an exposure and development process.

[0178] Therefore, the through electrodes 432, 433 penetrating the second insulating layer 412 and the third insulating layer 413 may have a width smaller than the through electrode 431 penetrating the first insulating layer 411. Furthermore, the difference between the upper and lower widths of the through electrodes 432, 433 penetrating the second insulating layer 412 and the third insulating layer 413 may be smaller than the difference between the upper and lower widths of the through electrode 431 penetrating the first insulating layer 411.

[0179] Meanwhile, the circuit board 400 of the embodiment may include a protective layer.

[0180] For example, the circuit board 400 may include a first protective layer 450 disposed on the second insulating layer 412. For example, the circuit board 400 may include a second protective layer 460 disposed below the third insulating layer 413.

[0181] The first protective layer 450 and the second protective layer 460 may be resist layers. Preferably, the first protective layer 450 and the second protective layer 460 may be solder resist layers including an organic polymer material. For example, the first protective layer 450 and the second protective layer 460 may include an epoxy acrylate resin. More specifically, the first protective layer 450 and the second protective layer 460 may include a resin, a hardener, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc.

[0182] The total thickness of each of the first protective layer 450 and the second protective layer 460 may be greater than the thickness of each of the second circuit pattern layer 422 and the fourth circuit pattern layer 424. The total thickness may refer to the vertical distance between the lower surface and the upper surface of the first protective layer 450 and the second protective layer 460.

[0183] The total thickness of the first protective layer 450 may be in the range of 6.7 μm to 35.0 μm. Preferably, the total thickness of the first protective layer 450 may be in the range of 7.3 μm to 32 μm. More preferably, the total thickness of the first protective layer 450 may be in the range of 8.0 μm to 30 μm.

[0184] If the total thickness of the first protective layer 450 exceeds 30 μm, the thickness of the circuit board and the thickness of the semiconductor package may increase, and if the total thickness of the first protective layer 450 is less than 6.7 μm, the second circuit pattern layer 422 may not be stably protected, which may result in a decrease in electrical or physical reliability.

[0185] In addition, the second protective layer 460 may have a thickness corresponding to the thickness of the first protective layer 450, but is not limited thereto.

[0186] The first protective layer 450 and the second protective layer 460 may each include an opening.

[0187] For example, the first protective layer 450 may include a first opening that may vertically overlap at least a portion of the second circuit pattern layer 422. Through this, the first opening of the first protective layer 450 may expose at least a portion of the upper surface of the second circuit pattern layer 422.

[0188] The second protective layer 460 may also include a second opening. The second opening may vertically overlap at least a portion of the lower surface of the fourth circuit pattern layer 424. For example, the second opening may expose at least a portion of the lower surface of the fourth circuit pattern layer 424.

[0189] Meanwhile, the circuit board of the embodiment may include a buffer layer. The buffer layer may be an oxide layer. The buffer layer may be disposed at least one of between different insulating layers, between an insulating layer and a circuit pattern layer, between an insulating layer and a through electrode, between an insulating layer and a protective layer, and between a circuit pattern layer and a protective layer.

[0190] Specifically, the first insulating layer 411 and the second insulating layer 412 of the embodiment contain different insulating materials, and the first insulating layer 411 and the third insulating layer 413 of the embodiment contain different insulating materials.

[0191] This may result in a decrease in adhesion between the first insulating layer 411 and the second insulating layer 412 in the step of laminating the second insulating layer 412 on the first insulating layer 411. Furthermore, the adhesion between the first circuit pattern layer 421 disposed on the first insulating layer 411 and the second insulating layer 412 may also decrease.

[0192] Furthermore, in the step of laminating the third insulating layer 413 below the first insulating layer 411, the adhesion between the first insulating layer 411 and the third insulating layer 413 may decrease. Furthermore, the adhesion between the third insulating layer 413 and the third circuit pattern layer 423 disposed below the first insulating layer 411 may decrease.

[0193] More specifically, the first insulating layer 411 may include a thermosetting resin. The second insulating layer 412 and the third insulating layer 413 may include a photosetting resin. For example, the second insulating layer 412 and the third insulating layer 413 may include a PID. That is, the second insulating layer 412 may be referred to as a photosensitive insulating layer, and the first insulating layer 411 may be referred to as an additional insulating layer disposed below the second insulating layer 412. The third insulating layer 413 may be referred to as another photosensitive insulating layer disposed below the first insulating layer 411.

[0194] The photocurable resin has a higher cure shrinkage rate than the thermosetting resin, and also contains a higher amount of ceramic particles such as SiO2 inside than the thermosetting resin.

[0195] When XPS (X-ray Photoelectron Spectroscopy) analysis is performed on photocurable resins, relatively high power peak values can be detected for both acrylic and epoxy. When XPS analysis is performed on thermosetting resins that do not contain reinforcing fibers, a peak value can only be detected for epoxy. This makes it possible to distinguish between photocurable resins that do not contain reinforcing fibers and thermosetting resins.

[0196] On the other hand, if the second insulating layer 412 is made of a photocurable resin, the adhesion between the first insulating layer 411 and the second insulating layer 412 may be reduced. Also, the adhesion between the first circuit pattern layer 421 and the second insulating layer 412 may be reduced.

[0197] In addition, the circuit pattern layers used in recent circuit boards have low surface roughness to minimize signal transmission loss in the high frequency band. For example, the higher the frequency, the more signals flow through the surface of the circuit pattern layer. Furthermore, if the surface roughness of the circuit pattern layer is high, the signal transmission loss also increases.

[0198] The lower the surface roughness of the circuit pattern layer, the weaker the adhesion to the second insulating layer 412 becomes.

[0199] Correspondingly, the adhesion between the first insulating layer 411 and the third insulating layer 413 may decrease, and the adhesion between the third circuit pattern layer 423 and the third insulating layer 413 may decrease.

[0200] Accordingly, in the embodiment, a first buffer layer 441 may be disposed on the first insulating layer 411. The first buffer layer 441 may be disposed between the first insulating layer 411 and the second insulating layer 412. Thus, in the embodiment, the adhesion between the first insulating layer 411 and the second insulating layer 412 may be improved. The first buffer layer 441 may be referred to as a lower oxide layer.

[0201] Furthermore, the first buffer layer 441 may be disposed between the first circuit pattern layer 421 and the second insulating layer 412. Thus, the first buffer layer 441 may improve the adhesion between the first circuit pattern layer 421 and the second insulating layer 412.

[0202] In addition, at least a portion of the first buffer layer 441 may be in contact with the through electrode 432 that penetrates the second insulating layer 412. Thus, the first buffer layer 441 may improve the adhesion of the through electrode 432.

[0203] Meanwhile, the first buffer layer 441 may include at least one open region. Preferably, the first buffer layer 441 may open a region of the upper surface of the first circuit pattern layer 421 that vertically overlaps the through electrode 432. That is, if the first buffer layer 441 is disposed between the first circuit pattern layer 421 and the through electrode 432, electrical characteristics between the first circuit pattern layer 421 and the through electrode 432 may be degraded. Therefore, the first buffer layer 441 includes an open region that opens a region of the upper surface of the first circuit pattern layer 421 that vertically overlaps the through electrode 432. Thus, the through electrode 432 is disposed in the open region of the first buffer layer 441, and thus may be in direct contact with the upper surface of the first circuit pattern layer 421. Therefore, the through electrode 432 may have a structure that penetrates the first buffer layer 441 together with the second insulating layer 412.

[0204] Meanwhile, a second buffer layer 442 may be disposed on the second insulating layer 412. The second buffer layer 442 may be referred to as an upper oxide layer.

[0205] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. Thus, in this embodiment, the adhesion between the second insulating layer 412 and the first protective layer 450 may be improved.

[0206] Furthermore, the second buffer layer 442 may be disposed between the second circuit pattern layer 422 and the first protective layer 450. Through this, in this embodiment, the adhesion between the second circuit pattern layer 422 and the first protective layer 450 may be improved.

[0207] In addition, the second buffer layer 442 may be disposed on the inner wall of a through hole penetrating the second insulating layer 412. For example, the second buffer layer 442 may be disposed between the through hole of the second insulating layer 412 and the through electrode 432. Thus, the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the through electrode 432.

[0208] Meanwhile, the second buffer layer 442 may include at least one open region. For example, the second buffer layer 442 may include an open region that vertically overlaps the first opening of the first passivation layer 450. For example, the second buffer layer 442 may include an open region that exposes at least a portion of the upper surface of the second circuit pattern layer 422. For example, the second buffer layer 442 may include an open region that exposes a pad region of the upper surface of the second circuit pattern layer 422 to be coupled to a semiconductor device or an external substrate. Although the second buffer layer 442 includes an open region, this is not limiting. For example, a connecting member may be disposed in the pad region, and a reflow process may be performed on the connecting member. The second buffer layer 442 disposed on the pad region may be removed by the reflow process. Therefore, in this embodiment, a separate open region may not be formed in the second buffer layer 442.

[0209] In addition, a third buffer layer 443 may be disposed below the first insulating layer 411.

[0210] The third buffer layer 443 may be disposed between the first insulating layer 411 and the third insulating layer 413. Thus, in this embodiment, adhesion between the first insulating layer 411 and the third insulating layer 413 may be improved.

[0211] Furthermore, the third buffer layer 443 may be disposed between the third circuit pattern layer 423 and the third insulating layer 413. Thus, the third buffer layer 443 may improve adhesion between the third circuit pattern layer 423 and the third insulating layer 413.

[0212] Also, at least a portion of the third buffer layer 443 may be in contact with the through electrode 433 penetrating the third insulating layer 413. Thus, the third buffer layer 443 may improve adhesion with the through electrode 433.

[0213] Meanwhile, the third buffer layer 443 may include at least one open region. Preferably, the third buffer layer 443 may open a region of the lower surface of the third circuit pattern layer 423 that vertically overlaps the through electrode 433. That is, if the third buffer layer 443 is disposed between the third circuit pattern layer 423 and the through electrode 433, electrical characteristics between the third circuit pattern layer 423 and the through electrode 433 may be degraded. Therefore, the third buffer layer 443 includes an open region that opens a region of the lower surface of the third circuit pattern layer 423 that vertically overlaps the through electrode 433. Thus, the through electrode 433 is disposed in the open region of the third buffer layer 443, thereby making direct contact with the lower surface of the third circuit pattern layer 423. Therefore, the through electrode 433 may have a structure that penetrates the third buffer layer 443 together with the third insulating layer 413.

[0214] Meanwhile, a fourth buffer layer 444 may be disposed below the third insulating layer 413 .

[0215] The fourth buffer layer 444 may be disposed between the third insulating layer 413 and the second protective layer 460. Thus, in this embodiment, the adhesion between the third insulating layer 413 and the second protective layer 460 may be improved.

[0216] Furthermore, the fourth buffer layer 444 may be disposed between the fourth circuit pattern layer 424 and the second protective layer 460. Through this, in this embodiment, the adhesion between the fourth circuit pattern layer 424 and the second protective layer 460 may be improved.

[0217] In addition, the fourth buffer layer 444 may be disposed on an inner wall of a through hole penetrating the third insulating layer 413. For example, the fourth buffer layer 444 may be disposed between the through hole of the third insulating layer 413 and the through electrode 433. Thus, the fourth buffer layer 444 may improve adhesion between the third insulating layer 413 and the through electrode 433.

[0218] Meanwhile, the fourth buffer layer 444 may include at least one open region. For example, the fourth buffer layer 444 may include an open region vertically overlapping the second opening of the second passivation layer 460. For example, the fourth buffer layer 444 may include an open region that exposes at least a portion of the lower surface of the fourth circuit pattern layer 424. For example, the fourth buffer layer 444 may include an open region that exposes a pad region of the lower surface of the fourth circuit pattern layer 424 to be coupled to a semiconductor device or an external substrate. Although the fourth buffer layer 444 includes an open region, this is not limiting. For example, a connection member may be disposed on the pad region, and a reflow process may be performed on the connection member. The fourth buffer layer 444 disposed on the pad region may be removed by the reflow process. Therefore, in some embodiments, a separate open region may not be formed in the fourth buffer layer 444.

[0219] Meanwhile, each of the first to fourth buffer layers 441, 442, 443, and 444 may include an oxide. For example, each of the first to fourth buffer layers 441, 442, 443, and 444 may be an oxide layer containing an oxide. Preferably, the first to fourth buffer layers 441, 442, 443, and 444 may include aluminum oxide (Al2O3). However, embodiments are not limited thereto, and the first to fourth buffer layers 441, 442, 443, and 444 may include a material having at least one reactive group or functional group that reacts with the insulating layer or the protective layer.

[0220] Each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 5 nm to 100 nm. Preferably, each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 7 nm to 90 nm. More preferably, each of the first to fourth buffer layers 441, 442, 443, and 444 may have a thickness in the range of 10 nm to 50 nm.

[0221] If the thickness of each of the first to fourth buffer layers 441, 442, 443, and 444 is less than 5 nm, it may be impossible to form a buffer layer of uniform thickness on the insulating layer or circuit pattern layer. Furthermore, if the buffer layer does not have a uniform thickness, the adhesion strength may decrease in specific regions. Furthermore, if the thickness of each of the first to fourth buffer layers 441, 442, 443, and 444 is less than 5 nm, the effect of increasing the adhesion strength according to the embodiment may be insufficient.

[0222] Furthermore, if the thickness of the first to fourth buffer layers 441, 442, 443, and 444 exceeds 100 nm, the time required to form the first to fourth buffer layers 441, 442, 443, and 444 increases, which may result in a decrease in product yield.

[0223] Meanwhile, each of the first to fourth buffer layers 441, 442, 443, and 444 may be formed by applying a deposition method such as ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition), but is not limited thereto.

[0224] As mentioned above, embodiments include a buffer layer disposed between insulating layers comprising different insulating materials.

[0225] In this case, if the plurality of insulating layers are formed of the same insulating material, the buffer layer can be omitted. However, even if the plurality of insulating layers contain the same insulating material, it is preferable to provide the buffer layer in view of the characteristics of a circuit board having low surface roughness that is applicable to high frequency bands.

[0226] Furthermore, when the insulating layers are all formed of prepreg, there is a problem that the overall thickness of the circuit board increases. That is, the prepreg contains reinforcing fibers, which limits how thin the insulating layers can be reduced. This increases the overall thickness of the circuit board and semiconductor package.

[0227] Furthermore, when the insulating layers do not contain any reinforcing fibers, the warpage characteristics of the circuit board may be reduced. That is, when the insulating layers do not contain any reinforcing fibers, the warpage characteristics of the insulating layers may be reduced, which may result in a reduction in process characteristics in the manufacturing process of the circuit board.

[0228] In addition, there is a limit to how much the shape and size of the through electrodes can be reduced using only a thermosetting resin. Therefore, the circuit board may contain a photocurable resin. Furthermore, the properties of the photocurable resin may reduce the adhesive strength between the thermosetting resin and the circuit pattern layer.

[0229] Therefore, in the embodiment, the first to fourth buffer layers 441, 442, 443, and 444 as described above are applied to improve the overall adhesion between the layers that make up the circuit board.

[0230] The arrangement of the first to fourth buffer layers 441, 442, 443, and 444 will be described in more detail below.

[0231] However, the following description will focus on the first buffer layer 441 and the second buffer layer 442. The third buffer layer 443 and the fourth buffer layer 444 can have an arrangement structure corresponding to the first buffer layer 441 and the second buffer layer 442, which will be described later.

[0232] FIG. 3 is a cross-sectional view illustrating the arrangement structure of the first buffer layer according to one embodiment.

[0233] 3, a first buffer layer 441 is disposed on a first insulating layer 411. At this time, the first buffer layer 441 may include a plurality of portions.

[0234] The first buffer layer 441 may be formed after the first circuit pattern layer 421 is disposed on the first insulating layer 411. Therefore, the first buffer layer 441 does not need to be provided between the first insulating layer 411 and the first circuit pattern layer 421.

[0235] The first buffer layer 441 may include a first portion 441-1. The first portion 441-1 of the first buffer layer 441 may refer to a region of the entire region of the first buffer layer 441 that is disposed on the top surface of the first insulating layer 411.

[0236] The first portion 441-1 of the first insulating layer 411 may be disposed between an upper surface of the first insulating layer 411 and a lower surface of the second insulating layer 412. Thus, the first portion 441-1 of the first buffer layer 441 may improve adhesion between the first insulating layer 411 and the second insulating layer 412.

[0237] The first buffer layer 441 may include a second portion 441-2 and a third portion 441-3.

[0238] The second portion 441-2 and the third portion 441-3 of the first buffer layer 441 may refer to a region disposed on the surface of the first circuit pattern layer 421 among the entire region of the first buffer layer 441.

[0239] In this case, the second portion 441-2 and the third portion 441-3 of the first buffer layer 441 may have different arrangement structures. For example, the second portion 441-2 of the first buffer layer 441 may include an open region, and the third portion 441-3 of the first buffer layer 441 may not include an open region.

[0240] For example, the first circuit pattern layer 421 may include a plurality of patterns, for example, the first circuit pattern layer 421 may include a first pattern 421-1 and a second pattern 421-2.

[0241] The first pattern 421-1 of the first circuit pattern layer 421 may refer to a pattern of the first circuit pattern layer 421 that directly contacts the through electrode 432. For example, the first pattern 421-1 of the first circuit pattern layer 421 may refer to a pattern that vertically overlaps the through electrode 432.

[0242] The second pattern 421-2 of the first circuit pattern layer 421 may refer to a pattern of the first circuit pattern layer 421 that does not directly contact the through electrode 432. For example, the second pattern 421-2 of the first circuit pattern layer 421 may refer to a pattern that does not vertically overlap the through electrode 432.

[0243] The second part 441-2 of the first buffer layer 441 may partially cover a surface of the first pattern 421-1 of the first circuit pattern layer 421. For example, the second part 441-2 of the first buffer layer 441 may entirely cover a side surface of the first pattern 421-1. For example, the second part 441-2 of the first buffer layer 441 may partially cover an upper surface of the first pattern 421-1. For example, the second part 441-2 of the first buffer layer 441 may be selectively disposed in a region of the upper surface of the first pattern 421-1 that does not vertically overlap with the through electrode 432. For example, the second part 441-2 of the first buffer layer 441 may be disposed on the upper surface of the first pattern 421-1 and may include an open region in a region that vertically overlaps with the through electrode 432. Thus, the through electrode 432 is disposed in the open region of the second part 441-2 of the first buffer layer 441, and may thereby be in direct contact with an upper surface of the first pattern 421-1 of the first circuit pattern layer 421. For example, the through electrode 432 may penetrate the second part 441-2 of the first buffer layer 441 while penetrating the second insulating layer 412. At least a portion of a side surface of the through electrode 432 may be in contact with the second part 441-2 of the first buffer layer 441.

[0244] Thus, the second part 441-2 of the first buffer layer 441 may function to improve adhesion between the first pattern 421-1 of the first circuit pattern layer 421 and the second insulating layer 412. Furthermore, the second part 441-2 of the first buffer layer 441 may function to improve adhesion between the first pattern 421-1 of the first circuit pattern layer 421 and the through electrode 432.

[0245] Meanwhile, the third part 441-3 of the first buffer layer 441 may not include an open region. For example, the third part 441-3 of the first buffer layer 441 may entirely cover the side and upper surfaces of the second pattern 421-2 of the first circuit pattern layer 421. Thus, the second pattern 421-2 of the first circuit pattern layer 421 may not directly contact the second insulating layer 412. For example, the lower surface of the second pattern 421-2 of the first circuit pattern layer 421 may contact the first insulating layer 411, and the side and upper surfaces of the second pattern 421-2 of the first circuit pattern layer 421 may contact the first buffer layer 441.

[0246] In the embodiment, the first buffer layer 441 can be used to improve the adhesion between the first insulating layer 411 and the second insulating layer 412, the adhesion between the first circuit pattern layer 421 and the second insulating layer 412, and further the adhesion between the first circuit pattern layer 421 and the through electrode 432.

[0247] FIG. 4 is a cross-sectional view illustrating the arrangement structure of the second buffer layer according to the first embodiment.

[0248] 4, the second buffer layer 442 is disposed on the second insulating layer 412. In this case, if the second insulating layer 412 is composed of multiple layers, the second buffer layer 442 may be disposed between the multiple second insulating layers. However, the following description will focus on a second buffer layer disposed on a second insulating layer disposed adjacent to the first protective layer 450.

[0249] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. The second buffer layer 442 may also be disposed between the second circuit pattern layer 422 and the first protective layer 450.

[0250] That is, the second buffer layer 442 of the first embodiment may be formed in a state where the second circuit pattern layer 422 is disposed on the second insulating layer 412. As a result, the second buffer layer 442 of the first embodiment does not need to be disposed between the second insulating layer 412 and the second circuit pattern layer 422.

[0251] The second buffer layer 442 may include multiple portions.

[0252] The second buffer layer 442 may include a first portion 442-1. The first portion 442-1 of the second buffer layer 442 may refer to a region of the entire region of the second buffer layer 442 that is disposed on the upper surface of the second insulating layer 412.

[0253] The first portion 442-1 of the second buffer layer 442 may be disposed between an upper surface of the second insulating layer 412 and a lower surface of the first protective layer 450. Thus, the first portion 442-1 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the first protective layer 450.

[0254] The second buffer layer 442 may include a second portion 442-2 and a third portion 442-3.

[0255] The second portion 442-2 and the third portion 442-3 of the second buffer layer 442 may refer to a region disposed on the surface of the second circuit pattern layer 422 among the entire region of the second buffer layer 442.

[0256] In this case, the second portion 442-2 and the third portion 442-3 of the second buffer layer 442 may have different arrangement structures. For example, the second portion 442-2 of the second buffer layer 442 may include an open region, and the third portion 442-3 of the second buffer layer 442 may not include an open region.

[0257] For example, the second circuit pattern layer 422 may include a plurality of patterns, for example, the second circuit pattern layer 422 may include a first pattern 422-1 and a second pattern 422-2.

[0258] The first pattern 422-1 of the second circuit pattern layer 422 may refer to a pattern of the second circuit pattern layer 422 that vertically overlaps the first opening 451 of the first protective layer 450. For example, the first pattern 422-1 of the second circuit pattern layer 422 may refer to a pad to be coupled to a semiconductor device or an external substrate.

[0259] The second pattern 422 - 2 of the second circuit pattern layer 422 may refer to a pattern of the second circuit pattern layer 422 that does not vertically overlap the first opening 451 of the first protection layer 450 .

[0260] The second part 442-2 of the second buffer layer 442 may partially cover a surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second part 442-2 of the second buffer layer 442 may entirely cover a side surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second part 442-2 of the second buffer layer 442 may partially cover an upper surface of the first pattern 422-1 of the second circuit pattern layer 422. For example, the second part 442-2 of the second buffer layer 442 may be selectively disposed in a region of the upper surface of the first pattern 422-1 of the second circuit pattern layer 422 that does not vertically overlap the first opening 451 of the first protection layer 450. For example, the second portion 442-2 of the second buffer layer 442 may be disposed on the upper surface of the first pattern 422-1 of the second circuit pattern layer 422 and may include an open area that vertically overlaps the first opening 451 of the first protective layer 450.

[0261] Thus, the second portion 442-2 of the second buffer layer 442 may function to improve adhesion between the first pattern 422-1 of the second circuit pattern layer 422 and the first protective layer 450.

[0262] Meanwhile, the third part 442-3 of the second buffer layer 442 may not include an open region. For example, the third part 442-3 of the second buffer layer 442 may entirely cover the side and upper surfaces of the second pattern 422-2 of the second circuit pattern layer 422. Thus, the second pattern 422-2 of the second circuit pattern layer 422 may not directly contact the first protective layer 450. For example, the lower surface of the second pattern 422-2 of the second circuit pattern layer 422 may contact the second insulating layer 412, and the side and upper surfaces of the second pattern 422-2 of the second circuit pattern layer 422 may contact the second buffer layer 442.

[0263] In an embodiment, the second buffer layer 442 can be used to improve the adhesion between the second insulating layer 412 and the first protective layer 450 and the adhesion between the second circuit pattern layer 422 and the first protective layer 450.

[0264] FIG. 5 is a cross-sectional view illustrating the arrangement structure of the second buffer layer according to the second embodiment.

[0265] Referring to FIG. 5, a second buffer layer 442 is disposed on the second insulating layer 412 .

[0266] The second buffer layer 442 may be disposed between the second insulating layer 412 and the first protective layer 450. The second buffer layer 442 may also be disposed between the second insulating layer 412 and the first protective layer 450.

[0267] That is, the second buffer layer 442 of the second embodiment is disposed on the second insulating layer 412 before the second circuit pattern layer 422 is formed. Preferably, the second buffer layer 442 can be formed after the through holes are formed in the second insulating layer 412 and before the through electrodes 432 and the second circuit pattern layer 422 are formed.

[0268] Therefore, the second buffer layer 442 of the second embodiment does not have to be disposed between the second circuit pattern layer 422 and the first protective layer 450. However, the embodiment is not limited thereto. For example, in the embodiment, the process of forming the second buffer layer 442 may be performed multiple times. As a result, the second buffer layer 442 may have a structure of the second embodiment described below in combination with the structure of the first embodiment described above.

[0269] The second buffer layer 442 may include multiple portions.

[0270] The second buffer layer 442 may include a first portion 442-1. The first portion 442-1 of the second buffer layer 442 may refer to a region of the entire region of the second buffer layer 442 that is disposed between the second insulating layer 412 and the first protective layer 450.

[0271] The first portion 442-1 of the second buffer layer 442 may be disposed between an upper surface of the second insulating layer 412 and a lower surface of the first protective layer 450. Thus, the first portion 442-1 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the first protective layer 450.

[0272] The second buffer layer 442 may include a second portion 442-2 and a third portion 442-3.

[0273] The second portion 442-2 of the second buffer layer 442 may refer to a region disposed between the second insulating layer 412 and the second circuit pattern layer 442-2 among the entire region of the second buffer layer 442. Thus, the second portion 442-2 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the second circuit pattern layer 442-2.

[0274] Furthermore, the third portion 442-3 of the second buffer layer 442 may be disposed on the inner wall of the through hole of the second insulating layer 412. That is, the second buffer layer 442 is formed after the through hole is formed in the second insulating layer 412. Therefore, the second buffer layer 442 may include the third portion 442-3 provided on the inner wall of the through hole of the second insulating layer 412.

[0275] The third portion 442-3 of the second buffer layer 442 is disposed between the second insulating layer 412 and the through electrode 432. Thus, the third portion 442-3 of the second buffer layer 442 may improve adhesion between the second insulating layer 412 and the through electrode 432.

[0276] The circuit board of the embodiment can improve the adhesion between a plurality of layers.

[0277] Specifically, the circuit board of the embodiment includes a first insulating layer including a first insulating material, and a second insulating layer disposed on the first insulating layer and including a second insulating material different from the first insulating material.

[0278] In this case, the embodiment includes a buffer layer disposed between the first insulating layer and the second insulating layer. The buffer layer may function as an adhesive layer that improves adhesion between the first insulating layer and the second insulating layer. The buffer layer may be an oxide layer. For example, the buffer layer may include aluminum oxide.

[0279] Through this, the embodiment can improve the adhesion between the first insulating layer and the second insulating layer, thereby improving the physical reliability and / or electrical reliability of the circuit board and the semiconductor package including the same.

[0280] Furthermore, the first insulating layer can include a thermosetting resin, and the second insulating layer can include a photocurable resin. In an embodiment, the second insulating layer includes a photocurable resin, which can improve the physical and electrical reliability of the circuit pattern layer and the through electrodes disposed on the second insulating layer. Furthermore, the second insulating layer includes a photocurable resin, which can reduce the size of the circuit pattern layer and the through electrodes disposed on the second insulating layer.

[0281] In this case, the photocurable resin contains a relatively high amount of ceramic particles and has a relatively high cure shrinkage rate, which may result in a decrease in adhesion between the photocurable resin and other layers.

[0282] In contrast, in the embodiment, the buffer layer is disposed on the surface of the photocurable resin, so that even if the second insulating layer contains the photocurable resin, the circuit pattern layer and the through electrodes can be miniaturized without affecting the adhesion.

[0283] Therefore, the embodiment can improve the circuit integration density of the circuit board, and can further improve the physical and / or electrical reliability of the circuit board.

[0284] On the other hand, the buffer layer in the embodiment is also disposed between the second insulating layer and the circuit pattern layer, thereby improving the adhesion between the second insulating layer and the circuit pattern layer.

[0285] In addition, the buffer layer in the embodiment is also disposed between the second insulating layer and the through electrode, thereby improving the adhesion between the second insulating layer and the through electrode.

[0286] In addition, the buffer layer in the embodiment is also disposed between the second insulating layer and the first protective layer, thereby improving the adhesion between the second insulating layer and the first protective layer.

[0287] In addition, the buffer layer in the embodiment is also disposed between the circuit pattern layer and the first protective layer, thereby improving the adhesion between the circuit pattern layer and the first protective layer.

[0288] In the embodiment, by forming a buffer layer having the structure described above, the adhesion between the multiple layers constituting the circuit board can be improved, thereby improving the reliability of the product.

[0289] FIG. 6 is a diagram showing a circuit board according to the second embodiment.

[0290] 6, the circuit board of the second embodiment may have an overall similar structure to the circuit board of the first embodiment of FIG. 2. However, the circuit board of the second embodiment may have a cavity C in the second insulating layer, unlike the circuit board of the first embodiment. Therefore, the circuit board of the second embodiment may be distinguished from the circuit board of the first embodiment in the structure of the second insulating layer including the cavity C and the second buffer layer disposed on the second insulating layer.

[0291] The circuit board of the second embodiment will be described below, focusing on the features that distinguish it from the circuit board of the first embodiment.

[0292] The circuit board includes a first insulating layer 511 and a second insulating layer 512. A first circuit pattern layer 521 is disposed on the first insulating layer 511.

[0293] Although not shown in the drawing, a first buffer layer may be disposed on the first insulating layer 511.

[0294] Meanwhile, a second buffer layer 542 is disposed on the second insulating layer 512. At this time, the arrangement structure of the second buffer layer 542 may be similar to the structure shown in FIG.

[0295] However, the second insulating layer 512 includes a cavity C. Therefore, the second buffer layer 542 may include a portion formed in a region corresponding to the cavity C.

[0296] That is, the second insulating layer 512 includes a cavity C penetrating the upper and lower surfaces. In this case, the cavity C of the second insulating layer 512 may be formed together with a through hole corresponding to the through electrode 532 penetrating the second insulating layer 512.

[0297] The first circuit pattern layer 521 further includes a third pattern 521-3 that overlaps the cavity C vertically.

[0298] The third pattern 521-3 of the first circuit pattern layer 521 may have an upper surface exposed through the cavity C. The third pattern 521-3 of the first circuit pattern layer 521 may be a semiconductor device disposed in the cavity C or a pad to be coupled to an external substrate.

[0299] Meanwhile, the second buffer layer 542 disposed on the second insulating layer 512 may include multiple portions.

[0300] The second buffer layer 542 may include a first portion 542 - 1 disposed between the second insulating layer 512 and the first protective layer 550 .

[0301] The second buffer layer 542 may also include a second portion 542 - 2 disposed between the inner wall of the through-hole of the second insulating layer 512 and the through-electrode 532 .

[0302] The second buffer layer 542 may also include a third portion 542-3 disposed on the inner wall of the cavity C of the second insulating layer 512.

[0303] The second buffer layer 542 may also include a fourth portion 542-4 disposed on the bottom surface of the cavity C of the second insulating layer 512. In this case, the fourth portion 542-4 of the second buffer layer 542 may be a part of the first buffer layer described above.

[0304] The second buffer layer 542 included in the circuit board of the second embodiment includes a third portion 542-3 arranged on the inner wall of the cavity C and a fourth portion 542-4 arranged on the bottom surface of the cavity C to distinguish it from the circuit board of the first embodiment.

[0305] The third portion 542-3 of the second buffer layer 542 is disposed on the inner wall of the cavity C. In this case, in an embodiment, the third portion 542-3 of the second buffer layer 542 can be used to prevent debris from being exposed through the inner wall of the cavity C. For example, when the cavity C is formed in the second insulating layer 512, debris such as burrs may be present on the inner wall of the cavity C depending on the processing process of the cavity C.

[0306] This has traditionally led to an additional desmear process to remove the debris.

[0307] In contrast, in the embodiment, the third portion 542-3 of the second buffer layer 542 is formed on the inner wall of the cavity C. As a result, the embodiment can solve reliability problems that may occur due to the debris through the third portion 542-3 of the second buffer layer 542. Furthermore, in the embodiment, by disposing the third portion 542-3 of the second buffer layer 542, the desmear process can be omitted, thereby simplifying the manufacturing process.

[0308] The embodiment also includes a fourth portion 542-4 of the second buffer layer 542 disposed on the bottom surface of the cavity C. In this case, the bottom surface of the cavity C substantially corresponds to the top surface of the first insulating layer 511. Therefore, the fourth portion 542-4 of the second buffer layer 542 can also be said to be part of the first buffer layer 441 described in the above embodiment.

[0309] The fourth portion 542-4 of the second buffer layer 542 is disposed on the bottom surface of the cavity C, thereby preventing a portion of the insulating material contained in the first insulating layer 511 from being exposed through the cavity C.

[0310] For example, if a desmear process is performed after forming the cavity C, the surface of the first insulating layer 511 may also be removed during the desmear process. In addition, a portion of the reinforcing fibers disposed in the first insulating layer 511 may be exposed through the cavity C due to the desmear process. In addition, if the reinforcing fibers are exposed through the cavity C, problems with physical or electrical reliability may occur during a semiconductor device mounting process or an external substrate bonding process.

[0311] In contrast, in the embodiment, a fourth portion 542-4 of the second buffer layer 542 is disposed on the bottom surface of the cavity C. The fourth portion 542-4 of the second buffer layer 542 may function as a barrier layer that protects the surface of the first insulating layer 511 during the desmear process. As a result, the embodiment may prevent the reinforcing fibers included in the first insulating layer 511 from being exposed through the cavity C, thereby improving the overall physical and electrical reliability of the circuit board.

[0312] Meanwhile, the fourth part 542-4 of the second buffer layer 542 may include an open region exposing a surface of the third pattern 521-3 of the first circuit pattern layer 521. For example, the fourth part 542-4 of the second buffer layer 542 may entirely expose an upper surface of the third pattern 521-3 of the first circuit pattern layer 521. Furthermore, the fourth part 542-4 of the second buffer layer 542 may expose at least a portion of a side surface of the third pattern 521-3 of the first circuit pattern layer 521.

[0313] Meanwhile, although the drawings show the cavity C penetrating one second insulating layer 512, the cavity C is not limited thereto. For example, the cavity C may also penetrate at least two second insulating layers.

[0314] As described above, the circuit board according to the second embodiment includes a cavity, which can improve the overall product reliability of the circuit board.

[0315] That is, the second insulating layer includes a cavity. In this case, the buffer layer may also be disposed on the inner wall of the cavity of the second insulating layer. This allows the embodiment to omit a desmear process for removing debris remaining on the inner wall of the cavity. This simplifies the manufacturing process of the circuit board. Furthermore, by omitting the desmear process, the embodiment can prevent the size of the cavity from being expanded by the desmear process, thereby forming a cavity with an optimal size. Therefore, the embodiment can reduce the volume of the circuit board.

[0316] The buffer layer may also be disposed on the bottom surface of the cavity. When a desmear process is performed after the cavity is formed, the buffer layer disposed on the bottom surface of the cavity can function as a barrier layer. In the embodiment, the barrier layer can prevent the reinforcing fibers contained in the first insulating layer from being exposed during the desmear process. This can further improve the reliability of the product.

[0317] FIG. 7a is a cross-sectional view showing a circuit board according to a third embodiment, and FIG. 7b is a plan view of the circuit board of FIG. 7a.

[0318] Referring to Figures 7a and 7b, the circuit board of the third embodiment may have an overall structure similar to that of the circuit board of the second embodiment, except that a fourth pattern 542-4 is disposed on the first insulating layer 511.

[0319] In this case, the second insulating layer 512 of the embodiment includes a photo-curable resin, so that in the embodiment, when forming the cavity C in the second insulating layer 512, an exposure and development process can be performed instead of a laser process.

[0320] Here, the first insulating layer 511 includes a thermosetting resin. Therefore, when a development process is performed to form the cavity C in the second insulating layer 512, the first insulating layer 511 may not be removed. Therefore, in this embodiment, the cavity C can be formed penetrating only the second insulating layer 512 without a stopper for forming the cavity C.

[0321] Therefore, in this embodiment, a fourth pattern 521-4 of the first circuit pattern layer 521 may be provided that is directly connected to the third pattern 521-3 of the first circuit pattern layer 521 in an area that vertically overlaps the cavity C.

[0322] That is, in the conventional structure, the third pattern of the first circuit pattern layer, which is vertically overlapped with the cavity, and the fifth pattern of the first circuit pattern layer, which is not vertically overlapped with the cavity, cannot be directly connected to each other due to the presence of a stopper for forming the cavity C. For this reason, the third pattern and the fifth pattern of the first circuit pattern layer have been connected to each other using a through electrode that penetrates the first insulating layer 511.

[0323] Alternatively, the second insulating layer 512 of the embodiment may include a photo-curable resin, which may eliminate the stopper required to form the cavity C.

[0324] Therefore, in the embodiment, a fourth pattern 521-4 may be disposed on the first insulating layer 511 vertically overlapping the cavity C. The fourth pattern 521-4 may be a trace that directly connects between the third pattern 521-3 vertically overlapping the cavity C and the fifth pattern 521-5 that does not vertically overlap the cavity C. In this case, the fifth pattern 521-5 of the first circuit pattern layer 521 may refer to the first pattern 421-1 or / and the second pattern 421-2 of the first circuit pattern layer 421 included in the circuit board of the first embodiment.

[0325] Accordingly, in the embodiment, the fourth pattern 521-4 of the first circuit pattern layer 521 may be divided into a plurality of parts. The fourth pattern 521-4 of the first circuit pattern layer 521 may include a first part 521-41 that is directly connected to the third pattern 521-3 and vertically overlaps the cavity C. In addition, the fourth pattern 521-4 of the first circuit pattern layer 521 may include a second part 521-42 that extends from the first part 521-41 and does not vertically overlap the cavity C.

[0326] That is, the first part 521-41 of the fourth pattern 521-4 of the first circuit pattern layer 521 may refer to a portion exposed through the cavity C and directly connected to the third pattern 521-3. Also, the second part 521-42 of the fourth pattern 521-4 of the first circuit pattern layer 521 may refer to a portion covered with the second insulating layer 512 and connecting the first part 521-41 of the fourth pattern 521-4 and the fifth pattern 521-5.

[0327] Therefore, in the embodiment, the third pattern 521-3 and the fifth pattern 521-5 can be directly connected using the fourth pattern 521-4, thereby minimizing the signal transmission distance of a semiconductor device or an external board disposed on the third pattern 521-3 and minimizing signal transmission loss.

[0328] Meanwhile, the second buffer layer 542 may further include a fifth portion 542-5. The fifth portion 542-5 of the second buffer layer 542 may be disposed to cover the side and top surfaces of the first part 521-41 of the fourth pattern 521-4 exposed through the cavity C. As a result, the embodiment may stably protect the fourth pattern 521-4 exposed through the cavity C. Furthermore, the embodiment may improve adhesion with a molding layer when a molding layer is formed to fill the cavity C.

[0329] FIG. 8 is a diagram showing a semiconductor package according to a seventh embodiment, and FIG. 9 is a diagram showing a semiconductor package according to an eighth embodiment.

[0330] Referring to FIG. 8, the semiconductor package of the seventh embodiment includes a connection member 610 disposed on the third pattern 521-3 of the first circuit pattern layer 521 exposed through the cavity C.

[0331] The semiconductor package of the seventh embodiment includes a semiconductor element 620 disposed on the connection member 610. The semiconductor element 620 includes a terminal 625, and the terminal 625 may be electrically connected to the third pattern 521-3 of the first circuit pattern layer 521 via the connection member 610.

[0332] 9, the semiconductor package of the eighth embodiment may further include a molding layer 630 filling the cavity C. The molding layer 630 may be in contact with the second buffer layer 542.

[0333] The method for manufacturing a circuit board according to the embodiment will be described below in the order of steps.

[0334] 10 to 17 are cross-sectional views for explaining the manufacturing method of the circuit board of the embodiment in the order of steps. The manufacturing method of the circuit board including the cavity will be explained below. However, for the sake of convenience, the explanation will be centered on the first insulating layer 511, and the layers sequentially arranged above it.

[0335] 10 , the embodiment prepares a first insulating layer 511. Then, the embodiment forms a through hole penetrating the first insulating layer 511. Then, the embodiment performs a process of forming a through electrode 531 filling the through hole of the first insulating layer 511 and a first circuit pattern layer 521 disposed on the upper surface of the first insulating layer 511.

[0336] 11 , an embodiment may perform a process of forming a first buffer layer 541. At this time, the first buffer layer 541 may be formed entirely on the exposed surface of the first insulating layer 511 and the exposed surface of the first circuit pattern layer 521. Then, an embodiment may perform a process of removing a region of the first buffer layer 541 that vertically overlaps with a through electrode that penetrates the second insulating layer. However, the removing process may also be performed later after a through hole is formed in the second insulating layer 512. Hereinafter, the removing process will be described as being performed after a through hole is formed in the second insulating layer 512.

[0337] 12, in this embodiment, a process of depositing a second insulating layer 512 on the first buffer layer 541 may be performed. The second insulating layer 512 may include a photocurable resin.

[0338] 13, an embodiment may perform a process of processing the second insulating layer 512. Specifically, the process may refer to a process of exposing and developing the second insulating layer 512.

[0339] For example, in an embodiment, a region of the second insulating layer 512 where the through hole TH is to be formed may be exposed to light, developed, and removed. Also, in an embodiment, a region of the second insulating layer 512 where the cavity C is to be formed may be exposed to light, developed, and removed. In this case, the process of forming the through hole TH and the process of forming the cavity C may be performed simultaneously, but are not limited to this.

[0340] 14 , in this embodiment, a process of forming a second buffer layer 542 on the second insulating layer 512 may be performed. At this time, the second buffer layer 542 may be disposed on the upper surface of the second insulating layer 512, the inner wall of the through hole TH, and the inner wall of the cavity C. At least a portion of the second buffer layer 542 may be connected to the first buffer layer 541.

[0341] 15 , in an embodiment, a process of removing a region of the first buffer layer 541 that vertically overlaps the through hole TH may be performed. In other words, in an embodiment, a process of removing the first buffer layer 541 may be performed to expose an upper surface 521U of the first circuit pattern layer 521 that vertically overlaps the through hole TH. The process of removing the first buffer layer 541 may be performed using a wet method, or alternatively, a dry method. When using a wet method, a hydrofluoric acid-based chemical may be used to selectively remove a portion of the first buffer layer 541. When using a dry method, a laser may be used to selectively remove a portion of the first buffer layer 541.

[0342] In addition, in the embodiment, a process of removing a region of the first buffer layer 541 or the second buffer layer 542 adjacent to the third pattern 521-3 of the first circuit pattern layer 521 exposed through the cavity C may be performed. For example, in the embodiment, at least a portion of the first buffer layer 541 and the second buffer layer 542 may be removed to expose at least a portion of the side surface and the top surface of the third pattern 521-3 that vertically overlaps the cavity C.

[0343] Next, referring to FIG. 16, an embodiment can perform a process of forming a through electrode 532 that fills the through hole TH of the second insulating layer 512 and a second circuit pattern layer 522 that is disposed on the second insulating layer 512.

[0344] 17, in this embodiment, a process of forming a first protective layer 550 on the second buffer layer 542 may be performed. The first protective layer 550 may include an opening that vertically overlaps with the cavity C. In addition, the first protective layer 550 may be formed by removing at least a portion of the upper surface of the second circuit pattern layer 522.

[0345] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0346] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0347] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0348] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. a photosensitive insulating layer; and a first circuit pattern layer embedded in the photosensitive insulating layer; a lower oxide layer disposed at the interface between the photosensitive insulating layer and the first circuit pattern layer.

2. The semiconductor package of claim 1 , wherein the lower oxide layer is further provided on a lower surface of the photosensitive insulating layer that does not overlap the first circuit pattern layer in a vertical direction.

3. further comprising an additional insulating layer disposed on a lower surface of the photosensitive insulating layer; The semiconductor package of claim 2 , wherein the lower oxide layer provided on the lower surface of the photosensitive insulating layer contacts the upper surface of the additional insulating layer.

4. The semiconductor package of claim 2 , wherein the additional insulating layer comprises an insulating material different from an insulating material of the photosensitive insulating layer.

5. The semiconductor package of claim 2 , wherein the additional insulating layer comprises reinforced fibers.

6. The semiconductor package of claim 3 , wherein the additional insulating layer is a thermosetting insulating layer.

7. a through electrode that penetrates the photosensitive insulating layer; a second circuit pattern layer disposed on the photosensitive insulating layer; The semiconductor package of claim 1 , wherein the lower oxide layer includes an open area that vertically overlaps a lower surface of the through electrode.

8. The semiconductor package of claim 7 , further comprising a top oxide layer disposed on the photosensitive insulating layer.

9. The semiconductor package of claim 8 , wherein at least one of the upper oxide layer and the lower oxide layer comprises aluminum oxide.

10. the protective layer disposed on the top oxide layer; The upper oxide layer is a first portion provided at an interface between the photosensitive insulating layer and the protective layer; The semiconductor package according to claim 9 , further comprising: a second portion provided at an interface between the second circuit pattern layer and the protection layer.

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