Amorphous tellurium oxide-containing semiconductor, thin film transistor including the same, and method for manufacturing the same

Abstract

The present invention discloses a semiconductor containing amorphous tellurium oxide, a thin film transistor containing the same, and a method for manufacturing the same. The semiconductor contains chalcogen atoms including one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se), and a tellurium complex containing tellurium (Te) atoms and tellurium oxide, thereby forming a thin film transistor having a structure such as TeO. x Thin film transistors (TFTs) fabricated based on the channel layer have high hole field-effect mobility and 7 The high on / off current ratio provides excellent output / transfer characteristics and electrical performance.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor containing amorphous tellurium oxide, a thin film transistor containing the same, and a method for manufacturing the same. [Background technology]

[0002] Over the past few decades, metal oxide semiconductors have been widely used in transistors, photovoltaics, thermoelectrics, light-emitting diodes, displays, and other applications, driving significant advances in modern optoelectronics research. However, commercially available oxide semiconductors with high electrical performance are all n-type semiconductors that are efficient for electron transport only at room temperature, while the lack of p-type semiconductors capable of hole transport limits their applicability to a wide range of applications. Amorphous a-InGaZnO, a representative n-type semiconductor, has been commercialized as a backplane transistor for driving organic light-emitting diode (OLED) displays. While its highly distributed conduction band minimum (CBM) enables excellent electron transport properties even in its amorphous structure, it lacks p-type characteristics at room temperature.

[0003] Cu is a p-type metal oxide semiconductor that allows hole transport even at room temperature. x Materials such as O and SnO have been investigated, but they exhibit poor electrical performance, such as low hole field-effect mobility and low on / off current ratio compared to n-type metal oxides. This severely limits the development of pn junction diode-based optoelectronic and CMOS (Complementary Metal Oxide Semiconductor) circuits.

[0004] The main reason why metal oxide semiconductors have poor p-type properties is that the valence band maximum for hole transport in metal oxides is mainly anisotropic and consists of the oxygen 2p orbital, which is relatively small in size and highly localized. + and Sn 2+The metastable cationic valence state of is unstable under air conditions, resulting in poor ambient stability. In this context, the development of stable, high-mobility, low-cost p-type semiconductors is currently of great importance in the microelectronics industry. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to solve the above-mentioned problems, and its purpose is to form TeO by using a deposition technique such as thermal evaporation or sputtering. x The present invention proposes a new amorphous p-type semiconductor and provides a high-performance p-channel transistor using this semiconductor. Another object of the present invention is to provide a high-performance p-channel TeO semiconductor having high stability and high performance at low processing temperatures. x The object of the present invention is to provide a thin film transistor. Another object of the present invention is to provide a large area flexible thin film transistor using low cost. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor comprising: chalcogen atoms including one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); and a tellurium complex including tellurium (Te) atoms and tellurium oxide. The chalcogen atoms may be doped into a tellurium complex.

[0007] In addition, the tellurium complex may be represented by the following Chemical Formula 1. [Chemical formula 1] TeO x During the ceremony, x is 0.8≦x≦1.7. Additionally, the tellurium oxide may include tellurium monoxide (TeO) and tellurium dioxide (TeO2).

[0008] In addition, the semiconductor may be represented by the following Chemical Formula 2: [Chemical formula 2] TeO x :M During the ceremony, M is a sulfur atom (S) or a selenium atom (Se), x is 0.8≦x≦1.7, The content of M is 0.5 to 5 atom % relative to the total number of Te atoms, O atoms, and M atoms.

[0009] The semiconductor may also be amorphous. The tellurium semiconductor may be p-type. Also, the semiconductor is in an oxygen-deficient state, which means that the ratio of oxygen in the stoichiometric ratio of tellurium (Te):oxygen (O) is less than 1:2.

[0010] In addition, the tellurium atoms of the semiconductor are Te 4+ ionization state of Te 2+ ionization states of Te 0 Here, the semiconductor can use the shallow acceptor state formed by the 5p orbitals of Te and Te as a hole conduction channel.

[0011] In addition, the selenium atoms of the semiconductor are Se 2- where the semiconductor Se 2- The oxygen vacancy is passivated, allowing the partially vacant 4p state to be used as a hole conduction channel. At this time, the Te-Se cation-anion bond is formed, maximizing the overlap between the cation 5p orbital and the anion 4p orbital, allowing for smooth hole transfer.

[0012] The semiconductor may also be for use in the semiconductor layer of a thin film transistor. The thickness of the semiconductor layer may be 2 to 10 nm, preferably 3 to 9 nm, more preferably 4 to 8.5 nm, and even more preferably 5 to 7 nm.

[0013] According to another aspect of the present invention, there is provided a thin film transistor including: a gate electrode; an insulating layer located on the gate electrode; a semiconductor layer located on the insulating layer and including a semiconductor according to the present invention; and a source electrode and a drain electrode located spaced apart from each other on the semiconductor layer.

[0014] In addition, the gate electrode may include at least one material selected from the group consisting of n-doped silicon (n-doped Si), p-doped silicon (p-doped Si), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), magnesium (Mg), calcium (Ca), ytterbium (Yb), chromium (Cr), nickel (Ni), molybdenum (Mo), gold oxide, platinum oxide, silver oxide, palladium oxide, iron oxide, graphene, carbon nanotubes (CNT), silver nanowires (Ag NW), indium tin oxide, and poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS).

[0015] In addition, the source electrode and the drain electrode may each include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), magnesium (Mg), calcium (Ca), ytterbium (Yb), chromium (Cr), nickel (Ni), molybdenum (Mo), gold oxide, platinum oxide, silver oxide, palladium oxide, iron oxide, graphene, carbon nanotubes (CNT), silver nanowires (Ag NW), indium tin oxide, and poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS).

[0016] The insulating layer may include one or more materials selected from the group consisting of silicon dioxide, glass, quartz, alumina, silicon carbide, magnesium oxide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polystyrene (PS), polyimide (PI), polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyethylene (PE), silicon oxide (SiO2), germanium, polyvinyl alcohol (PVA), polymethyl methacrylate (PMMA), zirconium oxide (ZrO2), aluminum oxide (AlO2), and hafnium oxide (HfO2).

[0017] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor layer, comprising: (a) mixing a chalcogen containing one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se) with tellurium dioxide (TeO2) to produce a mixture; and (b) depositing the mixture to form a semiconductor layer containing a semiconductor, wherein the semiconductor comprises chalcogen atoms containing one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se), and a tellurium complex containing tellurium (Te) atoms and tellurium oxide.

[0018] Also, the deposition in step (b) can be performed by thermal evaporation, sputtering, vapor phase chemical vapor deposition (CVD), or solution coating. Also, the deposition in step (b) can be performed by thermal evaporation or sputtering. In addition, the temperature of the substrate on which the thermal evaporation is performed may be 15 to 35° C., preferably room temperature. The sputtering may be performed at a substrate temperature of 15 to 35° C., preferably room temperature. The thermal evaporation or sputtering may be performed in a range of 10 -3 This can be done under vacuum pressures of less than Torr. In addition, when the thermal deposition is performed, the thermal deposition rate may be 1 to 100 Å / s based on the semiconductor layer.

[0019] Also, the molar ratio of the chalcogen to the tellurium dioxide (TeO2) in step (a) may be 0.01:99.99 to 50:50 (mol:mol). Also, during the sputtering step (b), the partial pressures of oxygen and argon plasma can be adjusted to control the molar ratio of tellurium to oxygen in the semiconductor layer. Furthermore, after step (b), the method may further include step (c) of annealing the semiconductor layer of step (b) at a temperature of 100 to 300° C. in an air or oxygen atmosphere. After step (c), step (d) of annealing in air at a temperature of room temperature to 300°C may be further included.

[0020] According to another aspect of the present invention, there is provided a method for manufacturing a thin film transistor, comprising: (1) preparing a gate electrode / insulating layer stack including a gate electrode and an insulating layer located on the gate electrode; (2) forming a semiconductor layer including a semiconductor on the insulating layer; and (3) forming a source electrode and a drain electrode on the semiconductor layer, wherein the semiconductor includes chalcogen atoms including one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se), and a tellurium complex including tellurium (Te) atoms and tellurium oxide. [Effects of the Invention]

[0021] TeO according to the present invention x Thin film transistors (TFTs) fabricated based on the channel layer have high hole field-effect mobility and 7 The high on / off current ratio provides excellent output / transfer characteristics and electrical performance.

[0022] These drawings are to be referred to when describing exemplary embodiments of the present invention, and the technical concept of the present invention should not be interpreted as being limited to the accompanying drawings. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic diagram illustrating a method for fabricating a semiconductor layer for use in a selenium-doped amorphous p-channel thin film transistor using a thermal evaporation process according to Example 1. FIG. [Figure 2a] 1 is a graph showing the XRD (X-ray Diffractometer) spectrum results of the TeOx:Se thin film thermally evaporated and annealed at 225° C. in Example 1-1. [Figure 2b] 1 is a high-resolution transmission electron microscopy (HRTEM) image of the amorphous TeOx:Se thin film of Example 1-1. [Figure 2c] 1 is an image showing a selected area electron diffraction pattern of the amorphous TeOx:Se thin film of Example 1-1. [Figure 2d] 1 is a high-resolution transmission electron microscopy (HRTEM) image of the amorphous TeOx:Se thin film of Example 1-1. [Figure 2e] 1 is an image showing the Fourier transform point pattern of TeOx:Se annealed at 225° C. in Example 1-1.

[0024] [Figure 3]1 is a graph showing the X-ray absorption near-edge structure (XANES) of tellurium oxide doped with 2 atom % of selenium (Se) according to Example 1-1. [Figure 4] 1 is a graph showing element distribution in an XPS (X-ray Photoelectron Spectroscope) depth profile of a TeOx:Se thin film doped with 2 atom % of selenium (Se) according to Example 1-1.

[0025] [Figure 5a] 1 is a high-resolution transmission electron microscopy (HRTEM) image of an amorphous p-channel TeOx-based semiconductor layer doped with selenium according to Example 1-1. [Figure 5b] 1 is a graph showing XPS (X-ray Photoelectron Spectroscopy) tellurium (Te) 3d spectra of selenium (Se)-doped tellurium oxides of Examples 1-1 and 1-2 and of non-Se-doped tellurium oxide of Comparative Example 1-1. [Figure 5c] 1 is a graph showing XPS (X-ray Photoelectron Spectroscopy) oxygen (O) 2p spectra of selenium (Se)-doped tellurium oxides of Examples 1-1 and 1-2 and of non-selenium (Se)-doped tellurium oxide of Comparative Example 1-1.

[0026] [Figure 6] 1 is a graph showing the transfer characteristics of selenium (Se)-doped TeOx:Se thin film transistors (TFTs) according to Examples 1-1 and 1-2 and a TeOx thin film transistor (TFT) not doped with selenium (Se) according to Comparative Example 1-1 depending on the selenium doping ratio.

[0027] [Figure 7a]1 is a graph showing transfer curves (channel post-annealing temperature: 225° C.) of TeOx:Se thin film transistors (TFTs) fabricated with channel thicknesses of 2, 4, 6, and 8 nm using a thermal evaporation process according to Example 1-1. [Figure 7b] 1 is a graph showing transfer curves of TeOx:Se thin film transistors (TFTs) fabricated with a channel thickness of 6 nm, in which different channel layers are deposited at the post-annealing temperatures using a thermal evaporation process according to Example 1-1. [Figure 8] 1 is a graph showing XPS (X-ray Photoelectron Spectroscopy) selenium (Se) 3p spectra of TeOx:Se doped under optimized conditions using a thermal evaporation process according to Example 1-1 and a pristine TeOx sample not doped with selenium (Se) according to Comparative Example 1-1.

[0028] [Figure 9a] 1-1 shows transfer curve graphs of a thin film transistor (TFT) using a TeOx:Se channel that is not subjected to different patterning using a thermal evaporation process according to Example 1-1, and a thin film transistor (TFT) using a TeOx:Se channel that is patterned by photolithography according to Example 1-1. [Figure 9b] FIG. 1 is a schematic diagram showing the photolithography used for TeOx:Se channel patterning using a thermal evaporation process according to Example 1-1.

[0029] [Figure 10a] 1 is a graph showing the transfer characteristics of TeOx and TeOx:Se TFTs formed using the thermal evaporation process according to Example 1-1 and Comparative Example 1-1. [Figure 10b] 1 is a graph showing an output curve of a TeOx:Se thin film transistor (TFT) using a thermal evaporation process according to Example 1-1. [Figure 10c]1 is a graph showing benchmarks of μh and Ion / Ioff of a reported amorphous p-channel thin film transistor (TFT) using a thermal evaporation process according to Example 1-1. [Figure 10d] 1 is a graph showing the transfer curve and VTH shift of a TeOx:Se thin film transistor (TFT) in PBS and NBS tests (±20V) with different durations using a thermal evaporation process according to Example 1-1. [Figure 10e] 1 is a graph showing the transfer curve and VTH shift of a TeOx:Se thin film transistor (TFT) in PBS and NBS tests (±20V) with different durations using a thermal evaporation process according to Example 1-1. [Figure 10f] 1 is a graph showing the transfer curve of one TeOx:Se thin film transistor (TFT) as a function of air exposure time (relative humidity: 10-30%) using a thermal evaporation process according to Example 1-1.

[0030] [Figure 11a] 80 TeOx:Se thin film transistor (TFT) devices were fabricated on a 4-inch wafer under optimized conditions (VDS=-0.1V) using the thermal evaporation process according to Example 1-1, and the graph shows the transfer curves of the 80 TeOx:Se thin film transistor (TFT) devices randomly measured. The accompanying picture is an optical image of the thin film transistor (TFT) array on the 4-inch SiO2 wafer. [Figure 11b] 1 is a graph showing statistical results of the field-effect hole mobility (μh) of a thin film transistor (TFT) extracted using a thermal evaporation process according to Example 1-1. [Figure 12a] 1 is a diagram of a complementary inverter based on n-channel In2O3 and p-channel TeOx:Se thin film transistors (TFTs) at VDD=20V using a thermal evaporation process according to Example 1-1, and a graph showing voltage transfer and noise margin (NM) extraction and gain voltage curves. [Figure 12b]1 is a diagram of a complementary inverter based on n-channel In2O3 and p-channel TeOx:Se thin film transistors (TFTs) at VDD=20V using a thermal evaporation process according to Example 1-1, and a graph showing voltage transfer and noise margin (NM) extraction and gain voltage curves. [Figure 12c] 1 is a diagram of a complementary inverter based on n-channel In2O3 and p-channel TeOx:Se thin film transistors (TFTs) at VDD=20V using a thermal evaporation process according to Example 1-1, and a graph showing voltage transfer and noise margin (NM) extraction and gain voltage curves. [Figure 12d] 1 is a photograph and a graph of input and output waveforms for complementary NAND and NOR logic gates at VDD=12V using a thermal evaporation process according to Example 1-1. [Figure 12e] 1 is a photograph and a graph of input and output waveforms for complementary NAND and NOR logic gates at VDD=12V using a thermal evaporation process according to Example 1-1. [Figure 12f] 1 is a photograph and a graph of input and output waveforms for complementary NAND and NOR logic gates at VDD=12V using a thermal evaporation process according to Example 1-1. BEST MODE FOR CARRYING OUT THE INVENTION

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily understand the present invention. However, the following description does not limit the present invention to specific embodiments, and when describing the present invention, if it is determined that a specific description of related known technology may obscure the gist of the present invention, the detailed description will be omitted. The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the present invention. The singular expressions include the plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprise" or "have" and the like are intended to specify the presence of features, numbers, steps, operations, components, or combinations thereof described in the specification, and should be understood not to preclude the presence or additional possibility of one or more other features, numbers, steps, operations, components, or combinations thereof.

[0032] Furthermore, terms including ordinal numbers, such as "first" and "second," may be used below to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. For example, a first component can be named a second component, and similarly, a second component can be named a first component, without departing from the scope of the present invention.

[0033] Furthermore, when a component is said to be "formed" or "laminated" on another component, it should be understood that the component may be formed or laminated in direct contact with the entire surface or one side of the surface of the other component, or that there may be another component interposed therebetween.

[0034] Hereinafter, a semiconductor containing amorphous tellurium oxide, a thin film transistor containing the same, and a method for manufacturing the same according to the present invention will be described in detail, but these are presented as examples and are not intended to limit the present invention, which is defined only by the scope of the claims set forth below.

[0035] According to one aspect of the present invention, there is provided a semiconductor comprising: chalcogen atoms including one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); and a tellurium complex including tellurium (Te) atoms and tellurium oxide. The chalcogen atoms may be doped into a tellurium complex. The tellurium complex may be represented by the following Chemical Formula 1: [Chemical formula 1] TeO x During the ceremony, x is 0.8≦x≦1.7, preferably 1.0≦x≦1.5, and more preferably 1.1≦x≦1.4. When x is less than 0.8, a large number of Te-Te bonds are contained, resulting in a high charge amount, which is undesirable for a transistor semiconductor layer, whereas when x exceeds 1.7, the charge amount is too low, which is undesirable.

[0036] The tellurium oxide may include tellurium monoxide (TeO) and tellurium dioxide (TeO2).

[0037] The semiconductor may be represented by the following Chemical Formula 2: [Chemical formula 2] TeO x :M During the ceremony, M is a sulfur atom (S) or a selenium atom (Se), x is 0.8≦x≦1.7, preferably 1.0≦x≦1.5, and more preferably 1.1≦x≦1.4. When x is less than 0.8, a large number of Te-Te bonds are contained, resulting in a high charge amount, which is undesirable for a transistor semiconductor layer, whereas when x exceeds 1.7, the charge amount is too low, which is undesirable. M is 0.5 to 5 atom %, preferably 1 to 4.5 atom %, and more preferably 1.5 to 4 atom % based on the total number of Te atoms, O atoms, and M atoms. Here, if M is less than 0.5 atom %, the hole mobility becomes low due to a very low doping amount, which is not preferable, and if M is more than 5 atom %, the current value becomes low, which is not preferable.

[0038] The semiconductor may also be amorphous. The tellurium semiconductor may also be p-type. The semiconductor may also be in an oxygen-deficient state, which means that the ratio of oxygen in the stoichiometric ratio of tellurium (Te):oxygen (O) is less than 1:2.

[0039] The tellurium atoms in the semiconductor are Te 4+ ionization state of Te 2+ Ionization states of Te and Te 0 wherein the semiconductor can include the Te 2+ and Te 0 The shallow acceptor state formed by the 5p orbital of can be used as a hole conduction channel.

[0040] The selenium atoms in the semiconductor are Se 2- where the semiconductor Se 2- However, the oxygen vacancies are passivated, allowing the partially empty 4p states to be used as hole conduction channels.

[0041] The semiconductor may also be for use in the semiconductor layer of a thin film transistor. The thickness of the semiconductor layer may be 2 nm or more, preferably 2 to 100 nm. If the thickness of the semiconductor layer is less than 2 nm, the charge amount is small, making it difficult to obtain sufficient thin film coverage, which is undesirable. If the thickness of the thin film is too thick, the charge amount is too high, making it undesirable for use as a semiconductor layer in a transistor.

[0042] According to another aspect of the present invention, there is provided a thin film transistor comprising: a gate electrode; an insulating layer located on the gate electrode; a semiconductor layer located on the insulating layer and including a semiconductor according to the present invention; and a source electrode and a drain electrode located spaced apart from each other on the semiconductor layer.

[0043] In addition, the gate electrode may include at least one material selected from the group consisting of n-doped silicon (n-doped Si), p-doped silicon (p-doped Si), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), magnesium (Mg), calcium (Ca), ytterbium (Yb), chromium (Cr), nickel (Ni), molybdenum (Mo), gold oxide, platinum oxide, silver oxide, palladium oxide, iron oxide, graphene, carbon nanotubes (CNT), silver nanowires (Ag NW), indium tin oxide, and poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS).

[0044] In addition, the source electrode and the drain electrode may each include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), aluminum (Al), tungsten (W), magnesium (Mg), calcium (Ca), ytterbium (Yb), chromium (Cr), nickel (Ni), molybdenum (Mo), gold oxide, platinum oxide, silver oxide, palladium oxide, iron oxide, graphene, carbon nanotubes (CNT), silver nanowires (Ag NW), indium tin oxide, and poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS).

[0045] The insulating layer may include one or more materials selected from the group consisting of silicon dioxide, glass, quartz, alumina, silicon carbide, magnesium oxide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polystyrene (PS), polyimide (PI), polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polyethylene (PE), silicon oxide (SiO2), germanium, polyvinyl alcohol (PVA), polymethyl methacrylate (PMMA), zirconium oxide (ZrO2), aluminum oxide (AlO2), and hafnium oxide (HfO2).

[0046] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor layer, comprising: (a) mixing a chalcogen containing one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se) with tellurium dioxide (TeO2) to prepare a mixture; and (b) depositing the mixture to form a semiconductor layer containing a semiconductor, wherein the semiconductor contains chalcogen atoms containing one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se), and a tellurium complex containing tellurium (Te) atoms and tellurium oxide.

[0047] Also, the deposition in step (b) can be performed by thermal evaporation, sputtering, vapor phase chemical vapor deposition (CVD), or solution coating.

[0048] Also, the deposition in step (b) can be performed by thermal evaporation or sputtering.

[0049] In addition, the temperature of the substrate on which the thermal evaporation is performed may be 15 to 35° C., preferably room temperature.

[0050] The sputtering may be performed at a substrate temperature of 15 to 35° C., preferably room temperature.

[0051] The thermal evaporation or sputtering may be performed in a range of 10-3 The thermal evaporation or sputtering may be performed under a vacuum pressure of 10 Torr or less. -3 If the reaction is carried out under a vacuum pressure exceeding Torr, impurities may be included, which is undesirable.

[0052] In addition, the thermal deposition rate may be 1 to 100 Å / s based on the semiconductor layer. If the thermal deposition rate is less than 1 Å / s, the thin film deposition process takes too long, which is undesirable, and if the thermal deposition rate is more than 100 Å / s, the surface roughness of the thin film increases, which is undesirable.

[0053] The molar ratio of the chalcogen to the tellurium dioxide (TeO2) in step (a) can be 0.01:99.99 to 50:50 (mol:mol), preferably 0.1:99.9 to 30:70. That is, the doping concentration is 0.01 mol to 50 mol, preferably 0.1 mol to 30 mol, and the doping concentration is the ratio of the number of moles of chalcogen (C) to the total number of moles of chalcogen (C) and tellurium dioxide (T) (C+T) (C / (C+T) × 100, mol / mol%). Here, a molar ratio of less than 0.01:99.99 is undesirable because the doping effect is ineffective, while a molar ratio of more than 50:50 is undesirable because phase separation may occur.

[0054] In addition, when performing the sputtering in step (b), the molar ratio of tellurium to oxygen in the semiconductor layer can be controlled by adjusting the partial pressures of oxygen and argon plasma. Furthermore, after step (b), the method may further include step (c) of annealing the semiconductor layer of step (b) at a temperature of 100 to 300° C. in an air or oxygen atmosphere.

[0055] After step (c), step (d) of annealing in air at a temperature of room temperature to 300°C may be further included.

[0056] According to another aspect of the present invention, there is provided a method for manufacturing a thin film transistor, comprising: (1) the steps of preparing a gate electrode / insulating layer stack including a gate electrode and an insulating layer located on the gate electrode; (2) the step of forming a semiconductor layer including a semiconductor on the insulating layer; and (3) the step of forming a source electrode and a drain electrode on the semiconductor layer, wherein the semiconductor includes chalcogen atoms including one or more selected from the group consisting of sulfur atoms (S) and selenium atoms (Se), and a tellurium complex including tellurium (Te) atoms and tellurium oxide. DETAILED DESCRIPTION OF THE INVENTION

[0057] [Example] The present invention will be described below with reference to preferred examples, but these examples are for illustrative purposes only and are not intended to limit the scope of the present invention.

[0058] Example 1: Fabrication of selenium-doped amorphous p-channel thin film transistors Example 1-1: Contains 2 atom % Se-doped tellurium oxide FIG. 1 is a schematic diagram illustrating a method for fabricating a semiconductor layer for use in a selenium-doped amorphous p-channel thin film transistor using a thermal evaporation process according to Example 1. To deposit tellurium oxide-based semiconductor films, commercially available TeO2 powder (purity ≥ 97%) was used as the evaporation source. XPS analysis revealed that after mixing a trace amount of chalcogen powder (S or Se) with TeO2 and depositing it, the atomic ratio of tellurium oxide on the surface of the semiconductor layer was Te:O:Se = 38:60:2. However, X-ray absorption results indicated that the Te:O ratio was 1:1.2, indicating a higher oxygen content on the surface. TeO x The base film was deposited using a conventional thermal evaporator. The substrate temperature was 25 °C and the vacuum pressure before evaporation was 10 -3 The pressure was below Torr. The distance between the substrate and the boat loaded with TeO2 was 2-50 cm. The deposition rate was 1 Å / s. x The film thickness (1–100 nm) was monitored during the deposition process. 。The deposited sample was first annealed at 200 °C for 30 min in a glove box filled with N2, and then further annealed at 225 °C for 30 min in air. Then, source / drain electrodes were deposited using Ni, respectively, to fabricate thin film transistors (TFTs).

[0059] Example 1-2: Contains tellurium oxide doped with 4 atom % Se A thin film transistor (TFT) was manufactured in the same manner as in Example 1-1, except that tellurium oxide doped with 4 atom % of selenium (Se) was manufactured instead of tellurium oxide doped with 2 atom % of selenium (Se).

[0060] Comparative Example 1: Contains tellurium oxide with no selenium doping Comparative Example 1-1: Pristine tellurium oxide A thin film transistor (TFT) was manufactured in the same manner as in Example 1-1, except that tellurium oxide not doped with selenium (Se) was manufactured instead of tellurium oxide doped with 2 atom % of selenium (Se).

[0061] [Test example] Test Example 1: Amorphous and crystalline thin films FIG. 2a shows the thermally evaporated and annealed TeO at 225° C. in Example 1-1. x 2b and 2d are graphs showing the XRD (X-ray diffractometer) spectrum results of the amorphous TeO :Se thin film of Example 1-1. x 2c is a high-resolution transmission electron microscope (HRTEM) image of the amorphous TeO 3 of Example 1-1. x 2e is an image showing the selected area electron diffraction pattern of the TeO :Se thin film annealed at 225°C in Example 1-1. x 2a to 2e are images showing the Fourier transform point patterns of TeO. x It can be seen that the crystals of the Se thin film are amorphous.

[0062] Test Example 2: XANES (X-ray absorption near-edge structure) FIG. 3 is a graph showing X-ray absorption near-edge structure (XANES) measurements of tellurium oxide doped with 2 atom % of selenium (Se) using a thermal evaporation process according to Example 1-1. Referring to FIG. 3, tellurium atoms (Te), tellurium oxide (TeO x ) and tellurium dioxide (TeO2), and the atomic composition of Te and O in the selenium (Se)-doped tellurium oxide according to Example 1-1 was TeO 1.2 It can be confirmed that the doping was 2 atom % Se.

[0063] Test Example 3: Elemental distribution in XPS depth profile FIG. 4 shows the TeO of the semiconductor layer according to Example 1-1. x 4 is a graph showing the element distribution of the XPS (X-ray Photoelectron Spectroscopy) depth profile of the Se thin film. Referring to FIG. 4, it can be seen that tellurium (Te), oxygen (O), selenium (Se), and silicon (Si) are distributed uniformly in the thin film.

[0064] Test Example 4: High-resolution TEM FIG. 5a shows the TeO of the semiconductor layer according to Example 1-1. x High-resolution transmission electron microscopy (HRTEM) images of the TeO:Se thin film. x The microstructure of the semiconductor film, which is a thin :Se film, shows a typical amorphous pattern with no crystalline regions.

[0065] Test Example 5: XPS spectrum 5b is a graph showing XPS (X-ray Photoelectron Spectroscopy) tellurium (Te) 3d spectra of the selenium (Se)-doped tellurium oxides of Examples 1-1 and 1-2 and the tellurium oxide of Comparative Example 1-1, and FIG. 5c is a graph showing XPS (X-ray Photoelectron Spectroscopy) oxygen (O) 2p spectra of the selenium (Se)-doped tellurium oxides of Examples 1-1 and 1-2 and the tellurium oxide of Comparative Example 1-1 that is not doped with selenium (Se). x (4.9%), TeO x (5.2%) and TeO x (5.1%) x is 0 <x<2である。

[0066] Referring to FIGS. 5b and 5c, tellurium atoms (Te), tellurium oxide (TeO x In the tellurium oxides according to Examples 1-1, 1-2, and Comparative Example 1-1, the atomic compositions of tellurium (Te) and oxygen (O) were TeO, 1.58 It can be seen that the atomic ratios on the surface of the tellurium oxide thin films doped with selenium (Se) according to Examples 1-1 and 1-2 were analyzed to be Te:O:Se = 38:60:2 and 38:60:4, respectively. In addition, in Example 1-1, as in Test Example 2, TeO 1.2 :Se 0.052 Here, it can be seen that the oxygen composition in the XPS results for Test Example 5 is greater than the oxygen composition in the XANES results for Test Example 2. This result is believed to be due to the fact that XPS analyzes the surface portion of the sample, while XANES analyzes the interior of the bulk of the sample, and therefore the surface of the sample contains more oxygen than the bulk due to oxidation. However, it can be said that the bulk components have a greater impact on device performance.

[0067] Test Example 6: TeO x Transfer characteristics of :Se TFT FIG. 6 shows the selenium (Se)-doped TeO according to Examples 1-1 and 1-2. x : Se thin film transistor (TFT), and TeO not doped with selenium (Se) according to Comparative Example 1-1 x 1 is a graph showing the transfer characteristics of a :Se thin film transistor (TFT) depending on the selenium doping ratio. Referring to FIG. 6, it can be seen that the highest hole mobility can be obtained when selenium (Se) is doped at 2 atom %, and the amount of charge decreases when the doping concentration exceeds this.

[0068] Test Example 7: TeO x :Se TFT transfer curve FIG. 7a shows TeO films fabricated with channel thicknesses of 2, 4, 6, and 8 nm using the thermal evaporation process according to Example 1-1, respectively. x 7a and 7b are graphs showing the transfer curves of TeO thin film transistors (TFTs) (channel post-annealing temperature: 225° C.), and FIG. 7b shows the transfer curves of TeO thin film transistors (TFTs) with a channel thickness of 6 nm deposited at the post-annealing temperatures of different channel layers using the thermal evaporation process according to Example 1-1. x 1 is a graph showing the transfer curve of a :Se thin film transistor (TFT). 7a and 7b, it can be seen that the charge amount increases as the thickness increases, and the optimum process temperature is 225°C.

[0069] Test Example 8: XPS Se 3p spectrum FIG. 8 shows the TeO x : Se and pristine TeO according to Comparative Example 1-1 x 8 is a graph showing the X-ray photoelectron spectroscopy (XPS) selenium (Se) 3p spectrum of the sample. x Se in the thin film - It can be confirmed that the anion phase of

[0070] Test Example 9: TeOx :Se channel TFT FIG. 9a shows different unpatterned TeO films prepared using a thermal evaporation process according to Example 1-1. x : A thin film transistor (TFT) using a Se channel and TeO to which patterning by photolithography according to Example 1-1 was applied. x 9b is a graph showing the transfer curve of a thin film transistor (TFT) using a TeO:Se channel using a thermal evaporation process according to Example 1-1. x 9a and 9b are schematic diagrams showing photolithography used for Se channel patterning. It can be seen that there is no change in the performance of the thin film transistor (TFT) after the photolithography patterning process.

[0071] Test Example 10: Amorphous p-channel TeO x Electrical characteristics of :Se TFTs FIG. 10a shows the TeO films prepared by the thermal evaporation process according to Example 1-1 and Comparative Example 1-1. x :Se and TeO x 10b is a graph showing the transfer characteristics of a TeO TFT using a thermal evaporation process according to Example 1-1. x 10c is a graph showing the benchmarks of μh and Ion / Ioff of amorphous p-channel thin film transistors (TFTs) reported using the thermal evaporation process according to Example 1-1; and FIGS. 10d and 10e are graphs showing the results of PBS and NBS tests (±20V) for different durations using the thermal evaporation process according to Example 1-1. x FIG. 10f is a graph showing the transfer curve and VTH shift of a TeO:Se thin film transistor (TFT) as a function of air exposure time (relative humidity: 10-30%) using the thermal evaporation process according to Example 1-1. x 10a-10f are graphs showing transfer curves of a :Se thin film transistor (TFT). Referring to Figures 10a-10f, the geometry of the thin film transistor (TFT) used in this study can be seen.

[0072] Test Example 11: TFT field-effect hole mobility (μh) FIG. 11a shows the thermal evaporation process of Example 1-1 under the optimized conditions (VDS=−0.1 V) for 80 TeO x :Se thin film transistor (TFT) devices were fabricated and 80 TeO x 11a and 11b are graphs showing the transfer curves of a :Se thin film transistor (TFT) device, and the accompanying picture is an optical image of a thin film transistor (TFT) array on a 4-inch SiO2 wafer. FIG. 11b is a graph showing the statistical results of the extracted thin film transistor (TFT) field-effect hole mobility (μh) using the thermal evaporation process according to Example 1-1. Referring to FIGS. 11a and 11b, the average mobility was 20 cm 2 / VS, on / off is 10 7 It can be seen that...

[0073] Test Example 12: TFT-Based Oxide Integrated Circuit 12a, 12b, and 12c show the results of the thermal evaporation process of Example 1-1 for n-channel In2O3 and p-channel TeO x 12a to 12f are diagrams of a complementary inverter based on a TeO thin film transistor (TFT), and graphs showing voltage transfer and noise margin (NM) extraction and gain voltage curves. Also, FIGS. 12d, 12e, and 12f are photographs and graphs of input and output waveforms for complementary NAND and NOR logic gates at VDD=12V using the thermal evaporation process according to Example 1-1. Referring to FIGS. 12a to 12f, TeO was deposited on the gate via photolithographic patterning. x It can be confirmed that even if the Se portion is successfully patterned, the device operates well without any change in characteristics.

[0074] The scope of the present invention is indicated by the claims set forth below rather than by the above detailed description, and all changes and modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included within the scope of the present invention.

Claims

1. chalcogen atoms including at least one selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); a tellurium complex comprising tellurium (Te) atoms and tellurium oxide.

2. 2. The semiconductor of claim 1, wherein the chalcogen atoms are doped into a tellurium complex.

3. 2. The semiconductor of claim 1, wherein the tellurium complex is represented by the following formula 1: [Chemical formula 1] Tet ｘ (In the formula, x is 0.8≦x≦1.7.)

4. The tellurium oxide is tellurium monoxide (TeO) and tellurium dioxide (TeO ２ 4. The semiconductor of claim 3, comprising:

5. The semiconductor of claim 1 , wherein the semiconductor is represented by the following formula 2: [Chemical formula 2] TeO ｘ :M (wherein M is a sulfur atom (S) or a selenium atom (Se), x is 0.8≦x≦1.7, M is 0.5 to 5 atom % of the total number of Te atoms, O atoms, and M atoms.

6. 2. The semiconductor of claim 1, wherein the semiconductor is amorphous.

7. 2. The semiconductor of claim 1, wherein the tellurium semiconductor is p-type.

8. 10. The semiconductor of claim 1, wherein the semiconductor is oxygen deficient.

9. The tellurium atoms in the semiconductor are Te ４＋ ionization state of Te ２＋ and Te ０ 9. The semiconductor of claim 8, wherein the non-ionized state is:

10. The selenium atoms of the semiconductor are Se ２－ 2. The semiconductor of claim 1, comprising an ionization state of

11. 10. The semiconductor of claim 1, wherein the semiconductor is for use as a semiconductor layer in a thin film transistor.

12. The semiconductor according to claim 11, wherein the thickness of the semiconductor layer is 2 to 10 nm.

13. (a) A chalcogen containing at least one selected from the group consisting of sulfur atom (S) and selenium atom (Se) and tellurium dioxide (TeO ２ ) to produce a mixture; (b) depositing the mixture to form a semiconductor layer comprising a semiconductor; The semiconductor is chalcogen atoms including at least one selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); a tellurium complex containing tellurium (Te) atoms and tellurium oxide.

14. 14. The method for producing a semiconductor layer according to claim 13, wherein the deposition in step (b) is performed by thermal evaporation, sputtering, vapor phase chemical vapor deposition (CVD), or solution coating.

15. 15. The method for manufacturing a semiconductor layer according to claim 14, wherein the deposition in step (b) is performed by thermal evaporation or sputtering.

16. 16. The method of claim 15, wherein the thermal evaporation is performed at a rate of 1 to 100 Å / s based on the semiconductor layer.

17. The chalcogen and the tellurium dioxide (TeO ２ 14. The method for producing a semiconductor layer according to claim 13, wherein the molar ratio of the compound (II) and the compound (II) is 0.01:99.99 to 50:50 (mol:mol).

18. 15. The method for manufacturing a semiconductor layer according to claim 14, wherein the molar ratio of tellurium to oxygen in the semiconductor layer is controlled by adjusting the partial pressures of oxygen and argon plasma during the sputtering in step (b).

19. After step (b), 14. The method for manufacturing a semiconductor layer according to claim 13, further comprising a step (c) of annealing the semiconductor layer of step (b) at a temperature of 100 to 300° C. in an air or oxygen atmosphere.

20. (1) providing a gate electrode / insulating layer stack including a gate electrode and an insulating layer overlying the gate electrode; (2) forming a semiconductor layer containing a semiconductor on the insulating layer; (3) forming a source electrode and a drain electrode on the semiconductor layer; The semiconductor is chalcogen atoms including at least one selected from the group consisting of sulfur atoms (S) and selenium atoms (Se); a tellurium complex containing tellurium (Te) atoms and tellurium oxide.

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