Heteroepitaxial wafers for depositing gallium nitride

Abstract

A heteroepitaxial wafer comprising, in the following order: (1) a substrate made of silicon having a thickness, a diameter, a crystal orientation, a resistivity, a front surface, and a back surface; (2) a nucleation layer comprising AlN and 3C-SiC; (3) a first boron nitride layer having a first boron nitride layer thickness; and (4) a nitride layer having a nitride layer thickness comprising one element from the list of elements: aluminum, gallium, indium, and thallium.

Description

[Technical Field]

[0001] The present invention relates to heteroepitaxial wafers that can be used to deposit gallium nitride thereon. [Background technology]

[0002] Background technology Gallium nitride (GaN) offers fundamental advantages over silicon. In particular, its higher breakdown voltage makes it very attractive for power semiconductor devices, with significant specific dynamic on-state resistance and lower capacitance compared to silicon MOSFETs, making GaN HEMTs suitable for high-speed switching. This not only results in power savings and reduced total system cost, but also enables higher operating frequencies, improving power density and overall system efficiency.

[0003] Group III nitride semiconductors, such as gallium nitride (GaN), are expected to have a wide range of applications, as they can be used in fields such as blue light-emitting diodes (LEDs), high-density optical storage, high-temperature, high-power, and high-frequency electronic devices, and ultraviolet detectors.

[0004] However, obtaining high-quality GaN films is difficult due to the lack of uniform substrates. Most device-grade GaN films fabricated to date are grown on sapphire substrates. Sapphire substrates are hard, non-conductive, and expensive, making mass production difficult. To overcome these drawbacks, researchers have attempted to grow high-quality GaN on silicon substrates, which are inexpensive, thermally and electrically conductive, large in size, easily melted, and easy to integrate with photonics and electronics.

[0005] However, the lattice mismatch between silicon (Si) and gallium nitride (GaN) can be as high as 20%, and the thermal mismatch can be as high as 56%, making epitaxial growth of GaN on silicon substrates highly prone to cracking.

[0006] Chinese Patent Application No. 105861987 discloses a method for growing a gallium nitride layer on a hexagonal boron nitride transition layer. Silicon can be used as the substrate.

[0007] Japanese Patent Application Publication No. 2021020819 discloses a method for growing epitaxial 3C-SiC on a crystal substrate. Japanese Patent Application Publication No. 2000178740 discloses a further method for growing epitaxial 3C-SiC on a silicon substrate.

[0008] Chinese Patent Application No. 1825539 discloses a method for growing a crack-free group III nitride layer on a silicon substrate.

[0009] Chinese Patent Application No. 106684139 discloses a gallium nitride structure based on a Si substrate, including a first AlN buffer layer, a layer slip layer, a second AlN buffer layer, an Al x Ga 1-x N buffer layer, and a GaN epitaxial layer, wherein the Al x Ga 1-x N buffer layer has an Al content x within the range of 0 < x < 1.

Summary of the Invention

Problems to be Solved by the Invention

[0010] The above patent applications aim to reduce the influence of lattice mismatch between silicon and gallium nitride (or other group III nitrides).

[0011] The object of the present invention is to avoid the substrate itself having an adverse effect on the function of the group III nitride device constructed thereon.

Means for Solving the Problems

[0012] This solution is achieved by the features of the independent claims of the present invention and its dependent claims. DETAILED DESCRIPTION OF THE INVENTION

[0013] Detailed Description With several technical measures in place known in the prior art, the inventors have realized that the substrate itself still adversely affects the function of III-nitride devices to some extent.

[0014] A primary motivation is therefore to provide improved heteroepitaxial wafers for this purpose, in particular heteroepitaxial wafers that are substantially crack-free and suitable for fabricating high breakdown voltage nitride-based devices.

[0015] A given problem is solved by a heteroepitaxial wafer comprising, in a given order:

[0016] (1) A silicon substrate having a front surface, a back surface, a thickness, a diameter, and a resistivity (2) A nucleation layer containing aluminum nitride (AlN) and 3C-SiC (3) a first boron nitride layer having a thickness of the first boron nitride layer; (4) a nitride layer having a nitride layer thickness containing one element from the list of elements aluminum, gallium, indium, and thallium; The crystal orientation of the silicon substrate is preferably 1-1-1. Preferably, the heteroepitaxial wafer has a diameter of more than 125 mm, preferably more than 200 mm and less than 300 mm.

[0017] The crystals preferably used for the production of the substrate are obtained by the float-zone process. Such a process is described, for example, in EP 2142686. The dopant of the crystal is preferably arsenic, red phosphor, or boron. The most preferred resistivity is 0.5 mOhm cm to 100 mOhm cm.

[0018] More preferably, the crystals used were produced by the Czochralski method with a nominal diameter of more than 200 mm, preferably 300 mm. Furthermore, the interstitial oxygen concentration of such crystals is less than 2×10 17 At / cm 3 (ASTM F121). The dopant of the crystal is preferably arsenic, red phosphor, or boron. The most preferred resistivity of the crystal is 1 mOhm·cm or more and 100 mOhm·cm or less.

[0019] The crystals resulting from the crystal growth process are then preferably cut into crystal pieces, which are then cut into wafers, cleaned and polished.

[0020] The cleaning process removes contamination and particles from the wafer surface prior to epitaxial deposition. It is preferable to use a standard SC1 clean followed by an SC2 clean.

[0021] Preferably, a layer of boron nitride is deposited on the front side of the substrate. The deposition process can preferably be carried out by vapor deposition, preferably using metal organic chemical vapor deposition (MOCVD). A suitable process is described in Chinese Patent Application No. 1825539. The thickness of the boron nitride layer is preferably between 1 μm and 10 μm.

[0022] Preferably, a nitride layer having a thickness containing one element from the list of elements aluminum (Al), gallium (Ga), indium (In), and thallium (Tl) is disposed on the boron nitride layer. More preferably, the layer contains gallium. The nitride layer preferably has a thickness of 1 μm to 10 μm.

[0023] The combined thickness of the first boron nitride layer and the nitride layer (the sum of both thicknesses) is 2 μm or more and 12 μm or less.

[0024] Preferably, a second boron nitride layer having a thickness of the second boron nitride layer is disposed on the back surface of the substrate, more preferably the thickness of the layer is 50 nm or more and 10 μm or less.

[0025] The inventors have recognized that it is particularly advantageous to place an additional nucleation layer on the front surface of the substrate before the first boron nitride layer is added. The nucleation layer preferably comprises aluminum nitride and 3C-SiC and has a thickness of 50 nm to 500 nm. This nucleation layer has the effect of reducing crystal defects caused by the lattice mismatch between Si and BN. Furthermore, the breakdown voltage of III-N devices fabricated on this additional layer is increased.

[0026] The inventors further recognized that by using a combination of a nucleation layer and a boron nitride layer, the crystalline defect quality of the nitride layer is significantly improved.

Claims

1. In the following order: (1) a substrate made of silicon having a thickness, a diameter, a crystal orientation, a resistivity, a front surface, and a back surface; (2) a nucleation layer comprising aluminum nitride (AlN) and 3C—SiC; (3) a first boron nitride layer having a first boron nitride layer thickness; (4) a nitride layer comprising one element from the list of elements aluminum, gallium, indium, and thallium, and having a nitride layer thickness.

2. The heteroepitaxial wafer of claim 1 , wherein the nitride layer comprises gallium nitride.

3. 3. The heteroepitaxial wafer according to claim 1, wherein the diameter is greater than 125 mm and equal to or less than 300 mm.

4. 4. The heteroepitaxial wafer according to claim 1, wherein the diameter is greater than 200 mm and equal to or less than 300 mm.

5. 5. The heteroepitaxial wafer according to claim 1, wherein the resistivity of the substrate is 0.5 mOhm·cm or more and 100 mOhm·cm or less.

6. 6. The heteroepitaxial wafer according to claim 1, wherein the crystal orientation of the substrate is [1-1-1].

7. 7. The heteroepitaxial wafer of claim 1, further comprising a first nucleation layer having a first nucleation layer thickness disposed between the substrate and the boron nitride layer.

8. 8. The heteroepitaxial wafer of claim 7, wherein the first nucleation layer comprises epitaxial AlN and epitaxial SiC.

9. 9. The heteroepitaxial wafer according to claim 1, wherein the first boron nitride layer has a thickness of 1 μm or more and 10 μm or less.

10. 10. The heteroepitaxial wafer according to claim 1, wherein the first boron nitride layer has a thickness of 50 nm or more and 10 μm or less.

11. 11. The heteroepitaxial wafer according to claim 1, wherein the nitride layer has a thickness of 1 μm or more and 10 μm or less.

12. 12. The heteroepitaxial wafer according to claim 1, wherein the combined thickness of said first boron nitride layer and said nitride layer is 2 μm or more and 12 μm or less.

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