Monolithic three-dimensional (3D) complementary field-effect transistor (CFET) circuits and fabrication methods

Abstract

A monolithic 3D complementary field effect transistor (FET) (CFET) circuit includes a first CFET structure (102A) and a second CFET structure (102B) in a logic circuit within a device layer (108). A first interconnect layer (112) disposed on the device layer provides first and second input contacts (IN-1, IN-2) and output contacts (120-1, 120-6) of the logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs within the monolithic 3D CFET circuit can be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) can be formed within the device layer to interconnect the FETs externally and to each other. The FETs can be formed as bulk or SOI transistors.

Description

[Technical Field]

[0001] Priority application This application claims priority to U.S. Patent Application No. 17 / 818,048, filed August 8, 2022, entitled "MONOLITHIC THREE-DIMENSIONAL (3D) COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) CIRCUITS AND METHOD OF MANUFACTURE," which is incorporated herein by reference in its entirety.

[0002] I. Areas of Disclosure The technology of this disclosure relates generally to complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) (CFETs), and particularly to monolithic three-dimensional (3D) CFET circuits. [Background technology]

[0003] II. Background Complementary metal-oxide semiconductor (CMOS) technology is commonly employed in digital logic within integrated circuits (ICs) due to its power efficiency, performance, and noise immunity compared to circuits containing only N-type (NMOS) or P-type MOS (PMOS) technology. A CMOS logic circuit includes at least one PMOS transistor and at least one NMOS transistor. Therefore, a CMOS field-effect transistor (FET) (CFET) circuit includes at least one PMOS FET (PFET) and at least one NMOS FET (NFET). An IC may include logic circuits made of millions of interconnected CFETs. Therefore, stacking FETs in a three-dimensional (3D) structure can significantly reduce the area of an IC occupied by CFET circuits. Wafer-to-wafer layer transfer techniques have been employed to fabricate ICs in which one type of FET (e.g., N-type or P-type) is on top of (e.g., above) the other type (e.g., P-type or N-type) of FET. However, in addition to the process issues associated with the transfer method, existing methods consume a significant amount of area to interconnect the FETs in the CFET logic circuitry. Summary of the Invention [Means for solving the problem]

[0004] Embodiments disclosed in the Detailed Description include a monolithic three-dimensional (3D) complementary field-effect transistor (FET) (CFET) circuit. Related methods of fabricating the monolithic 3D CFET circuit are also disclosed. The 3D CFET circuit, configured as a logic circuit, includes a first monolithic CFET structure and a second monolithic CFET structure in a device layer of an integrated circuit (IC). Each monolithic CFET structure includes an upper FET of a first type (e.g., P-type or N-type) on a lower FET of a second type (e.g., N-type or P-type). The CFET circuit also includes an interconnect layer disposed on the device layer to provide contacts for external circuitry to couple to the input and output(s) of the logic circuit. Specifically, a first input contact is coupled to the gate of the FET in the first CFET structure, and a second input contact is coupled to the gate of the FET in the second CFET structure. An output contact is coupled to the output of the CFET circuit. In some embodiments, the CFET circuit includes vertical access interconnects (vias) in the device layers to interconnect the FETs to each other and to the contact layers. In some embodiments, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NOR circuit. In some embodiments, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input Not-AND (NAND) circuit.

[0005] In an exemplary embodiment, a monolithic complementary field effect transistor (CFET) logic circuit is disclosed, comprising: a device layer; and a first interconnect layer disposed on the device layer. The device layer includes a first CFET structure having a first FET of a first type on a second FET of a second type and a second CFET structure having a third FET of the first type on a fourth FET of the second type. The first interconnect layer includes a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET, a second input contact configured to couple a second input signal to a gate of the third FET and a gate of the fourth FET, and an output contact configured to generate an output signal based on a logical operation of the first input signal and the second input signal.

[0006] In another exemplary embodiment, an integrated circuit (IC) is disclosed that includes a monolithic complementary field effect transistor (CFET) logic circuit. The monolithic 3D CFET circuit includes a monolithic complementary field effect transistor (CFET) logic circuit including a device layer and a first interconnect layer disposed on the device layer. The device layer includes a first CFET structure having a first FET of a first type above a second FET of a second type, and a second CFET structure having a third FET of the first type above a fourth FET of the second type. The first interconnect layer includes a first input contact configured to couple a first input. The first interconnect layer includes a first input contact configured to couple a first input signal to the gate of the first FET and the gate of the second FET, a second input contact configured to couple a second input signal to the gate of the third FET and the gate of the fourth FET, and an output contact configured to generate an output signal based on a logical operation of the first input signal and the second input signal.

[0007] In another exemplary aspect, a method for forming a monolithic complementary field effect transistor (CFET) logic circuit is disclosed. The method includes forming a device layer including forming a first CFET structure having a first FET of a first type over a second FET of a second type and forming a second CFET structure having a third FET of the first type over a fourth FET of the second type. The method includes forming a first interconnect layer disposed on the device layer, the first interconnect layer including a first input contact configured to couple a first input signal to a gate of the first FET and a gate of the second FET, a second input contact configured to couple a second input signal to the gate of the third FET and a gate of the fourth FET, and an output contact configured to generate an output signal based on a logical operation of the first input signal and the second input signal. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional side view of a monolithic 3D complementary field effect transistor (FET) (CFET) circuit including interconnected CFET structures on a semiconductor substrate in a first configuration of a logic circuit. [Figure 2] 2 is a flowchart of a method for fabricating the monolithic 3D CFET circuit of FIG. 1. [Figure 3] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a second configuration of a NAND circuit. [Figure 4] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a third configuration of a NAND circuit. [Figure 5] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a fourth configuration of a NAND circuit. [Figure 6] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulator layer in a fifth configuration of a NAND circuit. [Figure 7] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulator layer in a sixth configuration of a NAND circuit. [Figure 8] 1 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a first configuration of a NOR circuit. FIG. [Figure 9] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a second configuration of a NOR circuit. [Figure 10] FIG. 10 is a cross-sectional side view of a monolithic CFET circuit including a CFET structure formed on a semiconductor substrate in a third configuration of a NOR circuit. [Figure 11] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on a semiconductor substrate in a fourth configuration of a NOR circuit. [Figure 12] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulator layer in a fifth configuration of a NOR circuit. [Figure 13] FIG. 10 is a cross-sectional side view of a monolithic 3D CFET circuit including a CFET structure formed on an insulator layer in a sixth configuration of a NOR circuit. [Figure 14] FIG. 14 is a block diagram of an example wireless communication device that may include the monolithic 3D CFET circuit of any of FIGS. 1 and 3-13. [Figure 15] FIG. 14 is a block diagram of an exemplary processor-based system that may include the monolithic 3D CFET circuits of any of FIGS. 1 and 3-13. DETAILED DESCRIPTION OF THE INVENTION

[0009] Several exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0010] Embodiments disclosed in the Detailed Description include a monolithic three-dimensional (3D) complementary field-effect transistor (FET) (CFET) circuit. Related methods of fabricating the monolithic 3D CFET circuit are also disclosed. The 3D CFET circuit, configured as a logic circuit, includes a first monolithic CFET structure and a second monolithic CFET structure in a device layer of an integrated circuit (IC). Each monolithic CFET structure includes an upper FET of a first type (e.g., P-type or N-type) on a lower FET of a second type (e.g., N-type or P-type). The CFET circuit also includes an interconnect layer disposed on the device layer to provide contacts for external circuitry to couple to the input and output(s) of the logic circuit. Specifically, a first input contact is coupled to the gate of the FET in the first CFET structure, and a second input contact is coupled to the gate of the FET in the second CFET structure. An output contact is coupled to the output of the CFET circuit. In some embodiments, the CFET circuit includes vertical access interconnects (vias) in the device layers to interconnect the FETs to each other and to the contact layers. In some embodiments, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NOR circuit. In some embodiments, the first monolithic CFET structure and the second monolithic CFET structure are interconnected to form a two-input NAND circuit.

[0011] CMOS circuits offer improved performance, reduced power consumption, and better noise immunity than circuits with only one type of FET. CMOS circuits also offer a good reference voltage source (e.g., ground or V SS) and a good supply voltage source (e.g., 1.8 volts or V DD and at least one P-type FET providing a current source. As used herein, the term "first type" may refer to either N-type or P-type, and the term "second type" may refer to the other of N-type or P-type. N-type FETs and P-type FETs may also be referred to as N-channel FETs and P-channel FETs, or NFETs and PFETs, respectively. In an N-type device, the semiconductor source and drain are doped with a pentavalent dopant, and a supply voltage applied to the gate in the channel region creates an N-channel in which electrons are the majority carriers. In a P-type or P-channel device, the semiconductor source and drain are doped with a trivalent dopant, and a reference voltage (e.g., ground) applied to the gate creates a P-channel in the channel region in which holes are the majority carriers.

[0012] The examples shown in Figures 1-12 are gate-all-around (GAA) FETs, however, CFET structures with FETs using other channel structures are also within the scope of this disclosure.

[0013] 1 is a cross-sectional side view of a monolithic 3D CFET circuit 100 including CFET structures 102A and 102B, each including an upper FET 104A, 104B disposed above (e.g., above in the Y-axis direction) a lower FET 106A, 106B, respectively. CFET structures 102A, 102B are monolithic CFET structures within a device layer 108, within which CFET structures 102A, 102B are disposed. A thickness T of dielectric material 110 is provided. 110can be considered to be the thickness of the device layer 108. A monolithic CFET structure, as the term is used herein, refers to a structure that is formed (e.g., constructed) in place on a substrate in a process flow, rather than being composed of separately fabricated parts that are bonded, stacked, or otherwise placed on top of each other.

[0014] As described further below, the upper FETs 104A, 104B and the lower FETs 106A, 106B are interconnected to each other and to external circuitry (not shown) through an interconnect layer 112 disposed on the device layer 108. The upper FETs 104A, 104B and the lower FETs 106A, 106B are coupled to external circuitry and to each other by vertical interconnect accesses (vias) 114 to the interconnect layer 112. The vias 114 will be individually discussed as vias 114(1)-114(12), but will be collectively referred to herein as vias 114. As shown below in each of the configurations of Figures 1-12, vias such as via 114 can be disposed in the dielectric material 110 in the device layer 108 to indirectly connect the upper FETs 104A, 104B and the lower FETs 106A, 106B to the interconnect layer 112, and can also extend through the insulating layer 116 and the semiconductor substrate 118 supporting the CFET structures 102A, 102B of Figure 1.

[0015] For example, insulating layer 116 may be an oxide material used for shallow trench isolation (STI). Semiconductor substrate 118 may be silicon, a silicon alloy, or a different semiconductor material than that forming upper FETs 104A, 104B and lower FETs 106A, 106B.

[0016] The interconnect layer 112 includes contacts 120(1)-120(6), which are conductive (e.g., metal) contacts disposed in an insulating or dielectric material 122 on the device layer 108. The routing configuration disclosed herein, such as in the monolithic 3D CFET circuit 100, allows CMOS logic circuits to be integrated in a compact area and provides external access to the upper FETs 104A, 104B and the lower FETs 106A, 106B.

[0017] Each CFET structure 102A and CFET structure 102B includes a P-type FET and an N-type FET for their complementary operating characteristics. The upper FETs 104A, 104B are FETs of a first type, meaning that the upper FET 104A of the first CFET structure 102A and the upper FET 104B of the second CFET structure 102B are both formed of semiconductor material having the same doping (e.g., P-type or N-type). The lower FETs 106A, 106B are both formed of semiconductor material having a doping of a second type (e.g., N-type or P-type) opposite to the first type. In other words, if the upper FETs 104A, 104B are PFETs, then the lower FETs 106A, 106B are NFETs, and vice versa.

[0018] For example, gate 124A of upper FET 104A in first CFET structure 102A is coupled to gate 126A of lower FET 106A. Similarly, gate 124B of upper FET 104B in second CFET structure 102B is coupled to gate 126B of lower FET 106B. In this configuration, a first input signal IN-1 received on contact 120(3) is coupled to both gate 124A and gate 126A. The first input signal IN-1 is coupled to a supply voltage V that turns on one of upper FET 104A and lower FET 106A, which is an N-type FET, and turns off the other of upper FET 104A and lower FET 106A, which is a P-type FET. DDThe first input signal IN-1 may alternatively provide a reference voltage V that turns on one of the upper FET 104A and the lower FET 106A, which may be a P-type FET, and turns off the other (e.g., an N-type FET). SS A second input signal IN-2 received on contact 120(5) is coupled to gate 124B and gate 126B and provides a supply voltage V for controlling the operation (e.g., turning on and off) of upper FET 104B and lower FET 106B. DD or reference voltage V SS can be provided.

[0019] As described above, first input signal IN-1 and second input signal IN-2 can be received from an external circuit at contact 120(3) and contact 120(5), respectively. Interconnect layer 112 also includes output contact 120(1) and output contact 120(6), which are coupled to each other by external interconnect 128. Monolithic 3D CFET circuit 100 can generate an output signal OUT on one of output contact 120(1) and output contact 120(6) and provide it to an external circuit (not shown) by external interconnect 128. The state of output signal OUT is based on a logical operation of input signals IN-1 and IN-2. Upper FETs 104A, 104B and lower FETs 106A, 106B are interconnected as a digital logic circuit to perform a binary NOT AND (NAND) operation. In the binary operation, a first voltage (e.g., V SS ) may correspond to "0" and a second voltage (e.g., V DD In a NAND operation, the output signal OUT is generated when both the first input signal IN-1 and the second input signal IN-2 are at a voltage corresponding to "1" (for example, V DD ) only in response to a voltage corresponding to a "0" state (e.g., V SS ) otherwise, the output signal OUT is in a "1" state. As is understood in the art, in some embodiments, the second voltage V DDmay correspond to "0", and the first voltage V SS may correspond to a "1", which will also invert the voltage of the output signal OUT in response to the "1" indicated by both the input signal IN-1 and the input signal IN-2.

[0020] Upper FET 104A may be a different type of FET than lower FET 106A, yet may be similar in structure. Furthermore, upper FET 104B and lower FET 106B are similar in structure to upper FET 104A and lower FET 106A. Therefore, the detailed description of upper FET 104A provided below also describes upper FET 104B, lower FET 106A, and lower FET 106B, and further details of such FETs will not be provided unless necessary.

[0021] The upper FET 104A in this embodiment is a gate-all-around (GAA) FET that includes semiconductor slabs 132(1), 132(2), and 132(3), collectively referred to as slab 132, that form a channel region 134A. Slab 132 in a P-type device may include, for example, silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or a combination thereof. For example, slab 132 in an N-type device may include Si, GaAs, or a combination thereof. As described above, CFET structures 102A and 102B are disposed on insulating layer 116 and semiconductor substrate 118. CFETs 104A, 104B, 106A, and 106B are formed on semiconductor substrate 118 as bulk transistors.

[0022] On a first side SA1 of the first CFET structure 102A, a first source / drain SD1-UA1 is coupled to a first end of the slab 132, and a second source / drain SD1-UA2 is coupled to a second end of the slab 132 on a second side SA2 of the first CFET structure 102A. The first source / drain SD1-UA1 and the second source / drain SD1-UA2 may be epitaxially grown on the semiconductor material of the slab 132. The direction of current flow through the channel region 134A is along the X-axis of FIG. 1 and can be from left to right or right to left, depending on the voltage applied between the source / drains SD1-UA1 and SD1-UA2, which determines which of the source / drains SD1-UA1 and SD1-UA2 functions as a source and which functions as a drain.

[0023] The source / drain SD1-UB1 is on a first side SB1 of the second CFET structure 102B, and the source / drain SD1-UB2 is on a second side SB2 of the second CFET structure 102B. The source / drain SD1-UB1 and the source / drain SD1-UB2 are coupled to opposite ends of the channel region 134B in the upper FET 104B. Note that the first side SA1 of the CFET structure 102A and the first side SB1 of the second CFET structure 102B are between the CFET structures 102A and 102B. The second sides SA2 and SB2 are outside of (e.g., not between) the CFET structures 102A and 102B.

[0024] In the lower FET 106A, the source / drain SD1-LA1 is on a first side SA1 and the source / drain SD1-LA2 is on a second side SA2 of the second CFET structure 102B. In the lower FET 106B, the source / drain SD1-LB1 is on a first side SB1 and the source / drain SD1-LB2 is on a second side SB2.

[0025] Vias 114, coupled to CFET structures 102A, 102B, provide monolithic 3D CFET circuit 100 with access to external circuitry and reduce the total area occupied by monolithic 3D CFET circuit 100. Vias 114 extend in the vertical Y-axis direction in FIG. 1 . Vias 114 include vias 114(1) through 114(12). Vias 114(2) through 114(7) are also referred to herein as upper vias because they connect first CFET structure 102A and second CFET structure 102B to interconnect layer 112.

[0026] Vias 114(1)-114(12) will be described individually. Via 114(4) extends from a first source / drain SD1-UA1 of upper FET 104A on a first side SA1 of first CFET structure 102A to contact 120(4) in interconnect layer 112. Via 114(5) extends from a first source / drain SD1-UB1 of upper FET 104B on a first side SB1 of second CFET structure 102B to contact 120(4) in interconnect layer 112. Via 114(2) extends from a second source / drain SD1-UA2 of upper FET 104A on a second side SA2 of first CFET structure 102A to contact 120(2). Via 114(7) extends from the second source / drain SD1-UB2 of upper FET 104B to contact 120(6) on the second side SB2 of second CFET structure 102B. Via 114(3) couples gate 124A of upper FET 104A and gate 126A of lower FET 106A to interconnect layer 112. Via 114(6) couples gate 124B of upper FET 104B and gate 126B of lower FET 106B to interconnect layer 112.

[0027] The first source / drain SD1-UA1 and the second source / drain SD1-UA2 of the upper FET 104A have a source / drain width dimension W SD1 The first source / drain SD1-LA1 and the second source / drain SD1-LA2 also have a source / drain width W SD1Therefore, the first source / drain SD1-UA1 of upper FET 104A is directly in line with the first source / drain SD1-LA1 of lower FET 106A and interconnect layer 112 in the Y-axis direction, thereby blocking a vertical via path from the first source / drain SD1-LA1 to interconnect layer 112.

[0028] To couple the first source / drain SD1-LA1 to the interconnect layer 112, the monolithic 3D CFET circuit 100 also includes a via 114(10) that extends from the first source / drain SD1-LA1 of the lower FET 106A on the first side SA1 of the first CFET structure 102A to an interconnect 136(2) in a lower interconnect layer 138. The lower interconnect layer 138 is disposed below the semiconductor substrate 118 to provide interconnects 136(1)-136(3) in a horizontal direction (e.g., in the X-axis direction). Because via 114(1) and vias 114(8)-114(12) are coupled to the lower interconnect layer 138, they are referred to herein as lower vias. Via 114(9) extends from the second source / drain SD1-LA2 of lower FET 106A on the second side SA2 of first CFET structure 102A to interconnect 136(1) in lower interconnect layer 138. Via 114(11) extends from the first source / drain SD1-LB of lower FET 106B on the first side SB1 of second CFET structure 102B to interconnect 136(2) in lower interconnect layer 138. Via 114(12) extends from the second source / drain SD1-LB2 of lower FET 106B on the second side SB2 of second CFET structure 102B to interconnect 136(3) in lower interconnect layer 138.

[0029] The source / drains SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 have the same width dimension W as the source / drains SD1-UA1, SD1-UA2, SD1-UB1, and SD1-UB2. SD1, vias 114(9)-114(12) are needed to couple source / drains SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 to the lower interconnect layer 138. Source / drains SD1-UA1, SD1-UA2, SD1-UB1, and SD1-UB2 block the direct vertical path for vias to extend upward from source / drains SD1-LA1, SD1-LA2, SD1-LB1, and SD1-LB2 to the interconnect layer 112.

[0030] 1, interconnect 136(2) couples a first source / drain SD1-LA1 of lower FET 106A to a first source / drain SD1-LB1 of lower FET 106B through via 114(10) and via 114(11). A second source / drain SD1-LA2 of lower FET 106A is coupled to contact 120(1) in interconnect layer 112 through via 114(9), interconnect 136(1), and via 114(1). A second source / drain SD1-LB2 of lower FET 106B is coupled to contact 120(8) in interconnect layer 112 through via 114(12), interconnect 136(3), and via 114(8).

[0031] Those skilled in the art will readily understand the operation of the monolithic 3D CFET circuit 100 as a NAND circuit by referring to the circuit diagram 140 of Figure 1. In this embodiment, the upper FETs 104A, 104B are N-type FETs, the lower FETs 106A, 106B are P-type FETs, and the contacts 120(1)-120(6) are externally coupled as shown in the circuit diagram 140 and as described in more detail below.

[0032] Logic operations are provided by monolithic 3D CFET circuit 100 by coupling external circuitry as follows: Input signal IN-1 is received on contact 120(3). Input signal IN-2 is received on contact 120(5). Output signal OUT is generated on external interconnect 128 from one of contacts 120(1) and 120(8). Contact 120(2) is connected to reference voltage V SS Contact 120(4) couples a first source / drain SD1-UA1 of upper FET 104A to a first source / drain SD1-UB1 of upper FET 104B through vias 114(4) and 114(5). Interconnect 136(2) couples a first source / drain SD1-UA1 of upper FET 104A to a first source / drain SD1-UB1 of upper FET 104B through vias 114(4) and 114(5). DD A binary "1" in each of the input signals IN-1 and IN-2 produces a binary "0" in the output signal OUT.

[0033] 2 is a flowchart of a method 200 for fabricating a monolithic 3D CFET circuit 100. The method includes forming a device layer 108 (block 202), which includes forming a first CFET structure 102A (block 204) having a first FET 104A of a first type on a second FET 106A of a second type, and forming a second CFET structure 102B (block 206) having a third FET 104B of the first type on a fourth FET 106B of the second type. The method further includes forming an interconnect layer 112 (block 208) on the device layer 108, which further includes forming a first input contact 120(3) (block 210) configured to couple a first input signal IN-1 to a gate 124A of the first FET 104A and a gate 126A of the second FET 106A. Forming the interconnect layer 112 also includes forming a second input contact 120(5) configured to couple a second input signal IN-2 to the gate 124B of the third FET 104B and the gate 126B of the fourth FET 106B (block 212), and forming output contacts 120(1), 120(6) configured to generate an output signal OUT based on a logical operation of the first input signal IN-1 and the second input signal IN-2 (block 214).

[0034] 3-7 are cross-sectional side views of monolithic 3D CFET circuits 300-700, which are other embodiments of NAND circuits as disclosed herein. Each of the monolithic 3D CFET circuits 300-700 includes corresponding first and second CFET structures that correspond to and are similar to the first and second CFET structures 102A and 102B of FIG. 1.

[0035] 3 is a cross-sectional side view of a monolithic 3D CFET circuit 300 including a first CFET structure 302A and a second CFET structure 302B. CFET structure 302A includes an upper FET 304A on a lower FET 306A, and CFET structure 302B includes an upper FET 304B on a lower FET 306B. Upper FET 304A includes a first source / drain SD3-UA1 on a first side SA1 of first CFET structure 302A and a second source / drain SD3-UA2 on a second side SA2 of first CFET structure 302A. The lower FET 306A includes a first source / drain SD3-LA1 on a first side SA1 of the first CFET structure 302A and a second source / drain SD3-LA2 on a second side SA2 of the first CFET structure 302A. The first CFET structure 302A and the second CFET structure 302B are formed in a device layer 308.

[0036] The upper FET 304B includes a first source / drain SD3-UB1 on a first side SB1 of the second CFET structure 302B and a second source / drain SD3-UB2 on a second side SB2 of the second CFET structure 302B. The lower FET 306B includes a first source / drain SD3-LB1 on the first side SB1 and a second source / drain SD3-LB2 on the second side SB2.

[0037] 1, monolithic 3D CFET circuit 300 includes interconnect layer 312, insulator layer 316, and semiconductor substrate 318. Upper FETs 304A, 304B and lower FETs 306A, 306B are formed on semiconductor substrate 318 as bulk transistors. Interconnect layer 312 includes contacts 320(1)-320(8). The NAND operation of monolithic 3D CFET circuit 300 can be understood through analysis of circuit diagram 340, which corresponds to circuit diagram 140.

[0038] The first source / drain SD3-UA1 and the second source / drain SD3-UA2 of the CFET structure 302A, and the first source / drain SD3-UB1 and the second source / drain SD3-UB2 of the CFET structure 30B each have a first source / drain width W in the X-axis direction. SD1 1. Vias 314(2)-314(4) and vias 314(7)-314(9) of monolithic 3D CFET circuit 300 correspond to vias 114(2)-114(7) of FIG. 1. In this regard, vias 314(2)-314(4) and vias 314(7)-314(9) may be referred to as upper vias. The upper vias between FETs 304A, 304B and interconnect layer 312 are similar or identical to upper vias 114 between upper FETs 104A, 104B and interconnect layer 112 in FIG. 1.

[0039] However, unlike the monolithic 3D CFET circuit 100, in the monolithic 3D CFET circuit 300, the first source / drain SD3-LA1 and the second source / drain SD3-LA2 of the lower FET 306A and the first source / drain SD3-LB1 and the second source / drain SD3-LB2 of the lower FET 306B have a source / drain width dimension W SD1 The source / drain width dimension W in the X-axis direction is larger than SD2As a result, for example, the first source / drain SD3-LA1 extends further in the X-axis direction from the lower FET 306A on the first side SA1 than the first source / drain SD3-UA1, and the second source / drain SD3-LA2 extends further in the X-axis direction from the lower FET 306A on the second side SA2 than the second source / drain SD3-UA2. Therefore, the first source / drain SD3-UA1 of the upper FET 304A is not disposed between a portion of the first source / drain SD3-LA1 and the interconnect layer 312 in the Y-axis direction, and the second source / drain SD3-UA2 of the upper FET 304A is not disposed between a portion of the second source / drain SD3-LA2 and the interconnect layer 312 in the Y-axis direction. As a result, some of the vias 314 can extend unimpeded in the Y-axis direction to couple the first source / drain SD3-LA1 and the second source / drain SD3-LA2 of the lower FET 306A and the first source / drain SD3-LB1 and the second source / drain SD3-LB2 of the lower FET 306B to the interconnect layer 312. Because the first source / drain SD3-UA1 and SD3-UB1 and the second source / drain SD3-UA2 and SD3-UB2 do not obstruct the via paths in the Y-axis direction, a second interconnect layer (such as interconnect layer 138 in FIG. 1 ) to provide an offset in the X-axis direction is not needed, and the total number of vias 314 is reduced compared to FIG. 1 , further reducing the total area occupied by the monolithic 3D CFET circuit 300.

[0040] CFET structures 302A and 302B are coupled to interconnect layer 312 as follows: via 314(1) couples contact 320(1) to a second source / drain SD3-LA2 of lower FET 306A; via 314(2) couples contact 320(2) to a second source / drain SD3-UA2 of upper FET 304A; via 314(3) couples contact 320(3) to gate 324A of upper FET 304A and gate 326A of lower FET 306A; via 314(4) couples contact 320(4) to a first source / drain SD3-UA1 of upper FET 304A; and contact 320(5) is coupled to a first source / drain SD3-LA1 of lower FET 306A by via 314(5). Contact 320(5) is also coupled to the first source / drain SD3-LB1 of lower FET 306B by via 314(6). Thus, via 314(5), contact 320(5), and via 314(6) couple the first source / drain SD3-LA1 of lower FET 306A to the first source / drain SD3-LB1 of lower FET 306B.

[0041] Via 314(7) couples contact 320(6) to a first source / drain SD3-UB1 of upper FET 304B. External interconnect 342 couples contact 320(4) to contact 320(6) to couple a first source / drain SD3-UA1 of upper FET 304A to a first source / drain SD3-UB1 of upper FET 304B. Via 314(8) couples contact 320(7) to gate 324B of upper FET 304B and gate 326B of lower FET 306B. Contact 320(8) is coupled by via 314(9) to a second source / drain SD3-UB2 of upper FET 304B. Contact 320(8) is also coupled to a second source / drain SD3-LB2 of lower FET 306B. Thus, via 314(9), contact 320(8), and via 314(10) couple the second source / drain SD3-UB1 of upper FET 304B to the second source / drain SD3-LB2 of lower FET 306B.

[0042] For operation as a NAND logic circuit, a first input signal IN-1 is received from an external circuit on contact 320(3) and a second input signal IN-2 is received on contact 320(7). An external interconnect 328 couples contact 320(1) to contact 320(8) to provide a connection by which an output signal OUT can be connected to an external circuit. Contact 320(2) is connected to a reference voltage V SS (e.g., ground, 0 volts), and contact 320(5) receives a supply voltage V DD Receive.

[0043] 4 is a cross-sectional side view of a monolithic 3D CFET circuit 400 in another embodiment of a NAND logic circuit. The monolithic 3D CFET circuit 400 is structurally identical to the monolithic 3D CFET circuit 100 of FIG. 1, except as noted below.

[0044] The monolithic 3D CFET circuit 400 includes CFET structure 402A and CFET structure 402B, in which upper FETs 404A and 404B are a first type of FET and lower FET 406B is a second type of FET, similar to FIG. 1. However, the configuration of FIG. 1 is based on the upper FETs 104A and 104B being N-type FETs and the lower FETs 106A and 106B being P-type FETs. In the configuration of FIG. 4, the upper FETs 404A and 404B are P-type FETs and the lower FETs 406A and 406B are N-type FETs. In accordance with this difference, the monolithic 3D CFET circuit 400 is configured as a NAND logic circuit in the following manner.

[0045] The monolithic 3D CFET circuit 400 includes contacts 420(1)-420(6) in interconnect layer 412 and interconnects 436(1)-436(3) in interconnect layer 438. In place of external interconnect 128 of FIG. 1, external interconnect 428 couples contact 420(2) to contact 420(6) for electrically coupling the second source / drain SD4-UA2 of upper FET 404A to the second source / drain SD4-UB2 of upper FET 404B and the second source / drain SD4-LB2 of lower FET 406B. An output signal OUT is generated on external interconnect 428 for providing to external circuitry, not shown. A reference voltage V SS is supplied to contact 420(1). A first input signal IN-1 and a second input signal IN-2 are received at contact 420(3) and contact 420(5), respectively. A power supply voltage V DD is received at contact 420(4).

[0046] Figure 5 is a cross-sectional side view of a monolithic 3D CFET circuit 500 in another embodiment of a NAND logic circuit. The monolithic 3D CFET circuit 500 is structurally similar to the monolithic 3D CFET circuit 300 of Figure 3, except that in CFET structures 502A and 502B, the upper FETs 504A and 504B, which are P-type FETs, are positioned above the lower FETs 506A and 506B, which are N-type FETs, reversing the configuration of Figure 3.

[0047] The monolithic 3D CFET circuit 500 includes contacts 520(1)-520(8) in the interconnect layer 512. An external interconnect 528 couples contact 520(2) to contact 520(8) for electrically coupling the second source / drain SD5-UA2 of the upper FET 504A to the second source / drain SD5-UB2 of the upper FET 504B and also to the second source / drain SD5-LB2 of the lower FET 506B. An output signal OUT is generated on the external interconnect 528 for providing to external circuitry, not shown. A reference voltage V SSis supplied to contact 520(1). A first input signal IN-1 and a second input signal IN-2 are received at contact 520(3) and contact 520(7), respectively. A power supply voltage V DD is received at contact 520(4). A second external interconnect 542 couples contact 520(4) to contact 520(6). Contact 520(5) couples a first source / drain SD5-LA1 of lower FET 506A to a first source / drain SD5-LB1 of lower FET 506B.

[0048] 6 and 7 are cross-sectional side views of monolithic 3D CFET circuits 600 and 700, respectively, which are examples of NAND logic circuits. The structures of monolithic 3D CFET circuits 600 and 700, as well as the structures of the external interconnects for configuring their operation as NAND logic circuits, are identical to the structures of monolithic 3D CFET circuits 100 and 300, except that monolithic 3D CFET circuits 600 and 700 do not include a semiconductor substrate. Instead, monolithic 3D CFET circuits 600 and 700 are formed on an insulator substrate.

[0049] In particular, the monolithic 3D CFET circuit 600 includes CFET structures 602A, 602B in which upper FETs 604A, 604B are disposed above lower FETs 606A, 606B. The monolithic 3D CFET circuit 700 includes CFET structures 702A, 702B in which upper FETs 704A, 704B are disposed above lower FETs 706A, 706B. The FETs in the CFET structures 602A, 602B and the FETs in the CFET structures 702A, 702B are formed as silicon-on-insulator (SOI) transistors on the insulator layer 616 and the insulator layer 716, respectively. The monolithic 3D CFET circuit 600 includes an interconnect layer 638, which can provide additional structural support for the insulator layer 616. The insulator layer 716 may be disposed on a support substrate 750 .

[0050] Although not shown here, the monolithic 3D CFET circuits 400 and 500, in which the PFET is disposed above the NFET in a corresponding CFET structure, can alternatively be fabricated on an insulator layer using SOI transistors, similar to the embodiments of FIGS. 6 and 7.

[0051] It should be noted that the dimensions of features shown in Figures 1 and 3-13 are not to scale.

[0052] Figures 8-13 are cross-sectional side views of monolithic 3D CFET circuits 800-1300, respectively, which are structurally identical in character to the monolithic 3D CFET circuit 100 and circuits 300-700 shown in Figures 1 and 3-7. However, the monolithic 3D CFET circuits 800-1300 are configured to function as Not-OR (NOR) logic circuits via external interconnects and contacts, as follows:

[0053] The monolithic 3D CFET circuit 800 of Figure 8 is structurally similar to the monolithic 3D CFET circuit 100 of Figure 1, comparing the device layer 108 and interconnect layers 112 and 138 of Figure 1 with the device layer 808 and interconnect layers 812 and 838 of Figure 8. The monolithic 3D CFET circuit 800 includes CFET structures 802A and 802B in which upper FETs 804A and 804B of a first type are disposed on (e.g., above) lower FETs 806A and 806B of a second type. The upper FET 804 includes a first source / drain SD8-UA1 on a first side SA1 of the CFET structure 802A and a second source / drain SD8_UA2 on a second side SA2 of the CFET structure 802A. The upper FET 804B and the lower FETs 806A and 806B also have a first source / drain and a second source / drain according to FIG.

[0054] Monolithic 3D CFET circuit 800 is configured as a NOR logic circuit, as shown in circuit diagram 840, as follows: Interconnect layer 812 includes contacts 820(1) through 820(6), and interconnect layer 838 includes interconnects 836(1) through 836(3). Contact 820(1) is coupled to a power supply voltage V DD , which is coupled to the second source / drain SD8-LA2 of the lower FET 806A.

[0055] Contact 820(2) is coupled to contact 820(6) by external interconnect 828, on which an output signal OUT to an external circuit can be generated. Thus, external interconnect 828 is coupled to a second source / drain SD8-UA2 of upper FET 804A, a second source / drain SD8-UB2 of upper FET 804B, and a second source / drain SD8-LB2 of lower FET 806B. The output signal OUT is based on input signals IN-1 and IN-2. A first input signal IN-1 is received at contact 820(3), and a second input signal IN-2 is received at contact 820(5). Contact 820(4) couples a first source / drain SD8-UA1 of upper FET 804A to a first source / drain SD8-UB1 of upper FET 804B. The contact 820(4) is connected to the reference voltage (V SS ) is coupled to ground. Interconnect 836(2) couples a first source / drain SD8-LA1 of lower FET 806A to a first source / drain SD8-LB1 of lower FET 806B.

[0056] FIG. 9 is a cross-sectional side view of a monolithic 3D CFET circuit 900 having the same structure as monolithic 3D CFET circuit 300, but configured externally to function as a NOR logic circuit, as follows.

[0057] The contact 920(1) is connected to the power supply voltage V DD, which is supplied to the second source / drain SD9-LA2 of the lower FET 906A. The second source / drain SD9-LA2 has a larger source / drain width W SD2 , and is therefore directly coupled to contact 920(1) by via 914(1). Contact 920(2) provides a reference voltage V SS , which is supplied to the second source / drain SD9-UA2 of the upper FET 904A. SS is also received at contact 920(6) and provided to a first source / drain SD9-UB1 of upper FET 904B. Contact 920(3) receives a first input signal IN-1 for controlling upper FET 904A and lower FET 906A. Contact 920(7) receives a second input signal IN-2 for controlling upper FET 904B and lower FET 906B.

[0058] Contact 920(4) is coupled to contact 920(8) by external interconnect 928, which may also provide an output signal OUT to an external circuit. Contact 920(4) is coupled to a first source / drain SD9-UA1 of upper FET 904A. Contact 920(7) is coupled to a second source / drain SD9-UB2 of upper FET 904B and a second source / drain SD9-LB2 of lower FET 906B. Contact 920(5) is coupled to a first source / drain SD9-LA1 of lower FET 906A and a first source / drain SD9-LB1 of lower FET 906B.

[0059] 10 is a cross-sectional side view of a monolithic 3D CFET circuit 1000 that is structurally similar to monolithic 3D CFET circuit 400, but is externally configured to function as a NOR logic circuit. Monolithic 3D CFET circuit 1000 is also structurally similar to monolithic 3D CFET circuit 800, except that in monolithic 3D CFET circuit 1000, upper FETs 1004A and 1004B are P-type FETs and lower FETs 1006A and 1006B are N-type FETs.

[0060] The configuration for functioning as a NOR logic circuit includes the following: Contact 1020(1) is coupled to contact 1020(6) and can provide an output signal OUT to an external circuit; Contact 1020(1) is coupled to a second source / drain SD10-LB2 of lower FET 1006A; Contact 1020(6) is coupled to a second source / drain SD10-UB2 of upper FET 1004B and a second source / drain SD10-LB2 of lower FET 1006B; Contact 1020(2) is coupled to a power supply voltage V DD , which is provided to the second source / drain SD10-UA2 of the upper FET 1004A.

[0061] Contact 1020(3) receives a first input signal IN-1, which is provided to gates 1024A, 1026A of CFET structure 1002A to control upper FET 1004A and lower FET 1006A. Contact 1020(5) receives a second input signal IN-2, which is provided to gates 1024B, 1026B of CFET structure 1002B to control upper FET 1004B and lower FET 1006B. Contact 1020(4) is coupled to a first source / drain SD10-UA1 of upper FET 1004A and a first source / drain SD10-UB1 of upper FET 1004B. A first source / drain SD10-LA1 of lower FET 1006A is coupled to a first source / drain SD10-LB1 of lower FET 1006B by interconnect 1036(2).

[0062] 11 is a cross-sectional view of a monolithic 3D CFET circuit 1100 that is structurally identical to monolithic 3D CFET circuit 500 and externally configured to function as a NOR logic circuit. Contact 1120(1) and contact 1120(8) are connected to a reference voltage V SS The contact 1120(2) receives the power supply voltage V DD A first input signal IN-1 is received at contact 1120(3), and a second input signal IN-2 is received at contact 1120(6). Contact 1120(4) is coupled to contact 1120(7) by external interconnect 1128. Contact 1120(5) couples first source / drain SD11-LA1, first source / drain SD11-UB1, and first source / drain SD11-LB1.

[0063] Each of the monolithic 3D CFET circuits is formed using bulk transistors on a semiconductor substrate. Monolithic 3D CFET circuits 1200 and 1300 of Figures 12 and 13 are identical in all respects to monolithic 3D CFET circuits 800 and 900 of Figures 8 and 9, except that monolithic 3D CFET circuits 1200 and 1300 are formed using SOI transistors on insulator layer 1216 and insulator layer 1316, respectively. Alternatively, monolithic 3D CFET circuits 1000 and 1100 can also be formed using SOI transistors on an insulator layer, although such an embodiment is not shown here.

[0064] According to aspects disclosed herein, the monolithic 3D CFET circuit can be provided within or integrated into any processor-based device, including, but not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed position data unit, a mobile position data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopters.

[0065] FIG. 14 illustrates an exemplary wireless communication device 1400 including radio-frequency (RF) components formed from one or more integrated circuits (ICs) 1402, which may include an exemplary monolithic 3D CFET circuit including a CFET structure having a first type of upper FET above a second type of lower FET and configured as either a NAND circuit or a NOR circuit, according to any of the aspects disclosed herein, such as those shown in FIGS. 1 and 2-13. The wireless communication device 1400 may include or be provided within any of the devices mentioned above as examples. As shown in FIG. 14, the wireless communication device 1400 includes a transceiver 1404 and a data processor 1406. The data processor 1406 may include memory for storing data and program code. The transceiver 1404 includes a transmitter 1408 and a receiver 1410 that support bidirectional communication. In general, wireless communication device 1400 may include any number of transmitters 1408 and / or receivers 1410 for any number of communication systems and frequency bands. All or a portion of transceiver 1404 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0066] The transmitter 1408 or the receiver 1410 may be implemented using a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne architecture and the direct-conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1400 of FIG. 14, the transmitter 1408 and the receiver 1410 are implemented using a direct-conversion architecture.

[0067] On the transmit path, the data processor 1406 processes data to be transmitted and provides I and Q analog output signals to the transmitter 1408. In the exemplary wireless communication device 1400, the data processor 1406 includes digital-to-analog converters (DACs) 1412(1), 1412(2) to convert digital signals generated by the data processor 1406 into I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0068] Within transmitter 1408, lowpass filters 1414(1) and 1414(2) filter the I and Q analog output signals, respectively, to remove undesired signals resulting from previous digital-to-analog conversion. Amplifiers (AMPs) 1416(1) and 1416(2) amplify the signals from lowpass filters 1414(1) and 1414(2), respectively, to provide I and Q baseband signals. An upconverter 1418 upconverts the I and Q baseband signals using I and Q LO signals from a transmit (TX) local oscillator (LO) signal generator 1422 via mixers 1420(1) and 1420(2) to provide upconverted signals 1424. A filter 1426 filters the upconverted signal 1424 to remove undesired signals caused by the frequency upconversion as well as noise within the receive frequency band. A power amplifier (PA) 1428 amplifies the upconverted signal 1424 from filter 1426 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1430 and transmitted via an antenna 1432.

[0069] In the receive path, antenna 1432 receives a signal transmitted by the base station and provides a receive RF signal, which is routed through duplexer or switch 1430 and provided to low noise amplifier (LNA) 1434. Duplexer or switch 1430 is designed to operate with a specific RX-to-TX duplexer frequency separation so that the receive (RX) signal is separated from the TX signal. To obtain the desired RF input signal, the receive RF signal is amplified by LNA 1434 and filtered by filter 1436. Downconversion mixers 1438(1), 1438(2) mix the output of filter 1436 with I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1440 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1442(1), 1442(2) and further filtered by low-pass filters 1444(1), 1444(2) to obtain I and Q analog input signals, which are provided to data processor 1406. In this embodiment, data processor 1406 includes analog-to-digital converters (ADCs) 1446(1), 1446(2) to convert the analog input signals to digital signals that are further processed by data processor 1406.

[0070] In the wireless communication device 1400 of FIG. 14 , a TX LO signal generator 1422 generates an I TX LO signal and a Q TX LO signal used for frequency upconversion, while an RX LO signal generator 1440 generates an I RX LO signal and a Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1448 receives timing information from the data processor 1406 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1422. Similarly, an RX PLL circuit 1450 receives timing information from the data processor 1406 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1440.

[0071] The wireless communication device 1400 may include an exemplary monolithic 3D CFET circuit including a CFET structure having a first type of upper FET above a second type of lower FET according to any of the aspects disclosed herein, as shown in FIGS. 1 and 2-13, configured as either a NAND circuit or a NOR circuit, and may be provided within or integrated within any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed position data units, mobile position data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smart watches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0072] FIG. 15 illustrates an example of a processor-based system 1500 including a circuit, including an exemplary monolithic 3D CFET circuit, including a CFET structure having a first type of upper FET above a second type of lower FET, configured as either a NAND circuit or a NOR circuit, according to any aspect disclosed herein, as illustrated in FIGS. 1 and 2-13. In this example, the processor-based system 1500 includes one or more CPUs 1502, which may also be referred to as central processor units (CPUs) or processor cores, each including one or more processors 1504. The CPU(s) 1502 may have a cache memory 1506 coupled to the processor(s) 1504 for rapid access to temporarily stored data. The CPU(s) 1502 are coupled to a system bus 1508, which may interconnect master and slave devices included within the processor-based system 1500. As is well known, CPU(s) 1502 communicate with these other devices by exchanging address, control, and data information via system bus 1508. For example, CPU(s) 1502 may communicate bus transaction requests to memory controller 1510, an example of a slave device. Although not shown in Figure 15, multiple system buses 1508 may be provided, with each system bus 1508 constituting a different fabric.

[0073] Other master and slave devices may be connected to the system bus 1508. As shown in FIG. 15, these devices may include, by way of example, a memory system 1512 including a memory controller 1510 and one or more memory arrays 1514, one or more input devices 1516, one or more output devices 1518, one or more network interface devices 1520, and one or more display controllers 1522. The input device(s) 1516 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output device(s) 1518 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s) 1520 may be any device configured to enable the exchange of data with a network 1524. The network 1524 can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH network, and the Internet. The network interface device(s) 1520 can be configured to support any type of communication protocol desired.

[0074] The CPU(s) 1502 may also be configured to access display controller(s) 1522 via the system bus 1508 to control information sent to one or more displays 1526. The display controller(s) 1522 send information to be displayed to the display(s) 1526 via one or more video processors 1528, which process the information to be displayed into a format suitable for the display(s) 1526. The display(s) 1526 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light-emitting diode (LED) display.

[0075] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. By way of example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memories disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0076] The various illustrative logical blocks, modules, and circuits described in connection with aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0077] Aspects disclosed herein may be embodied in hardware or in instructions stored in the hardware and that may reside in, for example, a random access memory (RAM), a flash memory, a read-only memory (ROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0078] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that numerous and varied modifications may be made to the operational steps depicted in the flowchart diagrams, as would be readily apparent to one skilled in the art. Those skilled in the art will also appreciate that information and signals may be represented using a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, which may be referred to throughout the above description, may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0079] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0080] The following numbered clauses describe example implementations. 1. A complementary field effect transistor (CFET) circuit comprising: a device layer, a first monolithic CFET structure having a first FET of a first type on a second FET of a second type; a second monolithic CFET structure having a third FET of the first type on a fourth FET of the second type; and a first interconnect layer disposed over the device layer, a first input contact configured to couple a first input signal to the gate of the first FET and to the gate of the second FET; a second input contact configured to couple a second input signal to the gate of the third FET and to the gate of the fourth FET; a first interconnect layer including an output contact configured to generate an output signal based on a logical operation of a first input signal and a second input signal. 2. The CFET circuit of clause 1, further comprising a first interconnect extending in the first interconnect layer in a second direction to couple a first source / drain of the first FET on the first side of the first monolithic CFET structure to a first source / drain of a third FET on the first side of the second monolithic CFET structure, wherein the first side of the first monolithic CFET structure and the first side of the second monolithic CFET structure are between the first monolithic CFET structure and the second monolithic CFET structure. 3. The CFET circuit of clause 1 or clause 2, further comprising a two-input negative OR (NOR) circuit. 4. The CFET circuit of clause 1 or clause 2, further comprising a two-input non-and (NAND) circuit. 5. The device layer a first upper via on a first side of the first monolithic CFET structure, the first upper via extending from the first source / drain of the first FET to the first interconnect layer; a second upper via extending from the first source / drain of the third FET to the first interconnect layer on the first side of the second monolithic CFET structure; a third upper via on the second side of the first monolithic CFET structure, the third upper via extending from the second source / drain of the first FET to the first interconnect layer; a fourth upper via extending from the second source / drain of the third FET to the first interconnect layer on the second side of the second monolithic CFET structure; a fifth upper via coupling the gate of the first FET and the gate of the second FET to the first interconnect layer; 5. The CFET circuit of any of clauses 1-4, further comprising: a sixth upper via coupling a gate of the third FET and a gate of the fourth FET to the first interconnect layer. 6. The device layer a first lower via extending from the first source / drain of the second FET to the first interconnect layer on the first side of the first monolithic CFET structure; a second lower via extending from the first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure; a third lower via on the second side of the first monolithic CFET structure, the third lower via extending from the second source / drain of the second FET to the first interconnect layer; and a fourth lower via extending from the first source / drain of the fourth FET to the first interconnect layer on the second side of the first monolithic CFET structure. 7. a first source / drain of the first FET coupled to the first channel region on a first side of the first FET, and a second source / drain of the first FET coupled to the first channel region on a second side of the first FET; a first source / drain of the second FET coupled to a second channel region on a first side of the second FET, and a second source / drain of the second FET coupled to a second channel region on a second side of the second FET; a first source / drain of the first FET having a first source / drain width in the second direction; the first source / drain of the second FET has a second source / drain width in the second direction, the second source / drain width exceeding the first source / drain width; the device layer further includes a seventh upper via extending from the first source / drain of the second FET to the first interconnect layer on the first side of the first monolithic CFET structure; Any CFET circuit of clauses 1 to 5. 8. a second source / drain of the first FET having a first source / drain width; the first source / drain of the third FET has a first source / drain width; a second source / drain of the third FET having a first source / drain width; a second source / drain of the second FET having a second source / drain width; the first source / drain of the fourth FET has a second source / drain width; a second source / drain of the fourth FET having a second source / drain width; an eighth upper via extends from the second source / drain of the second FET to the first interconnect layer on the second side of the first monolithic CFET structure; a ninth upper via extends from the first source / drain of the fourth FET to the first interconnect layer on the first side of the second monolithic CFET structure; a tenth upper via extending from the second source / drain of the fourth FET to the first interconnect layer on the second side of the second monolithic CFET structure; Clause 7 CFET circuit. 9. Further comprising a second interconnect layer disposed below the device layer; The device layer a first lower via extending from the first source / drain of the second FET to the second interconnect layer on the first side of the first monolithic CFET structure; a second lower via extending from the first source / drain of the fourth FET to the second interconnect layer on the first side of the second monolithic CFET structure; a third lower via extending from the second source / drain of the second FET to the second interconnect layer on the second side of the first monolithic CFET structure; a fourth lower via extending from the second source / drain of the fourth FET to the second interconnect layer on the second side of the second monolithic CFET structure; a fifth via coupled to the third lower via through the second interconnect layer and extending between the second interconnect layer and the first interconnect layer on the second side of the first monolithic CFET structure; a sixth via coupled to the fourth lower via through the second interconnect layer and extending between the second interconnect layer and the first interconnect layer on the second side of the second monolithic CFET structure; 6. The CFET circuit of clause 5, wherein the second interconnect layer further comprises a lower interconnect coupled to the first lower via and the second lower via. 10. Further comprising a semiconductor substrate; 10. The CFET circuit of any of clauses 1 to 9, wherein the first FET, the second FET, the third FET, and the fourth FET comprise bulk type transistors formed on a semiconductor substrate. 11. Further comprising an oxide layer; 10. The CFET circuit of any of clauses 1 to 9, wherein the first FET, the second FET, the third FET, and the fourth FET further comprise silicon-on-insulator (SOI) transistors formed on an oxide layer. 12. The CFET circuit of any of clauses 2 through 11, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the second FET and to the second source / drain of the fourth FET. 13. The CFET circuit of any of clauses 2 through 11, further comprising an external interconnect coupling the second source / drain of the third FET to the second source / drain of the first FET and to the second source / drain of the fourth FET. 14. The CFET circuit of any of clauses 2-8, 10, and 11, further comprising an external interconnect coupling a first source / drain of the first FET to a first source / drain of the third FET. 15. The CFET circuit of any of clauses 2-8, 10, and 11, further comprising an external interconnect coupling a first source / drain of the first FET to a second source / drain of the fourth FET and to a second source / drain of the third FET. 16. The CFET circuit of any one of clauses 1 to 15, wherein the first FET, the second FET, the third FET, and the fourth FET each include a channel region that includes at least one nanoslab or nanowire. 17. The CFET circuit of any of clauses 1 to 16 integrated within a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. 18. An integrated circuit (IC) comprising: a processor; a complementary field effect transistor (CFET) circuit coupled to the processor; The CFET circuit is a device layer; a first monolithic CFET structure having a first FET of a first type above a second FET of a second type; a second monolithic CFET structure having a third FET of the first type above a fourth FET of the second type; a first interconnect layer disposed over the device layer, a first input contact configured to couple a first input signal to the gate of the first FET and to the gate of the second FET; a second input contact configured to couple a second input signal to the gate of the third FET and to the gate of the fourth FET; and a first interconnect layer including an output contact configured to generate an output signal based on a logical operation of a first input signal and a second input signal. 19. A method of forming a complementary field effect transistor (CFET) circuit, comprising: a device layer, a first monolithic CFET structure having a first FET of a first type above a second FET of a second type; forming a device layer including a second monolithic CFET structure having a third FET of the first type above a fourth FET of the second type; a first interconnect layer disposed over the device layer, a first input contact configured to couple a first input signal to the gate of the first FET and to the gate of the second FET; a second input contact configured to couple a second input signal to the gate of the third FET and to the gate of the fourth FET; forming a first interconnect layer including an output contact configured to generate an output signal based on a logical operation of a first input signal and a second input signal. 20. The method of clause 19, further comprising forming a first interconnect extending in the first interconnect layer in a second direction to couple a first source / drain of a first type FET in the first monolithic CFET structure to a first source / drain of a first type FET in the second monolithic CFET structure. [Explanation of symbols]

[0081] 100, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200, 1300 Monolithic 3D CFET circuits 102A, 302A First CFET structure 102B, 302B Second CFET structure 104A First FET 104B Third FET 106A Second FET 106B 4th FET 108, 308, 808 device layers 112, 312, 412, 438, 512, 638, 812, 838 interconnect layers 120(3) First input contact 120(5) Second input contact 120(1), 120(6) Output contact

Claims

1. A complementary field-effect transistor (CFET) circuit, The device layer, A first monolithic CFET structure having a first FET of the first type on a second FET of the second type, A device layer comprising: a second monolithic CFET structure having a third FET of the first type on a fourth FET of the second type; A first interconnection layer disposed on the device layer, A first input contact is configured to couple the first input signal to the gate of the first FET and the gate of the second FET, A second input contact is configured to couple the second input signal to the gate of the third FET and the gate of the fourth FET, A first interconnection layer including an output contact configured to generate an output signal based on a logical operation between the first input signal and the second input signal, A first interconnector extending within the first interconnection layer to couple the first source / drain of the first FET on the first side of the first monolithic CFET structure to the first source / drain of the third FET on the first side of the second monolithic CFET structure, wherein the first side of the first monolithic CFET structure and the first side of the second monolithic CFET structure are connected to the first interconnector located between the first monolithic CFET structure and the second monolithic CFET structure. Equipped with, The aforementioned device layer On the first side of the first monolithic CFET structure, a first upper via extends from the first source / drain of the first FET to the first interconnection layer, On the first side of the second monolithic CFET structure, a second upper via extends from the first source / drain of the third FET to the first interconnection layer, On the second side of the first monolithic CFET structure, a third upper via extends from the second source / drain of the first FET to the first interconnection layer, On the second side of the second monolithic CFET structure, a fourth upper via extends from the second source / drain of the third FET to the first interconnection layer, The gate of the first FET and the gate of the second FET are coupled to the first interconnection layer by a fifth upper via, A CFET circuit further comprising a sixth upper via coupling the gates of the third FET and the gate of the fourth FET to the first interconnection layer.

2. The CFET circuit according to claim 1, further comprising an interconnector located outside the device layer and the first interconnection layer, coupled to the second source / drain of the third FET to constitute the CFET circuit as a two-input negative OR (NOR) circuit.

3. The CFET circuit according to claim 1, further comprising an interconnector located outside the device layer and the first interconnection layer, coupled to the second source / drain of the third FET to constitute the CFET circuit as a two-input negative AND (NAND) circuit.

4. The aforementioned device layer On the first side of the first monolithic CFET structure, a first lower via extends from the first source / drain of the second FET to the first interconnection layer, On the first side of the second monolithic CFET structure, a second lower via extends from the first source / drain of the fourth FET to the first interconnection layer, On the second side of the first monolithic CFET structure, a third lower via extends from the second source / drain of the second FET to the first interconnection layer, The CFET circuit according to claim 1, further comprising: a fourth lower via extending from the first source / drain of the fourth FET to the first interconnection layer on the second side of the first monolithic CFET structure.

5. The first source / drain of the first FET is coupled to the first channel region on the first side of the first monolithic CFET structure, and the second source / drain of the first FET is coupled to the first channel region on the second side of the first monolithic CFET structure. The first source / drain of the second FET is coupled to the second channel region on the first side of the second monolithic CFET structure, and the second source / drain of the second FET is coupled to the second channel region on the second side of the second monolithic CFET structure, The first source / drain of the first FET has a first source / drain width, The first source / drain of the second FET has a second source / drain width that exceeds the first source / drain width. The device layer further includes a seventh lower via extending from the first source / drain of the second FET to the first interconnection layer on the first side of the first monolithic CFET structure. The CFET circuit according to claim 1.

6. The second source / drain of the first FET has the first source / drain width, The first source / drain of the third FET has the first source / drain width, The second source / drain of the third FET has the first source / drain width, The second source / drain of the second FET has the second source / drain width, The first source / drain of the fourth FET has the second source / drain width, The second source / drain of the fourth FET has the second source / drain width, The eighth upper via extends from the second source / drain of the second FET to the first interconnection layer on the second side of the first monolithic CFET structure. The ninth upper via extends from the first source / drain of the fourth FET to the first interconnection layer on the first side of the second monolithic CFET structure. The tenth upper via extends from the second source / drain of the fourth FET to the first interconnection layer on the second side of the second monolithic CFET structure. The CFET circuit according to claim 5.

7. The device further comprises a second interconnection layer located below the device layer, The aforementioned device layer On the first side of the first monolithic CFET structure, a first lower via extends from the first source / drain of the second FET to the second interconnection layer, On the first side of the second monolithic CFET structure, a second lower via extends from the first source / drain of the fourth FET to the second interconnection layer, On the second side of the first monolithic CFET structure, a third lower via extends from the second source / drain of the second FET to the second interconnection layer, On the second side of the second monolithic CFET structure, a fourth lower via extends from the second source / drain of the fourth FET to the second interconnection layer, A fifth via is coupled to the third lower via via the second interconnection layer, and extends between the second interconnection layer and the first interconnection layer on the second side of the first monolithic CFET structure, The present invention further includes a sixth via, which is coupled to the fourth lower via via the second interconnection layer and extends between the second interconnection layer and the first interconnection layer on the second side of the second monolithic CFET structure, The CFET circuit according to claim 1, further comprising a lower interconnector in which the second interconnection layer is coupled to the first lower via and the second lower via.

8. Further equipped with a semiconductor substrate, The CFET circuit according to claim 1, wherein the first FET, the second FET, the third FET, and the fourth FET include bulk transistors formed on the semiconductor substrate.

9. Further comprising an oxide layer, The CFET circuit according to claim 1, further comprising silicon-on-insulator (SOI) transistors formed on the oxide layer, the first FET, the second FET, the third FET, and the fourth FET.

10. The CFET circuit according to claim 1, further comprising an interconnector located outside the device layer and the first interconnection layer, which couples the second source / drain of the third FET to the second source / drain of the second FET and the second source / drain of the fourth FET.

11. The CFET circuit according to claim 1, further comprising an interconnector located outside the device layer and the first interconnection layer, which couples the second source / drain of the third FET to the second source / drain of the first FET and the second source / drain of the fourth FET.

12. The CFET circuit according to claim 1, wherein each of the first FET, the second FET, the third FET, and the fourth FET includes a channel region comprising at least one nanoslab or nanowire.

13. A set-top box, entertainment unit, navigation device, communication device, fixed-location data unit, mobile-location data unit, Global Positioning System (GPS) device, mobile phone, cellular phone, smartphone, Session Initiation Protocol (SIP) phone, tablet, phablet, server, computer, portable computer, mobile computing device, wearable computing device, desktop computer, personal digital assistant (PDA), monitor, computer monitor, television, tuner, radio, satellite radio, music player, digital music player, portable music player, digital video player, video player, digital video disc (DVD) player, portable digital video player, automobile, vehicle components, avionics system, drone, and multicopter, including the CFET circuit described in Claim 1. A processor-based device selected from the group consisting of the following.

14. Integrated circuits (ICs) Processor and An IC comprising a complementary field-effect transistor (CFET) circuit according to claim 1, coupled to the processor.

15. A method for forming a complementary field-effect transistor (CFET) circuit according to Claim 1, Forming the layer of the aforementioned device, To form the first interconnection layer disposed on the device layer, Forming the first interconnector that extends within the first interconnection layer, Methods that include...

Images