Self-aligned patterned projection liner for sidewall electrode PCM

Abstract

A memory device and method for forming a projection liner underneath a mushroom-type phase change memory device using a sidewall electrode process scheme to provide self-aligned patterning of the resistive projection liner during the formation of the sidewall electrodes.

Description

[Background technology]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly to phase change memory devices having resistive projection liners.

[0002] Phase change materials can change phase between an amorphous state and a crystalline state by applying a specific level of current or voltage. The amorphous state can be characterized by a relatively higher electrical resistivity than the crystalline state, and therefore different voltage or current levels can be used to set the phase of the phase change material. Phase change memory (PCM) elements can use phase change materials to increase memory capacity. In one aspect, by applying different voltage or current levels to change the phase between an off state (e.g., no voltage or current applied), an amorphous state, a crystalline state, and various types of crystalline states, phase change memory can represent more than two values (e.g., binary) of data that can be stored in a phase change memory element.

[0003] The use of phase change memory in analog computing requires memory cells that have a resistance that changes linearly with a program pulse and is predictable and repeatable.

[0004] Amorphous phase change materials often suffer from resistance drift, which causes the cell's resistance to change over time, making the cell's resistance unpredictable.

[0005] To mitigate resistance drift, a projection segment, a parallel resistor that bypasses current around the amorphous volume, is added to the cell.

[0006] However, depending on the geometry of the cell and projection segments, the resistance of the cell can be highly nonlinear. In conventional "mushroom" PCM cell designs, the simulated resistance of a cell with a small (e.g., 2 nm) projection segment covering the bottom of the phase change material (GST) is highly nonlinear with the side length of the amorphous volume. Summary of the Invention

[0007] In one embodiment, a semiconductor structure is generally described, which is a resistive projection liner formed underneath a memory device, which may be a mushroom-type PCM device.

[0008] Further to this embodiment, a projection liner underneath the PCM device is formed during the sidewall electrode process scheme to provide self-aligned patterning of the resistive projection liner during the formation of the sidewall electrodes.

[0009] A structure and method are provided for forming a projection liner underneath a mushroom-shaped PCM device using a sidewall electrode process scheme to provide self-aligned patterning of the resistive projection liner during the formation of the sidewall electrodes.

[0010] In one embodiment, a memory device is provided that includes: a bottom metal electrode having a top surface; a memory cell having a bottom layer disposed above the bottom electrode and including a phase change material; a resistive projection liner element connecting to the bottom layer of the memory cell; and a metal heater element connecting the top surface of the bottom electrode to the resistive projection liner element.

[0011] The resistive projection liner element self-aligns with the metal heater element, allowing for a reduced contact surface area with the memory cell.

[0012] In another embodiment, a memory device is provided that includes: a bottom metal electrode having a top surface; a memory cell disposed above the bottom electrode and having a bottom layer including a phase change material; and a metallic heater element connecting the top surface of the bottom electrode to a bottom surface of the bottom layer of the memory cell, the metallic heater element having sidewall liner portions extending substantially vertically and horizontal liner portions extending to an edge of the bottom layer.

[0013] The horizontal liner portion extends over less than the entire length of the lower layer of the memory cell, thereby reducing the contact surface with the memory cell.

[0014] A method for fabricating a memory device is generally described, comprising the steps of depositing one or more first heater dielectric material layer structures on a semiconductor structure including one or more formed bottom metal electrodes, each first heater dielectric material structure including a sidewall edge extending in a first orientation and aligned with a respective surface of the one or more formed bottom metal electrodes; forming a metal heater layer including a portion extending vertically along the sidewall edge of each deposited first (heater) dielectric material structure and a lower portion electrically connecting to the respective surface of the one or more formed bottom metal electrodes; depositing another dielectric material layer to fill openings in a surface of the semiconductor structure defined between the sidewall edges of the one or more first heater dielectric material layer structures and planarizing its upper surface; projecting a metal heater layer onto the planarized upper surface; and depositing a metal heater layer on the planarized upper surface. depositing a projection liner layer; forming a pattern of vertically extending spacer material structures on the projection liner layer, each of the formed vertically extending spacer material structures extending in a second orientation transverse to the first orientation and overlapping the sidewall portions of the metal heater layer with their vertical extensions; and etching the projection liner layer and metal heater layer to transfer the pattern defined by the vertically extending spacer material layer to the surface of each of a plurality of one or more formed bottom electrodes such that a width of a remaining projection liner layer portion self-aligns with a width of the cut-out vertically extending sidewall metal heater layer portion above each bottom electrode in the second orientation.

[0015] The method provides a resistive projection liner element that is self-aligned to the metal heater element, allowing for a reduced contact surface area with the PCM memory cell.

[0016] Further features, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings, where like reference numbers indicate identical or functionally similar elements. [Brief explanation of the drawings]

[0017] [Figure 1A] 1A-1C are cross-sectional views of exemplary structures that may be used to form self-aligned projection liners for phase change memory cells in one embodiment.

[0018] [Figure 1B] 1B is a cross-sectional view of the resulting structure after depositing a metal liner and spacer dielectric layer on the structure of FIG. 1A.

[0019] [Figure 1C] 1C is a cross-sectional view of the resulting structure after etching back a portion of the spacer and metal liner layer on the structure of FIG. 1B.

[0020] [Figure 1D] 1D is a cross-sectional view of the resulting structure after depositing another protective dielectric cap and dielectric material fill on the structure of FIG. 1C and performing CMP on top.

[0021] [Figure 1E] FIG. 1E is a top view layout view of a resulting structure corresponding to the structure of FIGS. 1E-1 and 1E-2 used to form a self-aligned projection liner for a phase change memory cell.

[0022] [Figure 1E-1] 1D is a cross-sectional view of the resulting structure taken along section XX of the structure formed after depositing a thin projection liner layer and laterally oriented mandrel structures on the structure of FIG. [Figure 1E-2] FIG. 1E-1 is a view taken along cross section YY of the formed structure of FIG.

[0023] [Figure 1F-1] 1E-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after depositing a layer of dielectric spacer material on the structure of FIG. 1E-1. [Figure 1F-2]FIG. 1F-1 is a view taken along cross section YY of the formed structure of FIG.

[0024] [Figure 1G-1] 1F-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after etching back a portion of the dielectric spacer material layer in the structure of FIG. 1F-1. [Figure 1G-2] FIG. 1G-1 is a view taken along cross section YY of the formed structure of FIG.

[0025] [Figure 1H-1] 1G-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after removing the laterally oriented mandrel structures in the structure of FIG. 1G-1. [Figure 1H-2] 1H-1 is a view taken along cross section YY of the formed structure of FIG.

[0026] [Figure 1I-1] 1H-1 is a cross-sectional view of the resulting structure taken along cross section XX of the structure formed after pattern transfer to form a self-aligned projection liner on the structure of FIG. 1H-1. [Figure 1I-2] FIG. 1I-1 is a view taken along cross section YY of the formed structure of FIG.

[0027] [Figure 1J-1] 1I-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after depositing another dielectric fill material on the structure of FIG. 1I-1. [Figure 1J-2] FIG. 1J-1 is a view taken along cross section YY of the formed structure of FIG.

[0028] [Figure 1K-1] 1J-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after depositing material layers for forming a PCM cell on the structure of FIG. [Figure 1K-2]FIG. 1K-1 is a view taken along cross section YY of the formed structure of FIG.

[0029] [Figure 1L-1] 1L-1 is a cross-sectional view of the resulting structure taken along cross section XX of the structure formed after patterning and etching the PCM cell in the structure of FIG. 1L-1. [Figure 1L-2] 1L-1 is a view taken along cross section YY of the formed structure of FIG. 1L-1.

[0030] [Figure 1M-1] 1L-1 is a cross-sectional view of the resulting structure taken along section XX of the structure formed after forming the top electrode connections to the PCM cells in the structure of FIG. 1L-1. [Figure 1M-2] FIG. 1M-1 is a view taken along cross section YY of the formed structure of FIG.

[0031] [Figure 2] FIG. 2 is a three-dimensional view of the resulting PCM cell with a self-aligned projection liner according to the first embodiment.

[0032] [Figure 3A] FIG. 10 is a diagram of the resulting PCM cell with a self-aligned projection liner extending along the length of the PCM cell. [Figure 3B] FIG. 10 is a diagram of the resulting PCM cell with a self-aligned projection liner that extends less than the length of the PCM cell.

[0033] [Figure 4A] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4B]10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4C] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4D] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4E] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4F] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4G] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4H] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4I]10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4J] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4K] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4L] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. [Figure 4M] 10A-10C are three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication steps for a PCM cell including a self-aligned heater metal liner integration scheme resulting in a semiconductor PCM structure having self-aligned sidewall metal heater and top metal heater portions according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0034] The present application will now be described in more detail by reference to the following discussion and the drawings that accompany this application. It should be noted that the drawings in this application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0035] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, those skilled in the art will understand that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0036] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that it may be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0037] Conventionally, to mitigate resistance drift in resistive memory cells such as PCM cells, a parallel resistor is added to the cell to bypass current around the amorphous volume.

[0038] Depending on the geometry of the PCM cell and the projection segment, the resistance of the PCM cell can be highly non-linear.

[0039] The present disclosure provides a projection liner integration scheme for sidewall electrode PCM cells. In embodiments, a patterned projection liner is formed when the width of the projection liner is etched at the same time as the heater is etched, forming a self-aligned projection liner.

[0040] In mushroom-type PCM cell designs, the present disclosure provides a projection liner integration scheme in which the projection liner can be self-aligned with the cell alignment, i.e., can be significantly thinner than a non-self-aligned projection liner, resulting in a larger dynamic range. Because liners typically significantly reduce dynamic range, self-aligned projection liners enable a larger switching window with drift mitigation. A large switching window combined with low drift is a key success factor in analog artificial intelligence (AI) applications.

[0041] 1A-1M1-2 illustrate cross-sectional views showing a sequence of semiconductor fabrication MOL and BEOL process steps of a self-aligned projection liner integration scheme that results in a semiconductor PCM structure that includes an additional self-aligned projection liner, according to a first embodiment. In this embodiment, the projection liner array is formed during the formation of the PCM cells without the use of a separate mask set, eliminating the need to pattern and etch the projection liner separately from the processing of the PCM.

[0042] FIG. 1A illustrates a cross-sectional view of an exemplary structure 100 that can be used as a basis for forming a PCM cell structure using a self-aligned projection liner integration scheme, according to one embodiment. The initial structure 100 is formed in a MOL or BEOL semiconductor manufacturing process for fabricating conductive traces, contacts, insulating material layers, metal levels, and the like that can interconnect previously formed individual devices such as transistors, capacitors, resistors, and the like (not shown). The starting structure 100 can include a stack of one or more dielectric layers 105, which, from bottom to top, includes a first dielectric layer 101, e.g., SiN, SiON, SiOCN, and similar materials, and a second interlevel dielectric level layer or dielectric cap layer 102. The second insulator layer 102 can be composed of a dielectric material such as silicon dioxide, silicon nitride, silicon carbide nitride, or other types of low-k dielectric materials. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0; all dielectric constants are measured under vacuum (unless otherwise specified herein). In one embodiment, the interlevel dielectric layer 102 may be a tetraethoxysilane (TEOS) or fluorinated tetraethyl orthosilicate (FTEOS) material, or other materials such as SiOCH or SiOC. Such dielectric films may be deposited using plasma enhanced physical vapor deposition (PECVD).

[0043] Formed within the dielectric layer stack 105 are a plurality of bottom electrodes 108 for eventual connection to the PCM cells, each bottom electrode 108 having a surface 128 that is coplanar with the top surface 107 of the interlevel dielectric layer 102. The metal bottom electrodes 108 may be composed of a metal such as graphite, copper, tungsten, Pt, Ru, Ni, or other metal or metal alloy suitable for forming electrodes that connect to other conductors / devices (not shown). The bottom electrode metal material structures 108 may be formed by photolithographic patterning, etching, and deposition processes including, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes.

[0044] 1A further illustrates the results of material deposition, photolithographic mask patterning, and etching processes to form each dielectric heater structure 120A, 120B on surface 107, covering a portion of each bottom electrode surface 128. In the non-limiting embodiment shown in FIG. 1A, each dielectric heater structure 120A overlaps and covers approximately one-half of the surface that is each electrode top surface 128, leaving approximately one-half of the surface 128 of each bottom electrode 108 exposed. In one embodiment, structure 100 of FIG. 1A results from depositing a dielectric heater material layer (not shown) and using a photolithographic mask patterning process and a plasma etching, dry etching, or ion beam etching, or laser ablation process to form openings 125 so that the remaining dielectric heater layer portions 120A, 120B cover a portion of each bottom electrode surface 128 on top of layer stack 105. In one embodiment, reactive-ion etching (RIE) is used to form openings that result in pre-formed dielectric heater layer portions 120A, 120B, each portion having inner sidewalls 133. The deposited dielectric heater layer portions 120A, 120B may be composed of a dielectric material such as silicon nitride (SiN), silicon carbide nitride, or other types of dielectric heater materials, e.g., high-k dielectrics such as Al2O3, HfO2, La2O3, AlN, etc.

[0045] FIG. 1B is a cross-sectional view of the resulting structure 130 formed after further deposition of a heater metal layer 135 and an overlying protective spacer layer 140 on the structure of FIG. 1A. As shown, a sidewall electrode process is applied to deposit heater metal 135 over the top surfaces of the first-deposited dielectric heater layer portions 120A, 120B, conforming to the inner sidewalls 133 and covering the exposed top surface 107 of the ILD layer 102, including portions extending over and electrically connecting to each remaining exposed surface of each bottom electrode. Heater metal layer 135 can be deposited to a thickness ranging between 6 nm and 8 nm; however, the heater metal layer thickness can range between 2 nm and 10 nm. A deposited protective spacer material layer 140 overlies heater metal layer 135 and is deposited to a thickness ranging anywhere between 10 nm and 30 nm. Without limitation, both layers 135, 140 may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. Metal heater materials may include, but are not limited to, W, Ti, TiN, or other liner metals or metal nitrides such as TaN, Ru, WOx, TeAsGeSiSe-based OTS, etc. Protective spacer materials may include, but are not limited to, oxide or nitride insulators such as silicon oxide, silicon nitride, or silicon oxynitride. Exemplary protective spacer materials may include SiN, AlN, Al2O3.

[0046] FIG. 1C is a cross-sectional view of a resulting structure 155 formed after structure 130 of FIG. 1B undergoes an RIE or plasma etching process to etch back a portion of spacer material layer 140 and a portion of heater metal material layer 135. FIG. 1C shows the remaining etched-back spacer material layer portions 148 and the remaining etched-back heater metal material portions 145 disposed along the sidewall edges 133 of dielectric heater layer portions 120A, 120B. The heater is etched back a distance that ensures that the lower portions of heater metal material portions 145 fully contact the underlying electrode 108 and do not extend beyond the edges of the underlying electrode 108. An opening 155 is formed as a result of the etching, exposing a surface of interlevel dielectric layer 102.

[0047] FIG. 1D is a cross-sectional view of the resulting structure 160 formed after depositing a protective cap layer 162 and a fill dielectric material 165 inside the opening 155 of the structure 150 of FIG. 1C. The protective cap layer 162 can be of a dielectric material such as a nitride dielectric composed of Si, C, H, and N, e.g., SiN, SiCHN, or a combination thereof, and can be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition processes. The fill dielectric material layer 165 can include a tetraethyl orthosilicate (TEOS) dielectric material layer 165 using a CVD, PECVD, or PVD process. The structure can then undergo a chemical mechanical polishing (CMP) process to planarize the top surface of the structure 160 of FIG. 1D and adjust the height of the heater metal layer 145 to match the desired heater electrode height. In one embodiment, the heater metal structure 145 can be of a height ranging between 20 nm and 200 nm.

[0048] 1E shows a top-down layout view of a portion of several physical intermediate PCM cell structures 200, including the formed interlevel dielectric stack and bottom electrodes. The top-down layout view of FIG. 1E shows an intermediate structure for forming several PCM cells 200, including bottom electrodes 108A, 108B, 108C, and 108D resulting from previous MOL and BEOL processing steps (not shown). The intermediate PCM cell structures 200 shown result from processing steps up to and including the steps performed that result in the structure shown in FIGS. 1E-1 and 1E-2, which are used to form self-aligned projection liners for phase-change memory cells.

[0049] Specifically, FIG. 1E-1 shows a cross-sectional view of the resulting structure taken along section XX of the structure formed after depositing a thin projection liner layer, a protective dielectric cap layer, and laterally oriented mandrel structures on the structure of FIG. 1D. Specifically, FIG. 1E-1 shows the resulting structure 202 formed after further depositing a projection liner material layer 175 on the top surface of the structure 160 of FIG. 1D. That is, after applying a CMP process to adjust the height of the heater metal material portion 145, the projection liner layer 175 of the liner material is deposited using a CVD, PVD, or ALD process. In one embodiment, the projection liner layer 175 may be deposited to a thickness ranging between 1 nm and 10 nm. As further shown, a protective dielectric cap layer 177 having a thickness ranging between 10 nm and 100 nm is further deposited on the projection liner layer 175. The projection liner layer 173 may be any type of metal nitride liner or metal liner material. The protective dielectric cap layer 175 can be any dielectric material, for example, SiN.

[0050] 1E-2 shows a view taken along the YY cross section of the formed intermediate PCM cell structure 202 shown in FIG. 1E-1. Specifically, FIG. 1E-2 shows a cross section of the resulting structure formed after further mask patterning and subsequent deposition of a projection liner layer 175, a protective dielectric cap layer 177, and a mandrel material structure 180 using a CVD, PVD, or ALD process. In one embodiment, the top surface of the dielectric cap layer 177 of structure 202 is patterned with a mask, mandrel material is deposited, and the mask is removed to form mandrel structure 180, which is oriented transversely to the orientation of the heater metal layer 145 on the top surface of structure 160 in FIG. 1D between two adjacent electrodes (e.g., bottom electrodes 108B, 108C) along the YY direction. Conventional semiconductor photolithography masking and etching techniques are used to create a mandrel material structure 180 having a width that defines two edges 181, each overlapping an adjacent bottom electrode, e.g., electrodes 108B, 108C. The deposited mandrel material structure 180 may be of amorphous silicon (a-Si) material. Other types of mandrel materials may include, but are not limited to, bottom anti-reflection coating (BARC), outer plexiform layer (OPL), SiO2, SiOC, AlN, Al2O3, TiN, and TaN.

[0051] FIG. 1F-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, which shows the resulting structure 210 formed after further deposition of a spacer material layer 190 on the exposed sidewall and top surfaces of structure 202 of FIGS. 1E-1 and 1E-2. That is, after depositing mandrel layer 180, a deposition process is performed to deposit spacer material layer 190 on the remaining exposed surfaces.

[0052] FIG. 1F-2 shows a view taken along cross section YY of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E after further deposition of a spacer material layer 190 on all exposed top surfaces of structure 202 in FIGS. 1E-1 and 1E-2. Spacer material layer 190 can be of a material such as AlN, Ti2O3, SiN, TiN, SiO2, SiOC, Al2O3, etc. As shown in FIG. 1F-2, spacer material layer 190 completely covers the exposed sidewall and top surfaces of mandrels 180 and cap layer 177 overlying the dielectric heater material layer 120 adjacent each side of the metal heater structure and heater metal 145.

[0053] 1G-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 corresponding to the layout shown in FIG. 1E, showing the resulting structure 220 formed after further processing to pattern and etch back the deposited spacer material layer 190. That is, after depositing the spacer material layer 190 completely covering the exposed surfaces of the mandrels 180 and cap layer 177, a dry or RIE etching process is performed to remove the portions of the spacer material layer 190 above the mandrel structures 190 while leaving thin sidewall spacer portions 191 on each side of the mandrel material layer 180.

[0054] FIG. 1G-2 shows a view taken along cross section YY of the formed structure of FIG. 1G-1 after etching back the deposited spacer material layer 190. The spacer material layer 190 can be etched back to remove all of the spacer material above the mandrel structures 190, while leaving thin sidewall spacer portions 191 on either side of the mandrel material layer 180. As shown in FIG. 1G-2, each respective thin sidewall spacer portion 191 is vertically aligned with a respective bottom electrode, e.g., electrodes 108B, 108C.

[0055] 1H-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, showing the resulting structure 230 formed after further processing to remove (pull out) the mandrels. That is, a mask patterning and dry etching (e.g., RIE) or plasma etching process is performed to remove the mandrel structures 180 from the surface of the cap layer 177 between the sidewall spacers 191, leaving the sidewall spacers 191.

[0056] Figure 1H-2 shows a view taken along cross section YY of the formed structure of Figure 1H-1 after removal of mandrel structure 180. As seen in Figure 1H-2, etching removes the mandrel structure while leaving pre-formed sidewall spacers 191 aligned with each face of each bottom electrode, e.g., electrodes 108B, 108C.

[0057] FIG. 1I-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, showing the resulting structure 240 formed after further processing to transfer the spacer pattern defined by the spacers 191 by etching the structure to cut out the heater structures 145. That is, mask patterning and a dry or plasma etching process are performed to remove those portions of the cap layer 177, projection liner 175, and heater metal structures 145 in the pattern defined by the spacers 191.

[0058] FIG. 1I-2 shows a view taken along cross section YY of the formed structure of FIG. 1I-1 after transferring the spacer pattern 195 defined by the spacers 191 by etching the structure to cut out the heater structures 145. As seen in FIG. 1I-2, a dry or plasma etching (e.g., RIE) process removes portions of the heater structures in a manner that self-aligns each heater with each sidewall spacer 191 and further aligns each bottom electrode, e.g., electrodes 108B, 108C. That is, when the width of the projection liner 175 is etched at the same time that the heater metal 145 is etched, a patterned projection liner is formed, forming a self-aligned projection liner.

[0059] 1I-1 and 11-2 show the results of further applying a lithographic patterning and RIE etching step to transfer the pattern formed by the sidewall spacers 191, which forms cuts 196 on either side of the dielectric heaters 120A, 120B that stop at what is the underlying dielectric layer surface 107, and forms trenches or openings 197 that stop at what is the bottom electrode surface 128. In one embodiment, the lithographic patterning step may include forming photoresist (not shown) over the surfaces of the spacers 191 and cap layer 177, exposing the photoresist to radiation in a desired pattern, and then developing the exposed photoresist using a conventional resist developer. The pattern in the photoresist is then transferred through the cap layer 177 and portions of the underlying projection liner 175 and heater metal structure 145, stopping at the surface of the bottom electrode. This further etching step to etch and remove the cap layer 177, the projection liner 175, and the portions of the heater metal structure 145 between the spacers 191 is selective to the underlying coplanar bottom electrode surface 128 and / or dielectric material layer material surface 107, thereby resulting in the structure 240 shown in Figures 1I-1 and 1I-2.

[0060] FIG. 1J-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, illustrating the resulting structure 250 formed after further processing to deposit and etch back protective spacers on the sides of the heater structure 145. That is, mask patterning and a CVD, PVD, or ALD process are performed to deposit a protective spacer material layer in the cuts 196 and openings 197 formed as a result of the spacer pattern transfer etch to cut out the heater in structure 240 of FIGS. 1I-1 and 1I-2. A dry or plasma etching process is then performed to remove the remaining sidewall spacers 191 with an etching process that is selective to the surface of the projection liner 175.

[0061] 1J-2 shows a view taken along cross section YY of the formed structure of FIG. 1J-1, illustrating the result of performing a CVD, PVD, or ALD process to deposit a protective spacer material layer 255 on the sides of the cut-out heater structure 145. Another step, such as CMP, is applied on top of the projection liner 175 to planarize the protective spacer material layer 255 and the surface 258 of the projection liner 175.

[0062] FIG. 1K-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, illustrating the resulting structure 300 formed after further processing to deposit the phase change material of the PCM cell. As shown in FIG. 1K-1, in one or more embodiments, a phase change material layer 302 may first be deposited using a CVD, PVD, or ALD process. The deposited phase change material may include chalcogenide glasses such as, but not limited to, germanium-antimony-tellurium (Ge2Sb2Te5) (GST), SbTe, and In2Se3. A further deposition process is performed to provide another metal nitride top electrode layer 304 on the GST layer 302. In one embodiment, the top electrode is composed of a metal or metal alloy material such as TaN, Ta, TiN, or W, formed by a CVD process. The method further includes depositing a hard mask layer 306 on the top electrode layer 304. Depending on these deposition processes, one or more phase change memory (PCM) cells can be formed. The thickness of the formed PCM cell layer can range between 3 nm and 800 nm. Figure 1K-2 shows a view taken along the YY cross section of the formed structure of Figure 1K-1.

[0063] FIG. 1L-1 shows another view taken along cross section XX of the formed intermediate PCM cell structure 200 of the layout shown in FIG. 1E, illustrating the resulting structure 320 formed after further processing of patterning a mask and etching the structure 300 of FIG. 1K-1 to physically separate the PCM cell layers 302, 304, and 306 into two individual PCM cells. This process includes forming trenches 350 having width dimensions corresponding to the desired dimensions of each PCM cell to be formed. The trenches are etched to expose a top surface 375 of the underlying interlevel dielectric fill layer 165. In one embodiment, one or more etching processes selective to the interlevel dielectric fill layer 165 are performed to form the trenches 350 by removing portions of the PCM layers 302, 304, and 306 and corresponding portions of the underlying projection liner layer 175. The formed trenches serve to separate and form each PCM cell structure 375A, 375B that connects to a corresponding sidewall heater structure 145A, 145B, which in turn connects to each adjacent bottom electrode, e.g., electrode 108A, 108B.

[0064] Figure 1L-2 shows a view taken along cross section YY of the formed structure of Figure 1L-1. As shown, as a result of etching structure 300 of Figure 1K-1, each edge of the stack including GST layer 302, top electrode layer 304 (e.g., TiN, W, TaN, Ru, a-C+metal, GST+metal, Co, etc.), and hard mask layer 306 is recessed to form cells of desired width dimensions.

[0065] FIG. 1M-1 shows another view taken along cross section XX of the final PCM cell structure according to the layout shown in FIG. 1E, showing the resulting structure 380 formed after further processing, including patterning and depositing an encapsulating dielectric material 392, such as SiN, and an interlevel dielectric layer 390, for example a low-k dielectric (ILD), such as a tetraethyl orthosilicate (TEOS) material, to encapsulate each PCM cell structure 375A, 375B, and finishing by forming top metal electrode contacts 395A, 395B connecting to the top electrode layer 304 of each respective PCM cell structure 375A, 375B.

[0066] FIG. 1M-2 shows a view taken along cross section YY of the formed structure of FIG. 1M-1. In the embodiment shown in FIG. 1M-2, there is a single PCM cell having a top electrode layer 304 connected to a single top electrode contact 395 and one GST layer, which is connected to two connecting sidewall metal heaters, e.g., sidewall metal heaters 145B, 145C, corresponding to the bottom electrodes 108B, 108C to which it is connected. In such a configuration, the circuitry can be controlled to turn on only one heater at a time to carry current to the common GST layer. It is contemplated that a single bottom electrode and one sidewall metal heater can be aligned to the GST layer of a single PCM cell.

[0067] FIG. 2 shows a three-dimensional view of the resulting PCM cell with a self-aligned projection liner. This three-dimensional view provides a final PCM cell structure 400 with an additional projection liner segment 405 electrically connected to the bottom electrode 408 by the sidewall heater electrode formed as a result of the sidewall electrode process and acting as a parallel resistor to bypass current around the amorphous volume of the PCM cell's GST layer. In the final PCM cell structure 400 of FIG. 2, the sidewall metal heater segment 410 has a connecting resistive projection liner segment 405 with a width that self-aligns to the width of the heater electrode. That is, the projection liner is patterned such that the width of the projection liner is etched simultaneously with the etching of the sidewall heater metal layer, thereby forming a self-aligned projection liner. In the embodiment shown in FIG. 2, the length of the resistive projection liner segment 410 is substantially equal to the length of the PCM memory cell bottom layer.

[0068] FIG. 3A shows a diagram of the resulting PCM cell 450 having an additional self-aligned projection liner structure 455 formed to extend along the entire length L of the PCM cell's bottom layer 452, electrically connected to and self-aligned with the heater electrode 460. FIG. 3B shows a diagram of the resulting PCM cell 475 having a self-aligned projection liner 456 formed to extend over a length less than (<) the entire length L of the bottom layer 452 PCM cell. As shown, the structure 475 in FIG. 3B includes a self-aligned projection liner 456 portion that extends from where the heater electrode 460 connects to the projection liner to the edge of the bottom layer 452 PCM cell. In one embodiment, the self-aligned projection liner 456 portion extends to the edge of the bottom PCM cell layer over a length that is approximately half the length of the bottom layer 452.

[0069] 4A-4M show three-dimensional cross-sectional views illustrating a sequence of semiconductor fabrication MOL and BEOL process steps of a self-aligned projection liner integration scheme resulting in a semiconductor PCM structure including an additional self-aligned projection liner according to a second embodiment.

[0070] FIG. 4A is a three-dimensional cross-sectional view of an exemplary structure 500 that can be used as a basis for forming a PCM cell structure using a self-aligned projection liner integration scheme, according to one embodiment. The initial structure 500 is identical to the structure 100 of FIG. 1A formed in a MOL or BEOL semiconductor fabrication process for fabricating conductive wiring, contacts, insulating material layers, metal levels, etc., that may interconnect previously formed individual devices such as transistors, capacitors, resistors, etc. (not shown). The starting structure 500 can include a stack 105 of one or more dielectric layers, which, from bottom to top, includes a first level of dielectric layers, including, for example, but not limited to, a first dielectric layer 101, a material including, for example, but not limited to, SiN, SiON, SiOCN, and a second interlevel dielectric level layer or dielectric cap layer 102. The second insulator layer 102 can be composed of a dielectric material such as silicon dioxide, silicon nitride, silicon carbide nitride, or other types of low-k dielectric materials. The term "low-k" as used throughout this application refers to a dielectric material having a dielectric constant less than 4.0; all dielectric constants are measured under vacuum (unless otherwise specified herein). In one embodiment, the interlevel dielectric layer 102 may be a tetraethoxysilane (TEOS) or fluorotetraethylorthosilicate (FTEOS) material. Such dielectric films may be deposited using plasma-enhanced physical vapor deposition (PECVD).

[0071] Formed within the dielectric layer stack 505 are a plurality of bottom electrodes 108 for eventual connection to the PCM cells, each bottom electrode 108 having a surface 128 that is coplanar with the top surface 107 of the interlevel dielectric layer 102. The metal bottom electrodes 108 may be composed of a metal such as graphite, copper, tungsten, Pt, Ru, Ni, or other metal or metal alloy suitable for forming electrodes that connect to other conductors / devices (not shown). The bottom electrode metal material structure 108 may be deposited by, but is not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes.

[0072] 4B is a three-dimensional cross-sectional view of an exemplary structure 510 resulting from performing further material deposition, photolithographic mask patterning, and etching processes to form each dielectric heater structure 120 on surface 107, covering a portion of each bottom electrode surface 128. As shown in FIG. 4A, in one embodiment, each structure 120A overlaps and covers approximately one-half of the surface that is each electrode top surface 128, leaving approximately one-half of the surface 128 of each bottom electrode 108 exposed. In one embodiment, structure 510 of FIG. 1B results from depositing a dielectric heater material layer (not shown) and using a photolithographic mask patterning process and plasma etching, dry etching, or ion beam etching, or laser ablation process to form openings 125 that result in the remaining dielectric heater layer portions 120A, 120B covering a portion of each electrode surface 128 on top of layer stack 505. In one embodiment, reactive ion etching (RIE) is used to form openings resulting in pre-formed dielectric heater layer portions 120, each portion having inner sidewalls 133. The deposited dielectric heater layer portions 120 may be composed of a dielectric material such as silicon nitride (SiN), silicon carbide nitride, or other types of dielectric heater materials, e.g., TEOS, SiOC, SiOCN.

[0073] 4C is a three-dimensional cross-sectional view of the exemplary structure 520 resulting from performing further processing steps to deposit a heater metal layer 535 and deposit an overlying protective spacer layer 540 on the deposited metal heater layer 535. As shown, the heater metal 535 is deposited to cover the top surfaces of the deposited dielectric heater layer portions 120A, 120B and to include sidewall portions 536 conforming to the inner sidewalls 133 of the dielectric heater layer portions, and includes portions 537 covering the exposed top surface 107 of the ILD layer 102, including covering the electrical connections between each of the remaining exposed surfaces of the bottom electrodes. The metal heater layer 535 can be deposited to a thickness ranging between 6 nm and 8 nm; however, the heater metal layer thickness can range between 2 nm and 10 nm. A deposited protective spacer material layer 540 overlies the heater metal layer 535 and is deposited to any thickness ranging between 10 nm and 30 nm. Both layers 535, 540 may be deposited by, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. Metal heater materials may include, but are not limited to, W, Ti, TiN, TaN, Ru, OTS, or other metals or metal nitrides. Protective spacer materials may include, but are not limited to, oxide or nitride insulators such as silicon oxide, silicon nitride, or silicon oxynitride. Other protective spacer materials may include Al2O3, AlN, SiOCN, Ge-Se-based ovonic threshold switching materials such as Sb and N doping of Se-rich Ge-Se.

[0074] Figure 4D is a three-dimensional cross-sectional view of an example structure 550 that results from performing an additional RIE or plasma etching process on structure 520 of Figure 4C to etch back spacer material layer 540, but avoiding etching back heater metal material layer 535. Figure 4D shows the remaining heater metal material layer 535 disposed along sidewall edges 133 of dielectric heater layer portions 120A, 120B. As a result of the etching process, openings 555 are formed, exposing surfaces 546 of metal heater layer 535.

[0075] 4E is a three-dimensional cross-sectional view of an exemplary structure 560 resulting from further depositing a protective cap layer 562 and a fill dielectric material 565 within opening 155 and over all exposed surfaces of structure 550 of FIG. 4D. Protective cap layer 562 may be of a dielectric material such as a nitride dielectric composed of Si, C, H, and N, e.g., SiN, SiCHN, or a combination thereof, and may be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition processes. Fill dielectric material layer 565 may include tetraethyl orthosilicate (TEOS) dielectric material layer 165 using a CVD, PECVD, or PVD process.

[0076] Figure 4F is a three-dimensional cross-sectional view of an example structure 570 resulting from performing a further processing step of depositing a hard mask layer 572 over the structure 560 of Figure 4E. The hard mask material may include metal nitrides such as SiN, or other materials such as Al2O3, AlN, HfO2, TiN, aC, etc. The structure 570 of Figure 4F may then undergo a chemical mechanical polishing (CMP) process to planarize the top surface.

[0077] Figure 4G is a three-dimensional cross-sectional view of an exemplary structure 575 resulting from performing further processing steps of deposition, photolithographic mask patterning, and etching processes to form mandrel structures 580. In one embodiment, the top surface of hard mask layer 572 of structure 570 is patterned with a mask, mandrel material is deposited, and the mask is removed to form mandrel structures 580 that are oriented laterally relative to the orientation of heater metal layer 535 on the top surface of dielectric heater 120A structure of Figure 4D. Using conventional semiconductor photolithographic masking and etching techniques results in a width of mandrel material structure 580 that defines two edges 581, each overlapping an adjacent bottom electrode 108 that is oriented laterally relative to the orientation of the heater metal and dielectric layers. The deposited mandrel material structure 580 can be of amorphous silicon (a-Si) material or other similar mandrel dielectric materials such as BARC (bottom antireflective coating), OPL (outer network layer), SiO, SiOC, AlN, AlO, TiN, TaN, etc.

[0078] 4H shows another three-dimensional cross-sectional view of an exemplary structure 585 resulting from further processing steps to deposit a spacer material layer on the exposed top surface of structure 575 of FIG. 4G, and further processing to pattern and etch back the deposited spacer material layer to form spacers 590 on each side edge 581 of patterned mandrels 580. In one embodiment, a dry or RIE etching process is performed to remove portions of the deposited spacer material layer (not shown) above mandrel structures 580, while leaving thin sidewall spacer portions 590 on each side of mandrel material layer 580. Each respective thin sidewall spacer portion 590 is vertically aligned with a respective bottom electrode, e.g., electrode 108. Sidewall spacers 590 can be of materials such as AlN, TiO, or other materials such as SiN, AlO, HfO, TiN, SiOCN, etc.

[0079] 41 shows another three-dimensional cross-sectional view of exemplary structure 600 resulting from performing a further processing step to remove (pull out) mandrel structures 580. That is, a mask patterning and dry etching (e.g., RIE) or plasma etching process is performed to remove mandrel structures 580 from the surface of mask layer 572 between sidewall spacers 590 while leaving sidewall spacers 590A, 590B intact. Each remaining respective thin sidewall spacer portion 590A, 590B is vertically aligned with a respective bottom electrode of the array, e.g., electrodes 108A, 108B.

[0080] 4J shows another three-dimensional cross-sectional view of an exemplary structure 610 resulting from performing a further processing step to transfer the spacer pattern defined by the remaining vertical spacers 590A, 590B by etching the structure 600 of FIG. 4I to cut out portions of the heater layer 535 according to the pattern defined by the spacers. That is, a mask patterning and dry or plasma etching (e.g., RIE) process is performed to remove the hard mask layer 572, portions of the dielectric heater layer 120, and portions of the heater metal structure 535 between the spacers 590A, 590B, etc. The etching results in each electrode, e.g., electrodes 108A, 108B, having overlying dielectric heater layers 120A, 120B and respective metal heater layers 535, each including a metal heater sidewall portion 536 and an overlying metal heater portion 537 on the surface of the bottom electrode. The example structure 610 of FIG. 4J shows the further result of performing a further etching process to remove each of the sidewall spacers 590A, 590B, selective to the surfaces of the dielectric heater layers 120A, 120B, etc.

[0081] 4K shows another three-dimensional cross-sectional view of an example structure 620 that results from performing further processing steps to deposit and etch back a protective spacer layer 625 on each side of the metal heater 535 and corresponding dielectric heater structure, such as dielectric heater structure 120A. The example structure 620 of FIG. 3K shows the further result of performing a further CMP process to planarize the top surfaces of the protective spacer layer 625 and the metal heater liner layer 535.

[0082] FIG. 4L illustrates another three-dimensional cross-sectional view of an exemplary structure 630 resulting from performing further mask patterning, deposition, and etching processing steps to deposit the phase change material layer, top electrode layer, and hard mask layer used to form the PCM cell 700 shown in FIG. 4M. As shown in FIG. 4L, in one or more embodiments, a patterning, CVD, PVD, or ALD deposition and etching process may be used to form the phase change material layer 602. The deposited phase change material may include, but is not limited to, chalcogenide glasses such as germanium-antimony-tellurium (Ge2Sb2Te5) (GST), SbTe, and In2Se3. Further patterning, deposition, and etching processes are performed to form another metal nitride top electrode layer 604 on the GST layer 602. In one embodiment, the top electrode is composed of a metal or metal alloy material such as TaN, Ta, TiN, or W, formed by a CVD process. The method further includes patterning, depositing, and etching a hard mask layer 606 over the top electrode layer 604. Depending on these deposition processes, one or more phase change memory (PCM) cells are formed. Furthermore, in forming the PCM cell structure 630 shown in FIG. 4L, after further photolithographic mask patterning, the PCM cell layer is etched down to the dielectric heater level. This process results in a PCM cell having an underlying metal heater 535, which serves as a projection liner segment for contacting the overlying lower GST layer of the PCM cell. The metal heater layer 535 includes a sidewall metal heater portion 536, which further extends from the sidewall portion 536 below the GST layer 602 to the edge 611 of the PCM cell.

[0083] FIG. 4M shows a resulting three-dimensional view of the final PCM cell structure 700 formed on the bottom electrode 108, with a sidewall metal heater 536 including a metal heater segment 535 that functions as a parallel resistor to bypass current around the amorphous volume of the PCM cell's GST layer 602. In the final PCM cell structure 700 of FIG. 4M, the sidewall metal heater segment 536 has a connecting metal heater portion 535 that functions as a resistive projection liner segment with a width that self-aligns to the width of the heater element 536. That is, the metal heater portion 535 is formed using a mandrel spacer patterning process such that the width of the metal heater portion 535 is etched simultaneously with the spacer pattern transfer etch, as shown in FIG. 4J, thereby forming a self-aligned metal heater segment. In the embodiment shown in FIG. 4M, the length of the metal heater segment 535 is substantially equal to one-half the length of the PCM memory cell's bottom GST layer. The resulting PCM cell structure 700, shown in the diagram of FIG. 4M, further illustrates the results of further processing to pattern and deposit an encapsulating dielectric material 790, such as an interlevel dielectric layer of a low-k dielectric (ILD), for example, tetraethyl orthosilicate (TEOS) material, and finish it off by forming respective top metal electrode contacts 795 that connect to the top electrode layer 604 of the PCM cell structure.

[0084] The disclosed process can be used to develop 3D cross-point based resistive memory technology. In one embodiment, the method can be used to provide a projection liner that can be significantly thinner than in the non-self-aligned case, thus reducing the contact area with the PCM memory cell, which can result in a larger dynamic range. Because the liner typically significantly reduces the dynamic range, the disclosed method and structure can enable a larger switching window with drift mitigation. Smaller drift migration coupled with a large switching window are key success factors in analog AI applications.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0086] Whenever a means- or step-plus-function element appears within the scope of the following claims, the corresponding structure, material, acts, and equivalents of all such elements are intended to include any structure, material, or acts for performing that function in combination with other specifically claimed claim elements. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments have been chosen and described to best explain the principles of the invention and its practical application and to enable others skilled in the art to understand the invention in terms of various embodiments with various modifications as suited to the particular uses contemplated.

Claims

1. a bottom metal electrode having a top surface; a memory cell having a lower layer disposed above the lower electrode and including a phase change material; a resistive projection liner element connecting to the lower layer of the memory cell; and a metallic heater element connecting the top surface of the bottom electrode to the resistive projection liner element; Equipped with A memory device wherein the resistive projection liner element is self-aligned to the metallic heater element to reduce contact surface area with the memory cell.

2. The memory device of claim 1 , wherein a width dimension of the resistive projection liner conductor is substantially equal to a width dimension of the metallic heater element.

3. The memory device of claim 2 , wherein a length of the resistive projection liner conductor is substantially equal to a length of the memory cell lower layer.

4. The memory device of claim 2 , wherein the length of the resistive projection liner conductor is less than the length of the memory cell lower layer.

5. 3. The memory device of claim 2, further comprising a dielectric material heater structure having sidewall edges extending in a first orientation and aligned with a surface of the bottom metal electrode, the metal heater element having a sidewall electrode portion formed to contact the sidewall edges of the dielectric material heater structure and a bottom portion connecting to the top surface of the bottom electrode.

6. The memory device of claim 2 , wherein the bottom electrode is formed in a dielectric material layer of a semiconductor wafer.

7. 3. The memory device of claim 2, further comprising a plurality of bottom metal electrodes each having a top surface, wherein a single memory cell is disposed above and electrically connected to two bottom electrodes via respective sidewall metal heater elements.

8. a bottom metal electrode having a top surface; a memory cell having a lower layer disposed above the lower electrode and including a phase change material; a metal heater element connecting the top surface of the bottom electrode to a bottom surface of the bottom layer of the memory cell; Equipped with A semiconductor structure, wherein the metallic heater element has a sidewall liner portion extending substantially vertically and a horizontal liner portion extending to an edge of the underlying layer, the horizontal liner portion extending over a length less than the entire length of the underlying layer of the memory cell to reduce contact surface area with the memory cell.

9. 9. The semiconductor structure of claim 8, wherein width dimensions of the vertically extending sidewall liner portion and horizontal liner portion of the metallic heater element are substantially equal.

10. 10. The memory device of claim 9, further comprising: a dielectric material heater structure extending in a first orientation and having sidewall edges aligned with a surface of the bottom metal electrode, the vertically extending sidewall liner portions being formed to contact the sidewall edges of the dielectric material heater structure and including a lower portion connecting to the top surface of the bottom electrode.

11. depositing one or more first heater dielectric material layer structures over a semiconductor structure including one or more formed bottom metal electrodes, each first heater dielectric material structure including a sidewall edge extending in a first orientation and aligned with a respective surface of the one or more formed bottom metal electrodes; forming a metal heater layer including a portion extending vertically along the sidewall edge of each of the deposited first (heater) dielectric material structures and a lower portion electrically connecting to the surface of each of the one or more formed lower metal electrodes; depositing another dielectric material layer to fill openings in the surface of the semiconductor structure defined between sidewall edges of the one or more first heater dielectric material layer structures and planarizing the upper surface thereof; depositing a projection liner layer over the planarized upper surface; forming a pattern of vertically extending spacer material structures on the projection liner layer, each of the formed vertically extending spacer material structures extending in a second orientation transverse to the first orientation, the vertical extensions overlying the sidewall portions of the metal heater layer; and etching the projection liner layer and metal heater layer to transfer the pattern defined by the vertically extending spacer material layer to the surface of each of a plurality of one or more formed bottom electrodes such that a width of the remaining projection liner layer portion self-aligns with a width of the cut-out vertically extending sidewall metal heater layer portion above each bottom electrode in the second orientation.

1. A method for fabricating a semiconductor memory device, comprising:

12. depositing a protective spacer material on both sides of the cut-out metal heater layer after etching the projection liner layer and the self-aligned metal heater layer; and etching back the protective spacer material on each of the sides of the cut-out metal heater layer to define a top surface that is coplanar with a top surface of the remaining portion of the projection liner. The method of claim 11 further comprising:

13. 13. The method of claim 12, further comprising forming each phase change memory cell on the coplanar top surface over a corresponding remaining portion of each projection liner and connecting sidewall edge metal heater portion.

14. The step of forming a metal heater layer having a portion extending vertically along the sidewall layer comprises: depositing a metallic heater material over the one or more first heater dielectric material layer structures and conformally to the sidewall edges extending in a first orientation; and depositing a spacer material over the deposited metallic heater material layer; etching back the spacers and a portion of the metal heater layer to form the vertically extending sidewall portions; 12. The method of claim 11, comprising:

15. 12. The method of claim 11, further comprising performing chemical mechanical polishing to adjust the height of the metal heater sidewalls to a desired height before depositing a projection liner layer on the planarized upper surface.

16. The step of forming a pattern of a vertically extending spacer material layer in the second orientation comprises: patterning and depositing a dielectric material mandrel on the top surface of the resulting structure, the dielectric material mandrel having at least one sidewall edge extending in a second orientation transverse to the first orientation and overlapping the vertically extending heater metal layer portion; forming vertically extending spacers on the at least one sidewall edge of each of the mandrels; and removing the dielectric material mandrel while maintaining respective formed vertically extending spacers on each sidewall edge of the mandrel; 12. The method of claim 11, comprising:

17. The step of depositing a projection liner layer over the planarized upper surface is an optional step, and the method further comprises: forming a metal heater layer including another upper portion connecting to a portion extending vertically along the sidewall edge of each of the deposited first heater dielectric material structures, the upper portion extending over a surface of the first heater dielectric material structure for electrical connection to a lower surface of a formed PMC memory cell; The method of claim 11 alternatively comprising:

18. The method comprises: forming a hard mask layer on top of the formed upper portion of the deposited metal heater layer; and forming a pattern of vertically extending spacer material structures on the hard mask layer, each of the formed vertically extending spacer material structures extending in a second orientation transverse to the first orientation, the vertical extensions overlying the sidewall portions of the metal heater layer; The method of claim 17 alternatively further comprising:

19. The method comprises: and etching the portions of the hard mask layer and the metal heater layer that extend in the second orientation to transfer the pattern defined by the vertically extending spacer material layer to the surface of each of a plurality of one or more formed bottom electrodes such that a remaining top portion of the metal heater layer above each bottom electrode is self-aligned to a width of the cut-out vertically extending sidewall metal heater layer portion. The method of claim 18 alternatively further comprising:

20. The method comprises: after etching the hard mask layer and the portion of the metal heater layer extending in the second orientation, depositing a protective spacer material on both sides of the cut-out metal heater layer; and etching back the protective spacer material on both sides of each of the cut-out metal heater layers to define upper surfaces of the metal heater layers that are coplanar with an upper surface of the remaining self-aligned upper portion. The method of claim 18 alternatively further comprising:

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