Gate driver circuit and method for reducing dead time duration during switching - Patents.com

Abstract

a first gate current mirroring circuit in a sink branch of the first gate driver buffer and a second gate current mirroring circuit in a sink branch of the second gate driver buffer; a first early gate pull-up command signal issued from the first gate current mirroring circuit to the second gate driver buffer under turn-off of the first switching element prior to the pulse signal issued from the controller; and a second early gate pull-up command signal issued from the second gate current mirroring circuit to the first gate driver buffer from turn-off of the second switching element prior to the gate pull-up pulse signal issued from the controller.

Description

[Technical Field]

[0001] The present disclosure relates to a power converter comprising at least one switching half-bridge, and more precisely to reducing the dead time during the switching transitions of the switches of the switching half-bridge. [Background technology]

[0002] In a power converter consisting of at least one half-bridge, the semiconductor switching elements are controlled independently and complementary to transition from conduction to non-conduction and from non-conduction to conduction. Between these transitions, a dead time is required during which both switching elements are off, i.e., non-conducting. The dead time corresponds to a switching transition period (hereinafter referred to as the transition period), which begins with an on / off command for the first switch and ends with an off / on command for the second switch. The primary reason for introducing the dead time is that multiple factors, including propagation delays, mismatches between the turn-on and turn-off delays of the switching elements, and temperature-dependent threshold voltage drift, can cause overlapping control voltages of the power switches, potentially resulting in shoot-through currents that can damage the semiconductor switching elements. To avoid this and ensure current continuity during the dead time (DT), either the inherent reverse capability of the switching elements, such as a freewheeling diode or a body diode in the case of a MOSFET, or the third-quadrant conduction capability of a lateral gallium nitride (GaN) device, is used.

[0003] Although this reverse conduction phase is necessary, it brings about disadvantages in converter operation. To reduce the number of components and the associated costs, some power modules do not include anti-parallel diodes and rely on the reverse capability of the switching elements. However, the switching or conduction performance of these intrinsic diodes (bipolar) of the elements is often significantly lower than that of external diodes, especially Schottky barrier diodes (unipolar). Therefore, the dead time duration significantly affects the power loss of the converter.

[0004] The nonlinearity associated with the dead time also introduces distortions into the control loop. By using a lookup table, a smart control method can be implemented that shortens the dead time according to the operating point, thereby limiting the reverse conduction time as much as possible. On the other hand, this requires fast computing power, which usually necessitates a faster and more expensive controller.

[0005] Below we briefly introduce some current state-of-the-art solutions. Patent Document 1 proposes a dead time optimization circuit. In this circuit, optimization relies on several sensors that detect the gate voltage, the drain-source voltage, and the load current. The current sensor determines the direction of the output current and can define a freewheeling element. The voltage sensor mainly monitors voltage transients that depend on the load current and / or temperature. The dead time optimization is then performed by a microcontroller. Therefore, the additional sensors and microcontroller make this solution extremely complex to implement and more expensive than conventional gate drivers.

[0006] In another solution, the dead time is controlled by a logic circuit provided by a current sense FET integrated into the SiC power MOSFET switch element. The sense FET corresponds to several cells of the entire element connected externally and provides an image of the main device current proportional to the surface area ratio between the sensor and the power device. This technique accurately reports the switch state, i.e., on or off, and allows for a reduction in the dead time through the associated gating circuitry. In practice, the proposed method is very effective and robust, since the temperature dependency is inherently taken into account through the integrated sense FET. However, this method relies on expensive and highly specialized technology, and very few companies offer power devices with integrated current sensors.

[0007] Similarly, the method presented in Patent Document 2 also reduces the dead time by sensing the current flowing through the switching element. In this case, a current shunt is inserted in the switching cell. However, such sensing techniques are not recommended because they can significantly increase the stray inductance of the switching cell. This issue is more of a concern when dealing with wide bandgap (WBG) elements such as silicon carbide (SiC) and / or gallium nitride (GaN), because large stray inductances result in fast current differentiation and significant voltage overshoot.

[0008] In Patent Document 3, dead time control relies on gate current measurement, and a current transformer is placed between the two gate driver circuits to provide an opposing current between them. This results in a gate voltage derivative that is equal in amplitude but opposite in sign. The main drawback of this method is that inserting an inductive element into the gate loop can slow down switching transients.

[0009] Generally, power conversion devices require high-speed and accurate control of two semiconductor switching elements. Wide bandgap elements such as SiC or GaN have high-speed switching capabilities, which can increase the switching frequency, but this increases the constraints on control.

[0010] As explained above, commonly implemented half-bridge configurations require dead times to avoid cross-conduction and shoot-through currents, but such dead times can lead to significant additional losses or even semiconductor destruction if not properly controlled.

[0011] During the dead-time transition, one of the semiconductor devices can conduct current in reverse conduction mode. However, as discussed in Non-Patent Document 1, high losses can occur during reverse conduction mode, primarily due to poor body diode characteristics, such as high forward voltage and large reverse recovery charge. Furthermore, conduction performance can also be degraded during dead time. As an example, when using a MOSFET's body diode, the on-state voltage is significantly higher compared to a MOSFET operating in the third quadrant (conducting channel, negative current).

[0012] To mitigate the losses, an anti-parallel diode (e.g., a SiC Schottky barrier diode) with better performance (lower voltage drop and zero recovery charge) can be added and operated during the dead time. However, even if the reverse recovery problem is mitigated, additional losses due to capacitive charge still exist. This is a costly solution (because more silicon is required), generally results in a larger system (two components instead of one), and introduces additional stray inductance due to complementary wiring. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Chinese Patent Application Publication No. 106160447 [Patent Document 2] European Patent Application Publication No. 2846447 [Patent Document 3] European Patent Application Publication No. 2618486 [Non-patent literature]

[0014] [Non-Patent Document 1] R. Horff, A. Marz, and M.-M. Bakran, “Analysis of Reverse-Recovery Behavior of SiC MOSFET Body-Diode - regarding Dead-Time” in Proceedings of PCIM Europe 2015; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2015, pp. 1114-1121 Summary of the Invention [Problem to be solved by the invention]

[0015] According to the dead-time reduction methods presented above, further limitations and / or drawbacks can be identified. First, some methods are implemented through complex circuits that require additional measurements of either voltage and / or current and / or a microcontroller. While these solutions are efficient, they are not cost-effective. Furthermore, inserting a current sensor into the switching cell can degrade the power loop, potentially increasing voltage overshoot and oscillation. In some cases, the circuit degrades the gate loop, slowing the switching speed of the power converter and making the gate voltage more prone to oscillation. Additionally, while dead-time reduction can be achieved up to a certain point, shoot-through currents can occur during transition periods, potentially leading to drastic failures.

[0016] The methods and devices proposed in this disclosure are intended to reduce the dead time that is essential in voltage source converters, thus mitigating the effects of the body diode without the risk of shoot-through current. [Means for solving the problem]

[0017] More precisely, the present disclosure proposes a gate driver circuit for a half-bridge of a converter, in which a first switching element having a first gate and a second switching element having a second gate are controlled independently and complementarily via a first gate driver buffer and a second gate driver buffer, respectively, and a controller provides gate pull-up pulse signals and gate pull-down pulse signals to the first gate driver buffer and the second gate driver buffer, the gate driver circuit comprising a first gate current mirroring circuit in a sink branch of the first gate driver buffer and a second gate current mirroring circuit in a sink branch of the second gate driver buffer, and providing a first early gate pull-up command signal issued from the first gate current mirroring circuit to the second gate driver buffer under turn-off of the first switching element prior to the pulse signal issued from the controller, and a second early gate pull-up command signal issued from the second gate current mirroring circuit to the first gate driver buffer from turn-off of the second switching element prior to the gate pull-up pulse signal issued from the controller.

[0018] The use of a gate current mirroring circuit allows for an accurate representation of the gate command signal without introducing perturbations into the gate command.

[0019] The gate driver buffer associated with the current mirroring circuit can be driven by a pre-driver circuit that transfers control signals from the controller to the gate driver buffer and provides first galvanic isolation between the controller and the gate driver buffer.

[0020] This separates the controller from the gate command circuitry.

[0021] The early gate pull-up command signals of the first gate mirroring circuit and the second gate mirroring circuit are transferred via second galvanic isolation means to the second gate driver buffer and the first gate driver buffer, respectively.

[0022] This allows for early gate pull-up command signals to be provided from the upper switch to the lower switch, or vice versa, even if the upper and lower gate driver power supplies have different electrical reference connections.

[0023] The gate driver circuit may comprise, for each gate driver buffer, a mixer circuit in which the early gate pull-up command signal is combined with the gate pulse signal originating from the pre-driver after the first galvanic isolation means.

[0024] The gate driver circuit may comprise means for conditioning and / or amplifying the early command signal.

[0025] The gate driver circuit may include a reset circuit configured to reset the early gate pull-up command signal when the gate pull-up pulse signal issued from the controller occurs, and such reset circuit is provided redundantly for both the upper leg gate driver and the lower leg gate driver of the half-bridge.

[0026] The present disclosure also relates to a method for reducing dead time duration during switching of switches in a half bridge of a converter, the method including: sensing a gate current in a gate driver circuit using a current mirror during an ON-to-OFF switching transition of a first switch of the half bridge to provide a mirrored gate current signal; routing the mirrored gate current signal through a galvanic isolation circuit; adjusting the mirrored gate current signal to generate a gate pull-up command signal; and combining the gate pull-up command signal with a gate command signal of a second switch of the half bridge to provide a preceding OFF-to-ON transition of the second switch.

[0027] The method can include resetting the gate pull-up command signal when a gate activation pulse of the gate command signal occurs.

[0028] A detailed description of the disclosed exemplary embodiments is discussed below with reference to the accompanying drawings. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a schematic diagram of a conventional half bridge in a converter; [Figure 2] FIG. 2 is a schematic diagram of an example of a dead-time reduction circuit according to an embodiment of the present disclosure. [Figure 3A] 1 is a chart showing conventional dead time timing. [Figure 3B] 1 is a timing chart including dead time reduction according to the present disclosure. [Figure 3C] 1 is a chart showing conventional dead time timing. [Figure 3D] 1 is a timing chart including dead time reduction according to the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary embodiment of a dead-time reduction circuit of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0030] Figure 1 shows the upper leg switch S H and lower leg switch S L 1 is a schematic diagram of a half-bridge in a converter having a MOSFET. The upper leg switch includes a transistor Q1. The transistor Q1 is a MOSFET and is represented by its body diode D1 and its parasitic output capacitor C1. The lower leg switch includes a transistor Q2. The transistor Q2 is represented by its body diode D2 and its parasitic output capacitor C2. The reverse diodes D1 and D2 may be additional components.

[0031] The switches are controlled via gate control circuits 50a for the upper leg switch and 50b for the lower leg switch, with DC side capacitor 52 filtering HF signals generated by the switching sequence. Gate control circuits 50a, 50b comprise push-pull output transistors as known in the art.

[0032] Starting with this basic circuit diagram, the first part of this disclosure relates to a circuit whose purpose is to shorten as much as possible the time interval during which both semiconductor switching elements (hereafter referred to as switches) that are part of the switching legs implemented in any kind of voltage source converter are off, during which the continuity of the output current depends only on the reverse conduction capability of one of the two switches. The proposed method is based on the current mirror technique, where a current mirror circuit senses the gate current of one switch during the turn-off transition period, and then the mirrored current is transferred across the isolation barrier and added to the gate driver control signal of the other switch. By implementing regulation and / or buffer circuits, the dead time can be shortened in the desired way.

[0033] In order to deal with the reduction of the dead time, the turn-off transition period of the conductive element is an important point.

[0034] Assuming an initial state where one device is conducting the load current (gate voltage is high) while the other device is blocking the DC voltage (gate voltage is low), the proposed invention is only active during the transition period. The main steps are as follows: Element S in Figure 1 H When a conductive switch element such as is turned off, its gate voltage goes from a high level to a low level.

[0035] Referring to Figure 2, this is done via push-pull transistors T1, T2 of gate driver buffer 1a. By turning Q1 off in this way, gate current IG1 flows through pull-down transistor T2 of gate driver buffer 1a.

[0036] The circuit presented in Figure 2 summarizes the important features for the dead time reduction circuit. The circuits for both switches are similar and will be referred to as switch S in the following. H This section describes the circuit that drives the gate driver. The gate driver buffer 1a is a standard buffer that drives a power device through one or two gate resistors. In this case, a push-pull configuration using BJTs T1 and T2 is shown, but MOSFETs can also be used. The other part is a current mirror 2a for discharging the gate current; such a current mirror is called a sink current mirror.

[0037] In this disclosure, a switch gate driver, e.g., switch S H The sink current of the gate is mirrored by the sink mirroring circuit 2a of the gate. The sink mirroring circuit comprises transistors T4 and T6 without degrading the gate loop. The mirroring circuit resistor R MOFF The resulting current signal flowing through 21a and the collector of T6 of the mirroring circuit 2a can be sensed directly as a current or can be sensed by the mirroring circuit resistor R MOFF21a. The resulting signal, either current or voltage, is transferred to the opposite gate driver via a link including an isolation barrier 4a, a regulator and / or amplifier 5a to provide a pulse signal delayed by the regulator and / or amplifier's inherent propagation delay represented by delay circuit 8a, which is latched in set / reset circuit 7a, resulting in a delay in mixer function 6a to the opposite switch, e.g., switch S L The conditioned and latched signal, which may be amplified if necessary, precedes a controller signal issued by the controller 60 to control the gate buffer 1b to turn on the opposite switch, e.g., switch S L The set / reset circuit 7a pulls the gate voltage of the opposite switch, e.g., switch S, to a high level. This reduces the dead time during the off-to-on transition of the opposite switch. The pull-up signal is maintained at a high level until the controller signal arrives, and is released when the controller gate command signal GP2 rises. The same circuit is used to pull the gate voltage of the opposite switch, e.g., switch S, to a high level. L The switch S H Mirroring circuit 2b provides a signal at resistor 21b. This signal passes through isolation barrier 4b, is amplified by amplifier 5b, delayed by delay circuit 8b, and latched by set / reset circuit 7b. This pull-up signal provides the lead drive signal to gate buffer 1a.

[0038] The system is activated during a transition period, and the controller 60 switches on a first switch, e.g., switch S H After the switch on the opposite side, for example, switch S L When switch S starts to turn on, the preceding signal is replaced by the signal coming from controller 60, keeping the gate voltage at a high level until the next switching transition. The same process occurs for switch S L It also applies to the on-to-off transition of the switch S HThe gate of is pulled up prior to the command signal from the controller.

[0039] In the sink current mirroring circuits 2a and 2b, the base and collector electrodes of transistor T4 are shorted, so that transistor T4 is in a diode configuration. The gate current at turn-off, that is, the current flowing through the collector of T4, is equal to the V BE The corresponding base-emitter voltage (V BE ) is generated. Therefore, the current flowing through T6 is an image of the gate current. R of mirror resistors 21a and 21b MOFF is the total gate resistance (R GTot ) or less. R MOFF >R GTot In the case of , the maximum current is limited, and (V DD -V SS -V CESat ) / R MOFF becomes equal to

[0040] Typically, transistors T4 and T6 are matched transistors with the same gain (β) and share the same package. The transistors selected to design the current mirror must have the same or similar characteristics (current carrying capacity, gain-bandwidth product) as the transistors in the buffer. Current mirror circuits are not limited to BJT components.

[0041] Next, R MOFF The mirrored current signals acquired at 21a, 21b are injected into the dead time circuit via isolation elements 4a, 4b. The transferred signals can be either voltages or currents, e.g., voltages across mirror resistors 21a, 21b or currents flowing through mirror resistors 21a, 21b. Depending on the circumstances, the isolation elements can be optocouplers, current transformers, voltage transformers, or even digital isolators.

[0042] The signals EC1 and EC2 transferred through the isolation elements 4a and 4b are then amplified by the amplifiers 5a and 5b, delayed by the delay circuits 8a and 8b, latched by the latch circuits 7a and 7b, and coupled to the lower switches S L The gate pulse signal GP2 and the upper switch S H , thereby causing the lower and upper switches to turn on earlier at their respective turn-on events, thereby shortening the dead time duration.

[0043] In Figure 3A, the lower switch S L and the turn-off of the upper switch S H 1 shows a conventional switching transient during turn-on of a transistor.

[0044] At t=0, the lower switch S L Starting from the bottom switch S L The MOS Q2 is conducting the load current, and the upper switch S H MOS Q1 holds the DC voltage. At t1, it starts to turn off and S L The control signal V Ctrl2 changes from a positive value to a negative value. At t2, S L Gate-source voltage V GS2 is V DD From Miller Plateau V PLT In fact, during this time interval, the gate current I G2 is sunk by the gate buffer. During the Miller plateau, from t2 to t3, the drain-source voltage V of Q2 DS2 is 0 to V DC while the drain-source voltage of Q1 decreases accordingly. V DS1 As soon as V reaches 0, the channel current controlled by the gate voltage drops to V at t4. GS2 is the threshold voltage V TH To ensure the continuity of the output current, the body diode D1 of Q1 begins to conduct current. After a stable dead time, which is the time interval from t1 to t6, the switch S HThe control signal V Ctrl1 At t7, the body diode D1 switches from low to high. TH From t7 to t8, current flows from the body diode D1 to the channel of Q1 according to the gate voltage. The gate current I G1 Note that is supplied by the gate buffer according to the derivative of the gate voltage. As soon as Q1's channel conducts all of the output current, corresponding to t8, the switching transition period can be considered complete.

[0045] In this configuration, the theoretical dead time 210 is from t1 to t7, and the actual dead time 200 is from t4 to t7. Reverse conduction 220 of Q2 begins at t3 and ends at t8, and V DS2 is changed from 0 to V during the crossing time 230 from t2 to t3. DC rises to.

[0046] As discussed above and shown in FIG. 3A, all switching transients are initiated by turning off the conduction element. Therefore, two reference signals can be selected to reduce the effective dead time. This can be done by measuring the gate voltage or the gate current. Using the sensed gate voltage may result in the gate loop being too high and therefore not representative of the actual voltage across the die electrode. This can result in suboptimal operation, inadequately reducing the dead time, or, in the worst case, reducing the dead time too much, resulting in shoot-through current. Therefore, this disclosure uses current sensing, a more reliable state variable than the far-field sensing method. The following illustrates the impact of the present invention on switching waveforms.

[0047] Figure 3B shows the results of current sensing for a device of the present disclosure, where the turn-off / turn-on process remains the same as in Figure 3A, with the main change being that the gate charge is proportional to the product of current and time, and the charge of device S during turn-off is proportional to the gate charge. LBy implementing the current mirror circuit of Figure 2, the power switch characteristics of the device S during turn-on are H also drives the gate current I to generate a delayed signal through the delay circuit 8a. G2 The image of this gate current I GS However, by converting this current into a voltage or by using the current directly, the upper switch S H Therefore, in Figure 3B, the V GS1 The gate voltage is determined by the corresponding signal V CTRL1 Therefore, the reverse conduction time 221 of the body diode can be significantly reduced from t3 to t7 as shown. The equivalent gate charge is such that the device being turned off always reaches the threshold voltage V before the device being turned on. TH is defined to reach

[0048] The delay circuit is V GS2 After V falls below 0V, GS1 It is adjusted to start the rise of

[0049] FIG. 3C corresponds to a conventional sequence of turning off the upper switch and turning on the lower switch.

[0050] The actual dead time 200' from t3 to t5 is delayed relative to the theoretical dead time 210' from t1 to t4, and the diode reverse conduction time 231 of Q1 starts at t2 and ends at t6.

[0051] FIG. 3D shows the effect of the dead time reduction circuit of the present disclosure, where I G1 After the existence of V at t4 GS2 begins to rise, thus reducing the reverse diode conduction time of Q1 from t2 to t6, allowing for a quicker change of conduction element from upper switch to lower switch.

[0052] FIG. 4 shows a possible implementation of the dead-time reduction circuit shown in FIG. 2 using MOS transistors.

[0053] In such a circuit, isolation between the current mirrors 2a, 2b and the dead time reduction circuitry is provided via current transformers 4a, 4b, MOS transistors 51a, 51b provide the dead time reduction signal which is mixed with the Vo+, Vo− signals originating from the pre-drivers via diodes 61a, 61b, while MOS transistors 52a, 52b amplify the output signals originating from the current transformers 4a, 4b, and MOS transistors 71a, 71b provide the reset signals originating from the pre-drivers when they activate their gates with a delay provided by capacitors 72a, 72b.

[0054] The dead time reduction circuit shown in FIG. 2 can also be implemented using bipolar transistors or logic gates.

Claims

1. a first switching element having a first gate and a second switching element having a second gate are independently and complementarily controlled via a first gate driver buffer and a second gate driver buffer, respectively, and a controller provides a gate pull-up pulse signal and a gate pull-down pulse signal to the first gate driver buffer and the second gate driver buffer, a first gate current mirroring circuit in a sink branch of the first gate driver buffer and a second gate current mirroring circuit in a sink branch of the second gate driver buffer; a first early gate pull-up command signal issued from the first gate current mirroring circuit to the second gate driver buffer under the turn-off of the first switching element prior to the pulse signal issued from the controller; a second early gate pull-up command signal from the second gate current mirroring circuit prior to the gate pull-up pulse signal from the controller to the first gate driver buffer from turning off the second switching element; A gate driver circuit comprising:

2. 2. The gate driver circuit of claim 1, wherein the gate driver buffer associated with the gate current mirroring circuit is driven by a pre-driver circuit that transfers control signals from the controller to the gate driver buffer and provides a first means of galvanic isolation between the controller and the gate driver buffer.

3. 3. The gate driver circuit of claim 1, wherein the early gate pull-up command signals of the first gate current mirroring circuit and the second gate current mirroring circuit are transferred to the second gate driver buffer and the first gate driver buffer, respectively, via second galvanic isolation means.

4. 4. The gate driver circuit of claim 3, further comprising a mixer circuit in which, for each gate driver buffer, the early gate pull-up command signal is combined with a gate pulse signal originating from a pre-driver after the second galvanic isolation means.

5. 3. A gate driver circuit as claimed in claim 1 or 2, comprising means for conditioning and / or amplifying the early gate pull-up command signal.

6. 3. The gate driver circuit of claim 1, further comprising a reset circuit configured to reset the early gate pull-up command signal when the gate pull-up pulse signal sent from the controller occurs.

7. 1. A method for reducing dead time duration during switching of switches in a half bridge of a converter, the method comprising: sensing a gate current in a gate driver circuit using a current mirror during an ON-to-OFF switching transition of a first switch of the half bridge to provide a mirrored gate current signal; routing the mirrored gate current signal through a galvanic isolation circuit; adjusting the mirrored gate current signal to generate a gate pull-up command signal; and combining the gate pull-up command signal with a gate command signal of a second switch of the half bridge to provide a preceding OFF-to-ON transition of the second switch.

8. 8. The method of claim 7, further comprising resetting the gate pull-up command signal when a gate activation pulse of the gate command signal occurs.

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