Quasi-asynchronous sampling frequency grid

Abstract

A global navigation satellite system (GNSS) receiver for processing GNSS satellite signals uses a quasi-asynchronous sampling frequency grid to process the received signals. The GNSS receiver includes a plurality of RF paths configured to receive the global navigation satellite system (GNSS) signals from an antenna and transmit the GNSS signals in a frequency band for digitizing the GNSS signals. A phase-locked loop is configured to generate a clock signal, and a plurality of clock dividers are configured to receive the clock signal and divide the clock signal. Each of a plurality of navigation systems receives the clock signal from one of the plurality of clock dividers.

Description

[Technical Field]

[0001] The present disclosure relates generally to receivers, and more particularly to receivers for processing satellite navigation signals using a quasi-asynchronous sampling frequency grid. [Background technology]

[0002] Global Navigation Satellite System (GNSS) receivers can provide navigation solutions (i.e., positioning information) provided that they reliably receive signals from the few GNSS satellites they contact. Reliable signal reception is typically only achieved under certain operating conditions, namely, open-sky environments where there are no obstructions to radio signals propagating from selected navigation satellites to the receiver's antenna. Signal reception quality degrades when antennas are blocked by natural or man-made obstructions (e.g., tall trees with dense foliage, vertical building walls, bridges, urban canyons, and structural elements of moving vehicles equipped with GNSS antennas). Consequently, the accuracy of these navigation solutions can be significantly impaired, including the complete loss of the ability to accurately provide any form of GNSS positioning. GNSS receivers must also have sufficient processing power to perform the calculations necessary to determine positioning information in a timely manner.

[0003] GNSS receivers typically process GNSS satellite signals in one clock cycle. Processing signals in one clock cycle requires significant processing power and memory storage. The large amount of processing power and memory storage required results in the use of expensive components, which increases the cost of the GNSS receiver. There is a need for a receiver that can process GNSS satellite signals at high speed using inexpensive components. Summary of the Invention [Means for solving the problem]

[0004] The navigation receiver includes multiple RF paths configured to receive Global Navigation Satellite System (GNSS) signals. A phase-locked loop is configured to generate a clock signal, and multiple clock dividers are configured to receive and divide the clock signal. Each of the multiple navigation systems receives the clock signal from one of the multiple clock dividers. Each of the multiple navigation systems includes multiple analog-to-digital converters, each configured to receive the GNSS signals. Each of the multiple navigation systems also includes multiple signal processors configured to process digitized signals, multiple decimators configured to decimate the digitized signals, multiple signal processors configured to process the decimated signals, multiple requantizers configured to convert the processed decimated signals to low-bit data, multiple navigation system-to-CPU system interface blocks (NS2CS) configured to generate packages, a MUX interconnect configured to distribute the data stream, and a time control unit configured to generate a tick signal. The navigation receiver also includes a CPU system including a memory, a multi-channel navigation direct memory access (DMA), multiple hardware accelerators, and multiple channels. The GPU system also includes a CPU configured to control the multiple navigation systems and the CPU system, and configured to process data received from the multiple channels.

[0005] In the drawings, like numbers refer to like components in different drawings. Like numbers with different subscripts represent different instances of similar components and / or signals. [Brief explanation of the drawings]

[0006] [Figure 1] 1 shows a prior art Global Navigation Satellite System (GNSS) receiver.

[0007] [Figure 2A] 1 illustrates a source clock for a GNSS receiver, according to one embodiment.

[0008] [Figure 2B] 1 illustrates a GNSS receiver according to an embodiment.

[0009] [Figure 2C] 1 illustrates a GNSS receiver according to an embodiment.

[0010] [Figure 3] 1 illustrates a navigation system communicating with a CPU system via an NS2CS interface block, according to one embodiment.

[0011] [Figure 4A] 1 illustrates a signal graph for the NS2CS interface block operating in single package mode, according to one embodiment.

[0012] [Figure 4B] 1 illustrates a signal graph for an NS2CS interface block operating in multi-package mode, according to one embodiment.

[0013] [Figure 5] 1 illustrates signals received by a multi-channel navigation direct memory access (DMA) according to one embodiment.

[0014] [Figure 6] 3 illustrates a clock that generates a clock signal, according to one embodiment.

[0015] [Figure 7] 1 illustrates a navigation channel in communication with a multi-channel navigation direct memory access (DMA), according to one embodiment.

[0016] [Figure 8A]4 illustrates package processing steps according to one embodiment.

[0017] [Figure 8B] 2B, 2C, 3, 5, and 7 operating in a fully CPU-controlled mode of operation, according to one embodiment.

[0018] [Figure 8C] 2B, 2C, 3, 5, and 7 operating in a first-time automatic mode of operation, according to one embodiment.

[0019] [Figure 9] 1 illustrates frequency reduction and energy savings according to one embodiment.

[0020] [Figure 10] 1 depicts a high-level block diagram of a computer for performing the operations of the components described herein, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] FIG. 1 shows a schematic diagram of components of a prior art navigation receiver 1 (e.g., a GNSS receiver) including a navigation system 100 that includes “A” analog-to-digital converters (ADCs), such as ADCs 101(1)...101(A). ADCs 101(1)...101(A) are collectively referred to as ADCs 101. The navigation system 100 also includes multiple signal processors that form multiple signal paths. A signal path that includes “S” signal processors is indicated by signal processors 102(1,1)...102(S,1). There are “P” signal paths, such as signal processors 102(1,P)...102(S,P). Thus, the first path is indicated by signal processors 102(1,1)...102(S,1), and the last path is indicated by signal processors 102(1,P)...102(S,P). The multiple signal processors, including signal processors 102(1,1)...102(1,P) and signal processors 102(S,1)...102(S,P), are collectively referred to as signal processor 102. Navigation receiver 1 also includes "Q" requantizers, such as requantizers 103(1)...103(Q). Requantizers 103(1)...103(Q) are collectively referred to as requantizers 103. Navigation receiver 1 shown in FIG. 1 also includes navigation channel 104, time control unit 105 that transmits tick signal S106, and CPU system 110, which includes CPU 107, bus 108, and memory 109 and receives data readiness flag signal S111.

[0022] GNSS signals received by one or more antennas (not shown) are transmitted to one or more of a plurality of RF paths connected to the input of the ADC 101. In one embodiment, the RF paths are configured to transmit the GNSS signals in a particular frequency band for digitization. In one embodiment, each of the ADCs 101 receives a signal from a corresponding one of the plurality of RF paths. In one embodiment, multiple or all of the ADCs 101 may receive a signal from a single RF path. From the output of the ADC 101, the digitized signal is input to a signal processor 102, which processes the signal.

[0023] One or more components may be used as the signal processor 102; for example, the signal processor 102 may be a filter, a noise suppressor, an equalizer, and / or a decimator, etc.

[0024] The signals output from signal processors 102(S,1)...102(S,P) are input to requantizers 103(1)...103(Q), which requantize the received data into low-bit data. The low-bit data output from requantizers 103(1)...103(Q) is input to navigation channel 104, which processes the low-bit data.

[0025] Navigation channel 104 transmits a data ready flag signal S111 to CPU 107. Data ready flag signal S111 indicates that data is ready in navigation channel 104.

[0026] Time control unit 105 generates a tick signal S106, which in one embodiment is a time scale. The period of tick signal S106 is equal to the number of clock cycles of CLKnav, which is set by CPU 107 prior to operation (as described in more detail below in conjunction with FIG. 6). CLKnav, in one embodiment, is set by CPU 107 before operation of navigation system 100 begins. Tick signal S106 is input to signal processor 102, requantizer 103, navigation channel 104, and CPU 107. A CPU clock (not shown), referred to as CLKcpu, is input to CPU 107, bus 108, and memory 109. A navigation clock (not shown), referred to as CLKnav, is input to 101, 102, 103, 104, and 105. Clocks CLKnav and CLKcpu are typically asynchronous, with the rate of CLKcpu generally being much greater than the rate of CLKnav.

[0027] The CPU 107, the memory 109, and all components of the navigation system 100 are respectively connected to a bus 108 that allows communication between the CPU 107, the memory 109, and all components of the navigation system 100. In one embodiment, when a tick signal S106 occurs, the CPU 107 receives data via the bus 108 and controls the navigation system 100 based on the received data. The memory 109 is used for data storage.

[0028] Figure 2A shows components of a source clock for a GNSS receiver comprising a phase-locked loop (PLL) 211 and "D" clock dividers 212(1)...212(D), according to one embodiment. Figure 2A shows "D" navigation systems 200(1)...200(D), each in communication with a CPU system 210. The PLL 211 is connected to each of the "D" clock dividers 212(1)...212(D). The navigation systems 200(1)...200(D) are collectively referred to as navigation systems 200. The clock dividers 212(1)...212(D) are collectively referred to as clock dividers 212.

[0029] In one embodiment, the GNSS receiver operates using a clock signal called CLKnav that is generated for use by the navigation system 200. The clock signal output from the PLL 211 is input to the clock dividers 212. Each of the clock dividers 212 can apply a different integer factor to divide the input clock. The clock signal output from each of the clock dividers 212 is input to a corresponding one of the navigation systems 200. The clock signals output from the clock dividers 212 are quasi-asynchronous, i.e., they are derived from a single clock signal (not shown) generated by the PLL 211, but are divided by different integer factors.

[0030] Signals from one or more RF paths that receive GNSS signals from one or more antennas (not shown) are input to the navigation system 200 for processing. The navigation system 200 exchanges data with a CPU system 210.

[0031] Figure 2B illustrates components of GNSS receiver 2, according to one embodiment. Figure 2B illustrates details of navigation systems 200(1)...200(D) and CPU system 210 as navigation system 200 and CPU system 210. Navigation system 200 includes a signal processing channel 214 that communicates with bus 108 of CPU system 210 via MUX interconnect 201 and "N" navigation system-to-CPU system interface blocks (NS2CS) 202(1)...202(N). NS2CS interface blocks 202(1)...202(N) are collectively referred to as NS2CS interface blocks 202.

[0032] The signal processing channel 214 includes "P+1" signal processors 102 that receive the tick signal S106 from the time control unit 105. One or more components can be used as the signal processors 102; for example, the signal processors 102 can be filters, noise suppressors, equalizers, and / or decimators. The signal processors 102(P+1) perform pre-processing before decimation at 110. The signal output from the signal processor(P+1) is input to "P" decimators 110(1)...110(P). The output of each of the decimators 110(1)...110(P) is input to a corresponding one of the "P" signal processors 102(1)...102(P). The output of each of the signal processors 102(1)...102(P) is input to a corresponding one of the "Q" requantizers 103(1)...103(Q). The "P" decimators, the "P" signal processors, and the "Q" requantizers are collectively referred to as signal processors 102, decimators 110, and requantizers 103, respectively.

[0033] The CPU system 210 includes a bus 108 that communicates with the components of the CPU system 210 and the navigation systems 200(1)...202(D). The bus 108 communicates with the "D" navigation systems 200(1)...202(D), the CPU 107, the memory 109, the "H" hardware accelerators 204(1)...204(H), the multi-channel navigation DMA 205, the "N" NS2CSs 202(1)...202(N), and the navigation channel 104. The hardware accelerators 204(1)...204(H) are collectively referred to as hardware accelerators 204.

[0034] In one embodiment, navigation system 200 operates as follows: A clock signal CLKnavS 213 is output from clock divider 212. GNSS satellite signals are received by an antenna and sent through an RF path to the input of ADC 101. From the ADC 101 output, the digitized signal enters the signal processor 102(P+1) input where it is processed. The signal processor 102(P+1) outputs a signal that is input to decimator 110 where it is decimated. From the output of decimator 110, the signal enters signal processor 102 where it is processed. The signal output from signal processor 102 is input to requantizer 103 where it is requantized to lower bit data.

[0035] In one embodiment, signal processing channel 214 (shown in FIG. 2B) can be replaced with multiple signal processing channels that process data in parallel. In one embodiment, navigation system 200 can be replaced with multiple navigation systems. In such an embodiment, each of the multiple navigation systems has its own tick signal S106, and the tick signals S106 of the navigation systems 200 are synchronous (i.e., the tick signals S106 start at the same time, last for the same amount of time, and are generated at the same instant each time).

[0036] The signals output from decimator 110, requantizer 103, ADC 101, and signal processor 102 are input to MUX interconnect 201. From MUX interconnect 201, the signals output from one or more of decimator 110, requantizer 103, ADC 101, and signal processor 102 can be input to any of NS2CS interface blocks 202 for further processing.

[0037] In one embodiment, time control unit 105 generates a tick signal S106. Tick signal S106 is used to control components and is input to decimator 110, signal processor 102, requantizer 103, CPU 107, and NS2CS interface block 202. In one embodiment, CPU 107 uses tick signal S106 to synchronize control between decimator 110, signal processor 102, requantizer 103, and NS2CS interface block 202.

[0038] The navigation clock signal (CLKnav at S213 shown as an output from clock divider 212 in FIG. 2B) and the CPU clock signal are asynchronous in one embodiment, with the frequency of CLKcpu being much higher than the frequency of CLKnav.

[0039] The CLKnav and CLKcpu clocks are generally asynchronous, with the frequency of CLKcpu being significantly higher than the frequency of CLKnav.

[0040] In one embodiment, the frequency of CPU 107 is synchronous and much higher than CLKcpu. In another embodiment, the operating frequencies of hardware accelerators 204, 205, and 104 are synchronous and significantly higher than CLKcpu.

[0041] In one embodiment, CPU 107 can write data to memory 109 for storage via bus 108. In one embodiment, CPU 107 can write data to hardware accelerator 204 for processing via bus 108. The following units can be sources of data for packaging: ADC 101, signal processor 102, requantizer 103, decimator 110, hardware accelerator 204, NS2CS interface block 202, and CPU 107.

[0042] After processing at the output of the requantizer 103, the number of samples over one time period may be different due to different decimation factors. The outputs of the requantizer 103 with the same number of samples in one time period can be collected into one stream and input to one NS2CS interface block 202 for further processing via MUX interconnect 201. After decimation at 110, the subsequent data processing (at 102, 103, 202) is synchronous and is performed with a clock slower than the clock CLKnav.

[0043] In one embodiment, each of the outputs of the requantizer 103 is connected directly to one of the inputs of the NS2CS interface block 202. The NS2CS interface block 202 can write data from the navigation system 200 to the memory 109, the hardware accelerator 204, and the CPU 107 via the bus 108.

[0044] In one embodiment, the hardware accelerator 204 may write the results of data processing to the memory 109, different ones of the hardware accelerators 204(1)...204(H), and the CPU 107 via the bus 108.

[0045] The hardware accelerator 204 may be an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) that may be embedded in an ASIC, a spectrum analyzer, or a coarse grain reconfigurable architecture (CGRA) that may be embedded in other devices. Once the data is processed, the hardware accelerator 204 generates an interrupt request (IRQ) that is sent to the CPU 107, and signal S707 (see FIG. 5) is sent to the multi-channel navigation DMA 205.

[0046] The multi-channel navigation DMA 205 reads data from memory 109 via bus 108. The multi-channel navigation DMA 205 sends the data from memory 109 to navigation channel 104, where the data is processed. After completing the operation, the multi-channel navigation DMA 205 outputs an IRQ signal S206 to the CPU 107. The multi-channel navigation DMA 205 can retrieve data from multiple memory areas simultaneously.

[0047] The CPU 107 uses the tick signal S106 and IRQs (e.g., IRQS206) from the multi-channel navigation DMA 205, the NS2CS interface block 202, and the hardware accelerator 204 to control the data stream between the multi-channel navigation DMA 205, the NS2CS interface block 202, and the hardware accelerator 204.

[0048] FIG. 2C illustrates components of a GNSS receiver 3 according to one embodiment. The components of the GNSS receiver 3 illustrated in FIG. 2C are similar to the components of the GNSS receiver 2 illustrated in FIG. 2B, although some components are not shown for clarity and new components have been added. A bus 213 is shown communicating with the NS2CS interface block 202, the bus 108, and the memory 109. In one embodiment, the GNSS signal via the antenna and RF path is input to the ADC 101. From the output of the ADC 101, the digitized signal is input to the signal processor 102(P+1) for processing. From the output of the signal processor 102(P+1), the signal is input to the decimator 110 for processing. From the output of the decimator 110, the signal is input to the signal processor 102 for processing.

[0049] From the output of signal processor 102, the signal is input to NS2CS interface block 202 where it is further processed. From the output of NS2CS interface block 202, data is written to memory 109 via bus 213, to hardware accelerator 204 via bus 108, or directly to CPU 107 via bus 108.

[0050] In one embodiment, the NS2CS 202 interface block performs pre-processing of the data, converting it into the format required by the multi-channel navigation DMA 205, CPU 107, memory 109, and hardware accelerator 204 (shown in FIGS. 2B and 2C). The data stream output from the interface block NS2CS 202 is a package.

[0051] FIG. 3 illustrates a navigation system 200 communicating with a CPU system 210 via an interface block NS2CS 202, according to one embodiment.

[0052] The interface block NS2CS 202, in one embodiment, comprises an NS2CS control unit 300 that receives a tick signal S106 from the time control unit 105. The NS2CS control unit 300 is in communication with a decimator NS2CS 301. The decimator NS2CS 301 and the MUX interconnect 201 send signals to a multiplexer 302 that is in communication with the NS2CS control unit 300. The MUX interconnect 201 sends a continuous data stream S308 to the multiplexer 302 and the decimator NS2CS 301. The signal output from the multiplexer 302 is sent to a data preparer and requantizer 303 that is in communication with the NS2CS control unit 300. The data preparer and requantizer 303 sends signals to an asynchronous asymmetric first-in-first-out (FIFO) buffer 304 (also referred to as FIFO 304) that is in communication with the NS2CS control unit 300. The asynchronous asymmetric FIFO buffer 304 sends a signal to a package manager 309, which communicates with the NS2CS control unit 300. The package manager 309 communicates with the bus 108. The bus 108 communicates with the CPU 107 and the multi-channel navigation direct memory access (DMA) 205. The multi-channel navigation DMA 205 also receives a run signal S307 from the NS2CS control unit 300.

[0053] The continuous data stream signal S308 from the MUX interconnect 201 is input to a decimator NS2CS 301, which optionally decimates the signal by different decimation factors. The signal output from the decimator NS2CS 301 is input to a data preparation and requantizer 303 via a multiplexer 302.

[0054] Data preparation and requantization 303 prepares the data and, if necessary, requantizes the data to lower bit data.

[0055] If decimation is not used, the continuous data stream signal S 308 from MUX interconnect 201 is input to multiplexer 302 and then sent to data preparation and requantizer 303 .

[0056] The data output from Data Preparation and Requantizer 303 is input to Asynchronous Asymmetric FIFO Buffer 304. The output of Asynchronous Asymmetric FIFO Buffer 304 is then input to Package Manager 309, which converts the data into packages of a predetermined number of samples.

[0057] In one embodiment, before starting operation, the NS2CS control unit 300 configures (as needed) the decimator NS2CS 301, the multiplexer 302, the data preparation and requantizer 303, the asynchronous asymmetric FIFO buffer 304, and the package manager 309. In one embodiment, decimation is used to reduce the amount of samples in a package without compromising signal quality for further processing.

[0058] In one embodiment, a package is a number of samples allocated / set by the CPU 107. A sample is data over one clock cycle CLKnav. The interface block NS2CS 202 starts generating a package according to the tick signal S106. In one embodiment, the interface block NS2CS 202 generates a package and puts it into the memory 109 (shown in Figures 2B and 2C).

[0059] In one embodiment, the data of the package may be processed in the navigation channel 104 using the multi-channel navigation DMA 205, the CPU 107, and / or the hardware accelerator 204 (shown in FIGS. 2B and 2C).

[0060] In one embodiment, the package may be generated by the CPU 107, the interface block NS2CS 202, and / or the hardware accelerator 204.

[0061] In one embodiment, the asynchronous asymmetric FIFO buffer 304 resynchronizes data from the clock CLKnav to the clock CLKcpu.

[0062] In one embodiment, during operation, interface block NS2CS202 stacks data at a predetermined address and generates an interrupt request signal S305 to CPU 107. If necessary, data is written cyclically. In another embodiment, decimator NS2CS301 is eliminated to reduce the interface block NS2CS202 space required on the ASIC.

[0063] The interface block NS2CS202 operates in two modes: single package mode and multi-package mode.

[0064] 4A shows a signal graph of interface block NS2CS 202 operating in single package mode. One package is formed in one tick period signal S106. When the package is formed, an IRQ signal S305 is generated and input to CPU 107. In this mode, CPU 107 controls the data stream using the tick signal S106 and the IRQ signals from interface block NS2CS 202 and hardware accelerators 204, 205. In one embodiment, multi-channel navigation DMA 205 forms multi-bit data signal S501 and enable signal S502 (see FIG. 7) for navigation channel 104.

[0065] FIG. 4B shows a signal graph of interface block NS2CS 202 operating in multi-package mode. Time control unit 105 generates tick signal S106, which initiates data processing. During one cycle of tick signal S106, U packages are formed. When the first package is formed and written to memory 109, signal S305 is generated. When each package is completed, run signal S307 is generated. In one embodiment, packages 1...U have the same size. In another embodiment, packages 1...U have different sizes. Based on signal S307, multi-channel navigation DMA 205 reads packages from memory 109 and forms multi-bit data signals S501 and S502 for navigation channel 104. Additional operations related to the packages are performed, if necessary. Specifically, interface block NS2CS generates signals S305 and S307 any time after writing a package to memory 109.

[0066]

[0067] 5 shows signals received by multi-channel navigation DMA 205. The signals received by multi-channel navigation DMA 205 include "N" signals from the outputs of interface blocks NS2CS 202(1)...202(N), as indicated by signals S307(1)...S307(N). The signals received by multi-channel navigation DMA 205 also include "H" run signals, as indicated by run signals S707(1)...S707(H), from the outputs of "H" hardware accelerators, as indicated by hardware accelerators 204(1)...204(H). The signals received by multi-channel navigation DMA as described above are used in initial automatic mode.

[0068] In one embodiment, signal S707 is received at multi-channel navigation DMA 205 from hardware accelerator 204. Signal S707 is sent at the end of writing a package to memory 109 (see FIGS. 2B and 2C). Signal S707 is used by multi-channel navigation DMA 205 in the same way as signal S307, and is also used in first-time automatic mode.

[0069] The multi-channel navigation DMA 205 uses signals S307 and S707 to read packages from memory 109 and simultaneously generates signals S501 and S502 (see Figures 4A, 4B, and 8) from different data sources, i.e., the NS2CS interface block 202 and / or the hardware accelerator 204.

[0070] In the navigation system 200 (as shown in FIGS. 2B and 2C), the signal is decimated by one of the decimators 110.

[0071] FIG. 6 shows one of several possible variations for the clock that generates the clock signal, referred to as the clock for decimation. The tick signal S106 has a specific tick period. The tick signal S106 is composed of multiple ClkNavs. The Clock Divider 2 signal represents a Clknav pulse divided by two. Similarly, the Clock Divider 3 signal represents a Clknav clock divided by three, and the Clock Divider 4 signal represents a Clknav clock divided by four. In one embodiment, a signal that controls the decimation is input to signal processor 102 (which is a decimator in this variation). In one embodiment, the tick signal S106 is used by all components (for all clock divisions) simultaneously (for all decimation factors).

[0072] When decimation is used, the number of samples at the input of the interface block NS2CS 202 is reduced, thereby reducing the size of the package. In one embodiment, the NS2CS interface block converts the received digitized signal into packages having a pre-set or specified size.

[0073] 7 illustrates a navigation channel in communication with the NS2CS CPU system 210 of FIG. 2B, according to one embodiment. As shown in FIG. 7, the navigation channel 104, in one embodiment, includes at least one channel 500. The channel 500 receives "D" signals, such as signals S501(1)...S501(D) and S502(1)...S502(D), from the multi-channel navigation DMA 205 and includes a code rate NCO (CRNCO) 503, a code generator 506, a strobe generator 508, an integration time counter 510, an intermediate frequency NCO (IFNCO) 512, a correlator 515, and a commutator 516. The transmitted and / or received signals include a code rate signal S504, a code phase signal S505, a code signal S507, a strobe signal S509, an integral time (IP) signal S511, a cosine signal S513, a sine signal S514, and an output signal S517 from the commutator.

[0074] In one embodiment, navigation channel 104 is comprised of multiple channels. FIG. 8 illustrates one of the multiple channels, channel 500. In one embodiment, a package can contain data from one or more data sources. Data from different sources can be combined into one package with the same number of samples over a period of time. Low-bit data received from the outputs of different requantizers 103 (shown in FIG. 2B) is multiplexed into a single multi-digit word and input to assigned interface block NS2CS 202 to generate a common package, which is sent to memory 109 for storage. Multi-channel navigation DMA 205 reads the packages from memory 109 and converts the data from requantizers 103(1)...103(Q) (shown in FIG. 2B) into "D" signals, as indicated by signals S501(1)...S501(D) and enable signals S502(1)...S502(D). Data from each of the requantizers 103(1)...103(Q) is transmitted as signals S501(1)...S501(D), respectively. Signals S501(1...D) and S502(1...D) are provided from 205 to the inputs of a commutator 516. Signals S501(1) and S502(1) are used simultaneously. Signals S501(D) and S502(D) are used simultaneously. With the help of the commutator 516, the CPU 107 connects the channel 500 to the required signals S501(i) and S502(i), where "i" is any number from 1...D. When signal S502(i) is active, processing of data S501(i) in channel 500 is enabled. When signal S502(i) is inactive, processing of data S501(i) in channel 500 is stopped.

[0075] In one embodiment, multi-channel navigation DMA 205 transmits one package to navigation channel 104 while the next package is being generated. In one embodiment, multi-channel navigation DMA 205 operates several packages in parallel and transmits them to navigation channel 104 while the next package is being generated. CPU 107 controls multi-channel navigation DMA 205 via bus 108. Prior to operation, CPU 107 adjusts multi-channel navigation DMA 205 to operate in one of several modes.

[0076] The multi-channel navigation DMA 205 can operate in the following modes: a fully CPU controlled operating mode and a first-run automatic mode.

[0077] In the full CPU control mode according to one embodiment, the CPU 107 controls the multi-channel navigation DMA 205 and the channel 500. In one embodiment, the full CPU control mode is used only when the interface block NS2CS 202 operates in the single package mode. The time control unit 105 generates a tick signal S106 that sets the amount of data to be processed. The interface block NS2CS 202 operates in the single package mode. When a package is formed, a signal S305 is generated. In accordance with the signal S305, the CPU 107 writes a control command to the navigation channel 104, and then, in accordance with the command from the CPU 107, the multi-channel navigation DMA 205 transmits the package (or multiple packages). When the package (or multiple packages) is transmitted, the multi-channel navigation DMA 205 generates a signal S206. The CPU 107 reads data from the navigation channel 104 based on the signal S206. The advantage of this mode is that the CPU 107 itself can determine to which block the data is to be transmitted, making the sequence of data processing more flexible.

[0078] In one embodiment, in first-time automatic mode, CPU 107 controls 205 and channel 500, and multi-channel navigation DMA 205 itself transmits packages to channel 500 using signals S307 (shown in FIGS. 7 and 5) and S707 (shown in FIG. 5). In one embodiment, first-time automatic mode is used only when interface block NS2CS 202 operates in multi-package mode. Time control unit 105 generates tick signal S106, which sets the amount of data to be processed. After the first package is completely transmitted, signal S305 is generated. CPU 107 transmits a control command to navigation channel 104 according to signal S305, and multi-channel navigation DMA 205 transmits the package according to the CPU command. At the end of each package, multi-channel navigation DMA 205 executes according to run signal S307, and the package is transmitted to navigation channel 104. After the last package, multi-channel navigation DMA 205 generates signal S206 based on the current tick signal S106. CPU 107 reads data from navigation channel 104 in accordance with signal S206. The advantage of this mode is that the smaller the package, the less memory required. In addition, this mode requires less control from the CPU, so it consumes less power.

[0079] Once the package is complete, multi-channel navigation DMA 205 reads the package from memory 109 and generates multi-bit data signal S501 and enabling signal S502. When data signal S501(1) is sent through commutator 516 and active S502(1), S501(1) is sent to current channel 500 and processed there. When data signal S501(D) is sent through commutator 516 and active S502(D), S501(D) is sent to current channel 500 and processed there. Multi-channel navigation DMA 205 reads a package (multiple packages) from memory 109 and converts the data into signal S501 and enabling signal S502.

[0080] In full CPU control mode, the multi-channel navigation DMA 205 generates an IRQ signal S206 corresponding to the period of the tick signal S106 at the end of the package after the data has been sent to the channel 500.

[0081] The multi-channel navigation DMA 205 in the initial automatic mode generates an IRQ signal S206 once for several packages when it finishes sending data to the channel 500, and the IRQ signal S206 corresponds to the period of the tick signal S106.

[0082] Signals S501(1)...S501(D) and S502(1)...S502(D) are transmitted from multi-channel navigation DMA 205 to inputs of commutator 516. CPU 107, in conjunction with commutator 516, connects channel 500 to signals S501(i) and S502(i), where i is any number from 1 to D.

[0083] If, while the multi-channel navigation DMA 205 is reading a package from memory 109, signal S502 indicates that there is not enough or sufficient time to prepare the next data or S501 has ended, the channel 500 stops processing data for this period.

[0084] The navigation channel 104 consists of a set of channels 500. The CPU 107 controls and acquires data from the channels 500 via the bus 108. In the channels 500, each sample from the package is processed with one clock CLKcpu.

[0085] In one embodiment, the period of tick signal S106 is shorter than the period of integration time signal S511.

[0086] The configuration of channel 500 is a set of settings defined for a selected processing mode of GNSS signals, e.g., the parameters are the selected signals S501(i) and S502(i) in 516 and the configuration of code generator 506.

[0087] In one embodiment, CPU 107 configures, controls, and acquires data from channel 500 when multi-channel navigation DMA 205 is not transmitting data signal S501. Prior to operation, CPU 107 sets the current configuration of channel 500 components and parameters, such as the code frequency and initial code phase in code rate NCO 503, code generator 506, strobe generator 508, duration of integration time signal S511 in integration time counter 510, intermediate frequency and initial code phase in intermediate frequency NCO 512, and commutator 516. In one embodiment, multi-channel navigation DMA arranges data readiness in multiple channels based on the integration time signal, and the CPU reads the data after processing the data.

[0088] In one embodiment, channel 500 processes input signal S501(i) from the beginning to the end of the package.

[0089] CRNCO 503 generates a code frequency signal S504 that is input to code generator 506 and integral time counter 510. Code generator 506 generates a code signal S507 at the rate of signal S504. Code signal S507 is input to strobe generator 508 and correlator 515. CRNCO 503 generates a code phase signal S505 that is input to strobe generator 508. Strobe generator 508 uses signals S507 and S505 to generate a strobe signal S509 that is input to correlator 515. IFNCO 512 generates a cosine (Cos) signal S513 and a sine signal S514 having an intermediate frequency. Signals S513 and S514 are input to correlator 515. From commutator 516, signal S517 is input to correlator 515. Integration time counter 510 generates integration time signal S511 based on code rate signal S504. Integration time signal S511 is input to correlator 515 and multi-channel navigation DMA 205. In one embodiment, signal S517 is signal S501(i).

[0090] In correlator 515, signal S517 is multiplied by Cos signal S513 and code signal S507, and the multiplication result is accumulated over integral time signal S511. According to integral time signal S511, the accumulated value is stored in buffer register 1 (component I shown below), and CPU 107 takes this value as needed and the accumulated value is set to zero.

number

[0091] In the correlator 515, the signal S517 is multiplied by the Sin signal S514 and the code signal S507, and the multiplication result is accumulated over the integration time signal S511. According to the signal S511, the accumulated value is stored in the buffer register 2 (component Q shown below), and the CPU 107 takes this value as needed and sets the accumulated value to zero.

number

number

number

[0092] Before processing according to signal S501(i), CPU 107 may control / change parameters of channel 500, including changing the code frequency in CRNCO 503, setting the code phase shift in CRNCO 503, changing the intermediate frequency in IFNCO 512, and setting the intermediate frequency phase shift in IFNCO 512.

[0093] The operation of strobe generator 508 is described in US Pat. No. 7,764,226 B1, the disclosure of which is incorporated herein by reference in its entirety.

[0094] FIG. 8A shows the package processing steps, which are explained as follows.

[0095] Signals S305, S307, and S707 indicate to multi-channel navigation DMA 205 that there is a new package in memory 109. CPU 107 uses a combination of signals S106, S206, S305, S307, and S707 to control the GNSS signals processed in channel 500. Package processing by multi-channel navigation DMA 205 includes the following steps. The table below describes the package processing steps. The number column in the table indicates that the last digit of the number in FIG. 8A is associated with the particular step (i.e., labels 9112, 9212, and 9312 are each associated with a configuration step, labels 9113, 9213, and 9313 are each associated with a control step, etc.). [Table 1]

[0096] In one embodiment, when a new package is formed, all steps required for each current configuration must be completed.

[0097] In the full CPU control mode, the configuration step and the control step are controlled by the CPU 107. In the configuration step and the control step, the CPU 107 controls the channel 500 before sending a package to the channel 500. The read step is controlled by the CPU 107. In the read step, the CPU 107 processes the package in the channel 500 and then reads ready data from the channel 500. The multi-channel navigation DMA 205 generates an IRQ signal S206 after processing the package (after the processing step).

[0098] In the initial automatic mode, the configuration step and the control step are controlled by the CPU 107. In the configuration step and the control step, the CPU 107 controls the channel 500 before the first package formed over the tick signal S106 is sent to the channel 500. The read step is controlled by the CPU 107. In the read step, the CPU 107 reads ready data from the channel 500 after the channel 500 processes the last package generated in the tick signal S106 period. The multi-channel navigation DMA 205 generates the IRQ signal S206 after the channel 500 processes the last package generated in the tick signal S106 period (after the processing step).

[0099] In one embodiment, the following steps are performed in the following order:

[0100] Configuration steps: For multiple channels 500, the configuration steps (e.g., step 9**2 shown in FIG. 8A) can be used one after the other. When new GNSS signal processing needs to be performed, the channel 500 is set to the new configuration. The channel 500 can also stop GNSS signal processing if necessary.

[0101] Control steps: In the case of multiple channels 500, the control steps (eg, step 9**3 shown in FIG. 8A) are used one after the other. Control commands are sent to the channels 500 as needed.

[0102] Processing Steps: The processing steps (e.g., step 9**4 shown in FIG. 8A) are applied simultaneously (in parallel) for all channels 500. A package (represented by signal S501) is transmitted simultaneously to all channels 500. Each channel 500 processes its own package received as signal S501(i).

[0103] Read steps: If necessary, for multiple channels 500, use the read step (e.g., step 9**5 shown in FIG. 8A) in sequence. When signal S511 is available in multi-channel navigation DMA 205, ready data is read from channel 500 by CPU 107.

[0104] In one embodiment, CPU 107 can temporarily suspend operation of 205 after signal S206 and read data from channel 500 without using multi-channel navigation DMA 205, if desired.

[0105] In one embodiment, because channel 500 does not process a previously configured current configuration and CPU 107 does not set one or more new current configurations for channel 500, multi-channel navigation DMA 205 does not send a package to channel 500 (i.e., multi-channel navigation DMA 205 skips all steps) and generates signal S206.

[0106] The use of the CPU 107 in the configuration and control steps in the CPU Full Control mode and First Time Automatic mode ensures synchronicity of the control of all channels 500 .

[0107] In Figure 8A, steps with a shaded background are inactive (i.e., not used). In one embodiment, the time for package generation is equal to the period of the tick signal S106 (see Figure 4A).

[0108] In one embodiment, channel 500(1) processes signal S501(i) in its current configuration, Configuration 1. In the Configuration 1 configuration, data packages are processed in a pipeline mode similar to the operation of channel 500 in a typical GNSS receiver (FIG. 1).

[0109] In one embodiment, configuration 1 is configured as follows: in tick 1 9100, the current configuration is set, GNSS signals are processed, and data is read if necessary, and in tick 2 9200 and tick 3 9300, GNSS signals continue to be processed and data is read if necessary.

[0110] In FIG. 8A, the steps are performed in the following order:

[0111] When the first tick signal S106 (ie, tick 1 9100) occurs, the following steps are performed: configuration 9112 sets configuration 1, process 9114, and read 9115.

[0112] When the second tick signal S106 (ie, tick 2 9200) occurs, the following steps are performed: control 9213, process 9214, and read 9215 for configuration 1.

[0113] When the third tick signal S106 (ie, tick 3 9300) occurs, the following steps are executed: control 9313 for configuration 1, processing 9314, and CPU read 9315.

[0114] Note that in one embodiment, in single GNSS signal processing mode, channel 500 always operates in a current configuration corresponding to configuration 1.

[0115] FIG. 8B shows a diagram of multi-channel navigation DMA 205 operation (shown in FIGS. 2B, 2C, 3, 4A, and 7) in full CPU control mode.

[0116] The package corresponds to the tick S106 period. In the full CPU control mode, the CPU 107 uses the tick signals S106, S305, and S206 to fully control the GNSS signal processing using the multi-channel navigation DMA 205 to control the configuration step, control step, and read step. The interface block NS2CS 202 starts forming a package based on the tick signal S106. The CPU 107 receives the signal S305 and performs the configuration step and the control step. In the processing step, the multi-channel navigation DMA 205 transmits the package to the navigation channel 104 by command CPU 107. The multi-channel navigation DMA 205 ends the package transmission and generates the signal S206. The CPU 107 receives the signal S206 and performs the read step. After that, all steps are repeated cyclically.

[0117] In one embodiment, FIG. 8C shows a diagram of multi-channel navigation DMA 205 operation in initial automatic (four packages formed per tick period) mode.

[0118] Over the period of the tick signal S106, four packages are formed (e.g., in multi-package mode). In the initial automatic mode, the processing of package 2 and package 3 does not require any control from the CPU 107. After processing package 4, the CPU 107 receives signal S206 and reads the ready data from channel 500. The NS2CS 202 starts forming packages with the tick signal S106. The CPU 107 receives signal S305 and performs configuration and control steps. In the processing step, the multi-channel navigation DMA 205 sends package 1 to the navigation channel 104 with a command from the CPU 107. In the processing step, the multi-channel navigation DMA 205 sends package 2, package 3, and package 4 to the navigation channel 104 with signal S307. The multi-channel navigation DMA 205 ends by sending package 4 and generates signal S206. The CPU 107 receives signal S206 and performs the read step. All steps are then repeated cyclically.

[0119] In one embodiment, Figure 9 illustrates frequency reduction and energy savings according to an embodiment using a quasi-asynchronous sampling frequency grid in which packages having a duration of 0.8 ms are transmitted. The NS2CS interface block 202 forms four packages. Figure 9 will be described in conjunction with the components shown in the other figures.

[0120] PLL 211 generates a clock signal with a frequency of 225 MHz. This clock signal output from PLL 211 is input to divider clock 212(1) and divider clock 212(2). Divider clock 212(1) has a division factor of 1, so the clock from the PLL passes through unchanged. The clock frequency at the output of divider clock 212(1) is 225 MHz. Divider clock 212(2) has a division factor of 2, so the clock from the PLL is divided by 2. The clock frequency at the output of divider clock 212(2) is 112.5 MHz.

[0121] The clock signal output from divider clock 212(1) is input to navigation system 200(1). ADC 101 in navigation system 200(1) digitizes the signal received from the RF path, output at a frequency of 225 MHz.

[0122] The clock signal output from the divider clock 212(2) is input to the navigation system 200(2). The ADC 101 of the navigation system 200(2) digitizes the signal received from the RF path, which is output at a frequency of 112.5 MHz.

[0123] In navigation system 200(1), decimator 110(1) has a decimation factor of 4. Samples with a frequency of 225 MHz are input to decimator 110(1), which outputs samples with a frequency of 56.25 MHz. Interface block NS2CS 202(1) (as shown in Figures 2B, 2C, and 3) generates package 1, which is equal to 45,000 samples for 0.8 ms.

[0124] In navigation system 200(1), decimator 110(2) has a decimation factor of 6. Samples with a frequency of 225 MHz are input to decimator 110(2), which outputs samples with a frequency of 37.5 MHz. Interface block NS2CS 202(2) generates package 2, which is equal to 30,000 samples for 0.8 ms.

[0125] In the navigation system 200(1), the decimation factor in the decimator 110(3) is 3. Samples with a frequency of 225 MHz are input to the decimator 110(3), which outputs samples with a frequency of 75 MHz. The interface block NS2CS202(3) generates package 3, which is equal to 60,000 samples for 0.8 ms.

[0126] In the navigation system 200(2), the decimation factor in the decimator 110(4) is 2. Samples with a frequency of 112.5 MHz are input to the decimator 110(4), which outputs samples with a frequency of 56.25 MHz. The interface block NS2CS202(N) generates package 4, which is equal to 45,000 samples for 0.8 ms.

[0127] Package 1...Package 4 are formed over the same time period. The number of samples in package 1 is equal to the number of samples in package 4. The number of samples in package 1, package 2, and package 3 are different.

[0128] Package 1...Package 4 are processed by multiple channels 500 simultaneously. In channel 500, each sample in a package is processed with one pulse of clock signal CLKcpu. Processing package 1 and package 4 requires 45,000 pulses of clock signal CLKcpu. Processing package 2 requires 30,000 pulses of clock signal CLKcpu. Processing package 3 requires 60,000 pulses of clock signal CLKcpu. In channel 500, clock CLKcpu becomes valid when channel 500 processes data S501(i) from 205.

[0129] The use of decimator 110 and divider clock 212 in navigation system 200 reduces the frequency of GNSS signal processing, which leads to reduced power consumption and a smaller package size due to the reduced number of samples. The reduced package size due to the reduced number of samples leads to faster processing times for packages using channel 500, reduced energy consumption, and smaller memory sizes being used.

[0130] The navigation system 200 processes GNSS signals in a pipeline mode using a clock signal CLKnav and generates packages using the NS2CS interface blocks 202, providing great flexibility in GNSS signal processing. In one embodiment, each of the NS2CS interface blocks generates packages one after the other without losing data. The formation of packages is related to the tick signal S106. The packages are further processed in the CPU system 210 based on the clock signal CLKcpu.

[0131] In one embodiment, the GNSS receiver architecture comprises a plurality of clock dividers 212 utilized to reduce power consumption, a plurality of navigation systems 200, and a plurality of decimators 110. In the navigation systems 200, the processed and decimated signals are converted into packages by a plurality of NS2CS interface blocks. The interface block NS2CS writes the packages to memory 109. The packages in the interface block NS2CS are formed simultaneously but have different numbers of samples due to the decimation.

[0132] After the package generation is complete for a period of time, multi-channel navigation DMA 205 reads the generated package from memory 109 and transmits it to navigation channel 104 .

[0133] Packages in the navigation channel 104 can be processed in the following modes: a fully CPU controlled operating mode and a first-run automatic mode.

[0134] In one embodiment, in full CPU control mode, CPU 107 controls all processes and the package is equal to the period of tick signal S106.

[0135] In one embodiment, in the first-time automatic mode, CPU 107 controls the processing for several packages, specifically, once during the period of tick signal S106. In this mode, the size of the package is reduced in several steps, reducing the storage space required in memory 109. Interface block NS2CS 202 automatically notifies multi-channel navigation DMA 205 of the readiness of a new package, and multi-channel navigation DMA 205 automatically enables transmission of part of the package to navigation channel 104. Multi-channel navigation DMA 205 reads the package from memory 109 and transmits it to navigation channel 104.

[0136] The use of the clock divider 212 and decimator 110 reduces the processing frequency of the GNSS signals in the navigation system 200 and also reduces the package size from the NS2CS interface block 202. Reducing the package size reduces the processing time in the navigation channel 104, which in turn reduces the power consumption of the GNSS receiver.

[0137] In one embodiment, some NS2CS interface blocks 202 bypass bus 108 and write data to memory 109 via bus 213. This reduces the load on bus 108 and allows packages to be written to memory 109 with minimal delay.

[0138] In one embodiment, a computer is used to perform the operations of the components and equations described herein and shown, for example, in FIGS. 2A, 2B, 2C, 3, 5, and 7. The components may be, for example, an ADC, a signal processor, a requantizer, etc. A high-level block diagram of such a computer is shown in FIG. 10. The computer 1102 includes a processor 1104 that controls the overall operation of the computer 1102 by executing computer program instructions that define such operations. The computer program instructions may be stored on a storage device 1112 or other computer-readable medium (e.g., a magnetic disk, a CD-ROM, etc.) and loaded into memory 1110 when execution of the computer program instructions is desired. Thus, the method steps described herein may be defined by computer program instructions stored in memory 1110 and / or storage 1112 and controlled by the processor 1104 executing the computer program instructions. For example, the computer program instructions may be implemented as computer-executable code programmed by one skilled in the art to perform an algorithm defined by one of the various methods described herein. Thus, by executing the computer program instructions, the processor 1004 performs the algorithms defined by the method steps described herein. The computer 1102 also includes one or more network interfaces 1106 for communicating with other devices over a network. The computer 1102 also includes input / output devices 1108 (e.g., a display, a keyboard, a mouse, speakers, buttons, etc.) that allow a user to interact with the computer 1102. Those skilled in the art will recognize that an actual computer implementation may include other components, and that Figure 10 is a high-level representation of some of the components of such a computer for illustrative purposes.

[0139] The foregoing detailed description should be understood in all respects to be illustrative and not restrictive, and the scope of the inventive concepts disclosed herein should be interpreted in accordance with the full breadth permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concepts, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the inventive concepts. Various other feature combinations could be implemented by those skilled in the art without departing from the scope and spirit of the inventive concepts.

Claims

1. a plurality of RF paths configured to receive GNSS signals; a phase locked loop configured to generate a clock signal; a plurality of clock dividers configured to receive the clock signal and divide the clock signal; a plurality of navigation systems, each of the plurality of navigation systems receiving a clock signal from one of the plurality of clock dividers, each of the plurality of navigation systems operating on CLKnav; a plurality of analog-to-digital converters (ADCs), each configured to receive a GNSS signal from a corresponding one of the plurality of RF paths and generate a digitized signal; a plurality of signal processors configured to process the digitized signals; a plurality of decimators configured to decimate the digitized signals; a plurality of signal processors configured to process the decimated signals; a plurality of requantizers configured to convert the processed decimated signals into lower-bit data; a plurality of navigation system-CPU system (NS2CS) interface blocks configured to generate packages of a predetermined size based on the low-bit data; a MUX interconnect configured to distribute the data stream; a time control unit configured to generate a tick signal that is a time scale; a plurality of navigation systems, A CPU system that operates based on the tick signal, wherein each navigation system communicates with the CPU system, and the CPU system operates on CLKcpu; a memory configured to store data and the package; a multi-channel navigation direct memory access (multi-channel navigation DMA) configured to convert the package into data; a plurality of hardware accelerators configured to process the packages; a plurality of channels configured to process data received from the multi-channel navigation DMA; a CPU configured to control the plurality of navigation systems and the CPU system and configured to process data received from the plurality of channels; a CPU configured to synchronize control among the plurality of decimators, the plurality of signal processors, the plurality of requantizers, the plurality of NS2CS interface blocks, the plurality of hardware accelerators, the plurality of channels, and the multi-channel navigation DMA; a CPU system comprising: A navigation receiver comprising:

2. The navigation receiver of claim 1 , wherein outputs of the plurality of requantizers are input to the plurality of NS2CS interface blocks via the MUX interconnect.

3. 2. The navigation receiver of claim 1, wherein each of the plurality of NS2CS interface blocks writes a package to the memory and generates an interrupt for the CPU, and the CPU processes the interrupts from the plurality of NS2CS interface blocks.

4. The navigation receiver of claim 1 , wherein each of the plurality of NS2CS interface blocks writes a package to the memory and generates a run signal.

5. 2. The navigation receiver of claim 1, wherein each of the plurality of NS2CS interface blocks initiates the formation of a package based on the tick signal and resynchronizes data from clock signal CLKnav to clock signal CLKcpu.

6. The navigation receiver of claim 1 , wherein each of the plurality of NS2CS interface blocks generates one package over a period of the tick signal.

7. The navigation receiver of claim 1 , wherein each of the plurality of NS2CS interface blocks generates a plurality of packages in the period of the tick signal.

8. 10. The navigation receiver of claim 1, wherein simultaneously formed packages contain different numbers of samples of low-bit data.

9. 2. The navigation receiver of claim 1, wherein the multi-channel navigation DMA reads simultaneously formed packages from the memory from the multiple NS2CS interface blocks, converts the packages to data, and transmits the data and enabling signals to the multiple channels.

10. 10. The navigation receiver of claim 9, wherein each of the plurality of data from the multi-channel navigation DMA has its own enable signal.

11. a channel commutator that receives data transmitted for the plurality of channels from the multi-channel navigation DMA, wherein each data is processed in the channel if a selected enable signal is available; The navigation receiver of claim 9 further comprising:

12. 2. The navigation receiver of claim 1, wherein the multi-channel navigation DMA reads packages from the memory in response to a signal from the CPU.

13. The navigation receiver of claim 4 , wherein the multi-channel navigation DMA reads packages from the memory based on a run signal.

14. 2. The navigation receiver of claim 1, wherein the multi-channel navigation DMA regulates data readiness in the multiple channels based on an integration time signal, and the CPU reads the data after processing the data.

15. 2. The navigation receiver of claim 1, wherein the CPU reads data from the plurality of channels and transmits a current configuration of the channels and control of the channels while processing packages.

16. The navigation receiver of claim 1 , wherein the CPU and the plurality of NS2CS interface blocks access the memory via a common bus or a dedicated bus.

17. 10. The navigation receiver of claim 9, wherein when the last package is formed in a current cycle of the tick signal, the multi-channel navigation DMA sends an interrupt request signal to the CPU, and the CPU processes the interrupt request signal.

18. 2. The navigation receiver of claim 1, wherein data from the output of the requantizers forming the same number of samples in one time period are converted into packages by one NS2CS.

19. 2. The navigation receiver of claim 1, wherein the decimated signal is processed with a reduced clock synchronized to a clock signal CLKnav.

20. 2. The navigation receiver of claim 1, wherein a channel clock CLKcpu becomes valid when the channel has processed data from the multi-channel navigation DMA.

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