Enhanced adhesion between low-k dielectric materials and cap layers

Abstract

An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be positioned within the processing region. The method may include forming a layer of low-k material on the semiconductor substrate. The method may include purging the processing region of the one or more deposition precursors. While purging the processing region, a plasma power may be maintained at about 750 W or less. The method may include forming an interfacial layer on the layer of low-k material. The method may include forming a cap layer on the interfacial layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 896,716, filed Aug. 26, 2022, entitled "ADHESION IMPROVEMENT BETWEEN LOW-K MATERIALS AND CAP LAYERS," the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to semiconductor processing and materials, and more particularly to enhancing adhesion between low-k materials and cap layers. [Background technology]

[0003]

[0003] Integrated circuits are realized by processes that produce intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires controlled methods for forming and removing materials. The properties of the materials can affect the operation of the device and can also affect how films are removed from one another. Plasma-enhanced deposition can produce films with specific properties. The desired properties of a film can vary depending on its application.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. This and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary semiconductor processing method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber. A semiconductor substrate may be positioned within the processing region. The method may include forming a layer of low-k material on the semiconductor substrate. The method may include purging the processing region of the one or more deposition precursors. A plasma power may be maintained at about 750 W or less while purging the processing region. The method may include forming an interfacial layer on the layer of low-k material. The method may include forming a cap layer on the interfacial layer.

[0006] In some embodiments, the semiconductor substrate may be maintained at a temperature of about 550° C. or less during the semiconductor processing method. The method may include purging the processing region of one or more deposition precursors. While purging the processing region, a plasma power may be maintained at about 750 W or less. The method may include stopping the flow of the one or more deposition precursors before forming the interfacial layer. The method may include supplying an oxygen-containing precursor to the processing region before forming the interfacial layer. A flow rate of the oxygen-containing precursor may be about 750 sccm or less. The method may include densifying the layer of low-k dielectric material while purging the processing region of the one or more deposition precursors. An adhesion value between the layer of low-k dielectric material and the cap layer is about 3.0 J / m 2 It could be more than that.

[0007] Some embodiments of the present technology include a semiconductor processing method. The method may include forming a layer of low-k material on a semiconductor substrate housed in a processing region of a semiconductor processing chamber. Plasma power may be maintained at a first plasma power level while forming the layer of low-k material. The method may include purging the processing region. Plasma power may be maintained at a second plasma power level while purging the processing region. The second plasma power level may be less than or equal to the first plasma power level. The method may include forming an interfacial layer on the layer of low-k material. The method may include forming a cap layer on the interfacial layer.

[0008] In some embodiments, the semiconductor substrate may include silicon. The layer of low-k dielectric material may be formed through plasma-enhanced chemical vapor deposition. The interfacial layer may be characterized by a lower methyl content than the layer of low-k dielectric material. The method may include supplying molecular oxygen to the processing region while purging the processing region. The method may include reducing a flow rate of one or more precursors used to form the layer of low-k dielectric material before purging the processing region. The temperature and pressure in the processing region during formation of the layer of low-k dielectric material may be maintained while forming the interfacial layer. The method may include reducing a flow rate of a carrier gas before purging the processing region.

[0009] Some embodiments of the present technology include a semiconductor structure. The structure may include a semiconductor substrate. The structure may include a layer of low-k dielectric material disposed on the semiconductor substrate. The structure may include a cap layer formed above the layer of low-k dielectric material. The structure may include an interfacial layer disposed between the layer of low-k dielectric material and the cap layer. An adhesion value between the layer of low-k dielectric material and the cap layer is about 4.0 J / m 2 That's all.

[0010] In some embodiments, the interfacial layer can be part of the layer of low-k dielectric material. The interfacial layer can be characterized by a lower methyl content than the layer of low-k dielectric material. The interfacial layer can be characterized by a higher oxygen concentration than the layer of low-k dielectric material.

[0011] Such techniques may offer numerous advantages over conventional systems and techniques. For example, process structures may form an interfacial layer between the low-k material and the cap layer. Furthermore, the formation of the interfacial layer may enhance adhesion between the low-k material and the cap layer while not substantially affecting device performance. The enhanced adhesion may reduce and / or eliminate the possibility of the cap layer delaminating from the low-k material during subsequent processing. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2]

[0014] 1 shows a schematic cross-sectional view of an exemplary plasma system in accordance with some embodiments of the present technique; [Figure 3]

[0015] 1 illustrates selected steps in a fabrication method according to some embodiments of the present technique. [Figure 4]

[0016] 1A-1C show exemplary schematic cross-sectional structures that include layers of material and are fabricated in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0017] Some drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to be drawn to scale unless specifically stated. Additionally, the figures are provided as schematic diagrams to aid understanding and may not include all aspects or information compared to actual depictions and may include material unnecessary or emphasized for illustrative purposes.

[0015]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numerals, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description may apply to any of the similar components having the same first reference numeral, whatever its letter.

[0016]

[0019] During back-end-of-line (BEOL) semiconductor processing, low-k dielectric films can serve multiple functions in the fabrication of metallization layers within integrated circuits. These functions may include incorporating electrically insulating low-k dielectric films between conductive metal-containing structures, such as interconnect lines, contact holes, and vias, among other structures. These functions may also include partially removing low-k dielectric films after the formation of metal structures. One common removal process in BEOL is chemical-mechanical polishing (CMP), which uses a combination of chemical etching and physical abrasion to remove low-k dielectric materials from the substrate surface. In some applications, a cap layer may be formed over the low-k dielectric film to further protect the low-k dielectric film.

[0017]

[0020] However, capping layers can face a number of challenges, which can be exacerbated by shrinking feature sizes. For example, the capping layer can make adhesion to the underlying low-k material difficult. Furthermore, the capping layer can delaminate and / or separate from the low-k dielectric film during BEOL processing. These and other challenges have limited the ability of conventional techniques to further shrink feature sizes or prevent delamination of the capping layer from the low-k film.

[0018]

[0021] The present technology overcomes these problems by performing post-deposition treatment of the low-k film. Through a number of steps, either together or separately, the deposited low-k film can be treated to form an interfacial layer that adheres more readily to the cap layer. This interfacial layer can be part of the low-k film. Furthermore, the treatment can be performed in the same chamber as the deposition, eliminating the need to break vacuum or expose the structure to the atmosphere. Finally, the treatment may not significantly affect the underlying low-k film, thereby preserving the integrity of the previously formed structure.

[0019]

[0022] The remainder of the disclosure will routinely identify particular deposition processes and post-deposition treatments utilizing the disclosed technology and will describe one type of semiconductor processing chamber, but it will be readily understood that the described processes are equally applicable to other deposition chambers and to processes that may be performed in any number of semiconductor processing chambers. Thus, the technology should not be considered limited to use with only these particular deposition processes or chambers. This disclosure will describe one possible chamber that may be used to perform processes in accordance with embodiments of the technology before describing methods of semiconductor processing according to the technology.

[0020]

[0023] FIG. 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In this illustration, a pair of front-opening unified pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104 and placed in a low-pressure holding area 106, which is then placed into one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform multiple substrate processing steps, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, pre-cleaning, degassing, orientation, and the formation of semiconductor material stacks as described herein, in addition to other substrate processes including annealing, ashing, and the like.

[0021]

[0024] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate. A third pair of processing chambers (e.g., 108a-b) may then be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a stack of alternating dielectric films on a substrate. Any one or more of the processes described may be performed in chambers separate from the fabrication system shown in various embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100.

[0022]

[0025] 2 shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the present technique. The plasma system 200 may illustrate a pair of processing chambers 108 that may be attached to one or more of the tandem sections 109 described above. The pair of processing chambers 108 may include lid stack components in accordance with embodiments of the present technique, which may be described further below. The plasma system 200 may generally include a chamber body 202. The chamber body 202 has a sidewall 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and include identical components.

[0023]

[0026] For example, processing region 220B, whose components may be included in processing region 220A, may include a pedestal 228 disposed in the processing region through a passageway 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, that may heat and control the substrate temperature to a desired processing temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0024]

[0027] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include interfaces for power and temperature indicators, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to removably couple with the power box 203. A perimeter ring 235 is shown on the power box 203. In some embodiments, the perimeter ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the upper surface of the power box 203.

[0025]

[0028] A rod 230 is provided through a passage 224 formed in the bottom wall 216 of the processing region 220B and can be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 can selectively space the substrate 229 from the pedestal to facilitate exchange of the substrate 229 by a robot utilized to transfer the substrate 229 into and out of the processing region 220B through the substrate transfer port 260.

[0026]

[0029] A chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled thereto. The precursor delivery system 208 may include a precursor inlet passage 240. The precursor inlet passage 240 may deliver reactants and cleaning precursors into the processing region 220B through a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 disposed intermediate a faceplate 246. A radio frequency (RF) source 265 may be coupled to the dual-channel showerhead 218. The RF source 265 may power the dual-channel showerhead 218 to facilitate generation of a plasma region between the faceplate 246 and the pedestal 228 of the dual-channel showerhead 218. The dual channel showerhead 218 and / or faceplate 246 may include one or more openings to allow precursor flow from the precursor distribution system 208 to the processing regions 220A and / or 220B. In some embodiments, the openings may include at least one of linear and conical openings. In some embodiments, an RF source may be coupled to other portions of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the dual channel showerhead 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 may be disposed around the periphery of the pedestal 228, engaging the pedestal 228.

[0027]

[0030] Optional cooling channels 247 may be formed in the annular base plate 248 of the precursor distribution system 208 to cool the annular base plate 248 during operation. A heat transfer fluid, such as water, ethylene glycol, or gas, may be circulated through the cooling channels 247 so that the base plate 248 may be maintained at a predetermined temperature. A liner assembly 227 may be positioned within the processing region 220B proximate the sidewalls 201, 212 of the chamber body 202 to prevent the sidewalls 201, 212 from being exposed to the processing environment within the processing region 220B. The liner assembly 227 may include a peripheral pumping cavity 225. The peripheral pumping cavity 225 may be coupled to a pumping system 264 configured to evacuate gases and byproducts from the processing region 220B and control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed on the liner assembly 227. The exhaust port 231 can be configured to allow gas flow from the processing region 220B to the peripheral pumping cavity 225 in a manner that facilitates processing within the system 200.

[0028]

[0031] While a plasma processing chamber may be used for one or more aspects of film processing according to the present technique, in some embodiments, a plasma-enhanced process may not be utilized to form the carbon film. The use of a plasma may limit the conformality of the resulting film by further releasing carbon from the precursor and may limit the carbon content of the resulting film by allowing the carbon to recombine with other radical species and exit the chamber. The present technique, in some embodiments, may form a film without generating at least a plasma. FIG. 3 illustrates steps of an exemplary method 300 of semiconductor processing according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the semiconductor processing system 200 described above, as well as any other chamber in which plasma deposition may be performed. The method 300 may include a number of optional steps, which may or may not be particularly relevant to some embodiments of the method according to the present technique. It should be understood that the method 300 may be performed on any number of semiconductor structures or substrates, including the exemplary structure 400 or substrate 405 shown in FIGS. 4A-4C upon which a layer of material may be formed. It should be understood that Figures 4A-4C show only partial schematic views, and that the substrate may include any number of structural portions having the features shown in the figures, as well as alternative structural features that can still benefit from the steps of the present technology.

[0029]

[0032] Method 300 may include a number of optional steps as illustrated. These steps may or may not be particularly relevant to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader range of structure formation, but are not critical to the present technology or may be performed by alternative methods, as described further below. As previously mentioned, method 300 may describe the steps shown generally in FIGS. 4A-4C, and those illustrations will be described in conjunction with the steps of method 300.

[0030]

[0033] Prior to the first step of method 300, substrate 405 may be processed with one or more methods and then placed in a processing region of a semiconductor processing system where method 300 may be performed. Some or all of the steps may be performed in a chamber or system tool, as previously described, or may be performed in different chambers on the same system tool, which may include a semiconductor processing chamber in which the steps of method 300 may be performed.

[0031]

[0034] The method may include providing one or more deposition precursors to a processing region of a semiconductor processing chamber in step 305. A substrate 405 may be placed in the processing region of the semiconductor processing chamber. In embodiments, the substrate 405 may have a substantially planar surface or a textured surface. The substrate may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have a variety of dimensions, such as 200 mm or 300 mm diameter wafers, as well as rectangular or square panels.

[0032]

[0035] The one or more deposition precursors may include a silicon-containing precursor. The silicon-containing precursor used for deposition may be or may include any number of silicon-containing precursors. The silicon-containing precursor may be any conventional semiconductor processing silicide for forming silicon-containing materials. For example, the silicon-containing precursor may be a ring-shaped precursor, a linear precursor, a Si-O-Si precursor, or a Si-C-Si precursor. Exemplary ring-shaped precursors may include, but are not limited to, octamethylcyclotetrasiloxane, 2,4,6,8-tetramethyl-2,4,6,8-tetravinylcyclotetrasiloxane, or 2,4,6,8-tetramethylcyclotetrasiloxane. Exemplary linear precursors may include, but are not limited to, dimethyldimethoxysilane, ethoxydimethylsilane, isobutylmethyldimethoxysilane, or vinylmethyldimethoxysilane. Exemplary Si-O-Si precursors can include, but are not limited to, 1,1,3,3-tetramethyl-1,3-dimethoxydisiloxane or 1,3-dimethyl-1,1,3,3-tetramethoxydisiloxane. Exemplary Si-C-Si precursors can include, but are not limited to, methoxy(dimethyl)silylmethane or methyl(dimethoxy)silylmethane.

[0033]

[0036] The flow rate of the silicon-containing precursor into the processing region of the semiconductor processing chamber is less than or about 2,500 mg / min, less than or about 2,250 mg / min, less than or about 2,250 mg / min, less than or about 2,000 mg / min, less than or about 1,750 mg / min, less than or about 1,750 mg / min, less than or about 1,500 mg / min, less than or about 1,400 mg / min, less than or about 1,300 mg / min, less than or about 1,300 mg / min, less than or about 1,200 mg / min , less than or about 1,100 mg / min, less than or about 1,100 mg / min, less than or about 1,000 mg / min, less than or about 900 mg / min, less than or about 800 mg / min, less than or about 700 mg / min, less than or about 600 mg / min, less than or about 500 mg / min, less than or about 400 mg / min, less than or about 300 mg / min, less than or about 200 mg / min, or less.

[0034]

[0037] In addition to silicon-containing precursor, oxygen-containing precursor can also be supplied to the processing region of semiconductor processing chamber.The flow rate of oxygen-containing precursor to the processing region of semiconductor processing chamber can be less than or about 1,000 sccm, less than or about 900 sccm, less than or about 800 sccm, less than or about 700 sccm, less than or about 600 sccm, less than or about 500 sccm, less than or about 450 sccm, less than or about 400 sccm, less than or about 350 sccm, less than or about 300 sccm, less than or about 250 sccm, less than or about 200 sccm, less than or about 150 sccm, less than or about 100 sccm or less. In embodiments, the oxygen-containing precursor may be or include molecular oxygen (O2).

[0035]

[0038] In some embodiments, additional precursors may be provided in addition to the silicon-containing precursor and, if present, the oxygen-containing precursor. For example, the deposition precursor may also include one or more carrier gases, such as helium (He), nitrogen (N), argon (Ar), etc. Although the one or more carrier gases may be provided along with the other deposition precursors, the carrier gases may be considered inert gases and therefore do not react to form part of the deposited low-k material 410.

[0036]

[0039] In step 310, the method 300 may include forming a low-k material 410. The low-k material 410 may be formed overlying the substrate 405. The low-k material 410 may include, but is not limited to, an oxide material such as silicon oxide, or an oxide doped with fluorine, carbon, or other low-k materials that may be used in processing. In embodiments, the low-k material may be characterized by Si-O-Si bonds. The low-k material may be characterized by a dielectric constant of less than or about 6.0, less than or about 5.5, less than or about 5.0, less than or about 4.5, less than or about 4.0, less than or about 3.5, less than or about 3.0, less than or about 2.7, less than or about 2.5, less than or about 2.3, or less than or equal to 2.3.

[0037]

[0040] The low-k material can be formed by various deposition methods, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or any other deposition method. In embodiments, the layer of low-k material can be formed through plasma-enhanced chemical vapor deposition. The plasma can be formed with a plasma power of less than or about 1,500 W. The plasma may be formed at a plasma power of less than or about 1,400 W, less than or about 1,300 W, less than or about 1,200 W, less than or about 1,200 W, less than or about 1,100 W, less than or about 1,000 W, less than or about 900 W, less than or about 800 W, less than or about 700 W, less than or about 600 W, less than or about 500 W, less than or about 400 W, less than or about 300 W, or less. When forming the layer 410 of low-k dielectric constant material through plasma-enhanced chemical vapor deposition, the material may include a large amount of methyl groups (-CH groups). The methyl groups may reduce adhesion between the low-k dielectric material 410 and a material (such as a cap layer) subsequently formed over the low-k dielectric material 410. Therefore, the method 300 may include a post-deposition treatment to enhance adhesion between the low-k dielectric material 410 and a material subsequently formed over the low-k dielectric material 410.

[0038]

[0041] The temperature within the semiconductor processing chamber may be maintained at less than or about 550° C. while forming the layer of low-k material 410. For example, the temperature within the semiconductor processing chamber may be maintained at less than or about 525° C., e.g., less than or about 500° C., less than or about 475° C., less than or about 450° C., less than or about 450° C., less than or about 425° C., less than or about 400° C., less than or about 375° C., less than or about 350° C., less than or about 325° C., less than or about 300° C., less than or about 275° C., less than or about 250° C., less than or about 225° C., or lower, etc. while forming the layer of material.

[0039]

[0042] The pressure in the semiconductor processing chamber can be maintained at less than or about 100 Torr while forming the layer of low-k material 410. For example, the pressure in the semiconductor processing chamber can be maintained at less than or about 90 Torr, e.g., less than or about 80 Torr, less than or about 70 Torr, less than or about 60 Torr, less than or about 50 Torr, less than or about 40 Torr, less than or about 30 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 12.5 Torr, less than or about 10 Torr, less than or about 9 Torr, less than or about 8 Torr, or less than or about 8 Torr while forming the layer of material.

[0040]

[0043] In optional step 315, method 300 may include reducing or stopping the flow of deposition precursors, such as silicon-containing precursors, oxygen-containing precursors, and / or any carrier gases or inert precursors. In some embodiments, method 300 may alternatively include reducing the flow of deposition precursors. For example, the flow rate of silicon-containing precursors may be reduced to about 100 mg / min or less, about 90 mg / min or less, about 80 mg / min or less, about 70 mg / min or less, about 60 mg / min or less, about 50 mg / min or less, about 40 mg / min or less, about 30 mg / min or less, about 20 mg / min or less, about 10 mg / min or less, or less. Reducing the flow rate of silicon-containing precursors may reduce the amount of deposition that occurs, allowing for processing of the existing low-k material layer 410.

[0041]

[0044] Simultaneously with or following the reduction or cessation of the flow of deposition precursors, the processing region of the semiconductor processing chamber may be purged in optional step 320. Accordingly, the flow rate of the carrier gas and / or inert gas may be maintained to purge the processing region of one or more deposition precursors. However, the flow rate of the carrier gas and / or inert gas may be maintained and / or reduced. During purging, plasma power may be provided. The plasma power may increase collisions between the carrier gas and / or inert gas and the deposited low-k material 410. The collisions may densify the layer of low-k material 410 while purging the processing region of one or more deposition precursors. In embodiments, the plasma power in steps 315-320 may be reduced from the plasma power level maintained during deposition to reduce carrier gas collisions and prevent any sputtering or damage to the film. For example, the plasma power in steps 315-320 can be maintained at or below 700 W, or about 700 W, or below 600 W, or below 600 W, or below 500 W, or below 500 W, or below 400 W, or below 400 W, or below 300 W, or below 300 W, or below 200 W, or below 200 W, or below 100 W, or below 75 W, or below 75 W, or below.

[0042]

[0045] In optional step 325, method 300 may include delivering an oxygen-containing precursor to the processing region. That is, in some embodiments, the oxygen-containing precursor may be delivered while purging the processing region of other deposition precursors. By delivering the oxygen-containing precursor while purging the processing region, the top surface of the low-k dielectric layer 410 opposite the substrate 405 may be treated with the oxygen-containing precursor and / or oxygen-containing plasma effluents. The oxygen-containing precursor and / or oxygen-containing plasma effluents may reduce the amount of methyl groups on the top surface of the low-k dielectric layer 410 and increase the oxygen concentration in the low-k dielectric layer 410, forming an interfacial layer 415 on the low-k dielectric layer 410 in step 330, as shown in FIG. 4B . The interfacial layer 415 may be a top portion of the low-k dielectric layer 410. It is contemplated that treating the terminal methyl groups on the top surface of the low-k dielectric layer 410 may replace the methyl groups with oxygen-containing groups such as —CHOH, —CHO, and / or —COOH, which may enhance adhesion with subsequently formed materials. Oxygen-containing groups such as —CH 2 OH, —CHO, and / or —COOH may more easily interface and / or bond with a cap layer formed on the low-k material 410, as further described below.

[0043]

[0046] In other embodiments, method 300 may not include purging the processing region in optional step 320 and / or reducing or stopping the flow of deposition precursors in optional step 315. Instead, one or more of the deposition precursors, such as a silicon-containing precursor and / or an oxygen-containing precursor, may be continuously supplied. However, it is contemplated that the flow rates of one or more deposition precursors may be changed. For example, the flow rate of the silicon-containing precursor may be maintained or reduced, while the flow rate of the oxygen-containing precursor may be maintained or increased. Once the flow rate of the silicon-containing precursor is reduced, the layer of low-k dielectric constant material 410 may be treated in a similar manner to supplying an oxygen-containing precursor while purging the processing region as described above. This results in the formation of an interfacial layer 415 on the layer of low-k dielectric constant material 410. Specifically, the layer of low-k dielectric constant material 410 may be treated with an oxygen-containing precursor and / or oxygen-containing plasma effluents to reduce the amount of methyl groups and / or increase the oxygen concentration at the top surface of the layer of low-k dielectric constant material 410. Alternatively, if the flow rate of the silicon-containing precursor is maintained or only slightly reduced, an oxygen-rich silicon oxide material may be formed as the interfacial layer 415 on the layer of low-k material 410. The oxygen-rich material may provide better adhesion with subsequently formed oxygen-containing materials, such as an oxygen-containing cap layer.

[0044]

[0047] The steps of method 300, such as steps 310 and 330, may be performed under the same or similar process conditions. For example, the temperature and / or pressure may be maintained during both the formation of the layer of low-k material 410 and the formation of the interfacial layer 415. Conversely, the temperature and / or pressure may be changed or adjusted between the formation of the layer of low-k material 410 and the formation of the interfacial layer 415. However, in embodiments, the plasma power may be reduced from a first plasma power level during the formation of the layer of low-k material 410 to a second plasma power level, lower than the first plasma power level, during the formation of the interfacial layer 415, as discussed above. As previously discussed, reducing the plasma power level may preserve the layer of low-k material 410 and not damage the material.

[0045]

[0048] As shown in FIG. 4C, following the formation of the interfacial layer 415, a cap layer 420 may be formed in step 335. The cap layer 420 may be an oxide cap layer, such as a layer formed from a silicon- and oxygen-containing material (e.g., tetraethyl orthosilicate, or TEOS). The cap layer 420 may also be an anti-reflective coating, such as a dielectric anti-reflective coating. The anti-reflective coating may be a silicon oxide film. The anti-reflective coating may further include carbon and / or nitrogen. In conventional processes, the interfacial layer may not be formed, and adhesion issues between the two films may result in delamination of the cap layer from the layer of low-k material. For example, without the interfacial layer, the adhesion value between the layer of low-k material and the cap layer may be 3.0 J / m 2 However, by forming the interface layer 415 according to an embodiment of the present disclosure, the adhesion value between the layer of low-k material 410 and the cap layer 420 via the interface layer 415 may be less than about 3.0 J / m 2 The adhesion value may be greater due to the oxygen concentration in the interface layer 415, which may interact more easily with the oxygen in the cap layer 420. In an embodiment, the adhesion value is about 3.5 J / m 2 Above, approximately 4.0J / m 2 Above, approximately 4.5J / m 2 Above, approximately 5.0J / m 2 Above, approximately 5.5J / m 2 Above, approximately 6.0J / m 2 These adhesion values, for example, 3.0 J / m 2 A higher adhesion value indicates sufficient adhesion between the layer of low-k material 410 and the cap layer 420, which may result in minimal or no delamination during subsequent processing.

[0046]

[0049] 4C illustrates a final structure 400 that may be formed according to method 300. Structure 400 may include any of the features previously described with respect to method 300. For example, structure 400 may include a semiconductor substrate 405. Structure 400 may include a layer of low-k dielectric material 410 disposed on semiconductor substrate 405. Structure 400 may include a cap layer 420 formed on layer of low-k dielectric material 410. Structure 400 may include an interface layer 415 disposed between layer of low-k dielectric material 410 and cap layer 420. As discussed, the adhesion value between layer of low-k dielectric material 410 and cap layer 420 is approximately 4.0 J / m 2 It could be more than that.

[0047]

[0050] In embodiments, the interfacial layer 415 may be part of the layer of low-k material 410. For example, an upper portion of the layer of low-k material 410 may be processed to form the interfacial layer 415. Alternatively, the interfacial layer 415 may be an oxygen-rich material specifically formed on the layer of low-k material 410. In embodiments, the interfacial layer 415 may be characterized by a lower methyl content and / or a higher oxygen concentration than the layer of low-k material 410.

[0048]

[0051] By utilizing one or more of the described processes, controlled, discrete formation of materials can be provided, resulting in improved layers of material, thus providing structure 400, where one layer, such as layer of low-k material 410, can be processed to form interface layer 415 that increases adhesion between layer of low-k material 410 and cap layer 420, all while being in the same chamber without exposing the structure to the atmosphere. As a result, improved structures can be achieved with the present techniques, which can produce structures with enhanced adhesion between the low-k material and the cap layer over prior art techniques.

[0049]

[0052] In the preceding description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details or with additional details.

[0050]

[0053] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. Furthermore, while a method or process may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in a different order than listed.

[0051]

[0054] Where a range of values ​​is given, unless the context clearly indicates otherwise, it is understood that each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest fraction of the unit of the lower limit. Any narrower range between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, is also encompassed. The upper and lower limits of such narrower ranges may individually be included or excluded within that range. Each range where either, neither, or both limits are included within this narrower range is also encompassed within the technology, even though there may be specifically excluded limits within the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0052]

[0055] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, a reference to "a deposition precursor" includes a plurality of such precursors, a reference to "the layer of low dielectric constant material" includes a reference to one or more layers of low dielectric constant material, and equivalents thereof known to those skilled in the art, and so forth.

[0053]

[0056] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. 1. A semiconductor processing method comprising: delivering one or more deposition precursors to a processing region of a semiconductor processing chamber, wherein a semiconductor substrate is positioned within the processing region; forming a layer of low dielectric constant material over the semiconductor substrate; forming an interfacial layer on the layer of low-k material; forming a cap layer on the interface layer; A method comprising:

2. 10. The semiconductor processing method of claim 1, wherein said semiconductor substrate is maintained at a temperature of about 550[deg.] C. or less during said semiconductor processing method.

3. purging the processing region of the one or more deposition precursors, wherein a plasma power is maintained at or below about 750 W while purging the processing region.

10. The semiconductor processing method of claim 1, further comprising:

4. stopping the flow of the one or more deposition precursors prior to forming the interfacial layer.

10. The semiconductor processing method of claim 1, further comprising:

5. providing an oxygen-containing precursor to the processing region prior to forming the interfacial layer; 10. The semiconductor processing method of claim 1, further comprising:

6. 6. The semiconductor processing method of claim 5, wherein the flow rate of the oxygen-containing precursor is about 750 sccm or less.

7. densifying the layer of low-k material while purging the processing region of the one or more deposition precursors.

10. The semiconductor processing method of claim 1, further comprising:

8. The adhesion value between the layer of low-k material and the cap layer is about 3.0 J / m ２ The semiconductor processing method of claim 1 .

9. 1. A semiconductor processing method comprising: forming a layer of low-dielectric constant material on a semiconductor substrate contained within a processing region of a semiconductor processing chamber, wherein plasma power is maintained at a first plasma power level while forming the layer of low-dielectric constant material; purging the processing region, wherein the plasma power is maintained at a second plasma power level while purging the processing region, the second plasma power level being less than or equal to the first plasma power level; forming an interfacial layer on the layer of low-k material; forming a cap layer on the interface layer; A method comprising:

10. 10. The semiconductor processing method of claim 9, wherein the semiconductor substrate comprises silicon.

11. 10. The semiconductor processing method of claim 9, wherein the layer of low-k dielectric material is formed through plasma-enhanced chemical vapor deposition.

12. 10. The semiconductor processing method of claim 9, wherein said interfacial layer has a lower methyl content than said layer of low-k material.

13. supplying molecular oxygen to the processing region while purging the processing region; 10. The semiconductor processing method of claim 9, further comprising:

14. reducing the flow rate of one or more precursors used to form the layer of low-k material before purging the processing region.

10. The semiconductor processing method of claim 9, further comprising:

15. 10. The semiconductor processing method of claim 9, wherein the temperature and pressure in the processing region during formation of the layer of low-k material are maintained during formation of the interfacial layer.

16. reducing the flow rate of the carrier gas before purging the processing region; 10. The semiconductor processing method of claim 9, further comprising:

17. a semiconductor substrate; a layer of low dielectric constant material disposed on the semiconductor substrate; a cap layer formed over the layer of low-k material; an interfacial layer disposed between the layer of low-k dielectric material and the cap layer, wherein the adhesion value between the layer of low-k dielectric material and the cap layer is about 4.0 J / m ２ That is all, the interface layer and 1. A semiconductor structure comprising:

18. 20. The semiconductor structure of claim 17, wherein the interfacial layer is part of the layer of low-k material.

19. 20. The semiconductor structure of claim 17, wherein said interfacial layer has a lower methyl content than said layer of low-k material.

20. 20. The semiconductor structure of claim 17, wherein said interfacial layer has a higher oxygen concentration than said layer of low-k material.

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