Method for etching features using HF gas

Abstract

A method is provided for etching a feature in a stack comprising at least one of silicon oxide and silicon nitride beneath a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas comprising a halogen-containing component and HF gas is provided. A plasma is formed from the etching gas. A feature is selectively etched in the stack relative to the mask.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS: This application claims the benefit of priority to U.S. Patent Application No. 63 / 406,026, filed September 13, 2022, which is incorporated herein by reference for all purposes. [Background technology]

[0002] FIELD OF THE DISCLOSURE This disclosure relates to methods of forming semiconductor devices on semiconductor wafers, and more particularly, to etching stacks in the formation of memory or other semiconductor devices.

[0003] In the formation of semiconductor devices, etching layers can be used to form memory holes or lines. Some semiconductor devices can be formed by etching a silicon oxide and silicon nitride bilayer (ONON) or silicon oxide and polysilicon bilayer (OPOP) stack. Such stacks can be used for memory applications, such as forming three-dimensional "negative AND" gates (3D NAND). Other stacks with thicker silicon oxide layers and thinner silicon nitride layers may be used for other memory applications, such as forming dynamic random access memories (DRAM).

[0004] The background description provided herein is intended to generally present the contents of the present disclosure. The information described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0005] To achieve the above, and in accordance with the objectives of the present disclosure, a method is provided for etching a feature in a stack comprising at least one of silicon oxide and silicon nitride under a mask. A substrate support for supporting the stack in an etching chamber is cooled to a temperature below 0° C. An etching gas comprising a halogen-containing component and HF gas is provided. A plasma is formed from the etching gas. A feature is selectively etched in the stack relative to the mask.

[0006] In another aspect, an apparatus is provided for processing a stack on a substrate having at least one of a silicon oxide layer and a silicon nitride layer under a mask. An etching chamber is provided. A substrate support supports the substrate within the etching chamber. A temperature controller controls the temperature of the substrate support. An electrode supplies RF power within the etching chamber. An RF power source supplies RF power to the electrode. A gas source supplies an etching gas to the etching chamber, the gas source including a halogen-containing component source and an HF gas source.

[0007] These and other features of the present disclosure are described in more detail in the following detailed description taken in conjunction with the following figures. [Brief explanation of the drawings]

[0008] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which like reference numerals refer to similar elements and in which:

[0009] [Figure 1] FIG. 1 is a high-level flow chart of one embodiment.

[0010] [Figure 2A] FIG. 2A is a schematic cross-sectional view of a stack processed according to one embodiment. [Figure 2B] FIG. 2B is a schematic cross-sectional view of a stack processed according to one embodiment.

[0011] [Figure 3]FIG. 3 is a schematic diagram of an etching chamber that may be used in one embodiment.

[0012] [Figure 4] FIG. 4 is a schematic diagram of a computer system that can be used to practice one embodiment.

[0013] In the drawings, like reference numerals may be used to denote like structural elements. It should also be understood that the depictions in the figures are schematic and not to scale. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present disclosure will be described in detail below with reference to several preferred embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process steps and / or structures have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0015] Prior art ONON and OPOP etching techniques, especially for holes, rely on low surface temperatures and plasma chemistries with high fluorine (F) and hydrogen (H) radical densities. F radicals are primarily controlled using nitrogen trifluoride (NF3) and sulfur hexafluoride (SF6), with additional hydrofluorocarbons (C x H y F z ), carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8), and / or other fluorocarbon gases also contribute. The H radicals are primarily controlled by hydrogen gas (H2), with additional contributions from hydrogen bromide (HBr), methane (CH4), and / or C x H y F zGases also contribute. Hydrogen fluoride (HF) is thought to be generated in plasmas through a series of dissociation, recombination, and / or exchange reactions. However, HF density is not directly controlled because it depends on multiple mechanisms, including electron-induced reactions.

[0016] These etch conditions combine to produce a relatively high etch rate, high mask selectivity, and a reasonably vertical etch profile, resulting in hole height-to-width aspect ratios up to approximately 60-70. However, extending the process to higher aspect ratios (deeper etches) reduces all of these benefits. This may limit the scaling of 3D NAND technology, requiring thicker stacks to accommodate more device layers.

[0017] Profile control presents a significant challenge in very high aspect ratio contact dielectric etching, specifically in cryogenic etching of 3D NAND pillar structures, where large bow CDs and small bottom CDs exist. This is believed to be due to increased accumulation of etch byproducts near the etch front, which reduces the rate of SiO2 reactive ion etching (RIE). The most common way to increase etch rate (ER) for high aspect ratios is to increase ion energy and ion flux, which results in poor bow CD control (larger bow). Another common practice to increase bottom CD and ER is to modify plasma chemistry. This approach introduces other tradeoffs, such as bow expansion, capping, or non-circular holes.

[0018] In some embodiments, HF gas is used as a component of the etching gas. Without being bound by theory, it is believed that HF ​​transports highly efficiently into high aspect ratio holes or slits compared to H and F radicals. By introducing HF as a source gas, a high density of HF can be generated in the plasma while reducing the density of F and H in the plasma. The resulting conditions deliver more etchant to high aspect ratio (HAR) features, promoting higher etch rates and enabling effective etching at higher aspect ratios. In addition, the reduced F and H radical density reduces hard mask etching and lateral erosion of ONON sidewalls, resulting in improved etch selectivity, improved mask CD control, and reduced ONON profile curvature.

[0019] For ease of understanding, FIG. 1 is a high-level flowchart that may be used in some embodiments. In some embodiments, a stack is placed in an etch chamber on a substrate support (step 104). In some embodiments, the stack is disposed beneath a carbon-containing patterned mask. In some embodiments, the carbon-containing mask is an amorphous carbon mask. FIG. 2A is a schematic cross-sectional view of a stack 200 used in one embodiment. In some embodiments, the stack comprises a substrate 208 beneath a plurality of bilayers 212 disposed beneath a carbon-containing patterned mask 216. One or more layers may be disposed between the substrate 208 and the plurality of bilayers 212, or between the plurality of bilayers 212 and the carbon-containing patterned mask 216. However, in some embodiments, no silicon-containing layer is provided above or below the plurality of bilayers 212. The carbon-containing patterned mask 216 may be amorphous carbon. In some embodiments, the patterned mask pattern provides mask features 220 for high aspect ratio contacts. In some embodiments, the mask features are formed before the substrate is placed in the etch chamber. In other embodiments, the mask feature 220 is formed while the substrate is in the etch chamber. In some embodiments, the plurality of bilayers 212 is a bilayer of a silicon oxide layer 224 and a silicon nitride layer 228. In some embodiments, the stack may include a repeating sequence of three or more layers.

[0020] The substrate support is cooled 108 to a temperature below 0° C. In some embodiments, the substrate support is cooled to a temperature below −20° C. Cooling the substrate support cools the stack, providing a cryogenic etching process.

[0021] An etching gas is provided (step 112) including a halogen-containing component and HF gas. In some embodiments, the etching gas includes a halogen-containing component, HF gas, and a hydrofluorocarbon-containing component. In some embodiments, the etching gas further includes an inert bombardment gas, such as argon (Ar), helium (He), krypton (Kr), neon (Ne), xenon (Xe), or nitrogen (N). In some embodiments, the inert bombardment gas provides ions for ion bombardment to facilitate etching. In some embodiments, the halogen-containing component is a chlorohydrocarbon C x H y Cl z In some embodiments, the etching gas further comprises at least one of carbonyl sulfide (COS), hydrogen sulfide (HS), a hydrogen-containing gas, methane (CH), and hydrogen (H). In some embodiments, the etching gas may include 0-200 sccm CH2F2, 1-1000 sccm HF, 0-200 sccm HBr, and 0-200 sccm NF3. In this example, a pressure of 5-60 mTorr is provided. In some embodiments, the halogen-containing component may include a chlorine- or bromine-containing component.

[0022] The etching gas is formed into an etching plasma (step 116). This can be accomplished by supplying excitation RF power having a frequency of 60 MHz at 200-25,000 watts. In some embodiments, the RF power ranges from 0-15,000 watts at a frequency of 60 MHz. The stack 200 is exposed to the plasma (step 120). A bias of at least about 400 volts is supplied. In some embodiments, a high bias is supplied by supplying RF power having a frequency of 400 kHz at 2 kW-150 kW. The bias accelerates ions into the stack 200, selectively etching high aspect ratio etch features in the stack 200 relative to the carbon-containing patterned mask (step 124). In some embodiments, RF power, either continuous or pulsed RF power with a peak power in the range of 3 kW-150 kW, can be used for both the excitation RF power, which uses a higher frequency, and the bias RF power, which uses a lower frequency. The plasma is maintained for 180-4,800 seconds. The etch can etch both silicon oxide and silicon nitride layers. After etching is completed, the substrate is removed from the etching chamber (step 128).

[0023] 2B is a cross-sectional view of stack 200 after contact 232 has been etched. The contact is a high aspect ratio contact. Preferably, a high aspect ratio contact has a height to CD width ratio greater than 40:1. More preferably, the contact has an etch depth to feature CD width aspect ratio greater than 100:1.

[0024] The etching process can selectively etch silicon oxide and silicon nitride layers relative to amorphous carbon with a selectivity of greater than 3:1 while etching high aspect ratio features. In some embodiments, etching of high aspect features with controlled CD, hole shape, capping, and tapering is possible. Additionally, in some embodiments, carbon-containing patterned masks, such as amorphous carbon, can be used, reducing cost and defects.

[0025] In some embodiments, at cryogenic temperatures, HF gas can act as both an etchant and a passivator. Adding HF gas to the etching gas increases the concentration of HF gas in the etching plasma relative to hydrogen and fluorine radicals, decreasing the concentration of hydrogen and fluorine radicals relative to the concentration of HF. The reduced concentration of hydrogen and fluorine radicals reduces etching of the etch mask. Without being bound by theory, it is believed that HF ​​gas at low temperatures may be adsorbed onto the surface of the etch feature. This adsorption increases the etchant density of HF on the etch front, increasing etching at the etch front. Additionally, it increases the density of fluorine at the etch front without increasing the density of halogen radicals, increasing the ratio of fluorine neutrals to radicals.

[0026] In some embodiments, the adsorbed HF gas reacts with silicon nitride, and possibly nitrogen, to form salts such as ammonium fluoride and ammonium fluorosilicate. In some embodiments, the salts provide sidewall passivation. Thus, not only does the HF gas etch the etch front, but the HF can also provide sidewall passivation. Because directional ions do not bombard the sidewalls with high energy, the sidewall passivation can protect the sidewalls and reduce undesirable curvature.

[0027] In some embodiments, the stack is cooled to a temperature below 20°C. In some embodiments, the substrate support is cooled to a temperature below -20°C. In some embodiments, the substrate support is cooled to a temperature between -80°C and 0°C to provide improved processing. In some embodiments, the substrate support is cooled to a temperature between -200°C and -20°C. In some embodiments, the substrate support is cooled to a temperature between -60°C and -40°C.

[0028] In some embodiments, the stack comprises one or more layers of at least one of silicon oxide and silicon nitride. In some embodiments, the stack is a single layer of silicon oxide or silicon nitride. In some embodiments, the stack comprises alternating layers of silicon oxide and polysilicon (OPOP). In some embodiments, the stack includes repeating units of two or more layers comprising two or more materials.

[0029] In some embodiments, when fabricating 3D NAND memory devices, ONON stacks can be etched to form contact holes, channel holes, or trenches. In other embodiments, when fabricating 3D NAND memory devices, OPOP (alternating layers of SiO2 and polysilicon) stacks can be etched to form contact holes, channel holes, or trenches. Other embodiments can be used to etch DRAM capacitors. The capacitor etch can have a depth greater than 0.8 microns with a small CD providing high aspect ratio features in silicon oxide. In other embodiments, CDs less than 95 nm are achieved with etch depths greater than 8 microns, providing features with a depth-to-width aspect ratio of at least 80:1.

[0030] In some embodiments, the supply of etching gas and the ion etching may be performed as successive steps in a cyclic process. Supplying the etching gas simultaneously with the ion etching provides a faster process than a continuous cyclic process.

[0031] FIG. 3 is a schematic diagram of an etching reactor that can be used in one embodiment. In one or more embodiments, the etching reactor 300 includes a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308 within an etching chamber 349 surrounded by chamber walls 352. Within the etching chamber 349, the stack 200 is positioned on top of the ESC 308, which also serves as a substrate support. The ESC 308 can be biased by an ESC source 348. An etching gas source 310 is connected to the etching chamber 349 through the gas distribution plate 306. In some embodiments, the etching gas source 310 includes an HF gas source 312, a halogen-containing component source, and other gas sources 318, such as a hydrogen-containing component source and a fluorocarbon-containing component source. An ESC temperature controller 350 is connected to a chiller 314. The chiller 314 can cool the ESC 308 to a temperature below 0° C. In this embodiment, chiller 314 supplies coolant to channels 392 in or near ESC 308. A radio frequency (RF) power supply 330 supplies RF power to the lower electrode and / or upper electrode (ESC 308 and gas distribution plate 306 in this embodiment). In some embodiments, a non-RF power source, such as a pulsed DC power supply, can replace or be used in conjunction with RF power supply 330 to control the plasma. In an exemplary embodiment, 400 kilohertz (kHz), 60 megahertz (MHz), and optionally 2 MHz and 27 MHz power supplies make up RF power supply 330 and ESC source 348. In this embodiment, the upper electrode is grounded. In this embodiment, one generator is provided for each frequency. In other embodiments, the generators may be on separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other arrangements of RF sources and electrodes may be used. RF power may be continuous or pulsed. A controller 335 is controllably connected to the RF power source 330 , the ESC source 348 , the exhaust pump 320 , and the etching gas source 310 .An example of such an etch chamber is the Exelan Flex® Dielectric Etch System or the Vantex® Dielectric Etch System manufactured by Lam Research, Inc. of Fremont, Calif. The etch chamber may be a CCP (Capacitively Coupled Plasma) reactor or an ICP (Inductively Coupled Plasma) reactor, and the electrode may be a coil.

[0032] FIG. 4 is a high-level block diagram illustrating a computer system 400 suitable for implementing the controller 335 used in the embodiments. Computer systems can have many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to massive supercomputers. The computer system 400 includes one or more processors 402 and may further include an electronic display device 404 (for displaying graphics, text, and other data), a main memory 406 (e.g., random access memory (RAM)), a storage device 408 (e.g., a hard disk drive), a removable storage device 410 (e.g., an optical disk drive), a user interface device 412 (e.g., a keyboard, touchscreen, keypad, mouse, or other pointing device, etc.), and a communication interface 414 (e.g., a wireless network interface). The communication interface 414 allows software and data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., a communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0033] Information transferred via communications interface 414 may be in the form of signals, such as electronic, electromagnetic, optical, or other signals receivable by communications interface 414, and transmitted over a communications link that transmits signals, which may be implemented using wire or cable, fiber optics, telephone lines, cellular phone links, radio frequency links, and / or other communications channels. Such communications interfaces may enable one or more processors 402 to receive information from a network or output information to a network in the course of performing the method steps described above. Furthermore, method embodiments may be performed solely on a processor or over a network, such as the Internet, in conjunction with a remote processor that shares some of the processing.

[0034] The term "non-transitory computer-readable medium" is generally used to refer to media such as main memory, secondary memory, removable storage, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering transitory content such as carrier waves or signals. Examples of computer-readable code include machine code, such as produced by a compiler, and files containing high-level code that are executed by a computer using an interpreter. The computer-readable medium may also be computer code embodied in a carrier wave and transmitted by a computer data signal representing a sequence of instructions executable by a processor.

[0035] In some embodiments, liquid nitrogen is used as the coolant that flows through the ESC 308 to provide cooling. In other embodiments, Vertel Sinera™ liquid, manufactured by DuPont of Wilmington, Delaware, can be used as the coolant.

[0036] While the present disclosure has been described based on several preferred embodiments, there are alterations, modifications, substitutions, and various substitute equivalents that fall within the scope of the present disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present disclosure. Therefore, it is intended that the following appended claims be interpreted as including all such alterations, modifications, substitutions, and various substitute equivalents that fall within the true spirit and scope of the present disclosure. As used herein, the phrase "A, B, or C" should be interpreted in the sense of a logic using a non-exclusive logical "OR" ("A or B or C"), and not in the sense of "only one of A or B or C." Each step within a process may be optional and not required. Different embodiments may omit one or more steps or provide steps in a different order. Additionally, various embodiments may provide different steps simultaneously rather than sequentially.

Claims

1. 1. A method for etching a feature in a stack comprising at least one of silicon oxide and silicon nitride beneath a mask, comprising: cooling a substrate support for supporting the stack in an etching chamber to a temperature below 0°C; providing an etching gas including a halogen-containing component and HF gas; generating a plasma from the etching gas; selectively etching features in the stack relative to the mask; A method comprising:

2. 10. The method of claim 1, The method, wherein the etching gas further comprises a hydrofluorocarbon-containing component.

3. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask.

4. 10. The method of claim 1, The etching gas is He, Ne, Ar, Kr, Xe, and N 2 The method further comprising:

5. 10. The method of claim 1, The halogen-containing component is a chlorohydrocarbon, SiCl 4 , BCl 3 , N.F. 3 , C 4 F 8 , C 3 F 8 , C 4 F 6 , SF 6 , C.F. 4 , Cl 2 , HBr, CF 3 I, CH 3 F, CH 2 F 2 , CHF 3 and HCl.

6. 10. The method of claim 1, The etching gas is a hydrogen-containing gas, H 2 , COS, H 2 S, and C.H. 4 The method further comprising at least one of:

7. 10. The method of claim 1, The method wherein the substrate support is cooled to a temperature below -20°C.

8. 10. The method of claim 1, The method further comprising supplying RF power having a peak power in the range of 3 kW to 150 kW.

9. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes a plurality of alternating silicon oxide and silicon nitride layers.

10. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack includes a plurality of alternating silicon oxide and polysilicon layers.

11. 10. The method of claim 1, The method, wherein the mask is a carbon-containing mask and the stack comprises at least one layer of silicon oxide.

12. 10. The method of claim 1, The method wherein the mask is an amorphous carbon mask.

13. 1. An apparatus for processing a stack on a substrate having at least one of a silicon oxide layer and a silicon nitride layer under a mask, comprising: an etching chamber; a substrate support for supporting a substrate within the etching chamber; a temperature controller for controlling the temperature of the substrate support; an electrode for supplying RF power into the etching chamber; an RF power source for supplying RF power to the electrode; a gas source for supplying an etching gas to the etching chamber, a source of halogen-containing components, and HF gas source a gas source comprising: An apparatus comprising:

14. 14. The apparatus of claim 13, a controller controllably connected to the gas source, the RF power source, and the temperature controller, a processor; 1. A computer readable medium having computer readable code thereon, the computer readable code comprising: computer readable code for cooling the substrate support to a temperature below 0° C.; computer readable code for supplying an etching gas comprising a halogen-containing component from the halogen-containing component source and HF gas from the HF gas source; computer readable code for supplying RF power to generate a plasma from the etching gas; and Computer readable code for generating a bias a computer-readable medium including: The apparatus further comprises a controller comprising:

15. 14. The apparatus of claim 13, The source of the halogen-containing component is SiCl 4 Source, BCl 3 Source, N.F. 3 Source, C 4 F 8 Source, C 3 F 8 Source, C 4 F 6 Source, SF 6 Gen, C.F. 4 source, Cl 2 source, HBr source, CF 3 I source, CH 3 F source, CH 2 F 2 Source, CHF 3 and an HCl source.

16. 14. The apparatus of claim 13, The apparatus, wherein the gas source further comprises a source of inert bombardment gas.

17. 14. The apparatus of claim 13, The gas source is H 2 source, COS source, H 2 S source, and CH 4 The apparatus further comprises at least one of the sources.

18. 14. The apparatus of claim 13, The apparatus further comprising a non-RF power source for controlling a plasma in the etching chamber.

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