Vacuum baking for EUV lithography

Abstract

A method and apparatus for performing a post-exposure bake operation is described herein. After exposure of the photoresist on the substrate, the substrate is heated during a bake process to facilitate protection of the resist. The bake process is performed at sub-atmospheric pressure in a vacuum environment. After the low-pressure bake, the substrate is cooled. The cool-down process is performed at sub-atmospheric pressure. Further development of the resist is performed at atmospheric pressure.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to methods and apparatus for semiconductor processing. More particularly, the present disclosure is directed to methods and apparatus for processing a substrate after exposure to radiation. [Background technology]

[0002] Integrated circuits have evolved into complex devices that can contain millions of components (e.g., transistors, capacitors, and resistors) on a single chip. Photolithography is a process that can be used to form components on a chip. Generally, the photolithography process involves several steps. First, a photoresist layer is formed on a substrate. Chemically amplified photoresists typically contain a resist resin and a photoacid generator. The photoacid generator changes the solubility of the photoresist in a development process when exposed to electromagnetic radiation in a subsequent exposure step. The electromagnetic radiation can be generated by any suitable radiation source, such as a laser, an electron beam, an ion beam, or other suitable electromagnetic radiation source. The electromagnetic radiation can also be selected to have any desired wavelength, such as 193 nm or other suitable wavelength.

[0003] During the exposure step, a photomask or reticle is used to selectively expose specific areas of the substrate to electromagnetic radiation. Other exposure methods include maskless exposure methods. The exposure decomposes the photoacid generator, generating acid and creating a latent acid image in the resist resin. After exposure, the substrate is heated in a post-exposure bake process. During the post-exposure bake process, the acid generated by the photoacid generator reacts with the resist resin, changing the solubility of the resist during the subsequent development process.

[0004] After a post-exposure bake, the substrate, particularly the photoresist layer, is developed and washed to create a patterned mask. Depending on the type of photoresist used, the areas of the substrate exposed to the electromagnetic radiation are either less susceptible to removal or more susceptible to removal. After development and washing, the pattern in the mask is transferred to the substrate using a wet or dry etching process.

[0005] Evolution in chip design continues to drive faster circuit speeds and increased circuit density. The demand for higher circuit density typically utilizes shrinking dimensions of integrated circuit components. As integrated circuit component dimensions shrink, more elements can be placed in a given area on a semiconductor integrated circuit. Therefore, lithography processes transfer smaller features onto substrates, and lithography does so precisely, accurately, and without damage to meet advanced chip design specifications. To precisely and accurately transfer features onto substrates, high-resolution lithography utilizes light sources that provide radiation at shorter wavelengths. Shorter wavelengths help reduce the minimum printable size on the substrate. However, short-wavelength lithography suffers from issues such as low throughput, increased line-edge roughness, and / or reduced resist sensitivity. Furthermore, it is difficult to reduce the print size on a substrate and maintain uniform critical dimensions of the patterned features using current photoresist materials and baking processes.

[0006] Therefore, there is a need for improved methods for forming resist patterns on substrates. Summary of the Invention

[0007] In one embodiment, a method of processing a substrate is provided that includes exposing photoresist disposed on a substrate to electromagnetic energy, transferring the substrate to a process chamber to bake the substrate at a sub-atmospheric pressure, and transferring the substrate from the process chamber to a chill plate to cool the substrate.

[0008] In another embodiment, a method for processing a substrate includes exposing a chemically amplified photoresist disposed on a substrate to a lithographic exposure process at sub-atmospheric pressure, transferring the substrate to a process chamber having a process volume, baking the substrate in the process volume at sub-atmospheric pressure, and cooling the substrate in the process volume of the process chamber at sub-atmospheric pressure.

[0009] In another embodiment, a method for processing a substrate includes exposing a chemically amplified photoresist disposed on a substrate to a lithographic exposure process at a pressure less than atmospheric pressure, transferring the substrate to a process chamber having a process volume, baking the substrate in the process volume at a pressure less than atmospheric pressure, cooling the substrate to less than 30°C at a pressure less than 100 Torr in the process volume of the process chamber, and transferring the substrate from the process chamber to a developer and developing the photoresist.

[0010] In order that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a processing chamber according to one embodiment. [Figure 2A] 2 is a schematic cross-sectional view of a portion of the processing chamber of FIG. 1, according to one embodiment. [Figure 2B] 1 is a schematic cross-sectional view of a portion of a processing chamber according to one embodiment. [Figure 3] 2 is a schematic diagram of the processing chamber and cool-down chamber of FIG. 1, according to one embodiment. [Figure 4]1A-1C illustrate operations of a method for baking a substrate in a vacuum pressure environment, according to one embodiment. [Figure 5] 1A-1C illustrate operations of a method for baking a substrate in a vacuum pressure environment, according to one embodiment. [Figure 6] FIG. 1 illustrates a substrate processing system according to one embodiment. [Figure 7] 5A-5C illustrate operations of a method for processing a substrate in a vacuum pressure environment, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] For ease of understanding, wherever possible, identical reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0013] The present disclosure is generally directed to apparatus and methods for use during post-exposure baking of semiconductor substrates. The methods and apparatus disclosed herein assist in reducing line edge / width roughness, improving critical dimension uniformity, and improving exposure resolution in photolithography processes for semiconductor processing applications. The methods and apparatus disclosed herein also assist in reducing the dose of radiation (eUV exposure) used to achieve similar critical dimensions compared to conventional techniques. The apparatus described herein enables post-exposure baking or field-induced baking of a resist layer on a substrate. The post-exposure baking or field-induced baking may be performed before developing the substrate. The post-exposure baking process described herein has been shown to improve dose sensitivity, reduce line width roughness, and improve critical dimension uniformity compared to conventional techniques.

[0014] As used herein, a "substrate" or "substrate surface" generally refers to any substrate surface on which processing occurs. Processing includes deposition, etching, patterning, and other methods utilized during semiconductor processing. Substrates or substrate surfaces that may be processed also include dielectric materials such as silicon dioxide, silicon nitride, organosilicates, and carbon-doped silicon oxide or silicon nitride materials. In certain embodiments, the substrate or substrate surface includes a photoresist material, a hard mask material, or other film or layer utilized in patterning the substrate. The substrate itself is not limited to any particular size or shape. While the embodiments described herein are generally formed with reference to circular 200 mm or 300 mm substrates, other sizes and shapes, such as polygonal, square, rectangular, curved, or other non-circular workpieces, may be utilized in accordance with the embodiments described herein. Other substrate sizes may include 100 mm, 150 mm, 250 mm, 350 mm, 400 mm, 450 mm, etc.

[0015] The methods and apparatus disclosed herein improve photoresist sensitivity and productivity of photolithography processes. Random diffusion of charged species generated by a photoacid generator during a post-exposure bake procedure contributes to line edge / width roughness and reduced resist sensitivity. An electrode assembly as described herein is utilized to apply an electric field and / or a magnetic field to a photoresist layer during a photolithography process. The application of the electric field and / or the magnetic field controls the diffusion of the charged species generated by the photoacid generator. Additionally, an intermediate medium is utilized between the photoresist layer and the electrode assembly to enhance the electric field generated therebetween. In some embodiments, the intermediate medium is a fluid, such as a liquid, a gas, or a plasma. In other embodiments, the intermediate medium is neither a liquid nor a solid.

[0016] The gap defined between the photoresist layer and the electrode assembly causes a voltage drop across the electrode assembly, thus adversely reducing the desired electric field strength to be generated and applied to the photoresist layer. Inaccurate (e.g., too little or too much voltage and / or current) and / or non-uniform electric field strength in the photoresist layer can result in insufficient or inaccurate voltage power to drive or generate charged species in a specific desired direction within the photoresist layer, thereby reducing line edge profile control over the photoresist layer. Generating a controlled or desired electric field strength increases the precision and sensitivity of the photoresist layer to the exposure and / or development processes.

[0017] In embodiments in which the intermediate medium is a non-gas-phase medium, such as a slurry, gel, liquid solution, or solid medium, a predetermined range of applied voltage levels can be efficiently maintained when transferred from the electrode assembly to the photoresist layer disposed on the substrate. However, the use of a non-gas-phase (e.g., liquid or liquid-like material) as the intermediate medium still presents several challenges. For example, the non-gas-phase intermediate medium has operating temperature limitations and may react with the resist layer disposed on the substrate.

[0018] The resistivity of non-gas-phase fluids is also difficult to control in a stable range. In certain embodiments and applications, the desired resistivity of the intermediate medium is about 6·10 10 Ohm·cm, but due to variations in semiconductor manufacturing, the actual resistivity is 5·10 10 The resistivity and temperature of the intermediate medium change during the substrate baking operation and are influenced by the oxygen content, impurities in the medium, and the potential for polymerization of the medium. The purity of non-vapor phase fluids is difficult to control and can cause defects in the processed substrate. Non-vapor phase fluids interact differently with the photoresist in exposed areas compared to unexposed areas, which can cause photoresist loss and roughness changes.

[0019] Therefore, a solution to the above problem is provided herein that utilizes a weakly ionized gas or a mixture of weakly ionized gases as an intermediate medium. The weakly ionized gas is a gas that is flowed into the plasma formation region to form a high ion density plasma (approximately 10 5 ions / cm 3 ~about 10 10 ions / cm 3 ) is generated by forming a low ion density plasma (10 4 ions / cm 3 ~10 7 ions / cm 3 ). The low ion density plasma mixture, including but not limited to radicals and neutrons, is flowed through the showerhead and delivered into the volume between the substrate and the counter electrode. As the low ion density plasma passes through the showerhead and enters the gap, the low ion density plasma mixture is filtered and exits the showerhead as a cloud of charged species. The low ion density plasma and the charged species cloud contain various types of ions and radicals from either the same gas or gas mixture. The charged species cloud can be approximately 10 4 ions / cm 3 ~about 10 6 ions / cm 3 and the like, contain a lower concentration of ions than a low ion density plasma.

[0020] Electron density is defined as the number of free electrons in a volume. The electron density of each plasma can be similar to the ion density, and in high ion density plasmas the electron density is about 10 5 electron / cm 3 ~about 10 10 electron / cm 3 The electron density in low ion density plasma is about 10 4 electron / cm 3 ~10 7 electron / cm 3 and the electron density between the substrate and the electrode is about 10 4 electron / cm 3 ~about 10 10 electron / cm 3The electron and ion densities immediately above the substrate are selected to form a plasma medium through which the electric field passes but does not process, react with, or remain substantially inert to the resist layer on the substrate. The electric field is coupled through the plasma medium, which thus becomes the charge-carrying medium through which the electric field is more efficiently maintained. The gas utilized to form the plasma medium, as well as the electron / ion density in the plasma medium, further influences when the plasma medium reacts with the resist layer on the substrate. Therefore, the shape, density, position, and configuration of the plasma medium are controlled to increase electric field coupling through the plasma medium while reducing reaction with the substrate.

[0021] In some embodiments, only one of the high ion density plasma or the low ion density plasma is formed before passing through a showerhead or diffuser and into the process volume between the substrate and the counter electrode. In these embodiments, the ion density between the substrate and the counter electrode is about 10 4 ions / cm 3 ~about 10 6 ions / cm 3 and the electron density is about 10 4 ions / cm 3 ~about 10 6 ions / cm 3 is.

[0022] The gases and plasma in the process chamber are selected and / or controlled with respect to resistivity, temperature, pressure, and composition. The pressure of the processing environment in the process chamber is between about 10 mTorr and about 800 Torr. A voltage is applied between the substrate and the counter electrode, thus creating an electric field through a gas or plasma phase medium between the substrate and the counter electrode. The electric field is controlled by applying either a constant voltage or a constant current to one or both of the substrate support or the electrode by a power supply. The direction of the current can be unipolar or bipolar, so that the electric field is either upward or downward relative to the top surface of the substrate. In some embodiments, an alternating current is applied by the power supply.

[0023] The low ion density plasma / charged species cloud is delivered into the gap or volume between the substrate and the counter electrode. In the embodiment described herein, the counter electrode is a secondary plasma injection (SPI) showerhead. The SPI showerhead has multiple holes for the passage of gases.

[0024] In one embodiment, the bottom surface of the SPI showerhead, which faces the substrate, is formed from a conductive material, such as a metal or semiconductor material, with controlled resistivity. The top surface of the SPI showerhead faces away from the substrate and is coated with a dielectric layer to reduce or eliminate current or electric fields from being directed in the opposite direction (upward) into other parts of the plate stack, such as another showerhead held at ground potential.

[0025] In another embodiment, the SPI showerhead is formed from a dielectric material such as ceramic, quartz, or a plastic material. In this embodiment, the bottom surface of the SPI showerhead is a metallized surface facing the substrate. Forming the SPI showerhead from a dielectric material with a metallized surface is beneficial because holes formed through the SPI showerhead have inner surfaces made from the dielectric material. When using a dielectric SPI showerhead with a metallized bottom surface, a voltage applied to the metallized bottom surface facing the substrate directs current and electric fields to flow through the low ion density plasma to or from the substrate.

[0026] In yet another embodiment, the SPI showerhead is formed from a silicon material, such as a crystalline silicon material, and the resistivity across the thickness of the SPI showerhead is controlled by doping the surface facing the substrate.

[0027] Another configuration for preventing or reducing current or electric fields from being directed upward from the SPI showerhead involves increasing the resistance of the gap between the SPI showerhead and a grounded or floating showerhead above the SPI showerhead. In this embodiment, the gap is filled with a dielectric medium that is permeable to the low ion density plasma, allowing the low ion density plasma to pass through without complete recombination.

[0028] When neutral or uncharged gas is desired to be added to the low-ion-density plasma, a dual-channel showerhead positioned above the SPI showerhead adds the neutral gas to the low-density plasma. The dual-channel showerhead includes at least one channel set that penetrates the entire thickness of the showerhead body and a second channel set that has openings on only one side of the showerhead body and is configured to provide one or more second gases / plasmas. A plasma generation source is positioned above the SPI showerhead and includes one or more of a capacitively coupled plasma (CCP) configuration, an inductively coupled plasma (ICP) configuration, an ultraviolet (UV) configuration, a microwave configuration, or a remote plasma source (RPS) configuration. In some embodiments, the lower electrode of the CCP architecture is a showerhead or diffuser and functions as a plasma recombination element. Plasma recombination involves removing ions in the plasma to increase the ratio of radicals to ions. In embodiments in which a diffuser is positioned at the bottom of the CCP architecture, a plate stack may be installed in an existing chamber architecture.

[0029] In one embodiment, the plate stack described herein can be utilized in a SELECTRA® chamber available from Applied Materials, Inc. (Santa Clara, California). It is contemplated that other appropriately configured devices from other manufacturers may also benefit from the embodiments described herein. The diffuser may be DC biased relative to the substrate support. In this example, the diffuser is connected to a DC power source through an RF filter that allows for an independent RF return path. The diffuser is electrically isolated from the chamber lid or body. Only a partially recombined plasma or a low ion density plasma flows into the process region where the substrate is disposed, and a current / field flows between the substrate and the diffuser. In this embodiment, neither an SPI showerhead nor a dual-channel showerhead is utilized.

[0030] In each embodiment described herein, the substrate is positioned on a substrate support pedestal while being exposed to the low ion density plasma. The substrate support pedestal is positively or negatively charged relative to the SPI showerhead. The substrate support pedestal includes vacuum chucking components and functions. The substrate support pedestal is a heated pedestal configured to control the temperature of the substrate. The heated pedestal is used to bake the substrate, and the process environment in the chamber is maintained at a subatmospheric pressure, e.g., a vacuum environment. During the substrate bake process in a subatmospheric environment, a current / electric field may be applied to the substrate.

[0031] FIG. 1 shows a schematic cross-sectional view of a process chamber 100 according to one embodiment. The process chamber 100 is configured to perform an electromagnetic field-induced post-exposure bake operation on a substrate having a photoresist or chemically modified resist layer disposed thereon. The process chamber 100 described herein may be configured as a mirror image about a centerline C, such that a second process chamber (not shown) forms an integral structure coupled to the same vacuum processing platform. In one embodiment, the platform is a PRODUCER® apparatus available from Applied Materials, Inc. (Santa Clara, Calif.). However, it is contemplated that other appropriately configured apparatus available from other manufacturers may benefit from the embodiments described herein.

[0032] The process chamber 100 includes a mixing block 102 that functions as an RF electrode and / or gas manifold. Process gas is provided to the mixing block 102 from a gas source 136. The process gas from the gas source 136 enters the mixing block 102 through a feedthrough member 103. In one embodiment, the feedthrough member 103 is formed from a polymeric material such as polytetrafluoroethylene. The mixing block 102 includes a flow centering insert 140 disposed therein. The flow centering insert 140 may be a ring-shaped device having an opening 204 formed therein. The opening 204 is formed through the center of the flow centering insert 140, and the opening 204 may be a single opening or multiple openings. The flow centering insert 140 improves the concentric flow distribution of the process gas within the plate stack of the process chamber 100. Additionally, the flow centering insert 140 helps reduce plasma backflow into the mixing block 102.

[0033] The mixing block 102 is electrically coupled to the first diffuser 104 and the faceplate 106, which serve to redirect the flow of source gas so that the gas flow is uniform (uniform from left to right in the diagram of FIG. 1 ). It should be noted that any such diffuser or screen may be coupled to a specific electrical potential, and therefore all of the diffusers or screens described herein may be characterized as electrodes. The insulator 108 electrically insulates the mixing block 102, including the faceplate 106, from the second diffuser 110. The second diffuser 110 functions as a second electrode facing the faceplate 106. In one embodiment, the second diffuser 110 is a selective modulation device (SMD) and functions as an ion blocker plate. The first diffuser 104 and the faceplate 106 are formed from a conductive material, such as a metal. The conductive material described herein may be aluminum or an aluminum alloy. The insulator 108 is an insulating material, such as a dielectric. The insulating material may be a ceramic, such as aluminum oxide, or a quartz material.

[0034] The first diffuser 104, faceplate 106, and second diffuser 110 each have a plurality of holes disposed therethrough to allow process gas to flow through the plate stack (e.g., first diffuser 104, faceplate 106, insulator 108, second diffuser 110, gas distribution device 112, insulator plate 156, and shielding screen 114). At least a portion of the mixing block 102, faceplate 106, and second diffuser 110 are formed from an electrically conductive material, such as aluminum or an aluminum alloy.

[0035] The surfaces of the faceplate 106, the second diffuser 110, and the insulator 108 define a first plasma generation region 210, in which a first plasma is generated when gas from the gas source 136 is present and energy is provided to the faceplate 106 through the mixing block 102.

[0036] Surfaces of the faceplate 106 and second diffuser 110 directly facing the first plasma generating region 210 may be coated with a ceramic layer, for example, yttria (YO) or alumina (AlO), to protect them from bombardment by energetic plasma products generated in the first plasma generating region 210. The ceramic coating may be formed by an electron beam coating process, an anodizing process, and / or a non-porous anodizing process. Other suitable coatings include nickel plating and surface oxidation processes, for example, by exposure to a concentrated HNO solution. Other surfaces of the faceplate 106 and second diffuser 110 that are not necessarily directly exposed to the plasma but are exposed to reactive gases and / or radicals generated by the plasma may be coated with either a ceramic layer (e.g., yttria, alumina) or a suitable passivation layer (e.g., an anodized layer or a chemically generated alumina layer) for chemical resistance. The insulator 108 may be any insulator and, in certain embodiments, is formed from a ceramic material.

[0037] The plasma products generated in the first plasma generating region 210 pass through the second diffuser 110, which further promotes uniform distribution of the plasma products and assists in electron temperature control. After passing through the second diffuser 110, the plasma products pass through the gas distribution device 112. Because the gas distribution device 112 and the second diffuser 110 contact each other at their edges, the gas distribution device 112 is also held at a similar voltage as the second diffuser 110. The apertures 216 (FIG. 2A) that extend completely through the gas distribution device 112 are at least three times larger in diameter than the apertures in the second diffuser 110. The gas distribution device 112 includes second and / or third sets of gas channels 214, which can be used to introduce one or more additional gases into the plasma products as they enter the second plasma generating region 218. The second and / or third gas channel sets 214 are coupled to a second gas source 142. The second gas source 142 may be configured to supply one or more inert or neutral gases to assist in reducing ionization of the plasma generated between the faceplate 106 and the second diffuser 110. The one or more additional gases exit a side of the gas distribution device 112 distal to the second diffuser 110. The gas distribution device 112 is made from aluminum or an aluminum alloy and, similar to the faceplate 106 and second diffuser 110 discussed above, may be coated with a passivation layer for chemical resistance or may be coated with a ceramic layer.

[0038] The gas and plasma flowing through the gas distribution device 112 enter a second plasma generating region 218 (FIG. 2A) where the gas and plasma mix. The second plasma generating region 218 is a plenum formed between the gas distribution device 112 and the shielding screen 114. Both the gas distribution device 112 and the shielding screen 114 can be held at different voltage potentials to control the ion density of the second plasma formed between them. In some embodiments, both the distribution device 112 and the shielding screen 114 are grounded; thus, the second diffuser 110 and the gas distribution device 112 are connected to a first ground 253, and the shielding screen 114 is connected to a second ground 255. The gas distribution device 112 and the shielding screen 114 are separated by an insulator plate 156. The insulator plate 156 may be formed from a ceramic or plastic material, similar to the insulator 108. In one embodiment, the insulator plate 156 is formed from an aluminum oxide material. In other embodiments, the insulator plate 156 is formed from a plastic material, such as a fluorocarbon-containing material. The plastic material may be polytetrafluoroethylene (PTFE) or polyetheretherketone (PEEK). The insulator plate 156 is selected to embody desired electrical insulation properties, such that the resistivity of the insulator plate 156 is about 10 15 greater than Ω·cm, e.g., about 10 16 greater than Ω·cm, e.g., about 10 17 greater than Ω·cm, e.g., about 10 18 The insulator plate 156 allows for control of the voltage difference between the gas distribution device 112 and the shielding screen 114. The shielding screen 114 is a plasma or ion shielding screen, so that the plasma is filtered as it passes through the shielding screen 114, reducing the concentration of ions. The shielding screen 114 may alternatively be described as a showerhead or a third diffuser plate.

[0039] The portions of the shielding screen 114 that are directly exposed to the plasma may be coated with a ceramic (e.g., alumina or yttria), and surfaces that are not directly exposed to the plasma may also be coated with a ceramic. Advantageously, both exposed and non-exposed surfaces are coated with a passivation layer for chemical resistance to reactive gases and species.

[0040] 1 and 2A. The shielding screen 114 is a showerhead configured to prevent plasma from backflowing up the plate stack from the process volume 170. The shielding screen 114 is also configured to reduce the number of ions in the plasma that pass through the shielding screen 114 and enter the process volume 170. The bottom surface of the shielding screen 114 faces the process volume 170 and the substrate support surface 132 of the substrate support 130.

[0041] The substrate support 130 is the upper portion of the substrate support assembly 126. The substrate support assembly 126 further includes a shaft 128 and a bellows 154 that connect the substrate support assembly 126 to the lower chamber body 120. The bellows 154 form a seal between the process volume 170 and the external environment. One or more backside gas sources 152 are coupled to the substrate support assembly 126 to supply a backside gas to a substrate support surface 132 of the substrate support 130. The backside gas source 152 may also include a pump to create a vacuum on the backside of the substrate 150.

[0042] Also coupled to the substrate support assembly 126 are a power source 146 and a movement device 148. The power source 146 can be an AC or DC power source. The power source 146 is configured to provide power to the movement device 148 and / or to one or more heating devices 228 ( FIG. 2A ) within the substrate support 130. The movement device 148 is configured to enable movement of the substrate support assembly 126, such as raising or lowering the substrate support assembly 126, rotating the substrate support assembly 126 about a central axis A, or tilting the substrate support assembly 126. In some embodiments, the substrate support 130 is an aluminum substrate support 130. In other embodiments, the substrate support 130 is a ceramic or metal alloy.

[0043] The process chamber 100 further includes an upper chamber body 116 coupled to a lower chamber body 120. The upper chamber body 116 and the lower chamber body 120 are coupled to each other to define at least a portion of a process volume 170. A plate stack, as described herein, is disposed on the upper chamber body 116. The lower chamber body 120 includes at least one transfer passage 160 disposed therethrough. A pumping liner 122 is disposed radially inward of the lower chamber body 120. The pumping liner 122 includes a plurality of openings 124 disposed therethrough. The openings 124 connect an exhaust plenum 134 to the process volume 170, allowing gas to be removed through the exhaust plenum 134 by a pump 144. The openings 124 are disposed symmetrically around the pumping liner 122. The showerhead spacer 118 is disposed radially inward of the upper chamber body 116 and is formed of a conductive material, such as an aluminum material. The showerhead spacer 118 further defines a portion of the process volume 170. The upper chamber liner 119 is disposed radially inward of the upper chamber body 116 and the showerhead spacer 118. The upper chamber liner 119 is an insulator. The upper chamber liner 119 is fabricated from a ceramic material. In some embodiments, the upper chamber liner 119 is fabricated from an aluminum oxide material or an aluminum nitride material.

[0044] A source matching device 138, such as an RF matching circuit, is coupled to the plate stack such that the source matching device 138 is configured to be in electrical communication with the faceplate 106. The source matching device 138 is configured to apply an RF current or voltage to the faceplate 106. The source matching device 138 is configured to generate a plasma between the faceplate 106 and the second diffuser 110.

[0045] 2A shows a schematic cross-sectional view of a portion of the processing chamber 100 of FIG. 1, according to one embodiment. FIG. 2A further shows passages and plenums formed within the plate stack. As described herein, an opening 204 is formed through the flow centering insert 140. An opening 202 is formed through the first diffuser 104 and is fluidly connected to a first plenum 206. An opening 208 is formed through the faceplate 106 and is fluidly connected to a first plasma generating region 210.

[0046] The second diffuser 110 also includes a plurality of openings that allow process gas from the first plasma generation region 210 to flow through the second diffuser 110 and into a second plenum 212 formed between the second diffuser 110 and the gas distribution device 112.

[0047] An aperture 216 through the gas distribution device 112 fluidly connects both the second plenum 212 and the second plasma generating region 218. The gas distribution device 112 further includes one or more heaters 250 disposed therein to enable controlled heating of the gas distribution device. The one or more heaters may include resistive heating elements, infrared heaters, or induction heaters. In some embodiments, the one or more heaters 250 may also be used to heat the substrate 150. The gas distribution device 112 and / or the second diffuser 110 are electrically coupled to a first ground 253. Alternatively, one of the gas distribution device 112 or the second diffuser 110 is coupled to a power source to enable a voltage differential different from the voltage differential applied to either the faceplate 106 or the shielding screen 114.

[0048] An opening 220 is formed in the insulator plate 156 to form a portion of the second plasma generating region 218. The shielding screen 114 further includes a plurality of apertures 222 that fluidly couple the second plasma generating region 218 to the process volume 170. The insulator plate 156 allows the shielding screen 114 and the gas distribution device 112 to be held at different potentials, allowing the plasma intensity in the second plasma generating region 218 to be controlled. The apertures 222 through the shielding screen 114 are offset from the apertures through the second diffuser 110, such that the central axis extending parallel to the direction of each aperture in the shielding screen 114 is offset from the central axis of any apertures formed through the second diffuser 110. The aperture offset reduces exposure of the photoresist on the substrate 150 to the high ion density plasma formed in the first plasma generating region 210. The shielding screen 114 includes a top surface 244 and a bottom surface 234. The shielding screen 114 may be coupled to the upper chamber body 116 via one or more fasteners 224 disposed through the shielding screen 114.

[0049] The plurality of openings 124 in the pumping liner 122 may further include individual apertures 226 formed through the pumping liner 122. The individual apertures 226 surround the pumping liner 122 and enable uniform removal of gas from the process volume 170 around the periphery of the substrate support 130. In the embodiments described herein, the one or more heating devices 228 disposed within the substrate support 130 are resistive heating devices. The backside gas source 152 is fluidly coupled to the substrate support surface 132 of the substrate support 130 via one or more gas conduits 230. An edge ring 232 may also be disposed at the edge of the substrate support 130 around the substrate 150.

[0050] A plurality of sealing rings 240 are disposed between each plate in the plate stack, for example, between the faceplate 106 and the insulator 108, between the insulator 108 and the second diffuser 110, between the second diffuser 110 and the gas distribution device 112, between the gas distribution device 112 and the insulator plate 156, and between the insulator plate 156 and the shielding screen 114. The sealing rings 240 are configured to seal the various regions 210, 218 and plenums 206, 212 to prevent plasma products from escaping the chamber 100 and to enable vacuum integrity within the chamber 100.

[0051] As mentioned above, the bottom surface 234 of the shielding screen 114, which faces the substrate 150, is formed from a conductive material, such as a metal or semiconductor material, having a controlled resistivity. The top surface 244 of the shielding screen 114 faces away from the substrate 150 and is coated with a dielectric layer (not shown) to direct current or electric fields in the opposite direction (upward) and reduce or eliminate them from entering other portions of the plate stack, such as the gas distribution device 112.

[0052] In another embodiment, the shielding screen 114 is formed from a dielectric material, such as a ceramic, quartz, or plastic material. In this embodiment, the bottom surface 234 of the shielding screen 114 is a metallized surface facing the substrate 150. Forming the shielding screen 114 from a dielectric material with a metallized surface is beneficial because the apertures 222 formed through the shielding screen 114 have an inner surface made from a dielectric material. When using a dielectric shielding screen 114 with a metallized bottom surface, a voltage applied to the metallized bottom surface facing the substrate 150 directs current and electric fields through the low ion density plasma in the process volume to or from the substrate 150.

[0053] In yet another embodiment, the shielding screen 114 is formed from a silicon material, such as a crystalline silicon material, and the resistivity through the thickness of the shielding screen 114 is controlled by doping the surface facing the substrate.

[0054] In some embodiments, coating the surface of the shielding screen 114 with a dielectric material is performed over the entire surface of the shielding screen 114. Similarly, it may be possible to form a metal coating over the entire ceramic shielding screen 114. The distance between the shielding screen 114 and other chamber components is separately controlled to account for changes in the electric field distribution within the plate stack.

[0055] A voltage supply 260 is connected between the shielding screen 114 and the substrate support 130. The voltage supply 260 allows for control of the voltage difference between the shielding screen 114 and the substrate support 130. The voltage supply 260 may be configured to generate a voltage difference between about 0 V and about 2000 V, for example, about 10 V to about 2000 V. The voltage supply may further include AC / DC waveform control, so that a DC voltage or an AC voltage having a frequency of about 7.5 kHz or less, for example, about 0 kHz to about 7.5 kHz, may be applied. Controlling the voltage difference between the substrate support 130 and the shielding screen 114 allows for control of the electric field therebetween during baking of the resist disposed on the substrate 150. Either the shielding screen 114 or the substrate support 130 may be grounded. In the embodiment of FIG. 2A, the shielding screen 114 is grounded, and the substrate support 130 is positively or negatively charged to form an electric field between the substrate support 130 and the shielding screen 114.

[0056] The substrate support 130 also includes coolant conduits 280. The coolant conduits 280 circulate a coolant or cooling fluid through coolant lines 281. The coolant lines 281 circulate the coolant through the substrate support 130. In one embodiment, the coolant lines 281 are disposed within the substrate support 130 and below the substrate support surface 132. The coolant lines 281 may be disposed in a circular pattern, a boustrophedonic pattern, or any other suitable pattern that enables substantially consistent and uniform cooling across the substrate support. In one embodiment, the coolant lines 281 are disposed in the same plane as the heating devices 228. Alternatively, the coolant lines 281 are disposed in a different plane than that occupied by the heating devices 228. The coolant lines 281 enable cooling and temperature control of the substrate 150 and the substrate support 130 during operation. Suitable heat transfer fluids that may be circulated through the coolant lines 281 include, but are not limited to, water, glycol-based fluids, and polymer-based fluids such as Galden®.

[0057] The chamber 100 described above can be controlled by a processor-based system controller, such as controller 270. For example, the controller 270 may be configured to control the flow of various precursor gases through the gas sources 136, 142, 152 and coordinate the operation of the source matching device 138 to facilitate plasma generation and flow within the chamber 100. The controller 270 may also be configured to control all aspects of electric field generation within the chamber 100 by varying and controlling the application of voltages to one or more of the components of the plate stack and pedestal to generate an electric field within the process volume 170. The controller 270 further operates to control various stages of a substrate processing sequence.

[0058] The controller 270 includes a programmable central processing unit (CPU) 272 operable with a memory 274 and mass storage device, an input control unit, and a display unit (not shown), such as power supplies, clocks, cache, input / output (I / O) circuits, etc., coupled to various components of the chamber 100 to facilitate control of substrate processing. The controller 270 also includes hardware for monitoring substrate processing via sensors within the chamber 100, including sensors that monitor flow rates, RF power, voltage potentials, etc. Other sensors measuring system parameters such as substrate temperature, chamber atmospheric pressure, etc. may also provide information to the controller 270.

[0059] To facilitate control of chamber 100 and associated plasma and electric field formation processes, CPU 272 may be any form of general-purpose computer processor, such as a programmable logic controller (PLC), that can be used in an industrial environment to control various chambers and subprocessors. Memory 274 is coupled to CPU 272 and is non-transitory and may be one or more of readily available memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any other form of local or remote digital storage. Support circuits 276 are coupled to CPU 272 for supporting the processor in a conventional manner. Plasma and electric field formation, as well as other processes, are typically stored in memory 274, typically as software routines. The software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware controlled by CPU 272.

[0060] The memory 274 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 272, facilitate operation of the chamber 100. The instructions in the memory 274 are in the form of a program product, such as a program that performs the methods of the present disclosure. The program code may conform to any of a number of different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The programs in the program product define the functions of embodiments (including the methods described herein).

[0061] In certain embodiments, the program embodies machine learning capabilities. Various data features include process parameters such as processing time, temperature, pressure, voltage, polarity, power, gas species, and precursor flow rates. Relationships between features are identified and defined, enabling analysis by machine learning algorithms to incorporate the data and adapt the process performed by the chamber 100. The machine learning algorithm may employ supervised or unsupervised learning techniques. Examples of machine learning algorithms embodied by the program include, but are not limited to, linear regression, logistic regression, decision trees, state vector machines, neural networks, naive Bayes, k-nearest neighbors, k-means, random forests, dimensionality reduction algorithms, and gradient boosting algorithms, among others. In one example, a machine learning algorithm is utilized to adjust RF power and precursor gas flow to form a plasma and facilitate maintaining a low ion density plasma with a higher concentration of radicals than ions. The formation of charged species in such a manner may be refined and improved by identifying the components of the charged species cloud (e.g., radicals and / or ions) and modifying chamber process or apparatus characteristics to form and maintain a charged species cloud that exhibits desired properties as an electric field coupling medium between an electrode (e.g., screen 114) and substrate support 130.

[0062] Exemplary computer-readable storage media include, but are not limited to, (i) non-writable storage media in which information is permanently stored (e.g., a read-only memory device in a computer, such as a CD-ROM disk readable by a CD-ROM drive, a flash memory, a ROM chip, or any type of solid-state non-volatile semiconductor memory), and (ii) writable storage media in which changeable information is stored (e.g., a floppy disk in a diskette drive or hard disk drive, or any type of solid-state random-access semiconductor memory). Such computer-readable storage media, when accompanied by computer-readable instructions that direct the functions of the methods described herein, are embodiments of the present disclosure.

[0063] The distance between the perforated bottom surface 242 of the gas distribution device 112 and the top surface 244 of the shielding screen 114 is less than about 20 mm, for example, less than about 20 mm, for example, about 5 mm to about 18 mm, for example, about 10 mm to about 18 mm, for example, about 12 mm to about 17 mm. The distance D between the bottom surface 234 of the shielding screen 114 and the substrate support surface 132 is about 2 mm to about 60 mm, for example, about 5 mm to about 56 mm, for example, about 16 mm to about 56 mm, for example, about 32 mm to about 56 mm. The gaps between the gas distribution device 112, the shielding screen 114, and the substrate support surface 132 are small enough to allow good electric field uniformity and large enough to prevent breakdown and discharge of gases in the second plasma generation region 218 and the process volume 170, respectively. The distance D between the shielding screen 114 and the substrate support surface 132 is configured to allow control of the plasma formed within the process volume 170 while reducing interaction of the plasma with the substrate 150. The plasma is controlled to provide a uniform, unidirectional electric field passing therethrough to interact with the substrate 150. The plasma within the process volume 170 acts to electrically couple the substrate 150 and the shielding screen 114, allowing for better control of the electric field through the process volume 170.

[0064] 2B shows a schematic cross-sectional view of a process chamber 100b according to one embodiment. The process chamber 100b is configured to perform an electromagnetic field-induced post-exposure bake operation on a substrate 150 having a photoresist or chemically modified resist layer disposed thereon. However, it is contemplated that other suitably configured process chambers may benefit from the embodiments described herein.

[0065] The process chamber 100b includes an upper chamber body 116 coupled to a lower chamber body 120. The upper chamber body 116 and the lower chamber body 120 are coupled to one another to define at least a portion of a process volume 170. A substrate support 130 is disposed within the process volume 170 and is utilized to support an overlying substrate 150 during processing. In the example of FIG. 2B, the cooling plate 265 is cooled using a temperature control technique, for example, by flowing a heat transfer fluid and / or by a thermoelectric device.

[0066] The lower chamber body 120 includes at least one substrate transfer passage 160 disposed therethrough. The transfer passage 160 may have a slit valve door configured to provide access to the process volume 170 by a transfer robot that moves the substrate 150 in and out of the process volume 170. A pumping liner may be disposed radially inward of the lower chamber body. The pumping liner includes a plurality of openings connecting an exhaust plenum and the process volume 170, allowing gases to be removed through the exhaust plenum by a pump.

[0067] A cooling plate 265 is disposed near the substrate support 130. The substrate 150 may be moved to a position immediately adjacent to the cooling plate 265 to aid in conditioning, e.g., cooling, of the substrate 150 after a post-bake process.

[0068] 2B, the cooling plate 265 has a bottom surface 141 facing the process volume 170. In the example shown in FIG. 2B, the cooling plate 265 is cooled and is immediately adjacent to the substrate support 130, although in other embodiments, other types of cooling plates may be disposed at a distance from the substrate support 130.

[0069] The cooling plate 265 has integral channels 267 connected to a coolant source 266. The integral channels 267 may extend spirally through the cooling plate 265. The coolant source 266 may provide a refrigerant such as deionized water, glycol, an inert, high-performance fluorinated heat transfer fluid, or other fluid suitable as a coolant. Alternatively, or additionally, the cooling plate 265 may have a thermoelectric cooling device, such as a Peltier cooling element. The thermoelectric cooling device may be electrically powered to provide cooling (or even heating) to the cooling plate 265.

[0070] The cooling plate 265 can be any electrically conductive material. For example, the cooling plate 265 is aluminum. In yet another example, the cooling plate 265 is an aluminum alloy having a coating. In some embodiments, the coolant source 266 supplies a coolant to the integral channels 267 during baking and cooling operations.

[0071] During exposure to the bake process, the substrate 150 rests on a substrate support 130 portion of the substrate support assembly 126. The substrate support 130 is a heated pedestal configured to control the temperature of the substrate. The substrate support assembly 126 further includes a shaft 128 and a bellows that connect the substrate support assembly 126 to the lower chamber body 120. The bellows form a seal between the process volume 170 and the external environment. One or more backside gas sources may be coupled to the substrate support assembly 126 and supply backside gas to a substrate support surface 132 of the substrate support 130.

[0072] A power source and an actuator are also coupled to the substrate support assembly 126. The power source may be an AC or DC power source. The power source is configured to provide power to the actuator 148 and / or the heating device 228 in the substrate support 130. The actuator 148 is configured to enable movement of the substrate support assembly 126, such as raising or lowering the substrate support assembly 126, rotating the substrate support assembly about a central axis, or tilting the substrate support 130.

[0073] The substrate support assembly 126 further includes a substrate lift device 137. The substrate lift device 137 is coupled to the translation assembly 135 for raising and lowering the substrate lift device 137. The substrate lift device 137 is raised to an upper position to receive the substrate 150 from the transfer robot. The substrate lift device 137 is lowered to place the substrate 150 on the substrate support surface 132 of the substrate support 130 for processing. The substrate lift device 137 may be lift pins, a hoop, an edge support ring, or any suitable device for receiving the substrate 150 from the robot blade and moving the substrate from the substrate support surface 132 of the substrate support 130 to an elevated position above the substrate support 130. In one example, the substrate lift device 137 is a plurality of lift pins. The lift pins can be moved to an upper position to pick up the substrate 150 and balance the substrate 150 on the pins. The upper position positions the substrate 150 proximate to the cooling plate 265. For example, the upper position positions the substrate 150 less than 10 millimeters from the cooling plate 265. For example, the upper position positions the substrate 150 between about 1 millimeter and about 10 millimeters from the cooling plate 265. During processing, while the heated substrate support 130 and the substrate 150 are engaged, the lift pins can move below the substrate support surface 132 of the substrate support 130 and enter into the lift pin holes. In another example, the substrate lift device 137 is a hoop with openings for a robot blade. The hoop can move to the upper position to pick up the substrate 150 and hold the substrate 150 along its edge. During processing, while the heated substrate support 130 and the substrate 150 are engaged, the hoop can move into grooves in the substrate support surface 132 of the substrate support 130.

[0074] 3 shows a schematic diagram of the process chamber 100 and cooldown chamber 302 of FIG. 1. As previously mentioned, one aspect of processing a substrate involves heating or baking the substrate to facilitate reaction of the chemically amplified resist and promote resist deprotection. In certain embodiments, a low ion density plasma is utilized as a charge transfer medium to couple a current / electric field to the substrate and facilitate directional migration of species nuclei within the resist during the resist deprotection process. In other embodiments, baking the substrate is performed without applying or generating a current or electric field to the photoresist.

[0075] In another embodiment, the substrate is heated and baked without applying a current / electric field to the substrate in the chamber 100. For example, the substrate is heated to between about 50°C and about 250°C for a period of between about 20 seconds and about 90 seconds. For example, between about 90°C and about 135°C for a period of between about 20 seconds and about 90 seconds. In yet another example, the bake process is performed at a subatmospheric pressure in a vacuum environment. For example, the process volume 170 of the process chamber 100 is maintained at a pressure between about 0.5 Torr and about 100 Torr in a vacuum environment. For example, the process volume 170 of the process chamber 100 is maintained at a pressure between about 1 Torr and about 55 Torr, such as between about 10 Torr and about 50 Torr. The subatmospheric pressure in the chamber 100 is generated by the pump 144. The subatmospheric pressure during the firing process may be kept constant or may be varied during the firing process. In one embodiment, an inert gas is delivered to the process volume 170 during the firing process. Suitable inert gases include, but are not limited to, nitrogen, helium, argon, and other sufficiently non-reactive gases.

[0076] The use of a vacuum environment during the baking process is believed to reduce the likelihood of trace contamination of the substrate, e.g., particulate contamination. Such contamination can lead to non-uniformity in the critical dimensions of features, such as contact holes. Thus, the vacuum baking process improves substrate-to-substrate uniformity. Furthermore, the vacuum baking environment is believed to provide the additional benefits of reduced line edge and width roughness, reduced device defects, and improved device yield.

[0077] After the bake process is complete, the substrate 150 is cooled. In one embodiment, the substrate 150 is cooled from the elevated bake temperature to near room temperature, for example, between about 20°C and about 30°C, over a period of between about 20 seconds and about 60 seconds. The substrate 150 may be cooled while still under vacuum in the process chamber 100. In another embodiment, to facilitate cooling, the substrate is transferred from the process chamber 100 to a cool-down chamber 302. In one embodiment, the cool-down chamber 302 is a transfer chamber or a load lock chamber. In one embodiment, the cool-down chamber 302 is coupled to the process chamber 100. Alternatively, a transfer chamber 320 is disposed between the process chamber 100 and the cool-down chamber 302. In a specific embodiment, a robot 322 is disposed within the transfer chamber 320, and the robot 322 includes a substrate transfer blade to facilitate movement of the substrate 150 from the process chamber 100 to the cool-down chamber 302.

[0078] In some embodiments, the baking and cooling of substrate 150 are performed at about the same pressure. In some embodiments, the baking is performed at a higher pressure than the cooling, but both pressures are below atmospheric pressure. In some embodiments, the baking is performed at a lower pressure than the cooling, but both pressures are below atmospheric pressure.

[0079] The cooling chamber 302 defines a volume 304. A chill plate 306 is disposed within the volume 304, and the substrate 150 is positioned on the chill plate 306 to facilitate cooling of the substrate 150 after a bake process performed in the process chamber 100. The chill plate 306 is a type of substrate support capable of cooling the substrate by flowing a coolant through an internal cavity within the chill plate. In one embodiment, the temperature of the chill plate is controlled by flowing a fluid through channels 308 within the chill plate 306. The channels 308 are in fluid communication with a fluid source 310, and fluid is flowed from the fluid source 310 through the channels 308 to cool the substrate 150 disposed on the chill plate 306. In one embodiment, the fluid provided by the fluid source 310 is a heat transfer liquid, such as water, or other suitable liquid.

[0080] In one embodiment, cooling of the substrate 150 in the cooling chamber 302 occurs in a vacuum environment. For example, the volume 304 is maintained at a subatmospheric pressure between about 0.5 Torr and about 100 Torr. The pressure maintained in the volume 304 may be constant or may be varied during the cooling process. A pump 312 or other suitable vacuum generating device is in fluid communication with the volume 304 and serves to reduce the pressure within the volume 304. In one embodiment, an inert gas is delivered to the volume 304 during the cooling process. Suitable inert gases include, but are not limited to, nitrogen, helium, argon, and other sufficiently non-reactive gases.

[0081] FIG. 4 illustrates operations of a method 400 for baking a substrate in a vacuum pressure environment, according to one embodiment. In operation 410, a mask feature is exposed on a photoresist disposed on a substrate in a lithography scanner. The lithography exposure process may be performed at atmospheric pressure or under vacuum pressure, depending on the type of exposure process utilized. In operation 420, the substrate is transferred to a post-exposure bake chamber and placed on a substrate support 130. The pressure maintained in the process volume in the post-exposure bake chamber is reduced to a pressure below atmospheric pressure, and the substrate is heated in the vacuum pressure environment. Example substrate bake parameters in a vacuum pressure environment are described with respect to FIG. 3.

[0082] In operation 430, the substrate is transferred to a chill plate, where the substrate is cooled. For example, referring to FIG. 3 , the substrate 150 is transferred from the process chamber 100 to the cooldown chamber 302, where the substrate 150 is positioned on the chill plate 306 to facilitate cooling of the substrate after the bake process performed in the process chamber 100. In operation 440, the substrate is transferred from the chill plate to a developer, where the photoresist pattern is developed. In some embodiments, at least operations 420, 430, and 440 are all performed while the substrate remains at a pressure below atmospheric pressure. In one embodiment, the substrate is transferred back to the lithography track apparatus, where a wet development process is performed at atmospheric pressure to further develop the resist.

[0083] FIG. 5 illustrates operations of a method 500 for baking a substrate in a vacuum pressure environment, according to one embodiment. In operation 510, a mask feature is exposed on a photoresist disposed on a substrate in a lithography scanner. The lithography exposure process may be performed at atmospheric pressure or under vacuum pressure, depending on the type of exposure process utilized. In operation 520, the substrate is transferred to a post-exposure bake chamber and placed on a substrate support. A process volume in the post-exposure bake chamber is brought to a sub-atmospheric pressure, and the substrate is heated in the vacuum pressure environment. In embodiments in which the substrate is maintained at a sub-atmospheric pressure during transfer from the lithography exposure process to the process chamber, the post-exposure bake chamber maintains the sub-atmospheric pressure. Example substrate bake parameters in a vacuum pressure environment are described with respect to FIG. 3.

[0084] In operation 530, the substrate 150 is cooled in the post-exposure bake chamber while remaining on the substrate support. For example, referring to FIG. 2A , the substrate 150 is in the process chamber 100, and the substrate 150 is positioned on the substrate support 130. In some embodiments, a coolant is circulated through coolant lines 281 in the substrate support 130 to facilitate cooling of the substrate 150 after the bake process performed in the process chamber 100. In other embodiments, the substrate can be cooled without the use of a coolant. In other words, the heating device 228 in the process chamber 100 stops receiving power, and as the process chamber 100 cools, the substrate 150 also cools. In some embodiments, at least operations 520, 530, and 540 are all performed, and the substrate remains at a pressure below atmospheric pressure. In operation 540, the substrate is transferred from the process chamber 100 to a developer, where the photoresist pattern is developed. In one embodiment, the substrate is transferred back to the lithography track apparatus, where a wet development process is performed at atmospheric pressure to further develop the resist. In some embodiments, referring to FIG. 2B , the substrate 150 is in the process chamber 100, and the substrate 150 is positioned on the substrate support 130. In some embodiments, the substrate 150 is raised from the substrate support 130 to stop residual heat transfer from the substrate support 130 to the substrate 150. During the raising, a coolant is circulated through integral channels 267 in the cooling plate 265 to facilitate cooling of the substrate 150 after the bake process performed in the process chamber 100. In some embodiments, during operation 530, the substrate 150 is under vacuum, but an inert gas is still disposed in the process volume 170.

[0085] By performing cooling in situ, cooling can be achieved much faster than in conventional processes where the substrate 150 is transported long distances or allowed to cool passively. Rapid cooling of the substrate 150 is enhanced by active cooling of the coolant flowing to the cooling plate 265 while remaining within the process chamber 100. Method and apparatus for rapidly cooling a substrate 150.

[0086] FIG. 6 illustrates one exemplary processing system that can be used to process substrates in accordance with embodiments disclosed herein. As illustrated, processing system 600 includes a load port 610, a coating chamber 620, a processing chamber 100, an exposure chamber 630 (such as a scanner), a second processing chamber 100, a development chamber 660, and a post-processing chamber 650. Each chamber in processing system 600 is coupled to each adjacent chamber by a transfer chamber 605 or a transfer chamber 615. Transfer chamber 605 and transfer chamber 615 may be substantially similar or different. Processing system 600 may be under vacuum. In some embodiments, one or more of chambers 100, 605, 615, 620, 630, 650, and 660 are all under vacuum, and thus, substrates are always under vacuum when transferred between chambers 100, 605, 615, 620, 630, 650, and 660.

[0087] The load port 610 can be used to introduce or remove a substrate from the processing system 600. The coating chamber 620 can be used to apply, for example, photoresist to a substrate. The coating chamber 620 can be, for example, a spin coater. The exposure chamber 630 includes a lithography scanner and can be used to expose a substrate to extreme ultraviolet (EUV) light under vacuum to form a latent acid image in a photoresist layer on the substrate. The processing chamber 100 is the chamber described above.

[0088] The developing chamber 660 can be used, for example, to remove portions of a photoresist layer. The developing chamber 660 can be a wet developing chamber or a dry developing chamber. The developing chamber 660 can develop the photoresist at a temperature between about 15° C. and about 30° C. and at atmospheric or subatmospheric pressures. For example, wet developing can occur at between about 0.5 torr and about 760 torr. For example, wet developing can occur between 100 torr and about 700 torr. In yet another example, wet developing can occur at less than 750 torr.

[0089] Post-processing chamber 650 can be used, for example, to perform various post-processing steps on the substrate. In some embodiments, post-processing chamber 650 can be the same as processing chamber 100. Processing chamber 100 can be used for pre-exposure bake, post-exposure bake, pre-develop bake, post-develop bake, and / or other processing steps.

[0090] 7 illustrates operations of a method 700 for processing a substrate in a vacuum pressure environment, according to one embodiment. In operation 710, a substrate is loaded into the processing system 600, and photoresist is applied to the substrate by the coating chamber 620. The photoresist may be applied by a spin-on process, for example, a wet spin-on process.

[0091] In operation 720, the substrate is transferred to the exposure chamber 630 and exposed to an EUV process to pattern the photoresist on the substrate. The lithography exposure process may be performed under atmospheric pressure or vacuum pressure, depending on the type of exposure process utilized. For example, the lithography exposure may be a 193 nm lithography process. The EUV process is performed under vacuum at a temperature between about 15° C. and about 30° C. For example, the EUV process is performed at a pressure between about 0.5 torr and about 760 torr, such as between 100 torr and about 700 torr. In yet another example, the pressure is less than 750 torr.

[0092] In operation 730, the substrate is transferred to the process chamber 100 / 100b, where the post-exposure bake method 400 / 500 described above is performed. The substrate is maintained at a sub-atmospheric pressure while being transferred from the lithography exposure process to the process chamber 100 / 100b, and the post-exposure bake chamber maintains the sub-atmospheric pressure. During the bake operation, the process volume and substrate within the process chamber 100 / 100b are heated in a vacuum pressure environment. Example substrate bake parameters in a vacuum pressure environment are described above.

[0093] In operation 740, the substrate 150 is cooled within the process chamber 100 / 100b. For example, referring to FIG. 2B , the substrate 150 is rapidly cooled in situ while raised from the substrate support 130 and positioned near the cooling plate 265. In some embodiments, a coolant is circulated through integral channels 267 within the cooling plate 265 to facilitate cooling of the substrate 150 after the bake process performed within the process chamber 100. In some embodiments, at least operations 720, 730, and 740 are all performed, with the substrate remaining at a subatmospheric pressure. In some embodiments, the substrate is moved to a specific cooling chamber, as described in FIG. 3, so that another substrate can be processed.

[0094] In operation 750, the substrate is transferred from process chamber 100 / 100b to developer chamber 660, where the photoresist pattern is developed. In one embodiment, the substrate is transferred back to the lithography track apparatus, where a wet development process is performed at atmospheric pressure to further develop the resist.

[0095] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the appended claims.

Claims

1. exposing a photoresist disposed on a substrate to electromagnetic energy; transferring the substrate onto a substrate support disposed within a process chamber; baking the substrate on the substrate support in a first vacuum environment at a pressure below atmospheric pressure; cooling the substrate in a second vacuum environment at a second sub-atmospheric pressure; A substrate processing method comprising:

2. The method of claim 1 , wherein the first sub-atmospheric pressure is between about 0.5 Torr and about 100 Torr.

3. The method of claim 2 , wherein the first subatmospheric pressure is constant during the firing.

4. The method of claim 2 , wherein the first sub-atmospheric pressure is varied during the calcination.

5. The method of claim 1 , wherein the substrate is heated to a temperature between about 50° C. and about 250° C. during the baking.

6. The method of claim 1 , wherein the cooling step is performed in a chamber different from the process chamber.

7. 7. The method of claim 6, wherein the second sub-atmospheric pressure is between about 0.5 Torr and about 100 Torr.

8. The method of claim 7 , wherein the second sub-atmospheric pressure is constant during cooling of the substrate.

9. The method of claim 7 , wherein the second sub-atmospheric pressure is changed during cooling of the substrate.

10. 10. The method of claim 1, wherein the step of baking the substrate is performed without applying or generating a current or electric field to the photoresist.

11. exposing a chemically amplified photoresist disposed on a substrate to a lithographic exposure process at a subatmospheric pressure; transferring the substrate onto a substrate support disposed within a process chamber having a process volume; baking the substrate in the process volume in a vacuum environment at sub-atmospheric pressure; cooling the substrate in the process volume of the process chamber at the subatmospheric pressure; A substrate processing method comprising:

12. The method of claim 11, wherein the subatmospheric pressure is between about 1 Torr and about 55 Torr.

13. The method of claim 11, wherein the substrate is heated to a temperature between about 90° C. and about 135° C. during the baking.

14. The method of claim 11 , wherein the substrate is maintained at the sub-atmospheric pressure during the exposing, the transferring, the baking, and the cooling.

15. The method of claim 11 , wherein cooling the substrate further comprises elevating the substrate proximate a cooling plate.

16. The method of claim 15 , wherein the substrate is less than 10 millimeters from the cooling plate.

17. applying a photoresist to a substrate in a coating chamber; transferring the substrate to an exposure chamber and performing an EUV exposure process under vacuum; transferring the substrate onto a substrate support within a process chamber having a process volume; baking the substrate on the substrate support in the process volume at subatmospheric pressure; cooling the substrate to less than 30° C. at a pressure less than 100 Torr in the process volume of the process chamber by raising the substrate toward a cooling plate opposite the substrate support; transferring the substrate from the process chamber to a developer and developing the photoresist; A substrate processing method comprising:

18. The method of claim 17, wherein the substrate is heated to a temperature between about 90° C. and about 135° C. during the baking.

19. 18. The method of claim 17, wherein the sub-atmospheric pressure is maintained between the exposing and the baking of the substrate.

20. 20. The method of claim 17, wherein the step of cooling the substrate is performed at a pressure lower than the pressure during the baking.

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