Data Reuse Cache

Abstract

A data reuse cache technique is described. In one example, a load instruction is generated by an execution unit of a processor unit. In response to the load instruction, data is loaded by a load-store unit for processing by the execution unit and stored in a data reuse cache communicatively coupled between the load-store unit and the execution unit. Upon receiving a subsequent load instruction for the data from the execution unit, the data is loaded from the data reuse cache for processing by the execution unit.

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to U.S. patent application Ser. No. 17 / 955,618, entitled "Data Reuse Cache," filed Sep. 22, 2022, the entire disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] Processor units, such as central processing units, parallel processors, and graphics processing units, are tasked with processing ever-increasing amounts of data. Access to this data is a key factor in the speed at which the processor unit can process data. To address this, cache systems are used to speed up this access. However, conventional techniques used to implement cache systems face various challenges, including latency, throughput, trade-offs between size and speed, etc. These challenges hinder the operation of processor units in conventional real-world scenarios, and their impact is compounded by ever-increasing amounts of data.

[0003] The detailed description is made with reference to the accompanying drawings. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram of a non-limiting exemplary system configured to employ data reuse caching techniques. [Figure 2] 2 is a block diagram of a non-limiting exemplary system configured to employ data reuse caching techniques in a multi-core processor architecture in which the level 1 cache of FIG. 1 is implemented as a split cache. [Figure 3] FIG. 1 is a block diagram of a non-limiting exemplary system configured to employ data reuse cache techniques to fill a data reuse cache using load responses as virtual memory addresses. [Figure 4] FIG. 1 is a block diagram of a non-limiting exemplary system configured to employ a filter module and a filter as part of a data reuse cache technique to control access to a data reuse cache. [Figure 5] FIG. 10 is a flow diagram illustrating a procedure in a non-limiting example embodiment of the operation of a data reuse cache. DETAILED DESCRIPTION OF THE INVENTION

[0005] (overview) The efficiency with which a processor unit accesses data has a significant impact on the overall speed and operation of the processor unit, and the efficiencies gained by providing this access capability improve the operating speed of the processor unit, reduce power consumption, conserve bandwidth, and support a variety of other technical advantages in the utilization of the processor unit and devices that use it.

[0006] Accordingly, data reuse cache techniques, systems, and devices are described that further increase the technical advantages obtained through the use of cache by a processor unit. In one example, the processor unit is implemented in hardware as, for example, a central processing unit, a graphics processing unit, a parallel processor, etc. The processor unit can be configured to include multiple cores, including cache levels that store data within the cores, cache levels that are shared between the cores, etc.

[0007] The core includes, for example, an execution unit, a load / store unit, and one or more cache levels. The execution unit is configured to issue instructions that process data using corresponding operations. The load / store unit is configured to load data to be processed by the execution unit and store the data in memory. The cache levels are configured to balance size and speed with progressively larger levels to improve data access efficiency. The configuration of the cache levels exploits various locality factors. Spatial locality is used to improve performance in situations where data stored physically close to data that is the subject of a previous request is required. Temporal locality is used to address scenarios where already requested data is required again.

[0008] In cache operations, a "hit" occurs at a cache level when the desired data that is the target of a load operation is available through that cache level, and a "miss" occurs when the desired data is not available through that cache level. When multiple cache levels are used, a request passes through successive cache levels until the data is found. However, frequent cache misses have the adverse effect of reducing or even completely eliminating the performance gains gained by incorporating cache levels as part of a processor unit.

[0009] To address these issues, a data reuse cache is implemented as part of the processor unit between the execution unit and the load store unit. For example, the data reuse cache is physically located closer to the execution unit than the load store unit or cache system, e.g., having a level 1 cache, a level 2 cache, etc. In one example, the data reuse cache is implemented solely for data reuse of load responses that include data fetched by the load store unit. Furthermore, in one example, the data reuse cache is configured to be accessed in parallel with a cache system, e.g., a level 1 data cache.

[0010] The data reuse cache is loaded based on a load response from, for example, a load-store unit. In real-world scenarios, data loaded in response to a load instruction is often reused by itself or other instructions in turn before going dormant. This keeps the data closer to the execution unit, speeding up reuse and reducing the computational cost of reloading the data. In effect, the four cycles typically used to access data from a level 1 cache are reduced to two cycles to access data from the data reuse cache, thereby improving the operation of the processor unit and the device as a whole.

[0011] Furthermore, as discussed above, cache misses introduce additional latency, reducing the benefits gained by incorporating a cache. For example, configuring a data reuse cache to be smaller in size to improve speed can increase the miss rate, creating challenges. To address these issues, filter techniques can be employed (e.g., by the execution units) to filter instructions based on the likelihood that the instruction will hit or miss the data reuse cache. In this manner, a filter is used to filter load instructions that always miss the data reuse cache, and these load instructions are passed directly to the cache levels via the load-store unit without incurring the performance degradation caused by incorporating a data reuse cache. Various other cases are also contemplated, examples of which are described below and illustrated using corresponding figures.

[0012] In some aspects, the techniques described herein relate to a method that includes generating a load instruction at an execution unit; loading, in response to the load instruction, data from a load response obtained from a load-store unit for processing by the execution unit; storing the data from the load response in a data reuse cache communicatively coupled between the load-store unit and the execution unit; generating a subsequent load instruction for the data at the execution unit; and loading the data from the data reuse cache in response to the subsequent load instruction for processing by the execution unit.

[0013] In some aspects, the techniques described herein relate to a method in which loading the data includes loading the data from a level of a cache system by a load store unit.

[0014] In some aspects, the techniques described herein relate to a method in which loading data from a load response is performed in four cycles from the cache system level, and loading data from a data reuse cache is performed in two cycles.

[0015] In some aspects, the techniques described herein relate to a method further including generating a subsequent load instruction and routing the subsequent load instruction for processing by a load-store unit based on detecting that the subsequent load instruction spans two or more cache lines of the data reuse cache.

[0016] In some aspects, the techniques described herein relate to a method further including generating a subsequent load instruction and triggering a resynchronization operation based on detecting that data targeted by the subsequent load instruction is stale.

[0017] In some aspects, the techniques described herein relate to a method further including self-broadcasting a data reuse cache response including the data, where the self-broadcast uses a broadcast port of the load store unit.

[0018] In some aspects, the techniques described herein relate to a method further including using a filter to control whether subsequent load instructions are allowed or restricted from accessing the data reuse cache.

[0019] In some aspects, the technology described herein relates to a method, wherein a filter indicates the likelihood that a subsequent load instruction is a hit or a miss to a data reuse cache.

[0020] In some aspects, the techniques described herein relate to a method in which a subsequent load instruction is included in a plurality of load instructions, the filter maintains a plurality of hit counters for the plurality of load instructions, respectively, and the control is based on values ​​of the plurality of hit counters.

[0021] In some aspects, the technology described herein relates to a processor unit that includes a cache system including multiple cache levels; a load-store unit configured to generate a load response from the cache system for processing by an execution unit; a data reuse cache communicatively coupled between the execution unit and the load-store unit, the data reuse cache configured to store data of the load response; and an execution unit configured to filter load instructions for access to the data reuse cache based on respective likelihoods that the load instructions will result in a hit or a miss, respectively, to the data reuse cache.

[0022] In some aspects, the techniques described herein relate to a processor unit in which a data reuse cache is physically located closer to the execution units on an integrated circuit than the load-store units or cache system.

[0023] In some aspects, the techniques described herein relate to a processor unit, wherein each probability is based on a value of a hit counter maintained for each load instruction, the value of the hit counter indicating a number of times the load instruction from the data reuse cache is a hit.

[0024] In some aspects, the techniques described herein relate to a processor unit, wherein the values ​​of the hit counters each indicate the number of times a load instruction from a data reuse cache is a hit over a window defining a threshold number of hits.

[0025] In some aspects, the techniques described herein relate to a processor unit, wherein the execution unit is configured to generate respective miss-hit probabilities for each of the load instructions, and, in response to the generation, control access to a data reuse cache by restricting access and allowing direct access to multiple cache levels.

[0026] In some aspects, the techniques described herein relate to a processor unit that includes a cache system including a cache level; an execution unit configured to access a data reuse cache in parallel with accesses to the cache level of the cache system via a load store unit; a data reuse cache communicatively coupled between the execution unit and the load store unit; and a load store unit configured to generate a load response from the cache system in response to a load instruction received from the execution unit, load data from the load response into the execution unit for processing, and store the data from the load response in the data reuse cache.

[0027] In some aspects, the techniques described herein relate to a processor unit, wherein a load instruction is included as part of a plurality of load instructions, and wherein an execution unit is configured to filter the plurality of load instructions to control access to the data reuse cache based on respective probabilities of a hit or miss to the data reuse cache.

[0028] In some aspects, the techniques described herein relate to a processor unit, where each probability is based on the value of a hit counter maintained for each of a plurality of load instructions.

[0029] In some aspects, the techniques described herein relate to a processor unit, wherein values ​​of hit counters each indicate a number of times that multiple load instructions from a data reuse cache are hits.

[0030] In some aspects, the techniques described herein relate to a processor unit, wherein the cache level is a level 1 data cache.

[0031] In some aspects, the techniques described herein relate to a processor unit where a load instruction is included as part of a plurality of load instructions, and the execution unit is configured to generate respective probabilities of misses for each of the plurality of load instructions, and in response to the generation, control access by restricting access to a data reuse cache and allowing direct access to a cache level.

[0032] 1 is a block diagram of a non-limiting exemplary system 100 configured to employ data reuse caching techniques. System 100 includes a device 102 having a processor unit 104, physical volatile memory 106 (e.g., random access memory), and persistent storage 108 (e.g., a hard drive). Device 102 can be configured in a variety of ways. Examples include, but are not limited to, computing devices, servers, mobile devices (e.g., wearables, mobile phones, tablets, laptops), processors (e.g., graphics processing units, central processing units, and accelerators), digital signal processors, disk array controllers, hard disk drive host adapters, memory cards, solid-state drives, wireless communication hardware connections, Ethernet hardware connections, switches, bridges, network interface controllers, and other device configurations. It should be understood that in various embodiments, device 102 can be configured as any one or more of the above-listed devices and / or various other devices without departing from the spirit or scope of the described technology.

[0033] Processor unit 104 includes execution unit 110, load store unit 112, and cache system 114. Execution unit 110 represents the functionality of processor unit 104 implemented in hardware to perform operations based on instructions received, for example, through the execution of software. Execution unit 110 includes registers 116 configured to maintain data to be processed by execution unit 110, for example, arithmetic and logical operations.

[0034] Load-store unit 112 represents the functionality of processor unit 104 for executing load and store instructions. Load instructions and corresponding operations involve loading data from cache system 114, physical volatile memory 106, and / or persistent storage 108 into registers 116 of execution units 110 for processing. Store instructions and corresponding operations involve saving data from registers 116 back to cache system 114, physical volatile memory 106, and / or persistent storage 108 (e.g., after processing by execution units 110).

[0035] Load store unit 112 is configured to support the use of virtual memory, for example, by translating virtual memory addresses used by software into physical memory addresses. Virtual memory is a technique for managing the use of shared physical memory. Virtual memory supports a variety of different functions. Examples of these functions include expanding the amount of storage made available to an application beyond the amount actually available in physical memory, offloading memory management from applications and the operating system, using a variety of different types of memory without application awareness, supporting memory optimization, addressing memory fragmentation, etc., which are further described in connection with FIG. 4.

[0036] Cache system 114 includes multiple cache levels 118, examples of which are shown as level 1 cache 120(1) through level "N" cache 120(N). The configuration of cache levels 118 is utilized to take advantage of various locality factors. Spatial locality is used to improve performance in situations where data stored in close physical proximity to data that is the subject of a previous request is requested. Temporal locality is used to address scenarios where data that has already been requested is requested again.

[0037] In a cache operation, a "hit" occurs for a cache level if the data that is the subject of the load operation is available through that cache level, and a "miss" occurs if the desired data is not available through that cache level. When multiple cache levels are used, the request proceeds through successive cache levels 118 until the data is found. The cache system 114 can be configured in various ways (e.g., in hardware) to accommodate various processor unit 104 configurations, such as central processing unit caches, graphics processing unit caches, parallel processor unit caches, digital signal processor caches, etc.

[0038] Processor unit 104 also includes data reuse cache 122. Data reuse cache 122 is physically located on processor unit 104 between load-store unit 112 and execution units 110 (e.g., using hardware circuitry on an integrated circuit). Data reuse cache 122 is configured to exploit scenarios in which data loaded by a load instruction of load-store unit 112 is subsequently accessed again, e.g., by itself or other instructions. Keeping this data close to execution unit 110 for faster reuse reduces the cost incurred in loading data from cache level 118, e.g., level 1 cache 120(1). In one example, data reuse cache 122 is accessible in parallel with cache system 114 via load-store unit 112, e.g., via a level 1 data cache, as further described in connection with FIG. 2.

[0039] The data reuse cache 122 can be configured to be "filled" based on load responses generated by the load store unit 112. In one example, the data reuse cache 122 is configured solely for data reuse. Any load response from the load store unit 112 can be used to fill the data reuse cache 122, for example, from a cache level 118 of the cache system 114, the physical volatile memory 106, the persistent storage 108, etc. In one embodiment, complex memory data communications are delegated to the load store unit 112, thereby improving operational efficiency, as further described below with respect to FIG. 4 . In this manner, the data stored in the data reuse cache 122 is more likely to be relevant to a subsequent load instruction, thereby reducing the probability of a cache miss.

[0040] In another example of a technique that can be used to solve these problems, filter module 124 and filter 126 are used by execution unit 110 to manage load operations. Filter module 124 uses filter 126 to control access by load operations to data reuse cache 122. For example, load operations that have less than a threshold amount of likelihood of resulting in a hit in data reuse cache 122 are restricted from accessing data reuse cache 122. Instead, these load operations are targeted directly to cache level 118 via load store unit 112.

[0041] As a result, performance degradation caused by cache misses to data reuse cache 122 is avoided, thereby supporting implementation as a smaller cache with improved access efficiency, i.e., speed. Other examples include the use of virtual memory addresses by data reuse cache 122, the use of self-broadcast to trigger dependent operations rather than using traditional broadcast, and leveraging logic in load store unit 112 to verify data correctness, such as ordering violations and data consistency. Further description of these and other examples is included in the following description and shown in the corresponding figures.

[0042] 2 is a block diagram of a non-limiting exemplary system 200 configured to employ data reuse caching techniques in a multi-core processor architecture in which the level 1 cache 120(1) of FIG. 1 is implemented as a split cache. The processor unit 104 is configured as a single integrated circuit having multiple cores, shown as a first core 202 through an "N" core 204. The first core 202 is shown in more detail and includes an execution unit 110 and a load store unit 112, as described above.

[0043] Cache system 114 is shown as having a level 1 cache 120(1) included as part of first core 202 and a level 2 cache 210. A level 3 cache 212 is shared by first core 202 and "N" core 204. Other examples are contemplated, such as level 2 cache 210 including a level 4 cache shared by first core 202 and "N" core 204.

[0044] Level 1 cache 120(1) is implemented using a split cache architecture in which two separate level 1 caches are maintained, e.g., level 1 instruction cache 206 and level 1 data cache 208. This architecture supports a number of technical features, such as concurrent operations in which data is read from level 1 data cache 208 while instructions are loaded from level 1 instruction cache 206.

[0045] As previously mentioned, data reuse cache 122 is physically located between execution units 110 and load store units 112, and is therefore physically closer to execution units 110 than the cache levels of cache system 114. In this example, data reuse cache 122 is accessible in parallel with level 1 data cache 208 via load store unit 112. Data reuse cache 122 is "filled" with data communicated in load responses, for example, in response to a "hit" to either a cache level or other memory, as further described below and in connection with the corresponding figures. Various other examples are also contemplated.

[0046] 3 is a block diagram of a non-limiting exemplary system 300 configured to employ data reuse cache techniques to fill data reuse cache 122 using load responses from a load-store unit as virtual memory addresses. As shown in this example, a load instruction 302 is received by load-store unit 112 and used to access cache system 114, e.g., level 1 data cache 208. A load response 304 from load-store unit 112 is then returned (e.g., to load register 116 of execution unit 110) and is also utilized to fill data reuse cache 122. In this manner, the existing load response bus from load-store unit 112 can also be used to fill data reuse cache 122, thereby saving power and not using additional hardware circuitry. The cache line size, in one example, is configured to match the width of these load response buses.

[0047] In one embodiment, data is accessible through data reuse cache 122 in fewer cycles than the number of cycles used to access data through each cache level 118 of cache system 114. Loading data from level 1 data cache 208 into execution units 110 in response to a load instruction 302 typically occurs in four cycles. However, loading data from data reuse cache 122 for processing by execution units 110 in response to a subsequent load instruction can occur in two cycles.

[0048] Data reuse cache 122 is configured to utilize virtual memory addresses 306 to locate corresponding data in data reuse cache 122. In some examples, the physical memory address of a load instruction is not available until a translation lookaside buffer (TLB) translation is performed by load store unit 112. Therefore, virtual memory addresses 306 are utilized with respective tags 308 and data blocks 310, thereby improving efficiency.

[0049] In some instances, aliasing occurs, where multiple virtual memory addresses point to the same physical address location. In these instances, the load operation may miss in data reuse cache 122, even though the data is actually available under different virtual memory addresses. Instead, these situations are handled by load-store unit 112 as, for example, a reuse cache miss, and handled in level 1 cache 120(1) using physical tags. Furthermore, in one embodiment, data reuse cache 122 supports load operations that align with cache line boundaries. Load operations that span more than one cache line can be handled as a miss, with the load instead being routed to load-store unit 112 for processing by the load-store unit, for example, to access another cache, physical memory, etc.

[0050] 4 is a block diagram of a non-limiting exemplary system 400 configured to employ a filter module 124 and a filter 126 as part of a data reuse cache technique to control access to the data reuse cache 122. The filter module 124 is implemented, in this example, by a dispatch unit as part of the execution unit 110. The filter module 124 is configured to remove and restrict (i.e., "filter") accesses of load instructions 302 to the data reuse cache 122 based on the likelihood of a miss occurring. Thus, the filtered load instructions 302 bypass access to the filter module 124 and directly access the cache level 118 without incurring performance degradation.

[0051] The filter module 124 is configured to train the filter 126, for example, by checking the tag 308 against a hit / miss indicator. The filter 126 can be configured as a set-associative structure indexed by a program counter (i.e., instruction pointer), where a hashed version of the program counter serves as the tag 308. For example, when the first hit to the data reuse cache 122 is detected, an entry is assigned to the respective program counter. Each entry in the filter 126 tracks a value (e.g., number of hits) using a hit counter 402 over a window, such as a threshold number of lookups against the program counter. In one example, both counters bit-shift right upon saturation.

[0052] The filter module 124 then decides whether to allow or restrict access based on the filter 126. Program counters with hit rates higher than a threshold amount (e.g., 50 percent) allow the filter module 124 to access the data reuse cache 122. In real-world scenarios, this reduces misses to the data reuse cache 122 by more than 20 times, allowing use of the data reuse cache 122.

[0053] Accesses to data reuse cache 122 can be treated as fixed-cycle execution unit 110 operations. Selected load operations that have exceeded their dispatch time in data reuse cache 122 (e.g., operations executed when an instruction or microinstruction {e.g., a UOP} is dispatched in the dispatch unit) “self-broadcast” to the address generation unit to invoke dependent operations rather than waiting for load-store unit 112. To avoid adding an additional broadcast port to each address generation unit (the arithmetic logic unit used to calculate the address of a load or store microinstruction), execution unit 110 opportunistically uses the broadcast port of load-store unit 112 to broadcast data reuse cache 122 data responses. If a conflict occurs between a data response of level 1 cache 120(1) and a data response attempt of data reuse cache 122 to broadcast in the same cycle, level 1 cache 120(1) takes priority, and the access attempt to data reuse cache 122 is dropped and instead treated as a data reuse cache miss.

[0054] When access attempts to data reuse cache 122 are restricted (i.e., filtered), the access attempts (i.e., corresponding load instructions) are subject to accesses to level 1 cache 120(1) by load store unit 112. These load operations can incur additional latency because load store unit 112 is tasked with waiting until it receives an indication of a hit or miss to data reuse cache 122. Therefore, in some instances, to conserve power, load store unit 112 is configured not to read data reuse cache 122 load accesses from level 1 cache 120(1).

[0055] Load store unit 112 includes a data verification module 404 that represents functionality that manages techniques to promote data correctness of load responses. Data verification module 404 is used, for example, to verify ordering violations and data consistency on hits from data reuse cache 122. Additionally, data verification module 404 is configured to trigger a resynchronization operation when warranted, for example, when data targeted by a load instruction in data reuse cache 122 is detected as stale.

[0056] Load store unit 112 may also be configured to perform the following functions in support of data reuse cache 122: To fill data reuse cache 122, load store unit 112 sends a load data size and waits for a load response from level 1 cache 120(1) to execution unit 110 as described above. In a further example, a resynchronization operation is triggered for a store-interlocked load operation that also hits in data reuse cache 122. In a further example, an invalidation probe is sent to data reuse cache 122 when a store operation commits to level 1 cache 208(1) (e.g., level 1 data cache 120), an invalidation probe is sent to data reuse cache 122 upon eviction of level 1 data cache 208, and so on.

[0057] In one example, as described above, data reuse cache 122 utilizes virtual memory addresses 306 rather than physical addresses. However, because of this, an L1 cache line cannot be invalidated from data reuse cache 122 using its physical address. To address this, in one example, physical addresses rather than virtual addresses are maintained in data reuse cache 122. In another example, each data reuse cache line in data reuse cache 122 is tagged with the way of the corresponding L1 line and also includes an L1 index (e.g., using additional bits) to implement similar functionality. This is due to the increased data storage size in this example of the L1 cache compared to data reuse cache 122, and therefore the data reuse cache index bits are a subset of the L1 cache index bits. The non-overlapping portions of the bits are preserved. An invalidation probe from a store operation (when committing to the L1 cache or from an evicted L1 cache line) includes the “L1 way” to correctly perform the invalidation operation in data reuse cache 122. In yet another example, a resynchronization operation is triggered if a load operation that "hits" in data reuse cache 122 misses in the level 1 cache, or if the "L1 way" information in data reuse cache 122 does not match the actual way of the level 1 hit.

[0058] The transfer of data from an in-flight store to an in-flight load involves complex timing of structure and priority encoding. In one embodiment, the load-store unit 112 is tasked with handling load operations that may be interlocked (full or partial address match) on older stores in-flight to the load-store unit, rather than adding complexity to the execution units. This can be done by triggering a resynchronization operation (e.g., full pipeline flush / restore and fetch resume) every time an interlock is detected for a load operation in data reuse cache 122.

[0059] Resynchronization operations are costly to performance and, if not controlled, can place an excessive burden on device operation. Various mitigation solutions can be used by processor unit 104 to reduce the number of resynchronization operations. In one example, when a store operation completes address calculation, the cache line in data reuse cache 122 is invalidated. This causes newer load operations that may interlock on the store to miss in data reuse cache 122 and be processed by load-store unit 112 instead.

[0060] In another example, load operations are precluded from reads to the data reuse cache 122 that are predicted to be transferred from an in-flight store or that are predicted to trigger a resync operation, thereby further reducing the chance of a resync operation. Memory dependency prediction, memory rename and resync operation prediction are available at runtime.

[0061] A store operation that invalidates a cache line in data reuse cache 122 using a virtual memory address may leave an aliased copy, keeping the old copy alive. To flush the old copy of data reuse cache 122, data reuse cache 122 is probed out when the store operation completes, i.e., when the data is written to level 1 data cache 208. Various other examples are also contemplated.

[0062] 5 illustrates a procedure 500 in an exemplary embodiment of the operation of data reuse cache 122. Data is stored (block 502). As an example, the data is stored by load store unit 112 in level 1 cache 120(1) (e.g., level 1 data cache 208) for processing by execution unit 110. Other examples include additional levels of cache system 114, physical volatile memory 106, persistent storage 108, etc.

[0063] A load instruction is generated by the execution unit (block 504). As an example, the load instruction 302 is generated and communicated to the load store unit 112.

[0064] In response to the load instruction (block 506), data is loaded from a load response obtained from the load-store unit for processing by the execution unit (block 508). The data is also stored in a data reuse cache communicatively coupled between the load-store unit and the execution unit (block 510). As an example, in response to the load instruction, data is loaded from level 1 cache 120(1) (e.g., level 1 data cache 208) into the execution unit 110 for processing and stored in data reuse cache 122.

[0065] A subsequent load instruction is generated (block 512). As an example, the subsequent load instruction is generated by execution unit 110. A filter module uses a filter to control whether to allow or restrict access of the subsequent load instruction to the data reuse cache (block 514). As an example, execution unit 110 includes filter module 124 and filter 126. Filter 126 is configured to predict the likelihood that each load instruction will result in a hit or miss to data reuse cache 122, for example, using a hit counter and a window relative to a threshold hit rate.

[0066] Depending on the access permission control by the filter module, the load instruction to the data reuse cache is executed (block 516). As an example, the execution unit 110 queries the tag 308 of the data reuse cache 122 to determine whether the data is available through the cache. If available, the data is returned for processing by the execution unit 110, e.g., in two execution cycles of the processor unit 104. If not available, the query passes through the cache level 118 of the cache system 114.

[0067] Depending on the control of the access restrictions by the filter module, the load instruction is executed directly to the cache level (block 518). By way of example, the request is not made to the data reuse cache 122. Rather, the level 1 cache 120(1) (e.g., the level 1 data cache 208) is checked to determine data availability by the load-store unit 112. If the data is available, the data is returned for processing by the execution unit 110. If the data is not available, the query passes through the cache level 118 of the cache system 114 to the physical volatile memory 106, persistent storage 108, etc.

[0068] It should be understood that many variations are possible based on the disclosure herein, and although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0069] The various functional units illustrated in the figures and / or described herein (including device 102, where appropriate) may be implemented in any of a variety of different ways, such as hardware circuits, software or firmware running on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods may be implemented in any of a variety of devices, such as a general-purpose computer, a processor, or a processor core. Suitable processors include, by way of example only, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), a graphics processing unit (GPU), a parallel-accelerated processor, multiple microprocessors, one or more microprocessors associated with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine.

[0070] In one or more embodiments, the methods and procedures provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

[0071] Although the systems and techniques have been described in language specific to structural features and / or methodological acts, it is to be understood that the systems and techniques defined in the appended claims are not necessarily limited to the particular features or acts described. Rather, the particular features and acts are disclosed as exemplary forms of implementing the claimed invention.

Claims

1. 1. A method comprising: generating a load instruction in an execution unit; In response to the load instruction: loading load response data obtained from a load store unit for processing by the execution unit; storing data of the load response in a data reuse cache communicatively coupled between the load store unit and the execution unit; generating a subsequent load instruction for the data in the execution unit; and loading the data from the data reuse cache for processing by the execution unit in response to the subsequent load instruction. method.

2. loading the data includes loading the data from a level of a cache system by the load store unit; 10. The method of claim 1.

3. loading the data of the load response is performed in four cycles from the cache system level, and loading the data from the data reuse cache is performed in two cycles. The method of claim 2.

4. generating a subsequent load instruction; and routing the subsequent load instruction for processing by the load store unit based on detecting that the subsequent load instruction spans two or more cache lines of the data reuse cache.

10. The method of claim 1.

5. generating a subsequent load instruction; triggering a resynchronization operation based on detecting that the data subject to the subsequent load instruction is stale; 10. The method of claim 1.

6. self-broadcasting a data reuse cache response including the data; the self-broadcasting uses a broadcast port of the load store unit.

10. The method of claim 1.

7. using a filter to control whether to allow or restrict access to the data reuse cache by the subsequent load instruction; 10. The method of claim 1.

8. the filter indicates the likelihood that the subsequent load instruction is a hit or a miss to the data reuse cache. The method of claim 7.

9. the subsequent load instruction is included in a plurality of load instructions, the filter maintains a plurality of hit counters for the plurality of load instructions, and the controlling is based on values ​​of the plurality of hit counters. The method of claim 7.

10. a cache system including multiple cache levels; a load store unit configured to generate a load response from the cache system for processing by an execution unit; a data reuse cache communicatively coupled between the execution unit and the load store unit, the data reuse cache configured to store data of the load response; the execution unit configured to filter load instructions for access to the data reuse cache based on a likelihood that the load instructions will result in a hit or a miss to the data reuse cache. Processor unit.

11. the data reuse cache is physically located closer to the execution unit on the integrated circuit than the load store unit or the cache system; The processor unit of claim 10.

12. the likelihood is based on a value of a hit counter maintained for the load instruction, the value of the hit counter indicating a number of times the load instruction from the data reuse cache is a hit; The processor unit of claim 10.

13. the value of the hit counter indicates the number of times the load instruction from the data reuse cache has hit over a window defining a threshold number of hits; The processor unit of claim 12.

14. The execution unit: generating a miss probability for each load instruction; In response to said generating, restricting access to said data reuse cache and allowing direct access to said plurality of cache levels; configured to control access by The processor unit of claim 10.

15. a cache system including a cache level; an execution unit configured to access a data reuse cache in parallel with accessing the cache level of the cache system via a load store unit; the data reuse cache communicatively coupled between the execution unit and the load store unit; the load store unit; The load store unit comprises: generating a load response from the cache system in response to a load instruction received from the execution unit; loading the load response data into the execution unit for processing; storing the load response data in the data reuse cache; configured to: Processor unit.

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