Fabrication method of oxide-nitride-oxide stack for nonvolatile memory and its integration into CMOS process flow

Abstract

A method for fabricating a semiconductor device is described. Generally, the method includes forming a customizable oxide-nitride (ONO) stack on a substrate in an in situ atomic layer deposition (ALD) tool or chamber. A radical oxidation or oxide deposition process step is performed to form a tunnel dielectric layer overlying the substrate. A silicon nitride deposition process step is also performed to form a multilayer charge trapping (CT) layer, and at least some of the process parameters of the silicon nitride deposition process step are adjusted in forming first and second CT sublayers of the multilayer CT layer. A subsequent radical oxidation or oxide deposition process step is performed in the ALD tool to form a blocking dielectric layer overlying the multilayer CT layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is an international application of U.S. Provisional Patent Application No. 17 / 954,141, filed September 27, 2022, the contents of which are incorporated herein by reference.

[0002] Technical Field The present disclosure relates generally to non-volatile memory (NVM) cells or devices, and more specifically to silicon (semiconductor)-oxide-nitride-oxide-silicon (semiconductor) (SONOS) based NVM cells or devices, and methods for fabricating same. [Background technology]

[0003] NVM is widely used in computer systems to store data and typically comprises a memory array with a large number of NVM cells arranged in rows and columns or other configurations. For the past several decades, scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increase in the density of functional units in the limited area of ​​a semiconductor chip. However, the drive to ever greater capacity is not without problems. The need to optimize the performance of each device as it scales becomes increasingly important.

[0004] In some embodiments, an NVM cell may include at least a nonvolatile element, such as a charge-trapping field-effect transistor (FET), a floating-gate transistor (programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between the control / memory gate and the substrate or drain / source region). For example, in an n-channel charge-trapping FET, a positive gate-to-substrate voltage causes electrons to tunnel from the channel by Fowler-Nordheim (FN) tunneling and be trapped in a charge-trapping dielectric layer, raising the transistor's threshold voltage (V T ) or increase the drain current (I DA negative gate-to-channel voltage causes holes to tunnel from the channel and get trapped in the charge-trapping dielectric layer, lowering the V T Lower or I D In some embodiments, a SONOS-based memory array is used and operated as a digital data storage device, where two separate V T or I D Based on the level or value of the bit, binary bits (0 and 1) of data are stored.

[0005] There is a demand for NVM technologies, such as SONOS, to be used for analog memory and processing because they allow for multiple discrete, configurable V T and I D SONOS memory cells offer desirable low latency, power, and noise behavior for analog processing, including edge inference computations, such as neuromorphic computing in artificial intelligence (AI) applications. However, multi-level SONOS memory cells present more challenges in scaling, such as charge retention in the ONO stack, V T This may induce degradation and / or migration of Summary of the Invention [Problem to be solved by the invention]

[0006] It is therefore an object of the present invention to propose an improved manufacturing method for forming an ONO stack in a SONOS memory cell and to integrate such a process into a baseline complementary metal oxide semiconductor (CMOS) process flow. [Means for solving the problem]

[0007] The present invention will be more fully understood from the following detailed description and from the accompanying drawings and claims provided below.

[0008] Detailed Description The following description sets forth numerous specific details, such as examples of specific systems, elements, methods, etc., to provide a thorough understanding of some embodiments of the subject matter. However, it will be apparent to those skilled in the art that at least some embodiments may be practiced without these specific details. In other instances, well-known elements or methods are not described in detail or are shown in simple block diagram form to avoid unnecessarily obscuring the technology described herein. Thus, the specific details set forth below are merely exemplary. Specific implementations may vary from these example details and still be construed as being within the spirit and scope of the subject matter.

[0009] Embodiments of memory cells including SONOS-based transistors, with or without metal-oxide-semiconductor (MOS) transistors or field-effect transistors (FETs), and methods for fabricating the same are described herein with reference to the drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods, materials, and devices in the relevant art. In the following description, numerous specific details, such as specific materials, dimensions, concentrations, and process parameters, are provided to provide a thorough understanding of the subject matter. In other instances, well-known semiconductor design and fabrication techniques are not described in particular detail to avoid unnecessarily obscuring the subject matter. References in the description to "an embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the subject matter. Furthermore, the appearances of the phrases "embodiment," "one embodiment," "example embodiment," "some embodiments," and "various embodiments" in various places in the description do not necessarily all refer to the same embodiment.

[0010] The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings illustrate illustrative embodiments. Those embodiments, sometimes referred to herein as "examples," are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to implement, manufacture, and / or use the subject matter.

[0011] The terms "over," "under," "between," and "on" as used herein refer to the relative position of one layer with respect to another layer. Thus, for example, a layer deposited or disposed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer deposited or disposed between layers may be in direct contact with those layers or may have one or more intervening layers. Furthermore, the relative position of one layer with respect to another layer is provided with respect to the operations of film deposition, modification, and removal relative to a starting substrate, without regard to the absolute orientation of the substrate.

[0012] Unless otherwise stated, and as will be apparent from the discussion that follows, discussions throughout the specification using terms such as "processing," "computing," "calculating," "determining," etc. will be understood to refer to the operation and / or processing of a computer or computing system or similar electronic computing device that manipulates and / or transforms data represented as physical, e.g., electronic, quantities in the registers and / or memory of the computing system into other data that are also represented as physical quantities in the computing system's memory, registers, or other such information storage, transmission, or display device.

[0013] Thematic Overview According to one embodiment of a method for manufacturing a semiconductor device, the method may include dividing a substrate into a first region and a second region and forming a customizable oxide-nitride-oxide (ONO) stack in the first region; performing at least one of a first radical oxidation and a first oxide deposition process step in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer overlying the substrate; performing a plurality of silicon nitride deposition process steps in the ALD tool to form a multilayer charge trapping (CT) layer; determining process parameters for a first silicon nitride deposition process step of the plurality of silicon nitride deposition process steps to form a first CT sublayer; modifying at least one of the process parameters; performing a second silicon nitride deposition process step to form a second CT sublayer overlying the first CT sublayer; and performing at least one of a second radical oxidation and a second oxide deposition process step in the ALD tool to form a blocking dielectric layer overlying the multilayer CT layer in the first region.

[0014] In one embodiment, the silicon nitride formed may include silicon oxynitride containing oxygen.

[0015] In one embodiment, the customizable ONO stack formation process steps are in-situ and performed within the same ALD tool.

[0016] In one embodiment, the silicon, oxygen, and nitrogen film compositions of the silicon nitride in the first and second CT sublayers are different, and in one embodiment, the first CT sublayer is oxygen-rich silicon nitride, thereby substantially free of charge traps, and the second CT sublayer is oxygen-poor silicon nitride, thereby substantially densely populated with charge traps.

[0017] According to one embodiment of the method for manufacturing a semiconductor device, the method may further include performing a plurality of third silicon nitride deposition process steps to form a plurality of third CT sublayers disposed between the first and second CT sublayers, wherein process parameters of the plurality of third silicon nitride deposition process steps are adjusted such that the oxygen-rich levels of the plurality of third CT sublayers are between the oxygen-rich levels of the first and second CT sublayers. In one embodiment, the method further includes performing at least one of a third radical oxidation and a third oxide deposition process step in the same ALD tool to form an oxide thin film overlying the first CT sublayer and below the second CT sublayer, the oxide thin film being formed to reduce electronic charge accumulation at the boundary of the second CT sublayer from tunneling into the first CT sublayer.

[0018] In one embodiment, the process parameters of the first and second radical oxidation process steps can include the type of reactant gas including O / H gas, the flow rate of the reactant gas into the ALD tool, the reaction time for each reactant gas, the sequence of the reactant gas entering the ALD tool, and the number of repeats and repeat sequences, and the process parameters are configured to control at least one of the thickness, density, and quality of the oxide formed in the tunnel dielectric layer.

[0019] In one embodiment, the process parameters of the first and second oxide deposition process steps can include type of silicon source precursor gas comprising HCD, type of reactant gas comprising O / H gas, flow rates of the reactant gas and silicon source precursor gas, reaction time for each reactant gas and silicon source precursor gas, and sequence of the reactant gas and silicon source precursor gas entering the ALD tool, wherein the process parameters are configured to control at least one of thickness, density, and quality of the oxide formed in the blocking dielectric layer.

[0020] In one embodiment, process parameters for the first and second silicon nitride deposition process steps can include the type of silicon source precursor gas comprising HCD, the type of reactant gas comprising NH3 / N2O, the flow rates of the reactant gas and silicon source precursor gas, and the reaction time for each reactant gas and silicon source precursor gas, the sequence of the reactant gas and silicon source precursor gas entering the ALD tool, and the number of repetitions and repeat sequences.

[0021] In one embodiment, at least one of the multiple silicon nitride deposition process steps may be plasma enhanced.

[0022] In one embodiment, the first radical oxidation and first oxide deposition process steps can be repeated individually, alternately, or a combination thereof to form a tunnel dielectric layer, and the second radical oxidation and second oxide deposition process steps can be repeated individually, alternately, or a combination thereof to form a blocking dielectric layer, and process parameters of the first and second radical oxidation process steps and the first and second oxide deposition process steps are adjusted during the repetition of the process steps to customize the tunnel dielectric layer and the blocking dielectric layer.

[0023] According to one embodiment of the method for manufacturing a semiconductor device, the method further includes forming a high-voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low-voltage (LV) gate oxide layer in a second region of the substrate, wherein at least one of the HV, I / O, and LV gate oxide layers is formed simultaneously with the customizable O·N·O layer blocking dielectric layer in the first region by at least one of a second radical oxidation and a second oxide deposition process step.

[0024] In one embodiment, the multi-layer CT layer can include at least three CT sublayers, and the process parameters of the multiple silicon nitride deposition process steps are modified so that in the multi-layer CT layer, the upper CT sublayer adjacent to the blocking dielectric layer is the most oxygen-poor, and the lower CT sublayer adjacent to the tunnel dielectric layer is the most oxygen-rich.

[0025] According to an embodiment of a method for manufacturing a memory device, the method may include forming a tunnel oxide layer in a memory area and a logic area of ​​a substrate; forming a customizable charge trapping (CT) layer and a cap layer overlying the tunnel oxide layer, wherein the customizable CT layer includes a plurality of CT sublayers, each CT sublayer being formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in the memory area while removing them in the logic area; and performing at least one radical oxidation process step in the ALD chamber to simultaneously convert the silicon nitride in at least the cap layer to form a blocking layer overlying the customizable CT layer and convert silicon in the substrate to form a first gate oxide layer in the logic layer.

[0026] In one embodiment, the method may also include performing at least one oxide deposition process step in an ALD chamber to simultaneously add thickness to the blocking oxide layer and the first gate oxide layer in the logic area.

[0027] In one embodiment, the process parameters for one or more silicon nitride deposition process steps can include the type of silicon source precursor gas comprising HCD, the type of reactant gas comprising NH3 / N2O, the flow rates of the reactant gas and the silicon source precursor gas, the reaction time for each reactant gas and silicon source precursor gas, and the sequence of the reactant gas and the silicon source precursor gas entering the ALD chamber.

[0028] In one embodiment, the process parameters of one or more silicon nitride deposition process steps can be adjusted to produce CT sublayers having different thicknesses, densities, and at least one of silicon nitride Si, O, and N film compositions in the CT sublayer.

[0029] According to one embodiment of a method for manufacturing a SONOS-based memory device, the method may include forming memory cells in a memory region of a substrate, the memory region including a SONOS transistor and a pass transistor, the method including forming a tunnel oxide layer in the memory region and a logic region of the substrate; forming a customizable charge trapping (CT) layer and a cap layer overlying the tunnel oxide layer, the customizable CT layer including a plurality of CT sublayers, each CT sublayer being formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in the memory region while removing the layers in the logic region; and forming a blocking oxide layer overlying the customizable CT layer and forming a first gate oxide of the pass transistor in the memory region; and forming an HV gate oxide layer for a high-voltage (HV) transistor, an input / output (I / O) gate oxide layer for an I / O transistor, and a LV gate oxide layer for a low-voltage (LV) transistor in the logic region. In one embodiment, at least one of the HV, I / O, and LV gate oxides is at least partially formed by performing at least one radical oxidation process step in an ALD chamber to simultaneously convert silicon nitride in at least the cap layer to form a blocking oxide layer, convert silicon to form a first gate oxide in the memory area, and convert silicon in the substrate to at least partially form at least one of the HV, I / O, and LV gate oxide in the logic area.

[0030] In one embodiment, the method may also include performing at least one oxide deposition process step in an ALD chamber to simultaneously add thicknesses of the blocking oxide layer and the first gate oxide layer in the memory area.

[0031] In one embodiment, the pass transistor and the HV transistor can be of the same type, with the first gate oxide and the HV gate oxide formed simultaneously and having approximately the same thickness.

[0032] In one embodiment, CT sublayers having different film compositions of Si, O, and N of silicon nitride in the CT sublayers are produced, and process parameters of one or more silicon nitride deposition process steps can be adjusted so that the upper CT sublayer is the most oxygen-poor and the lower CT sublayer is the most oxygen-rich in the customizable CT layer.

[0033] In one embodiment, the oxide deposition process step, the radical oxidation process step, and the silicon nitride deposition process step are performed in situ in an ALD chamber, and the process temperature is controlled to less than 650°C.

[0034] In one embodiment, the method may also include forming a high-K metal gate (HKMG) overlying the blocking oxide of the SONOS transistor and the first gate oxide layer of the pass transistor. [Brief explanation of the drawings]

[0035] [Figure 1] FIG. 1 is a block diagram illustrating a cross-sectional view of a SONOS-based non-volatile memory transistor or device. [Figure 2A] FIG. 2A is an exemplary flowchart illustrating an embodiment of a method for fabricating an oxide-nitride-oxide (ONO) stack in a SONOS-based non-volatile memory transistor according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a representative diagram illustrating an example of an atomic layer deposition (ALD) chamber or tool. [Figure 3A] FIG. 3A is a representative diagram showing a cross-sectional view of a tunnel dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 3B] FIG. 3B is a representative diagram showing a cross-sectional view of a tunnel dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 3C] FIG. 3C is a representative diagram showing a cross-sectional view of a tunnel dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 3D] FIG. 2D is a representative diagram showing a cross-sectional view of a tunnel dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 4A] FIG. 4A is a representative diagram showing a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 4B] FIG. 4B is a representative diagram showing a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 4C] FIG. 4C is a representative diagram showing a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 4D] FIG. 4D is a representative diagram showing a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 4E] FIG. E is a representative diagram showing a cross-sectional view of a charge trapping dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 5A] 5A-5D are representative diagrams showing cross-sectional views of the top or blocking dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 5B]FIG. 5B is a representative diagram showing a cross-sectional view of the top or blocking dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 5C] FIG. 5C is a representative diagram showing a cross-sectional view of the top or blocking dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 5D] FIG. 5D is a representative diagram showing a cross-sectional view of the top or blocking dielectric portion of a SONOS-based non-volatile memory transistor during fabrication according to the method of FIG. 2A. [Figure 5E] FIG. 5E is a representative diagram illustrating a cross-sectional view of a memory stack of a floating gate memory transistor including an ONO blocking dielectric stack according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a block diagram illustrating a cross-sectional view of a portion of a SONOS-based non-volatile memory cell or device according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is an exemplary flowchart illustrating an embodiment of the integration of a SONOS-based memory transistor manufacturing method into a MOS transistor process flow, according to an embodiment of the present disclosure. [Figure 8A] FIG. 8A is a representative diagram showing a cross-sectional view of a portion of a SONOS-based memory device according to the method of FIG. [Figure 8B] FIG. 8B is a representative diagram showing a cross-sectional view of a portion of a SONOS-based memory device according to the method of FIG. [Figure 8C] FIG. 8C is a representative diagram showing a cross-sectional view of a portion of a SONOS-based memory device according to the method of FIG. [Figure 8D] FIG. 8D is a representative diagram showing a cross-sectional view of a portion of a SONOS-based memory device according to the method of FIG. [Figure 8E] FIG. 8E is a representative diagram showing a cross-sectional view of a portion of a SONOS-based memory device according to the method of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0036] Description of the Embodiments FIG. 1 is a block diagram illustrating a cross-sectional view of a SONOS-based NVM device. In one embodiment shown in FIG. 1, NVM transistor 100 is a SONOS-type charge-trapping NVM transistor, which stores binary (“0” or “1”) or multi-level analog values ​​(e.g., 0-2) depending on the amount and polarity of the trapped charge it holds. n 1, NVM cell 90 includes a memory gate (MG) stack 150 formed on a substrate 102. NVM transistor 100 further includes source / drain regions 104 formed on, or possibly within, a shallow positive well (SPW (not shown)) on, or possibly within, substrate 102 on either side of MG stack 150. The SPW may be at least partially enclosed within a deep negative well (DNW (not shown)). In one embodiment, source / drain regions 104 are connected by a channel region 116 underlying MG stack 150. NVM transistor 100 includes a tunneling dielectric layer 106, a charge trapping layer 108, and a blocking dielectric layer 110 that form an ONO stack 120. In one embodiment, charge trapping layer 108 can be multi-layered and traps charge injected from substrate 102 by FN tunneling or other mechanisms. The V of NVM transistor 100 T and I D The value may vary, at least in part, depending on the amount and polarity of the trapped charge. In one embodiment, a high-K dielectric layer may form at least a portion of the blocking dielectric layer 110. A polysilicon (poly) or metal gate layer 112 overlies the ONO stack 120, which may function as a control gate (CG) or memory gate. The NVM transistor 100 may also include a spacer 114 to provide electrical isolation from adjacent or other devices.

[0037] In various embodiments, the ONO stack 120 can be formed by a series of oxidation (thermal and / or radical and / or other), deposition (physical, chemical, etc.), etching, and / or cleaning process steps. The process steps can occur in a single process chamber and / or tool or multiple process chambers / tools. In some embodiments, current ONO processes limit the compositional variation achievable in the thin layers of the SONOS stack, which is essential for advanced technology nodes, e.g., 22 nm and below. Current ONO formation processes / tools can also suffer from limitations in film stoichiometry and thickness, e.g., wafer-to-wafer (WTW) thickness and within-wafer (WIW) thickness uniformity. This can adversely affect the quality and productivity of the ONO stack by limiting batch sizes to around 50 wafers and reducing manufacturing plant capacity for the associated product. At advanced technology nodes, the thermal budget of certain ONO processes, such as in-situ steam generation (ISSG) oxidation, dry or wet furnace oxidation, and chemical vapor deposition of oxides and nitrides, can be too high. The high thermal budget for these processes can be significant enough to shift the parameters of the baseline CMOS device, requiring changes in the baseline FET model.

[0038] FIG. 2A is a representative flowchart illustrating an embodiment of a method for fabricating an oxide-nitride-oxide (ONO) stack in a SONOS-based nonvolatile memory transistor, such as the NVM transistor in FIG. 1, according to an embodiment of the present disclosure. Referring to FIGS. 2A and 3A, the process can begin with a series of pre-steps (step 202) including forming several isolation structures or shallow trench isolation (STI) 301 in a wafer or substrate 302. In some embodiments, the pre-steps can also include forming channels, such as channel 116 in FIG. 1 or source / drain 104 in FIG. 1, and / or deep wells and / or wells. Various processes, including pad oxide formation, wet / dry etching or cleaning, applying a tunnel mask, and dopant implantation, can be performed according to conventional practices in the art. It is understood that none, or several, of the above-mentioned or other pre-steps can be performed before the tunnel dielectric layer is formed. Subsequently, a pre-cleaning step is performed on the substrate surface 303 to remove pad oxide (if present) and / or other residual oxides, which can be a wet or dry process. In one embodiment, it can be a wet process using HF, followed by standard cleans (SC1) and (SC2), which is highly selective to the material of the substrate 302.

[0039] 2 and 3B, the formation of an ONO layer, e.g., the ONO stack 120 best shown in FIG. 1, begins with the formation of a tunnel dielectric in step 204. The tunnel dielectric can be any material and can have any thickness suitable to allow charge carriers to tunnel into the overlying charge trapping layer under applied gate bias while maintaining a suitable barrier against leakage when the transistor is not biased. In certain embodiments, the tunnel dielectric can be silicon dioxide, silicon nitride, e.g., an oxynitride, or a combination thereof, and can be deposited and / or grown by a thermal oxidation process in a furnace using ISSG or radical oxidation. As discussed above, forming a very thin (e.g., less than 20 Å) tunnel dielectric layer with a uniform film stoichiometry and WTW / WIW thickness under a thermal budget of less than 650°C using the above-described process is challenging. In one embodiment, which may be considered a preferred embodiment, the multilayer silicon oxide tunnel dielectric layer 306 can be formed in a single in situ atomic layer deposition (ALD) chamber capable of radical oxidation, thermal ALD, or plasma-enhanced ALD (PEALD) using either a batch or single tool. In one embodiment, both radical oxidation and ALD deposition processes can be performed in the same ALD chamber. The sequential, self-limiting surface reaction characteristics of ALD deposition and radical oxidation facilitate atomic-scale control of film thickness and uniformity with relatively low thermal budgets (e.g., below 650°C). Referring to FIG. 2B, an example of an ALD chamber or tool 90 is shown. The ALD chamber 90 can be a batch-type tool in which multiple wafers (substrates) can be processed simultaneously. Precursor gases, such as HCD as a silicon source, can be introduced. Other reactant gases, such as ammonia or nitrous oxide, can be enhanced by a plasma source, such as an inductively coupled plasma (ICP), before entering the chamber through a buffer nozzle with an electrode. Other reactant gases, such as H₂ / O₂, can be introduced by a cross-flow injector.It is understood that the ALD chamber 90, best shown in Figure 2B, is merely one example of an ALD tool capable of radical oxidation, thermal ALD, and PEALD processes and should not be construed as limiting. Depending on manufacturing requirements and other considerations, other ALD tools capable of performing the radical oxidation and ALD deposition disclosed in this patent document may be used.

[0040] 3B, in one embodiment, the tunnel dielectric sublayer 306a is formed by radical oxidation in an ALD chamber. The process includes flowing hydrogen (H) and oxygen (O) reactant gases into the ALD chamber in a ratio of approximately 1:4 to each other, or other configurable ratio, without an external ignition event, e.g., forming a plasma. The H and O react at a temperature ranging from approximately 300° C. to approximately 650° C. and a pressure ranging from approximately 0.5 Torr to approximately 10 Torr to form radicals, e.g., OH radicals, HO radicals, or O diradicals, at the interface of the substrate 302, which ultimately react directly with and consume portions of the exposed surface of the silicon substrate 302. In one embodiment, an exemplary process / task table for performing radical oxidation in an ALD chamber is as follows: [Table 1]

[0041] The thickness, quality and uniformity of the formed tunnel dielectric sublayer 306a can be fine-tuned or tailored by modifying or adjusting the sequence, flow rates, sequence, duration, temperature, gas flow ratios or other process parameters of the process gases depending on the requirements of the device being fabricated.

[0042] Referring to FIG. 3C, the tunnel dielectric sublayer 306b can also be formed using a deposition workflow in the same or a similar ALD chamber. In one embodiment, a chlorosilane, such as hexachlorodisilane SiCl (HCD), can be the precursor or silicon source gas. Hydrogen (H) and oxygen (O) gases are flowed into the ALD chamber at a ratio of approximately 1:4 relative to each other without an external ignition event, such as forming a plasma. The H and O react at a temperature ranging from approximately 300° C. to approximately 400° C. and a pressure ranging from approximately 0.5 Torr to approximately 10 Torr to form radicals, such as OH radicals, HO radicals, or O diradicals, which ultimately react with the HCD to form silicon oxide deposited on the surface of the substrate 302. During the same process, the generated radicals can also react directly with the silicon substrate 302 to form silicon oxide, as in the previously described radical oxidation. In one embodiment, an exemplary process / task table for performing silicon oxide deposition in an ALD chamber is as follows: [Table 2]

[0043] Similar to radical oxidation, the thickness, quality, and uniformity of the formed tunnel dielectric sublayer 306b can be fine-tuned or tailored by modifying the sequence, flow rates, duration, temperature, gas flow ratios, or other process parameters of the process gases depending on the requirements of the device being fabricated. In one embodiment, the tunnel dielectric layers 306a and 306b produced in the radical oxidation process or ADL deposition process are denser and substantially less than 1 cm thick than tunnel dielectrics formed by wet oxidation techniques, even at reduced thicknesses. 3 The uniform thickness of the tunnel dielectric layer 306, especially around the STI corners, can reduce the inhomogeneity of the FN implant at the STI 301 corners in the final SONOS device, and the I D or V T This leads to a lowering of the sigma.

[0044] In embodiments, radical oxidation as described in Table 1 and ALD oxide deposition as described in Table 2 can be repeated individually with or without modification of process parameters, alternately with or without modification of process parameters, in combinations thereof, or in any designed sequence to produce multiple tunnel dielectric sublayers 306a-306d. Each sublayer can be formed by one or more radical oxidation process steps alone (e.g., Table 1, or modifications thereof), one or more ALD oxide deposition steps alone (e.g., Table 2, or modifications thereof), or a combination thereof, until it reaches a predetermined thickness, and each sublayer can be formed to a thickness of 2 Å or less. The final tunnel dielectric layer 306 is a stack of multiple tunnel dielectric sublayers 306a-306d, as best shown in FIG. 3D. By controlling and adjusting process parameters, such as flow rates, reactants, duration, and temperature, during the radical oxidation and ALD deposition process steps, a tunnel dielectric layer 306 can be achieved with a customizable and desired thickness (WTW and WIW), uniformity, oxide-to-silicon substrate interface condition, and film stoichiometry. It is understood that the four-sublayer tunnel dielectric layer 306 shown in FIG. 3D is merely an example for illustrating the proposed ALD oxidation / deposition method and should not be construed as limiting. The tunnel dielectric layer 306 can have one or more sublayers, and each sublayer can have a different thickness, film stoichiometry, density, or other physical and chemical properties by fine-tuning the ALD radical oxidation and deposition process steps. In one embodiment, the tunnel dielectric layer 306 can be formed to a thickness ranging from approximately 5 Å to 30 Å.

[0045] Referring to FIG. 2, in step 204, a multi-layer silicon nitride or silicon oxynitride (Si x O y N z) The charge-trapping layer can be formed in the same ALD chamber. In embodiments, the silicon nitride or silicon oxynitride can have various ratios of silicon (x), oxygen (y), and nitrogen (z) in the formed film. The charge-trapping layer can be composed of a suitable material and have a suitable thickness for storing charge and thus varying the threshold voltage of the subsequently formed SONOS device. Referring to FIG. 4A, the charge-trapping dielectric sublayer 308a is formed in the same or similar in situ ALD chamber as the tunnel dielectric layer 306. In one embodiment, the process includes flowing precursor gases HCD as the silicon source, ammonia (NH) as the nitrogen source, and nitrous oxide (NO) as the oxygen source. In other embodiments, other chlorosilane gases can be used as the silicon source, and other nitrogen or oxygen source gases can be used according to the practice of those skilled in the art. In yet other embodiments, ammonia gas and nitrous oxide gas can be plasma-enhanced before introduction into the ALD chamber for higher silicon nitride deposition rates and better uniformity at low temperatures. In one embodiment, the silicon nitride ALD deposition process is performed at less than 650° C., which is lower than most thermal and chemical vapor deposition processes. In one embodiment, silicon nitride layers up to 2 Å thick can be formed in an ALD chamber. An exemplary process / task table for performing silicon nitride deposition in an ALD chamber is as follows: [Table 3]

[0046] Similar to the silicon oxide ALD process described above, the thickness, uniformity, and ratio of oxygen, nitrogen, and / or silicon in the formed silicon nitride can be tailored to produce a customizable charge-trapping dielectric sublayer 308a. In one embodiment, the silicon nitride ALD process may have little effect on the already formed tunnel dielectric layer 306. Referring to FIG. 4B , another charge-trapping dielectric sublayer 308b can be formed on the charge-trapping dielectric sublayer 308a. In one embodiment, the charge-trapping dielectric sublayer 308b can be formed in the same ALD chamber using the process parameters listed in Table 3 or modified process parameters. For example, the flow rate and / or flow time of NO gas can be increased to produce an oxygen-rich nitride layer, or the HCD gas and ammonia gas can be adjusted, or increased or decreased, to produce a silicon-rich nitride layer and a nitrogen-rich nitride layer, respectively. Referring to FIG. 4C , yet another charge-trapping dielectric sublayer 308c can be formed on the charge-trapping dielectric sublayer 308b using an ALD deposition process similar to that described in Table 3, with or without modifying the process parameters. In one embodiment, the charge-trapping dielectric sublayers 308a-308c can collectively form the charge-trapping dielectric layer 308 for the finished SONOS device. It is understood that the three-layer charge-trapping dielectric layer 308 shown in FIG. 4C is merely an example for illustrating the proposed ALD deposition of silicon nitride and should not be construed as limiting. The charge-trapping dielectric layer 308 can have one or more sublayers, and each sublayer can have a different thickness, film composition of Si, O, and N in the silicon nitride, or other physical and chemical properties by fine-tuning the ALD deposition process. In one embodiment, the charge trapping dielectric layer 308 can be a multi-layer silicon nitride with an oxygen richness gradient rising from the top, where the upper sublayer 308c is the most oxygen-poor silicon nitride sublayer, while the lower sublayer 308a is the most oxygen-rich.

[0047] As used herein, the terms "oxygen-rich" and "silicon-rich" refer to stoichiometric silicon nitride, commonly used in the art, having a composition of (Si3N4) and a refractive index of approximately 2.0. Thus, "oxygen-rich" silicon nitride involves a shift from stoichiometric silicon nitride (sometimes referred to as silicon nitride or oxynitride (oxygen-containing silicon nitride)) toward higher mass percent silicon and oxygen (i.e., less nitrogen). Oxygen-rich silicon nitride or silicon oxynitride films thus resemble silicon dioxide, with a reduced RI toward the 1.45 RI of pure silicon dioxide. Similarly, films described herein as "silicon-rich" involve a shift from stoichiometric silicon nitride toward a higher mass percent silicon and have less oxygen than "oxygen-rich" films. Thus, silicon-rich silicon nitride films resemble silicon, with a reduced RI toward the 3.5 RI of pure silicon. Throughout this document, "silicon nitride" and "silicon oxynitride" are used interchangeably, and the films formed may or may not contain oxygen.

[0048] In one embodiment, it may be desirable to produce a charge-trapping dielectric film in which the majority of charge traps are distributed in the upper portion of the film, which can minimize charge leakage through the underlying tunnel dielectric layer. For example, using the charge-trapping dielectric layer 308 in FIG. 4C , the process parameters during the ALD deposition of the charge-trapping dielectric sublayer 308a can be configured to produce an oxygen-rich, nitrogen-poor silicon nitride film. By adjusting the process parameters and using the same ALD chamber, the charge-trapping dielectric sublayer 308c can be formed as an oxygen-poor, nitrogen-rich silicon nitride film that contains the majority of charge traps throughout the multi-layer charge-trapping dielectric layer 308.

[0049] In some embodiments, a silicon oxide thin film can be formed within the charge-trapping nitride layer, sandwiched between two nitride layers. Referring to FIG. 4D , a dielectric thin film 330 can be formed on the lower charge-trapping dielectric layer 308′. The lower charge-trapping dielectric 308′ is one or more sublayers of silicon nitride formed similarly to the charge-trapping dielectric layer 308. The dielectric thin film 330 can be silicon oxide or highly oxygen-rich silicon nitride and can be formed using ALD radical oxidation or ALD oxide deposition, similar to the formation of the tunnel dielectric sublayers 306a-306d described above. The silicon oxide can be deposited directly on the lower charge-trapping dielectric layer 308′, or radicals can convert a portion of the silicon nitride in the lower charge-trapping dielectric layer 308′ to silicon oxide or highly oxygen-rich nitride. In embodiments, the dielectric thin film can be a single layer or have multiple sublayers, and each sublayer is formed in the same ALD chamber using the ALD radical oxidation or oxide deposition process steps described above.

[0050] Referring to FIG. 4E, an upper charge-trapping dielectric layer 332 is subsequently formed on the dielectric thin film 330, resulting in a finished charge-trapping dielectric layer 350 of nitride (332)-oxide (330)-nitride (308′) (lower) (N·O·N) stack 350 with a thickness ranging from approximately 50 Å to 150 Å. In one embodiment, like the lower charge-trapping dielectric layer 308′, the upper charge-trapping dielectric layer 332 includes one or more sublayers (not shown) of silicon nitride formed similarly to the charge-trapping dielectric sublayers 308a-308c. The upper charge-trapping dielectric layer 332 is also customizable, and each silicon nitride sublayer therein can have a different thickness, Si:O:N ratio in the formed silicon nitride, or other physical and chemical properties by fine-tuning the ALD deposition process. In one embodiment, the dielectric thin film 330 essentially reduces the likelihood of electron charge accumulating at the boundary of the upper charge-trapping layer 332 from tunneling into the lower charge-trapping layer 308′ during programming, resulting in lower leakage current than conventional memory devices. In one preferred embodiment, the nitride sublayer in the upper charge-trapping dielectric layer 332 can be customized to be oxygen-poor to contain the majority of the charge traps, while the nitride sublayer in the lower charge-trapping dielectric layer 308′ can be customized to be oxygen-rich.

[0051] Referring to FIG. 2, in step 208, a blocking dielectric layer 310 is formed on the charge-trapping dielectric layer 308 or the non-charge-trapping dielectric layer 350. The process begins with forming a blocking dielectric sublayer 310a on the charge-trapping dielectric layer 308 or 350. In one embodiment, the blocking dielectric sublayer 310a is silicon oxide and is formed by radical oxidation as previously described in Table 1, or ALD oxide deposition as described in Table 2, or modifications, combinations, or variations thereof. The silicon oxide is deposited on the charge-trapping dielectric layer 308 or 350, or radicals can convert a portion of the silicon oxynitride in the charge-trapping dielectric layer 308 or 350 to silicon oxide. Referring to FIG. 5B, other blocking dielectric sublayers 310b-310c can subsequently be formed. In one embodiment, blocking dielectric sublayers 310b-310c are formed by similar radical oxidation or ALD oxide deposition to silicon oxide films with customizable thickness, uniformity, and quality by modifying the process performed in the ALD chamber. As a result, blocking dielectric layer 332 can be a single or multiple silicon oxide layers with a total thickness ranging approximately from 10 Å to 100 Å. Referring to FIG. 5C, an ONO stack layer 320 is then formed over at least a portion of substrate 302, all in the same in situ ALD tool. Referring to FIG. 5D, in one embodiment, ONO stack layer 320 can be patterned to form one or more ONO stacks 320′ for a SONOS-based transistor, similar to ONO stack 120 of NVM transistor 100 of FIG. 1. A mask can be formed on or over ONO stack layer 320, and ONO stack layer 320 is etched to form one or more ONO stacks 320′ over substrate 320. The manufacturing method can then proceed with the remaining processes in stage 210. Process steps such as source / drain formation, spacer formation, memory gate formation, etc. are performed according to the practices of those skilled in the art.It is understood that the above-described process steps may be performed before, during, or after the formation of ONO stack layer 320 (in steps 204-208) without departing from the principles of the present disclosure.

[0052] 5E , instead of being the ONO stack of a SONOS-based transistor, and instead of being formed directly on the substrate 302, the ONO stack layer 320 can be formed as part of the memory stack layer 540 of a floating gate transistor 550. In one embodiment, the ONO stack layer 320, which collectively functions as a blocking dielectric layer for the floating gate transistor 550, is formed on the tunnel oxide layer 502 and the floating gate layer 504. The tunnel oxide layer 502, which is primarily silicon oxide, and the floating gate layer 504, which can be polycrystalline silicon, can be formed in the same ALD chamber as the ONO stack layer 320, or can be formed using other techniques practiced by those skilled in the art.

[0053] Referring to FIG. 6, a portion of a SONOS-based non-volatile memory (NVM) device 600 formed on a single substrate 102 is shown. In one embodiment, the substrate 102 is divided into a memory region where memory cells 620 are disposed and a logic region where HV MOS 604, I / O MOS 606, and LV MOS 608 are disposed. In one embodiment, only a single device of each type (i.e., memory cell 620, HV MOS 604, I / O MOS 606, and LV MOS 608) is shown for illustrative purposes only. Multiple devices of each type, as well as other semiconductor devices, may be disposed within the SONOS-based NVM device 600 and may be formed simultaneously or sequentially. As best shown in FIG. 6, the NVM transistor 100 may have a polysilicon (poly) or high-K metal gate (HKMG) layer 634 overlying the ONO stack 320′, which may function as a control gate (CG) or memory gate (MG) for the memory cell 620.

[0054] As best shown in FIG. 6 , in a two-transistor (2T) configuration, memory cell 620 further includes a pass or select transistor 602 located adjacent to SONOS-based NVM transistor 100 (also referred to as the memory transistor). Pass transistor 602 is, for example, a conventional MOSFET that shares a common substrate connection or internal node with NVM transistor 100. In one embodiment, pass transistor 602 includes a high-K metal gate or polysilicon select gate (collectively “SG”) 632 located overlying an oxide or high-K dielectric gate dielectric layer 612. SG 632 is appropriately biased to open or close the channel underlying pass transistor 602. In other embodiments, memory cell 620 may employ a one-transistor (1T) configuration and include only NVM transistor 100.

[0055] 6, in the logic region, the HV MOS, I / O MOS, and LV MOS transistors 604, 606, 608 are field effect transistors (FETs) with a logic gate 632, which is either an HKMG gate or a polysilicon gate, formed overlying an HV gate oxide 614, an I / O gate oxide 616, and an LV gate oxide 618, respectively. In one embodiment, the HV gate oxide 614 is the thickest, followed by the I / O gate oxide 616, and then the LV gate oxide 618. In one embodiment, the pass transistor 602 in the memory region can have a similar or the same structure and dimensions as one of the HV MOS, I / O MOS, and LV MOS transistors 604, 606, 608.

[0056] FIG. 7 is a process flowchart illustrating the major fabrication steps for integrating SONOS or NVM transistors (in the memory region) into a baseline complementary metal-oxide semiconductor (CMOS) process flow (in the logic region) according to one embodiment of the present disclosure. Referring to FIG. 7, the process begins with several prior steps in step 702, including the formation of several isolation structures or shallow trench isolation (STI), pad oxide formation, source / drain formation, well formation, substrate pre-cleaning, etc. Pad oxide 870 may be formed on the surface of substrate 102 in both the memory region and the logic region. In one embodiment, pad oxide 860 may be silicon dioxide (SiO ) having a thickness of about 10 nanometers (nm) to about 20 nm and may be formed in an ADL chamber using a radical oxidation or oxide deposition process, as previously described, or other oxidation or deposition processes known in the art. It is understood that pad oxide 870 may not be necessary or formed in some embodiments. Dopants are implanted into the substrate 102 through the pad oxide 870 (if present) to form wells (deep or shallow), source / drains, or channels for one or more NVM transistors 100 and pass transistors 602 in the memory area, and MOS transistors 604, 606, 608 in the logic area. It is understood that one or more of the previous steps may occur later in the fabrication process without departing from the principles of the present disclosure.

[0057] 7 and 8A, the surface of the substrate 102 in the memory region is cleaned or pre-cleaned, and several dielectric layers are formed in steps 704 and 706. Subsequently, in step 706, a mask is formed on or overlying the dielectric layers, and the dielectric layers are etched to form the NV gate stacks in the memory region. The pre-clean can be a wet or dry process to remove pad oxide 870 on the substrate 102 (at least in the memory region).

[0058] 7 and 8A, in step 704, the dielectric or NV gate stack layer process may begin with the formation of tunnel dielectric layer 306 in the memory area and extend onto the logic area where MOS transistors 604, 606, 608 are to be formed. In one embodiment, tunnel dielectric layer 306 may be any material and have a thickness suitable to allow charge carriers to tunnel into the overlying charge trapping layer under application of a gate bias, while maintaining a suitable barrier against leakage when multilevel NVM transistor 926 is not biased. As previously described in at least FIGS. 2 and 3A-3D and their corresponding descriptions, in a preferred embodiment, tunnel dielectric layer 306 may include one or more sublayers of silicon oxide formed by a radical oxidation or ALD oxide deposition process step in an ALD chamber, such as ALD chamber 90 in FIG. 2B. By controlling and modifying the process parameters in the radical oxidation process and the ALD deposition process, such as flow rates, reactants, duration, temperature, etc., a tunnel dielectric layer 306 with customizable and desired thickness (WTW and WIW), uniformity, interface condition between the oxide and the silicon substrate, and film stoichiometry can be achieved.

[0059] 8A, in step 704, a charge-trapping layer 308 or 350 is formed on or overlying the tunnel dielectric 306. In one embodiment, the charge-trapping layer 308 or 350 can be a multi-layer silicon nitride (one or more sub-layers) formed by ALD deposition process steps, as previously described in FIGS. 4A-4E and their respective descriptions. In one embodiment, as best shown in FIG. 4E, the charge-trapping layer can be a multi-layer charge-trapping layer 308 having at least one sub-layer (e.g., 308a-308c, best shown in FIG. 4C), where each sub-layer can have a different thickness, Si, O, N film ratio, or physical and chemical properties by fine-tuning the ALD deposition process steps.

[0060] In another embodiment, the charge-trapping dielectric layer 350 is an N·O·N layer comprising multiple layers, including at least a lower charge-trapping layer 308′ physically close to the tunneling dielectric layer 306, and an upper charge-trapping layer 332 having one or more nitride sublayers and being oxygen-poor relative to the oxygen-rich lower charge-trapping layer 308′ having one or more sublayers, and comprising the majority of the charge traps distributed within the multi-layer charge-trapping layer 350. As best shown in FIG. 4E , there may be a thin oxide film formed between the upper charge-trapping dielectric layer 332 and the lower charge-trapping dielectric layer 308′, which essentially reduces the likelihood of electron charge accumulating at the boundary of the upper charge-trapping layer 332 from tunneling into the lower charge-trapping layer 308′ during programming, resulting in lower leakage current than conventional memory devices. In one embodiment, all sublayers of the charge-trapping dielectric layer 308 or 350 may be formed in situ in the same ALD chamber by radical oxidation, oxide deposition, or nitride deposition process steps.

[0061] 7 and 8A, in step 706, a cap layer 802 is formed on or overlying the charge trapping layer 308 or 350. In some embodiments as shown, the cap layer 802 is a multi-layer cap layer including at least a lower or first cap layer 802a overlying the charge trapping layer 308 or 350 and a second cap layer 802b overlying the first cap layer 802a.

[0062] In one embodiment, the first cap layer 802a can comprise a high-temperature oxide (HTO), e.g., silicon oxide (SiO), having a thickness of 2.0 nm to 4.0 nm deposited using a low-pressure chemical vapor deposition (LPCVD) thermal oxidation process. In one embodiment, the second cap layer 802b can comprise a silicon nitride, silicon-rich silicon nitride, or silicon-rich silicon oxynitride layer having a thickness of 2.0 nm to 4.0 nm formed by a CVD process using N2O / NH3 and DCS / NH3 gas mixtures. In other embodiments, the cap layer 802 can also be formed using radical oxidation or oxide or nitride deposition process steps in an ALD chamber, as described in the preceding paragraphs, e.g., Tables 1-3 and their respective descriptions.

[0063] 7 and 8A, in step 706, a sacrificial oxide layer 806 is formed on or overlying the cap layer 802. In one embodiment, the sacrificial oxide layer 806 may comprise a high-temperature oxide (HTO) layer grown by a thermal oxidation process or radical oxidation and having a thickness of 2.0 nm to 4.0 nm. In other embodiments, the sacrificial oxide layer 806 may be formed using a radical oxidation or oxide deposition process step in an ALD chamber, as previously described.

[0064] 7 and 8A, a patterned mask layer 850 is then formed on or overlying the sacrificial oxide layer 806, and, with reference to FIG. 8B, the sacrificial oxide layer 806, the cap layer 802, and the charge trapping layer 308 or 350, and the tunnel dielectric layer 306 are etched or patterned to form an NV gate stack 860. In one embodiment, the NV gate stack 860 may be disposed substantially overlying the channel of the NVM transistor 100 in the memory region. The etching or patterning process may further remove various dielectric layers of the NV gate stack 860 from the logic region (step 706). The patterned mask layer 850 may include a photoresist layer patterned using standard lithography techniques, and the NV gate stack 860 layer in the logic region may be etched or removed using a dry etching process that includes one or more additional steps that stop on the surface of the substrate 102 or on pad oxide 870 (if present) that is not removed. In one embodiment, a well (not shown) may be formed in the logic region. It will be understood that FIG. 8B is a representative view and that one or more NV gate stacks 860 may be formed in the memory region or other regions on the substrate 102 in the same patterning process step.

[0065] 7 and 8C, in a highly selective cleaning process (stage 708), the sacrificial oxide layer 806 and the top or substantially all of the second cap layer 802b in the multi-layer cap layer 802 are removed from the NV gate stack 860. This cleaning process also removes any oxide, for example, oxide in the tunnel dielectric layer 306 and / or pad oxide 870 remaining in the memory or logic regions above the NV gate stack 860, to prepare the substrate 102 for oxide formation.

[0066] 7 and 8D, in step 710, blocking dielectric layer 310 of NVM transistor 100 in the memory region, gate oxide 612 of the pass transistor (if present for a 2T configuration), and LV gate oxide layer 618, I / O gate oxide layer 616, and HV gate oxide layer 614 are formed. In one embodiment, an oxidation process is performed to oxidize remaining portions of second cap layer 802b and / or first cap layer 802a of multi-layer cap layer 802, and possibly a portion of charge trapping dielectric layer 308 or 350, to form blocking dielectric layer 310 overlying charge trapping dielectric layer 308 or 350. In one embodiment, the oxidation process is adapted to oxidize or consume remaining portions of first cap layer 802a, or second cap layer 802b, or possibly a portion of charge trapping dielectric layer 308 or 350, in the memory region to form blocking dielectric layer 310 and gate oxide layer 612 of pass transistor 602 (if present), while simultaneously oxidizing at least portions of substrate 102 where I / O MOS 606, LV MOS 608, or HV MOS 604 will be disposed to form a gate oxide layer in the logic region. In one embodiment, the oxidation process can include in situ radical oxidation performed in an ALD chamber, such as ALD chamber 90. The in situ radical oxidation process can be similar to the ALD radical oxidation process steps described in Table 1, FIGS. 5A-5C, and their corresponding descriptions, in which one or more silicon oxide sublayers (e.g., 310a-310c, best shown in FIG. 5b) are formed in NVM transistor 100 in the memory region. In one embodiment, the silicon oxide in the blocking dielectric layer 310 is formed by radicals reacting with or eventually converting to nitride or oxynitride on top of the cap layer 802 or possibly the charge trapping dielectric layer 308 or 350.In one embodiment, radicals generated during the in situ ALD radical oxidation process step, such as OH radicals, HO radicals, or O diradicals, can simultaneously react with and consume the silicon substrate 102 to form one or more sublayers in the gate oxide 612 of the pass transistor in the memory area and in the gate oxide layers 612, 614, and 616 in the logic area. The process parameters (e.g., Table 1) of the in situ ALD radical oxidation process step can be modified to produce oxide sublayers of various thicknesses, qualities, uniformities, stoichiometries, or other chemical and physical properties in both the memory and logic areas. The radical oxidation process steps can also be repeated, alternating, and modified to achieve ideal thicknesses T1 for the blocking dielectric layer 310, T2 for the gate oxide layer 612 of the pass transistor, and T3, T4, and T5 for the gate oxide layers 614, 616, and 618 of the HV MOS 604, I / O MOS 606, and LV MOS 608, respectively. In one embodiment, T1 can be in the approximate range of 30-50 Å, T2 can be 50-150 Å, T3 can be 50-150 Å, T4 can be 50-150 Å, and T5 can be 10-30 Å.

[0067] Alternatively or additionally, in situ ALD oxide deposition (e.g., Table 2 or modifications thereof) can be performed in the same ALD chamber to produce one or more oxide sublayers in at least one of the blocking dielectric layer 310 and the gate oxide 612, 614, 616, 618. As previously described in Table 2, FIGS. 5A-5C, and their respective descriptions, radicals generated in the ALD chamber can react with a silicon source gas, e.g., HCD, or an oxynitride / nitride or silicon substrate to form one or more silicon oxide sublayers. In embodiments, in situ ALD oxide deposition process steps and radical oxidation process steps can be performed in the same ALD chamber repeatedly, modified, alternating, and in combination until predetermined thicknesses T1-T5 of the respective dielectric / oxide layers 310, 612, 614, 616, 618 are achieved. In alternative embodiments, in situ ALD oxide deposition process steps or radical oxidation process steps may not be applied to all regions. A mask (not shown) can be applied to protect one or more regions from having the gate oxide layer therein affected by subsequent radical oxidation or ALD oxide deposition process steps. In one embodiment, gate oxide layer 618 of LV MOS 608 in the logic area can be protected by a mask (not shown) to prevent further oxide from adding thickness in subsequent in-situ ALD process steps (radical oxidation, deposition, or both) after thickness T5 is achieved. In another example, gate oxide layer 612 of pass transistor 602 and gate oxide layer 614 of HV MOS 604 can be roughly identical and formed simultaneously or sequentially in the same process step.A primary objective and advantage of fabricating the blocking dielectric layer 310 of the NVM transistor and one or more gate oxides of the MOS transistors 602, 604, 606, 608 in in situ ALD process steps (both radical oxidation and oxide deposition) in the same or similar ALD chamber / tool ​​is that the oxide sublayers and layers are formed with a relatively low thermal budget (less than 650°C) and therefore may not adversely affect the CMOS process flow in the logic area. Another objective and advantage is that both the N·O·N stack 320 of the NVM transistor 100 and the gate oxide layers 612, 614, 616, 618 are each highly customizable by varying the configuration of the in situ process steps in the ALD chamber or tool. In one embodiment, the ONO layer of the SONOS transistor and the gate oxide layers 612, 614, 616, 618 of all FETs are all formed in situ in the same ALD chamber or tool.

[0068] In an alternative embodiment, at least a portion of the gate oxide layers 612, 614, 616, 618 may be formed using RTO, furnace oxidation, radical oxidation, CVD, in-situ steam generation (ISSG), or a combination thereof, and the oxidation process steps may be performed in a separate process tool.

[0069] In an embodiment, the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 may be formed simultaneously or individually. Subsequently, as best shown in Figure 8E, in step 710, the LV gate oxide layer 618, the I / O gate oxide layer 616, and the HV gate oxide layer 614 are patterned. Although only one transistor of each type (SONOS NVM, pass, HV MOS, I / O MOS, LV MOS transistor) is shown, it will be understood that multiple transistors of each type (not shown in Figure 8D) may be fabricated simultaneously or sequentially using the methods and process steps described above.

[0070] Finally, a standard or baseline CMOS process flow follows, substantially completing front-end device fabrication (stage 712). The process flow may include forming HKMG, spacers, channels, source / drain regions, etc. for each type of transistor. In one embodiment, the completed NVM transistor 100 and HV, I / O, or LV MOS transistors 604, 606, 608 may be configured to form an embodiment of NVM cell 620. In an alternative embodiment, pass transistor 602 may have a different structure, e.g., gate oxide thickness, than HV, I / O, or LV MOS transistors 604, 606, 608. In another alternative embodiment, memory cell 620 may contain only NVM transistor 100 in a one-transistor configuration.

[0071] Thus, embodiments of a SONOS-based nonvolatile memory including a customizable O·N·O stack and methods of fabrication and integration into a baseline CMOS process flow are presented. While the present disclosure has been described with reference to certain exemplary embodiments, it will be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0072] The Abstract of the Disclosure is provided in accordance with 37 CFR §1.72(b), requiring an abstract that will enable the reader to quickly ascertain the nature of one or more embodiments of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the foregoing Detailed Description, various features may be grouped together in a single embodiment to streamline the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Accordingly, the following claims are incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

[0073] A reference in the description to an embodiment or embodiments means that the particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the circuit or method. The appearances of the phrase "an embodiment" in various places in the specification do not necessarily all refer to the same embodiment.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: Dividing the substrate into a first region and a second region; forming a customizable oxide-nitride-oxide (ONO) stack in the first region; and said forming comprises: performing at least one of a first radical oxidation and a first oxide deposition process step in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer overlying the substrate; performing multiple silicon nitride deposition process steps in the ALD tool to form a multi-layer charge trapping (CT) layer; wherein the plurality of silicon nitride deposition process steps comprises: determining process parameters for a first silicon nitride deposition process step of the plurality of silicon nitride deposition process steps to form a first CT sublayer; modifying at least one of the process parameters; performing a second silicon nitride deposition process step to form a second CT sublayer overlying the first CT sublayer; and performing at least one of a second radical oxidation and a second oxide deposition process step in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer in the first region; Including, The method, wherein the multi-layer CT layer includes at least three CT sublayers, and process parameters of multiple silicon nitride deposition process steps are modified so that in the multi-layer CT layer, an upper CT sublayer adjacent to the blocking dielectric layer is the most oxygen-poor, and a lower CT sublayer adjacent to the tunnel dielectric layer is the most oxygen-rich.

2. The method of claim 1 , wherein the silicon nitride comprises silicon oxynitride containing oxygen.

3. The method of claim 1 , wherein the customizable ONO stack formation process steps are in-situ and performed within the same ADL tool.

4. The method of claim 1 , wherein the first and second CT sub-layers have different silicon, oxygen, and nitrogen silicon nitride film compositions.

5. 2. The method of claim 1, wherein the first CT sublayer is oxygen-rich silicon nitride and therefore substantially free of charge traps, and the second CT sublayer is oxygen-poor silicon nitride and therefore substantially densely populated with charge traps.

6. 6. The method of claim 5, further comprising performing a plurality of third silicon nitride deposition process steps to form a plurality of third CT sublayers disposed between the first CT sublayer and the second CT sublayer, wherein process parameters of the plurality of third silicon nitride deposition process steps are adjusted such that the oxygen-rich levels of the plurality of third CT sublayers are between the oxygen-rich levels of the first CT sublayer and the second CT sublayer.

7. 6. The method of claim 5, further comprising performing at least one of a third radical oxidation and a third oxide deposition process step in the ALD tool to form a thin oxide film overlying the first CT sublayer and below the second CT sublayer, the thin oxide film being formed to reduce electron charge accumulation at the boundary of the second CT sublayer from tunneling into the first CT sublayer.

8. process parameters of the first and second radical oxidation process steps: O 2 / H 2 the type of reactant gas containing the gas; the flow rate of reactant gases into the ALD tool; Reaction time for each reactant gas, The sequence of reactant gases entering the ALD tool; and Repetitions and number of repeat sequences 10. The method of claim 1, wherein the process parameters are configured to control at least one of a thickness, density, and quality of an oxide formed in the tunnel dielectric layer.

9. wherein the process parameters of the first and second oxide deposition process steps are: a type of silicon source precursor gas including hexachlorodisilane (HCD); O 2 / H 2 the type of reactant gas containing the gas; flow rates of reactant gases and silicon source precursor gases; the reaction time for each reactant gas and silicon source precursor gas, and Sequence of reactant gases and silicon source precursor gases entering the ALD tool 10. The method of claim 1, wherein the process parameters are configured to control at least one of a thickness, density, and quality of an oxide formed in the blocking dielectric layer.

10. wherein the process parameters of the first and second silicon nitride deposition process steps are: a type of silicon source precursor gas including hexachlorodisilane (HCD); NH 3 / N 2 The type of reaction gas containing O gas, flow rates of the reactant gas and the silicon source precursor gas; and reaction time for each reactant gas and silicon source precursor gas; a sequence of reactant gases and silicon source precursor gases entering the ALD tool; and Repetitions and number of repeat sequences The method of claim 1 , comprising:

11. The method of claim 1 , wherein at least one of the plurality of silicon nitride deposition process steps is plasma enhanced.

12. the first radical oxidation and the first oxide deposition process steps are repeated individually, alternately, or in combination to form a tunnel dielectric layer; and the second radical oxidation and the second oxide deposition process steps are repeated individually, alternately, or in combination to form a blocking dielectric layer; 10. The method of claim 1, wherein process parameters of the first and second radical oxidation process steps and the first and second oxide deposition process steps are adjusted during repetition of process steps to customize the tunnel dielectric layer and the blocking dielectric layer.

13. 10. The method of claim 1, further comprising forming a high-voltage (HV) gate oxide layer, an input / output (I / O) gate oxide layer, and a low-voltage (LV) gate oxide layer in a second region of the substrate, wherein at least one of the HV, I / O, and LV gate oxide layers is formed simultaneously with a customizable O.N.O layer blocking dielectric layer in the first region by at least one of the second radical oxidation and the second oxide deposition process steps.

14. 1. A method for manufacturing a memory device, comprising: forming a tunnel oxide layer in a memory region and a logic region of a substrate; forming a customizable charge trapping (CT) layer and a capping layer overlying the tunnel oxide layer, the customizable CT layer including a plurality of CT sub-layers, each CT sub-layer being formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in a memory area, while removing the tunnel oxide layer, the customizable CT layer, and the cap layer in a logic area; and performing at least one radical oxidation process step in the ALD chamber to simultaneously convert silicon nitride in at least the cap layer to form a blocking oxide layer overlying the customizable CT layer and convert silicon in the substrate to form a first gate oxide layer in the logic region; Including, process parameters of the one or more silicon nitride deposition process steps: a type of silicon source precursor gas including hexachlorodisilane (HCD); The type of reaction gas containing NH 3 / N 2 O gas, flow rates of reactant gases and silicon source precursor gases; the reaction time for each reactant gas and silicon source precursor gas, and Sequence of reactant gases and silicon source precursor gases entering the ALD chamber The method comprising:

15. 15. The method of claim 14, further comprising performing at least one oxide deposition process step in the ALD chamber to simultaneously add a thickness of a blocking oxide layer and a first gate oxide layer in the logic area.

16. 15. The method of claim 14, wherein process parameters of the one or more silicon nitride deposition process steps are adjusted to produce CT sub-layers having different thicknesses, densities, and / or film compositions of silicon nitride Si, O, and N in the CT sub-layers.

17. 1. A method of manufacturing a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based memory device, comprising forming memory cells in a memory region of a substrate, the memory cells including a SONOS transistor and a pass transistor, the forming comprising: forming a tunnel oxide layer in a memory region and a logic region of a substrate; forming a customizable charge trapping (CT) layer and a capping layer overlying the tunnel oxide layer, the customizable CT layer comprising at least three CT sub-layers, each CT sub-layer being formed by one or more silicon nitride deposition process steps performed in an atomic layer deposition (ALD) chamber, wherein process parameters of the one or more silicon nitride deposition process steps are modified such that an upper CT sub-layer is the most oxygen-poor and a lower CT sub-layer adjacent to the tunnel dielectric layer is the most oxygen-rich of the at least three CT sub-layers; patterning the tunnel oxide layer, the customizable CT layer, and the cap layer to form a memory stack in a memory area, while removing the tunnel oxide layer, the customizable CT layer, and the cap layer in a logic area; and forming a blocking oxide layer overlying the customizable CT layer and forming a first gate oxide of a pass transistor in a memory area; and forming a high-voltage (HV) gate oxide layer of an input / output (I / O) transistor, an I / O gate oxide layer of an I / O transistor, and a low-voltage (LV) gate oxide layer of an LV transistor in a logic area, wherein at least one of the HV, I / O, and LV gate oxides is at least partially formed by performing at least one radical oxidation process step in the ALD chamber and simultaneously converting silicon nitride in at least the cap layer to form a blocking oxide layer, converting silicon to form a first gate oxide in a memory area, and converting silicon in the substrate to at least partially form at least one of the HV, I / O, and LV gate oxides in the logic area; The method comprising:

18. 20. The method of claim 17, further comprising performing at least one oxide deposition process step in the ALD chamber to simultaneously add a thickness of a blocking oxide layer and a first gate oxide layer in the memory area.

19. 18. The method of claim 17, wherein the pass transistor and the HV transistor are of the same type, and the first gate oxide and the HV gate oxide are formed simultaneously and have approximately the same thickness.

20. 18. The method of claim 17, wherein CT sub-layers having different film compositions of Si, O, and N of silicon nitride in the CT sub-layers are produced, and process parameters of one or more silicon nitride deposition process steps are adjusted such that an upper CT sub-layer is the most oxygen-poor and a lower CT sub-layer is the most oxygen-rich in the customizable CT layer.

21. 20. The method of claim 18, wherein the oxide deposition process step, the radical oxidation process step, and the silicon nitride deposition process step are performed in situ in the ALD chamber, and the process temperature is controlled to be less than 650°C.

22. 20. The method of claim 17, further comprising forming a high-K metal gate (HKMG) overlying a blocking oxide of the SONOS transistor and a first gate oxide layer of the pass transistor.

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