Connecting a chiplet to an interposer die and package interface using spacer interconnects coupled to a portion of the chiplet

Abstract

The semiconductor package assembly includes a package interface. An interposer die has a first surface and a second surface opposite the first surface, the first surface of the interposer being a die positioned on the package interface. The interposer die includes a plurality of conductive connections between the first surface and the second surface. The chiplet includes a connection region having conductive paths, a first portion of the connection region coupled to the conductive connections of the interposer die, and a second portion of the connection region cantilevered from the interposer die.

Description

[Background technology]

[0001] The number of interconnected components in semiconductor assemblies is increasing. To connect different components, some semiconductor assemblies include conductive traces that are parallel to the substrate to which the components are coupled. In some variations, such conductive traces are above the surface of the substrate itself. While this elevation of the conductive traces above the substrate simplifies manufacturing, the use of such elevated conductive traces interrupts the power supply to portions of the system-on-chip or die that are coupled to the elevated conductive traces. [Brief explanation of the drawings]

[0002] [Figure 1] 1 is a cross-sectional view of a semiconductor assembly including a portion of an interposer die and a chiplet coupled to a spacer interconnect, according to some embodiments. [Figure 2] 1 is a cross-sectional view of another semiconductor assembly including chiplets coupled to an interposer die and spacer interconnects according to some embodiments. [Figure 3] 1 is a cross-sectional comparison of configurations for coupling chiplets to an interposer die, according to some embodiments. [Figure 4] 1 is a cross-sectional view of an exemplary integrated circuit device including a portion of an interposer die and a chiplet coupled to a spacer interconnect according to some embodiments. [Figure 5] 1 is an exemplary computing device according to some embodiments. [Figure 6] 1 is a flowchart illustrating an exemplary method for manufacturing an integrated circuit device including a portion of an interposer die and a chiplet coupled to a spacer interconnect, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] As semiconductor technology continues to advance, stacked semiconductor devices (e.g., three dimensional integrated circuits (3DICs)) have emerged as an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, and processor circuits are fabricated on different semiconductor dies. To further reduce the form factor of a semiconductor device, two or more semiconductor dies can be placed or stacked on top of each other. To provide a specific type of function, a stacked semiconductor device includes one or more function-specific chiplets. For example, a stacked semiconductor device includes input / output chiplets for providing input signals to and output signals from the stacked semiconductor device.

[0004] Various types of functional chiplets receive signals from the package interface of the stacked semiconductor device. This prevents these functional chiplets from being stacked on top of another die because such stacking would involve including through-silicon vias in the other die to enable the functional chiplets to receive signals from the package interface of the stacked semiconductor device. Such through-silicon vias would adversely affect the active portion of the die on which the functional chiplet is stacked. Similarly, including the functionality of a functional chiplet in a die on which another die is stacked would result in through-silicon vias in the portion of the die that performs the functionality of the functional chiplet to enable the die to communicate with the other die, preventing the functionality of the functional chiplet from being performed. Conventional methods place functional chiplets side-by-side with other dies, which increases the overall area of ​​the stacked semiconductor device and increases the distance between the functional chiplet and the other dies, thereby increasing the latency of the functional chiplet communicating with the other dies.

[0005] To reduce the overall area of ​​a stacked semiconductor device while reducing the latency at which chiplets coupled to an interposer die communicate with other dies, this specification describes coupling a portion of a chiplet to a first surface of an interposer die. The first surface of the interposer die is opposite a second surface of the interposer die positioned on a package substrate. This raises the chiplet above the package substrate, resulting in a portion of the chiplet being cantilevered from the interposer die. To support the cantilevered portion of the chiplet, a spacer interconnect is positioned between the chiplet and the package substrate. Such a configuration reduces the overall area of ​​the semiconductor device by repositioning the chiplet from adjacent to the interposer die to a position partially overlapping the interposer die. Furthermore, the above-described configuration allows the chiplet to receive signals or power through the spacer interconnect rather than from through-silicon vias formed in the interposer die.

[0006] To that end, this specification describes various embodiments of a semiconductor package assembly that includes a package interface and an interposer die having a first surface and a second surface opposite the first surface, where the first surface of the interposer die is positioned on the package interface and the interposer die includes a plurality of conductive connections between the first surface and the second surface. The semiconductor package assembly further includes a chiplet including a connection region having conductive paths, where a first portion of the connection region is coupled to the conductive connections of the interposer die and a second portion of the connection region is not coupled to the interposer die. In various embodiments, the first portion of the connection region of the chiplet is configured to communicate with the interposer die and the second portion of the connection region of the chiplet is configured to communicate with the package substrate.

[0007] In some embodiments, the semiconductor package assembly also includes a spacer interconnect spacer device disposed between a second portion of the connection region of the chiplet and the package interface, the spacer device including a spacer conductive connection coupling the conductive pathway of the second portion of the connection region to one or more connections in the package interface. In various embodiments, the spacer interconnect comprises a passive die. In some embodiments, a diameter of the spacer conductive connection is different from a diameter of a connector included in the package interface. In some embodiments, the diameter of the spacer conductive connection is smaller than a diameter of the connector included in the package interface. In some embodiments, a plurality of spacer conductive connections are coupled to the connector included in the package interface. In various embodiments, a diameter of the spacer conductive connection is equal to a diameter of the connector included in the package interface. In some embodiments, the spacer interconnect includes a molding compound that fills a distance between the second portion of the connection region and a surface of the package interface and fills areas between and around one or more other chiplets included in the semiconductor package assembly. In some embodiments, the spacer interconnect has a thickness based on the distance between the second portion of the connection region of the chiplet and a surface of the package interface.

[0008] In some embodiments, the interposer die includes an active interposer die.Chiplets are configured to perform one or more input / output functions in various embodiments.

[0009] The present specification further describes a method including coupling a first portion of a connection area of ​​a chiplet to a conductive connection of an interposer die to a second surface of the interposer die, the conductive connection being between the second surface and the first surface of the interposer die, the connection area having one or more conductive paths, and the second portion of the connection area being cantilevered from the interposer die. In some embodiments, the method further couples a spacer interconnect to the second portion of the connection area of ​​the chiplet and to a package interface coupled to the first surface of the interposer die, the spacer interconnect including one or more spacer conductive connections coupled to one or more of the conductive paths of the second portion of the connection area and coupled to a connector in the package interface to which the interposer die is coupled. In some embodiments, the spacer interconnect comprises a passive die. In some embodiments, a diameter of the spacer conductive connection is smaller than a diameter of a connector included in the package interface. In some embodiments, a plurality of spacer conductive connections are coupled to a connector included in the package interface. In various embodiments, a diameter of the spacer conductive connection is equal to a diameter of a connector included in the package interface. The spacer interconnect, in various embodiments, has a thickness based on the distance between the second portion of the connection area of ​​the chiplet and the surface of the package interface. In some embodiments, the interpose die is an active interposer die.

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature includes embodiments in which the first and second features are formed in direct contact, as well as embodiments in which an additional feature is formed between the first and second features such that the first and second features are in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "front," "back," "top," and "bottom" are used herein to facilitate descriptions that describe the relationship of one element or feature to another, as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "back" are used herein to more easily identify various components and to identify those components as being on opposite sides of another component, for example. Spatially relative terms are intended to encompass different orientations of the device during use or processing in addition to the orientation depicted in the figures.

[0011] FIG. 1 is a cross-sectional view of a semiconductor assembly including a chiplet 100 coupled to an interposer die 105 and a spacer interconnect 120. In various embodiments, chiplet 100 implements one or more specific functions for a system on chip (SoC). For example, chiplet 100 performs one or more input / output functions for the SoC, enables communication between one or more other dies in the semiconductor assembly and components external to the semiconductor assembly, and performs one or more direct memory access (DMA) functions for the semiconductor assembly, one or more address translation functions for the semiconductor assembly, one or more input / output memory management functions for the semiconductor assembly, one or more security functions for the semiconductor assembly, or one or more compression functions for the semiconductor assembly. However, in other embodiments, chiplet 100 performs any suitable function or combination of functions for the semiconductor assembly.

[0012] The interposer die 105 receives power or other signals and routes power to other components of the semiconductor assembly, such as other dies or chiplets included in the semiconductor assembly. The interposer die 105 has a first surface 104 and a second surface 106 opposite and parallel to the first surface 104, with a plurality of conductive connections 107 between the first surface 104 and the second surface 106. In some embodiments, the interposer die 105 is an active interposer that includes logic for routing signals, power, etc. received by the interposer die 105 to one or more of the conductive paths. Such routing logic enables the interposer die 105 to direct signals, power, etc. received by the interposer die 105 to other components. In some embodiments, the first surface 104 of the interposer die 105 is the front surface of the interposer die 105, and the second surface 106 of the interposer die 105 is the back surface of the interposer die 105. Alternatively, in other embodiments, first surface 104 of interposer die 105 is a backside of interposer die 105 and second surface 106 of interposer die 105 is a front side of interposer die 105 .

[0013] In various embodiments, interposer die 105 receives power and ground through package interface 110, which in the embodiment shown in FIG. 1 couples interposer die 105 to a substrate (not shown). In various embodiments, package interface 110 includes connectors 140, such as copper pillars, solder bumps (e.g., C4 bumps), or other types of package interconnects. One or more of connectors 140 are coupled to conductive connections 107 of interposer die 105, allowing interposer die 105 to be coupled to components external to the semiconductor assembly via connectors 140 and conductive connections 107 of interposer die 105. In various embodiments, one or more connectors 140 are coupled to a power source and conductive connections 107 of interposer die 105, allowing interposer die 107 to receive power from a power source.

[0014] Additionally, interposer die 105 includes one or more connection layers 135. In some examples, connection regions 135 include layers of metallization and interlevel dielectric material, as well as conductive structures such as vias, traces, and pads. In these examples, one or more connection layers 135 form connections between circuit components configured within the die substrate to implement the functional circuit blocks of interposer die 105. One or more connection layers 135 implement die-level redistribution layer structures, such as back-end of line (BEOL) structures, created during the die fabrication process. In another example, one or more connection layers 135 are implemented using bond pads or bond pad vias. In another example, one or more connection layers 135 are redistribution layers (RDLs) included in interposer die 105. In another example, one or more connection layers 135 are implemented using two or more structures (e.g., BEOL and bond pad vias). During the manufacturing process, the interconnects are created with a very fine line / space pitch of less than 1 μm, thus enabling high-density connections. In these examples, one or more connection layers include bonding sites to which metal connectors (e.g., die pads, microbumps, Controlled Collapse Chip Connection (C4) bumps) can be attached, either during the manufacturing process or in a post-manufacturing process such as die packaging. In various embodiments, one or more of the connection layers 135 are coupled to one or more of the conductive connections 107 of the interposer die 105. By coupling the conductive connections 107 of the interposer die 105 to the connection layers 135, the interposer die 105 can distribute signals or power received via the conductive connections 107 to other components of the semiconductor assembly via the connection layers 135 of the interposer die 105.For illustrative purposes, FIG. 1 shows one or more connection layers 135 closest to the second surface 106 of the interposer die 105, which includes one or more connection layers near the first surface 104 of the interposer die 105, and these connection layers include bonding sites to which metal connectors (e.g., die pads, microbumps, Controlled Collapse Chip Connection (C4) bumps) can be attached in various embodiments.

[0015] 1 , a first portion of chiplet 100 is positioned on a portion of second surface 106 of interposer die 105. In various embodiments, a first portion of the first surface of chiplet 100 is coupled to a portion of second surface 106 of interposer die 105. The first surface of chiplet 100 is closest to package interface 110 in various embodiments. Chiplet 100 includes a connection region 115 proximate to the first surface of chiplet 100. Connection region 115 includes conductive paths that are generally parallel to second surface 106 of interposer die 105. In various embodiments, the conductive paths include layers of metallization and interlevel dielectric material, as well as conductive structures such as vias, traces, and pads. 1, a first portion of chiplet 100 is face-to-second (F2B) bonded to a portion of second surface 106 of interposer die 105 through various bonding techniques, such as hybrid bonding, thermo-compression bonding, solder reflow, and other techniques. However, it is further contemplated that chiplet 100 may be face-to-face (F2F) bonded to interposer die 105 through various bonding techniques, such as hybrid bonding, thermo-compression bonding, solder reflow, and other techniques.

[0016] A first portion of the connection region 115 within the first portion of the chiplet 100 is coupled to one or more conductive connections 107 of the interposer die 105. However, a second portion of the connection region 115 is not coupled to the chiplet 100. Thus, the second portion of the connection region 115 is cantilevered from the chiplet 100 above the surface of the package interface 110. In some embodiments, the one or more conductive connections 107 of the interposer die 105 are directly coupled to one or more conductive paths of the first portion of the connection region 115. In other embodiments, the one or more conductive paths of the first portion of the connection region 115 are coupled to one or more connection layers 135 of the interposer die 105, and the one or more connection layers 135 are coupled to one or more conductive connections 107 of the interposer die 105. For example, the first portion of the connection region 115 within the first portion of the chiplet 100 is coupled to one or more conductive connections 107 through the second surface 106 of the interposer die 105. As shown in FIG. 1 , conductive connections 107 of interposer die 105 provide connections from one or more connection layers 135 of interposer die 105 or from die second surface 106 to first surface 104 of interposer die 105. Thus, conductive connections 107 provide signals (as well as power and ground) on one surface of interposer die 105 to the opposing surface of interposer die 105 for interconnection to another component. In the example shown by FIG. 1 , second surface 106 of interposer die 105 includes one or more connection layers 135 including a metallization layer or multiple levels of metallization and dielectric layers generated on die second surface 106 to connect conductive connections 107 to another component. Conductive connections 107 are through-die vias in various embodiments. In some examples, conductive connections 107 are fabricated before device layers (transistors, capacitors, resistors, etc.) are patterned on interposer die 105. In some examples, the conductive connections 107 are fabricated after the individual devices are patterned, but before one or more connection layers are created on the interposer die 105. In some examples, the conductive connections 107 are fabricated after (or during) the fabrication of one or more connection layers.After formation, the conductive connections 107 can be selectively filled or plated with a conductive material (e.g., copper) to create the interconnect. In some examples, the diameter of the conductive connections 107 is less than 10 μm. In some examples, the conductive connections 107 are buried, so that a large portion of the substrate must be ground or etched away to expose the conductive connections 107. The conductive connections 107 provide a high-density, short-channel, wide interconnect useful for die separation and die stacking. In some embodiments, one or more of the conductive connections 107 are bonded to one or more of the connection layers 135 of the interposer die 105.

[0017] As shown in FIG. 1 , spacer interconnect 120 is disposed between package interface 110 and a second portion of a first surface of chiplet 100, the second portion including a second portion of connection region 115 of chiplet 100. Spacer interconnect 120 is a passive die in some embodiments and in still other embodiments. In various embodiments, the passive die comprises silicon that does not include active components but includes spacer conductive connections 125, which are described further below. In another embodiment, spacer interconnect 120 is a dielectric material. In other embodiments, spacer interconnect 120 is a die that includes one or more active components. In various embodiments, spacer interconnect 120 is coupled to an edge 130 of the first surface of chiplet 100 opposite the edge of chiplet 100 to which interposer die 105 is coupled. For example, spacer interconnect 120 is coupled to a second portion of connection region 115 of chiplet 100. Additionally, spacer interconnect 120 includes spacer conductive connections 125 that couple one or more conductive paths of connection region 115 in the second portion of chiplet 100 to one or more connections 140 in package interface 110. For example, one or more of spacer conductive connections 125 of spacer interconnect 120 are coupled to one or more connectors 140 in package interface 110 and one or more conductive paths of connection region 115 in the second portion of chiplet 100. In various embodiments, spacer conductive connections 125 of spacer interconnect 120 are through vias within spacer interconnect 120, such as through silicon vias within spacer interconnect 120. In some embodiments, the through vias are selectively filled or plated with a conductive material (e.g., copper) to create the interconnect.

[0018] The spacer conductive connections 125 extend through a thickness 145 of the spacer interconnects 120. The thickness 145 of the spacer interconnects 120 is based on the vertical distance between the first surface of the chiplet 100 and the surface of the package interface 110. Thus, the spacer conductive connections 125 enable coupling of the chiplet 100 to the connectors 140 included in the package interface 110 for coupling components external to the semiconductor assembly to components within the semiconductor assembly. Furthermore, the spacer interconnects 120 compensate for the height difference between the surface of the package interface 110 and the first surface of the chiplet 100. In the example shown by FIG. 1 , the thickness 145 of the spacer interconnects 120 is based on the distance between the first surface of the chiplet 100 and the top surface of the package interface 110. For example, the spacer interconnects 120 have a thickness 145 equal to the distance between the top surface of the package interface 110 parallel to the chiplet 100 and the first surface of the chiplet 100. As another example, spacer interconnect 120 has a thickness 145 that is within a threshold amount of the distance between the top surface of package interface 110, which is parallel to the first surface of chiplet 100, and the first surface of chiplet 100. Thus, thickness 145 of spacer interconnect 120 can be customized for different embodiments to account for different distances between the first surface of chiplet 100 and the surface of package interface 110 of the semiconductor assembly.

[0019] In different embodiments, the diameter of the spacer conductive connections 125 included in the spacer interconnect 120 is different from the diameter of the conductive connections 107 in the interposer die 105. In some embodiments, the spacer conductive connections 125 in the spacer interconnect 120 have a diameter smaller than the diameter of the connector 140 in the package interface 110, such that multiple spacer conductive connections 125 are grouped together to reduce impedance for delivering signals from the connector 140 of the package interface 110 to the chiplet 100. For example, the spacer conductive connections 125 have a minimum diameter for the manufacturing method used to manufacture the semiconductor assembly. In other embodiments, the diameter of the spacer conductive connections 125 is determined based on the diameter of the connector 140 of the package interface 110. As one example, the diameter of the spacer conductive connections 210 is equal to the diameter of the connector of the package interface 110. In another example, the diameter of the spacer conductive connections 125 is within a threshold amount of the diameter of the connector 140 of the package interface 110, resulting in relatively wide spacer conductive connections 125 that improve resilience to electromigration-related long-term wear.

[0020] One or more of the spacer conductive connections 125 are coupled to one or more connectors 140 of the package interface 110. This electrically couples the one or more spacer conductive connections 125 to components external to the semiconductor assembly via the one or more connectors 140 of the package interface 110. Thus, the spacer conductive connections 125 and the connectors 140 of the package interface 110 enable the chiplet 100 to be coupled to one or more components external to the semiconductor assembly that includes the chiplet 100.

[0021] As shown in FIG. 1 , positioning the first portion of the chiplet 100 on a portion of the second surface 106 of the interposer die 105 reduces the overall area of ​​the semiconductor assembly compared to a technique in which the chiplet 100 and the interposer die 105 are adjacent to each other in a common plane. Positioning the spacer interconnect 120 between the second portion of the chiplet 100 and the package interface 110 also simplifies the provision of power or other signals to the chiplet 100 from the package interface 110. Additionally, this configuration prevents perforation of the chiplet 100 by through-vias while keeping a majority of the first surface of the chiplet 100 exposed for connection to the connector 140 within the package interface 110. Furthermore, positioning the first portion of the chiplet 100 on the second surface 106 of the interposer die 105 elevates the chiplet 100 above the package interface 110, reducing the overall semiconductor assembly size and enabling an increased yield of semiconductor assemblies per wafer.

[0022] 2 is a cross-sectional view of a semiconductor assembly including an interposer die 105 and a chiplet 100 coupled to a spacer interconnect. In the example illustrated by FIG. 2, an additional die 200 is stacked on top of the interposer die 105. In various embodiments, the additional die 200 is coupled to one or more connection layers 135 closest to the second surface 106 of the interposer die 105. The additional die 200 implements one or more additional component functions for a system-on-chip (SoC). For example, the interposer die 105 is an active interposer die configured to direct signals or power to other components of the semiconductor assembly, such as the additional die 200, and the additional die 200 performs one or more computational functions for the semiconductor assembly.

[0023] As further described above in connection with FIG. 1 , a first portion of chiplet 100 is positioned on a portion of the second surface 106 of interposer die 105. In various embodiments, a first portion of the first surface of chiplet 100 is positioned on a portion of the second surface 106 of interposer die 105. In the example illustrated by FIG. 2 , when manufacturing a semiconductor assembly, molding compound 205 (or other material) is used to fill areas between different chiplets or components included in the semiconductor assembly. As shown in FIG. 2 , a portion 207 of molding compound 205 fills the area between package interface 110 and the first surface of chiplet 100. In addition, other portions of molding compound 205 fill areas between chiplets or other components of the semiconductor assembly. In the example illustrated by FIG. 2 , molding compound 205 not only fills the area between chiplet 100 and additional die 200, but also fills the area around additional die 200 and the area around interposer die 105. Thus, the portion 207 of the molding compound 205 between the first surface of the chiplet 100 and the package interface 110 functions as the spacer interconnect 120 of FIG.

[0024] One or more of the spacer conductive connections 210 are coupled to one or more connectors 140 of the package interface 110. This electrically couples the one or more spacer conductive connections 210 to components external to the semiconductor assembly via the one or more connectors 140 of the package interface 110. Thus, the spacer conductive connections 210 and the connectors 140 of the package interface 110 enable the chiplet 100 to be coupled to one or more components external to the semiconductor assembly that includes the chiplet 100.

[0025] 2 , spacer interconnect 120 includes molding compound 205, and spacer conductive connections 210 are included in molding compound 205 to couple one or more traces in connection regions 115 of chiplets 100 to one or more connectors 140 in the package interface. Thus, one or more of spacer conductive connections 210 of spacer interconnect 120 are coupled to one or more of the conductive traces in connection regions 115 of chiplets 100 and to one or more of the connectors 140 of package interface 110. In various embodiments, when molding compound 205 is used as spacer interconnect 120, spacer conductive connections 210 of spacer interconnect 120 are through-mold vias in molding compound 205. In some embodiments, the through-mold vias are selectively filled or plated with a conductive material (e.g., copper) to create the interconnects.

[0026] 1 and 2 illustrate different embodiments for creating spacer interconnects 120 used to fill the area between package interface 110 and the first surface of chiplet 100. In the example of Fig. 1, spacer interconnects 120 can be constructed independently and included in the semiconductor assembly. In the example of Fig. 2, spacer interconnects 120 are created during assembly of the semiconductor assembly by constructing through-mold vias for spacer conductive connections 210 of spacer interconnects 120 during fabrication of the semiconductor assembly.

[0027] FIG. 3 is a cross-sectional comparison of configurations for coupling chiplets 100 to an interposer die 105. For purposes of illustration, FIG. 3 shows a conventional configuration 300 in which chiplets 100 and interposer die 105 are positioned side-by-side. In conventional configuration 300, functional chiplets are coupled to interposer die 105 via interconnect die 305. Thus, in conventional configuration 300, chiplets 100 and interposer die 105 are adjacent in a common plane, and interconnect die 305 is coupled to a first surface of chiplet 100 and a first surface of interposer die 105. For example, in conventional configuration 300, first surface 105 of interposer die 105 and a first surface of chiplet 100 are in a common plane, and both portions are coupled to interconnect die 305. A portion of interconnect die 305 is coupled to a portion of the first surface of chiplet 100 and a portion of the first surface of interposer die 105.

[0028] In contrast, configuration 310 couples chiplet 100 to interposer die 105, as further described above in connection with FIGS. 1 and 2. In configuration 210, a first portion of chiplet 100 is coupled to interposer die 105, as further described above in connection with FIGS. 1 and 2. For example, a first portion of a first surface of chiplet 100 is coupled to a portion of second surface 106 of interposer die 105, the second surface 106 of interposer die 106 being opposite first surface 104 and closest to a package interface (not shown). In configuration 310, spacer interconnect 120, as further described above in connection with FIGS. 1 and 2, is coupled to the first surface of chiplet 100. As further described above in connection with FIGS. 1 and 2, spacer interconnect 120 offsets the height difference between the first surface of chiplet 100 coupled to the second surface of interposer die 105 and a plane containing the first surface of interposer die 105.

[0029] 3 , instead of positioning chiplets 100 and interposer die 105 side-by-side in configuration 300, by coupling a first portion of chiplet 100 to interposer die 105 in configuration 310, the overall width of the combination of interposer die 105 and chiplet 100 is reduced. In FIG. 3 , configuration 310 reduces the width of the combination of interposer die 105 and chiplet 100 by distance 315 relative to configuration 300. By coupling a first portion of a first surface of chiplet 100 to a portion of second surface 106 of interposer die 105 as shown in FIG. 3 , configuration 300 reduces the area used to couple chiplet 100 to interposer die 105 by distance 315 relative to conventional configuration 300 in which interposer die 105 and chiplet 100 are positioned adjacent to each other and coupled to each other via interconnect die 305.

[0030] FIG. 4 is a cross-sectional view of an exemplary integrated circuit device 400 including chiplets 100 coupled to an interposer die 105 and spacer interconnects 120, in accordance with some embodiments of the present disclosure. The exemplary integrated circuit device 400 may be implemented in a variety of computing devices, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, smartphones, and the like (as shown in FIG. 6 ). The exemplary integrated circuit device 400 of FIG. 4 includes a semiconductor assembly 405 including chiplets 100 and an interposer die 105, as further described above in connection with FIGS. 1-3 . The interposer die 105 has a first surface 104 and a second surface 106 that is parallel to and opposite the first surface 104. A first portion of the chiplet 100 is coupled to the interposer die 105. In various embodiments, a first portion of the first surface of the chiplet 100 is coupled to a portion of the second surface 106 of the interposer die 105. A spacer interconnect 120 is coupled to a second portion of the first surface of the chiplet 100. In some embodiments, spacer interconnects 120 are silicon, while in other embodiments, spacer interconnects 120 are a dielectric material. In various embodiments, spacer interconnects 120 are coupled to an edge of the first surface of chiplet 100 that is opposite the edge of chiplet 100 to which interposer die 105 is coupled. Additionally, spacer interconnects 120 include conductive connections 125 that are generally perpendicular to connection regions 115 of chiplet 100.

[0031] As an example, semiconductor assembly 405 includes one or more processors 505 of a computing device 500, such as that shown in FIG. 5. Computing device 500 may be implemented as, for example, a desktop computer, a laptop, a server, a game console, a smartphone, a tablet, or the like. In addition to one or more processors 505, computing device 500 includes memory 510. Memory 510 may include random access memory (RAM) or other volatile memory. Memory 510 may also include non-volatile memory, such as disk storage, solid-state storage, or the like.

[0032] In some embodiments, computing device 500 also includes one or more network interfaces 515. In some embodiments, network interface 515 includes a wired network interface 515, such as an Ethernet or another wired network connection, as may be appreciated. In some embodiments, network interface 515 includes a wireless network interface 515, such as a WiFi, BLUETOOTH, cellular, or other wireless network interface 515, as may be appreciated. In some embodiments, computing device 500 includes one or more input devices 520 that accept user input. Exemplary input devices 520 include a keyboard, touchpad, touchscreen interface, etc. Those skilled in the art will appreciate that in some embodiments, input device 520 includes peripheral devices such as an external keyboard, mouse, etc.

[0033] In some embodiments, computing device 500 includes display 525. In some embodiments, display 525 includes an external display connected via a video or display port. In some embodiments, display 525 is contained within the housing of computing device 500. For example, display 525 includes the screen of a tablet, laptop, smartphone, or other mobile device. In embodiments in which display 525 includes a touchscreen, display 525 also functions as input device 520.

[0034] The semiconductor assembly 405 is coupled to a substrate 410. The substrate 410 is a piece of material that provides mechanical support for coupled components, such as the semiconductor assembly 405. In some embodiments, the substrate 410 electrically couples various components attached to the substrate 410 via conductive traces, tracks, pads, etc. For example, the substrate 410 electrically couples components of the semiconductor assembly 405 to one or more other components via connecting traces and solder joints formed from solder balls coupled to conductive pads, such as via a connector 140 within the package interface 110 of the semiconductor assembly 405. One or more of the spacer conductive connections 125, in various embodiments, are coupled to a connector 140 to couple the chiplet 100 to one or more components external to the semiconductor assembly 405.

[0035] In some embodiments, the substrate 410 comprises a printed circuit board (PCB), while in other embodiments, the substrate 410 is another semiconductor device, such as the semiconductor assembly 405 (which may include active components therein). In some embodiments, the connector 140 that couples the semiconductor assembly 405 to the substrate 410 is included in a socket (not shown), and the semiconductor assembly 405 is soldered or otherwise attached to the socket. In other embodiments, as shown in FIG. 4 , the connector 140 of the package interface 110 directly couples the semiconductor assembly 405 and is directly coupled to the substrate 410 via a direct solder connection or other connection, as can be appreciated. In some embodiments, the semiconductor assembly 405 is coupled to the substrate 410 using a land grid array (LGA), pin grid array (PGA), or other packaging technology, as can be appreciated.

[0036] For further explanation, FIG. 6 presents a flowchart illustrating an exemplary method for fabricating chiplets 100 coupled to an interposer die 105 and spacer interconnects 120. The method illustrated in FIG. 6 includes coupling (605) a first portion of a connection region 115 of the chiplet 100 to one or more conductive connections 107 on a second surface of the interposer die 105 that is opposite and parallel to the first surface of the interposer die 105. The second portion of the connection region 115 of the chiplet 100 is cantilevered from the interposer die 105. Thus, the first portion of the connection region 115 of the chiplet is coupled to the chiplet's conductive connections 107, and the second portion of the connection region 115 is not coupled to the interposer die 105, causing portions of the chiplet 100 other than the first portion of the connection region 115 to overhang the interposer die 105. The one or more conductive connections 107 are between the first surface of the interposer die 105 and the second surface of the interposer die 105. Connection region 115 includes at least one conductive path coupled to at least one conductive connection 107, as further described above in connection with FIG. 1. In some embodiments, the chiplets are configured to perform one or more input / output functions. Furthermore, in some embodiments, interposer die 105 is an active interposer.

[0037] In some embodiments, the method further includes coupling (610) the spacer interconnect 120 such that it is coupled to a second portion of the connection region 115 of the chiplet 100. The spacer interconnect 120 is coupled to the package interface 110 opposite the second portion of the connection region 115. Thus, the spacer interconnect 120 fills the distance between the package interface 110 and the second portion of the connection region 115 cantilevered from the interposer die 105. The spacer interconnect 120 includes one or more spacer conductive connections 125 coupled to one or more conductive paths of the connection region 115 within the second portion of the connection region 115 of the chiplet 100. The one or more spacer conductive connections 125 are also coupled to a connector 140 included in the package interface 110. In various embodiments, the spacer interconnect 120 is a passive die (i.e., a die that does not include any active components). In other embodiments, the spacer interconnect 120 is a molding compound that fills the distance between the first surface of the chiplet and the package interface. 2, the molding compound fills the areas between and around chiplet 100 and one or more other chiplets included in a semiconductor package assembly that includes interposer die 105. Spacer conductive connections 125 are through-mold vias in some of these embodiments.

[0038] In various embodiments, the diameter of the spacer conductive connections 125 is equal to the diameter of the connectors 140 included in the package interface 110. In other embodiments, the diameter of the spacer conductive connections 125 is smaller than the diameter of the connectors 140 included in the package interface 110. When the diameter of the spacer conductive connections 125 is smaller than the diameter of the connectors 140 included in the package interface 110, multiple spacer conductive connections 125 are coupled to the connectors 140 included in the package interface 110. The spacer interconnects 120 have a thickness based on the distance between the first surface of the chiplet 100, including the connection region 115, and the surface of the package interface 110, which determines the thickness of the spacer interconnects 120 in various embodiments.

[0039] In consideration of the above discussion, the reader will appreciate that fabricating a semiconductor assembly including a die coupled to an interconnect die coupled to a spacer interconnect allows the die to be coupled to another component having a different height or temperature constraints than the die. Additionally, bonding the die to an interconnect die coupled to a spacer interconnect simplifies connection of the die to other components when the semiconductor assembly is a stacked semiconductor assembly by including the interconnect die during fabrication of the semiconductor assembly. Furthermore, bonding the second surface of the die to an interconnect die coupled to a spacer interconnect allows the first surface of the die to remain unobstructed, simplifying the transfer of power, ground, or other signals to the first surface of the die.

[0040] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A semiconductor package assembly, comprising: The package interface an interposer die having a first surface and a second surface opposite the first surface, the first surface of the interposer die being disposed on the package interface, the interposer die including a plurality of conductive connections between the first surface and the second surface; a chiplet including a connection region having conductive paths, a first portion of the connection region coupled to a conductive connection of the interposer die and a second portion of the connection region cantilevered from the interposer die; Semiconductor package assembly.

2. a spacer interconnect disposed between a second portion of the connection region of the chiplet and the package interface, the spacer interconnect including a spacer conductive connection coupling a conductive path of the second portion of the connection region to one or more connectors in the package interface; The semiconductor package assembly of claim 1 .

3. the spacer interconnect includes a passive die; The semiconductor package assembly of claim 2 .

4. The diameter of the spacer conductive connection is different from the diameter of the connector included in the package interface; The semiconductor package assembly of claim 2 .

5. The diameter of the spacer conductive connection is smaller than the diameter of the connector included in the package interface; 5. The semiconductor package assembly of claim 4.

6. a plurality of spacer conductive connections coupled to the connector included in the package interface; 6. The semiconductor package assembly of claim 5.

7. the diameter of the spacer conductive connection is equal to the diameter of the connector included in the package interface; The semiconductor package assembly of claim 2 .

8. the spacer interconnect includes a molding compound that fills a distance between the second portion of the connection region and a surface of the package interface and fills areas between and around one or more other chiplets included in the semiconductor package assembly. The semiconductor package assembly of claim 2 .

9. the spacer interconnect has a thickness based on a distance between the second portion of the connection region of the chiplet and a surface of the package interface. The semiconductor package assembly of claim 2 .

10. the interposer die includes an active interposer die; The semiconductor package assembly of claim 1 .

11. The chiplets are configured to perform one or more input / output functions. The semiconductor package assembly of claim 1 .

12. the first portion of the connection area of ​​the chiplet is configured to communicate with the interposer die, and the second portion of the connection area of ​​the chiplet is configured to communicate with a package substrate to which the interposer die is coupled. The semiconductor package assembly of claim 1 .

13. 1. A method comprising: coupling a first portion of the connection area of ​​the chiplet to the conductive connection of the interposer die and to a second surface of the interposer die; the conductive connection is between the second surface and a first surface of the interposer die; the connection region having one or more conductive paths; a second portion of the connection area cantilevered from the interposer die; method.

14. coupling a spacer interconnect to a second portion of the connection area of ​​the chiplet and to a package interface coupled to the first surface of the interposer die; the spacer interconnects are coupled to one or more conductive paths in the second portion of the connection region and include one or more spacer conductive connections coupled to a connector in a package interface to which the interposer die is coupled.

14. The method of claim 13.

15. the spacer interconnect includes a passive die; 15. The method of claim 14.

16. The diameter of the spacer conductive connection is smaller than the diameter of the connector included in the package interface; 15. The method of claim 14.

17. a plurality of spacer conductive connections coupled to the connector included in the package interface; 15. The method of claim 14.

18. the diameter of the spacer conductive connection is equal to the diameter of the connector included in the package interface; 15. The method of claim 14.

19. the spacer interconnect has a thickness based on a distance between a second portion of the connection region of the chiplet and a surface of the package interface.

15. The method of claim 14.

20. the interposer die includes an active interposer die; 14. The method of claim 13.

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