Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer, a first pad arranged on an upper surface of the insulating layer, and a first protective layer arranged on the upper surface of the insulating layer and having an opening that vertically overlaps the first pad, wherein the opening in the first protective layer includes an area having a horizontal width greater than the width of the first pad, and the first protective layer is arranged to cover at least a portion of a side surface of the first pad.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] 2. Description of the Related Art In general, a printed circuit board (PCB) is a laminated structure in which insulating layers and conductive layers are alternately stacked, and the conductive layers can be formed into a circuit pattern by patterning.

[0003] Such a printed circuit board is provided with a solder resist SR that protects the circuit formed on the outermost layer of the laminate, prevents oxidation of the conductor layer, and acts as an insulator when electrically connecting to a chip or other substrate mounted on the printed circuit board.

[0004] In general, solder resist has opening areas (SRO) that serve as electrical connection paths when connecting means such as solder or bumps are bonded. As the performance and density of printed circuit boards increase, the I / O (Input / Output) performance improves, and more opening areas are required in solder resist, which in turn requires a smaller bump pitch. In this case, the bump pitch in the opening area refers to the center distance between adjacent opening areas.

[0005] On the other hand, the solder resist opening region SRO includes a solder mask defined type (SMD) and a non-solder mask defined type (NSMD).

[0006] The SMD type is characterized in that the width of the opening region SRO is smaller than the width of the pad exposed through the opening region SRO, so that in the SMD type, at least a portion of the upper surface of the pad is covered with the solder resist.

[0007] In addition, the NSMD type is characterized in that the width of the opening region SRO is larger than the width of the pad exposed through the opening region SRO. As a result, in the NSMD type, the solder resist is disposed at a certain distance from the pad, thereby exposing both the top and side surfaces of the pad.

[0008] However, in the case of SMD type, there is a problem that the solder balls separate from the pads exposed through the opening region SRO during a solder ball joint reliability test for the bonding strength of the solder balls after the semiconductor package is attached to the main board, and in the case of NSMD type, there is a problem that the pads on which the solder balls are placed separate from the board. Summary of the Invention [Problem to be solved by the invention]

[0009] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0010] Alternatively, an embodiment provides a circuit board including a protective layer having an opening with a stepped structure, and a semiconductor package including the same.

[0011] Alternatively, the embodiments provide a circuit board capable of increasing the contact area between a connection member and a pad, and a semiconductor package including the same.

[0012] Alternatively, the embodiments provide a circuit board and a semiconductor package including the same that can improve the physical and / or electrical reliability of the metal bonding layer IMC between the pad and the connection member.

[0013] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0014] A circuit board according to an embodiment includes an insulating layer, a first pad arranged on an upper surface of the insulating layer, and a first protective layer arranged on the upper surface of the insulating layer and having an opening that vertically overlaps the first pad, wherein the opening in the first protective layer includes an area having a horizontal width greater than the width of the first pad, and the first protective layer is arranged to cover at least a portion of a side surface of the first pad.

[0015] The circuit board further includes a second pad disposed on the lower surface of the insulating layer, and a second protective layer disposed on the lower surface of the insulating layer and including an opening that vertically overlaps with the second pad.

[0016] Furthermore, a plurality of the first pads are provided, and the spacing between the plurality of first pads is in the range of 20% to 90% of the width of each of the plurality of first pads.

[0017] The width of the region of the opening in the first protective layer is in the range of 105% to 150% of the width of the first pad.

[0018] The first protective layer also includes sidewalls that form the opening and a bottom surface of the opening that is connected to the sidewalls, and the bottom surface is located lower than the top surface of the first pad and higher than the bottom surface of the first pad.

[0019] The first protective layer also has a recess between the sidewall and the bottom surface that is recessed inward of the first protective layer and away from the first pad.

[0020] The first protective layer is provided between the sidewall and the bottom surface and includes an inclined wall that is inclined from the sidewall toward the bottom surface and toward an outer surface of the first pad.

[0021] The vertical distance from the lower surface of the first protective layer to the bottom surface is in the range of 20% to 90% of the thickness of the first pad.

[0022] Furthermore, the horizontal separation distance from the outer surface of the first pad to the side wall of the opening in the first protective layer satisfies the range of 5% to 45% of the interval between the plurality of first pads.

[0023] The opening in the first protective layer has a step whose width changes along the vertical direction.

[0024] Further, the opening in the first protective layer includes a first part adjacent to the upper surface of the first protective layer and having a width greater than a width of the first pad, and a second part provided below the first part and having a width smaller than a width of the first pad.

[0025] Further, the opening in the first protective layer includes a first part adjacent to the upper surface of the first protective layer and having a width greater than the width of the first pad, and a second part provided below the first part and having a width greater than the width of the first pad and smaller than the width of the first part.

[0026] Furthermore, a step portion between the first part and the second part is positioned higher than the upper surface of the first pad.

[0027] Furthermore, the vertical distance from the lower surface of the first protective layer to the step portion satisfies the range of 110% to 140% of the thickness of the first pad.

[0028] Further, the first protective layer includes a first protective member arranged on the insulating layer and a second protective member arranged on the first protective member, and the first part of the opening is provided in the first protective member and the second part of the opening is provided in the second protective member.

[0029] Furthermore, the thickness of the first layer of the first protective layer is greater than the thickness of the first pad, and the upper surface of the first layer of the first protective layer is located higher than the upper surface of the first pad.

[0030] On the other hand, a semiconductor package of an embodiment includes an insulating layer, a first circuit layer disposed on one side of the insulating layer and including a first pad, a first protective layer disposed on one side of the insulating layer and including an opening with a step while vertically overlapping the first pad, a second circuit layer disposed on the other side of the insulating layer and including a second pad, a second protective layer disposed on the other side of the insulating layer and including an opening vertically overlapping the second pad, a first connecting member disposed on the first pad while filling the opening in the first protective layer, a main board disposed on the first connecting member, a second connecting member disposed on the second pad while filling the opening in the second protective layer, and a semiconductor element disposed on the second connecting member, wherein the opening in the first protective layer includes a first part adjacent to the upper surface of the first protective layer and having a width greater than that of the first pad, and a second part provided below the first part and having a width smaller than that of the first part, and at least a portion of the side of the first pad is covered with the first protective layer.

[0031] The semiconductor package further includes at least one semiconductor element disposed on the first circuit layer.

[0032] Additionally, the width of the first pads on the first circuit layer is greater than the width of the second pads on the second circuit layer. [Effects of the Invention]

[0033] The circuit board of the embodiment may include a first insulating layer and a first circuit layer disposed on the first insulating layer. The first circuit layer may include pads that contact electrodes on the main board. The circuit board may include openings disposed on the first insulating layer and vertically overlapping the pads. In this case, the openings may include areas with a width greater than the width of the pads. Furthermore, at least a portion of the side surfaces of the pads may be covered with a first protective layer.

[0034] Therefore, in the embodiment, by covering at least a portion of the side surface of the pad with the first protective layer, the bonding strength between the first insulating layer and the first pad can be improved. Furthermore, in the embodiment, by making at least a portion of the opening wider than the first pad, the contact area between the pad and the connecting member placed on the pad can be improved. That is, in the comparative example, the width of the opening is smaller than the width of the pad, and therefore the contact area between the pad and the connecting member is smaller than the planar area of ​​the pad.

[0035] In contrast, the contact area between the pad and the connection member in the circuit board of the embodiment is equal to or greater than the planar area of ​​the pad. Therefore, the embodiment can improve the bonding strength between the pad and the connection member. As a result, the embodiment can solve the physical and / or electrical reliability problem of the connection member being separated from the pad. Therefore, the embodiment can improve the product characteristics of the circuit board. Furthermore, the embodiment can improve the bonding strength with a main board coupled to the circuit board.

[0036] Meanwhile, in the embodiment, an opening can be formed in the first protective layer through a removal process that thins the thickness. Furthermore, since the opening in the first protective layer is formed through a removal process that thins the thickness, the embodiment allows for easy adjustment of the bottom height of the opening. For example, in the past, an opening was formed through an exposure and development process, and it was impossible to adjust the bottom height of the opening thus formed. In contrast, in the embodiment, the opening is formed through a removal process that thins the thickness, allowing for easy adjustment of the bottom height.

[0037] Therefore, the sidewall of the opening in the first protective layer may include a sloped portion. For example, the first protective layer may include a sloped wall having a certain slope angle between the sidewall and the bottom surface of the opening. In this case, the sloped wall may be closer to the pad of the first circuit layer as it moves from the sidewall toward the bottom surface. Therefore, the embodiment may improve the flowability of the connecting member during the process of placing the connecting member, thereby improving the bonding strength between the pad and the connecting member.

[0038] Alternatively, in the embodiment, the opening of the first protective layer may have a step. Through this, the embodiment can solve the problem of the connection member disposed in the opening of the first protective layer overflowing. Therefore, the embodiment can further improve the electrical reliability of the circuit board.

[0039] Furthermore, a connecting member such as solder is disposed in the opening of the first protective layer. When the connecting member is disposed on a pad, a metal bonding layer may be formed between the connecting member and the pad. In this embodiment, the opening of the first protective layer has a step, thereby increasing the length of the sidewall of the opening between the upper surface of the first protective layer and the metal bonding layer. For example, in the comparative example, the sidewall of the opening connecting the upper surface of the protective layer and the metal bonding layer (IMC) has a structure without an inflection portion. Therefore, in the comparative example, the thickness of the first protective layer had to be increased to increase the distance of the inner wall of the opening between the upper surface of the protective layer and the metal bonding layer (IMC).

[0040] In contrast, in the embodiment, by forming a step in the opening, the length of the sidewall of the opening between the metal bonding layer IMC and the upper surface of the first protective layer can be increased without increasing the thickness of the first protective layer, thereby improving the physical reliability of the metal bonding layer IMC. [Brief explanation of the drawings]

[0041] [Figure 1] FIG. 10 is a cross-sectional view showing a circuit board according to a comparative example. [Figure 2]FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment. [Figure 3] 3 is a plan view of the circuit board in FIG. 2 with the first protective layer removed. FIG. [Figure 4] FIG. 3 is a plan view of the circuit board of FIG. 2. [Figure 5] FIG. 3 is an enlarged view of a portion of FIG. 2. [Figure 6] FIG. 6 is a diagram showing a first modified example of the circuit board of FIG. [Figure 7] FIG. 6 is a diagram showing a second modified example of the circuit board of FIG. [Figure 8] FIG. 10 is a cross-sectional view showing a circuit board according to a second embodiment. [Figure 9] FIG. 9 is an enlarged view of a portion of FIG. 8. [Figure 10] FIG. 10 is an enlarged view of a partial area of ​​a circuit board according to a third embodiment. [Figure 11] FIG. 10 is an enlarged view of a partial area of ​​a circuit board according to a fourth embodiment. [Figure 12a] FIG. 10 is a cross-sectional view showing a circuit board according to a fifth embodiment. [Figure 12b] FIG. 10 is a cross-sectional view showing a circuit board according to a sixth embodiment. [Figure 12c] FIG. 13 is a cross-sectional view showing a circuit board according to a seventh embodiment. [Figure 13] FIG. 1 is a diagram illustrating a semiconductor package according to a first embodiment. [Figure 14a] FIG. 10 is a diagram illustrating a semiconductor package according to a second embodiment. [Figure 14b] FIG. 10 is a diagram showing a semiconductor package according to a third embodiment. [Figure 14c] FIG. 10 is a diagram showing a semiconductor package according to a fourth embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a semiconductor package according to a fifth embodiment. [Figure 16-24] 3A to 3C are diagrams for explaining the manufacturing method of the circuit board of the first embodiment shown in FIG. 2 in the order of steps. [Figure 25-28] 11A to 11C are diagrams for explaining the manufacturing method of the circuit board of the third embodiment shown in FIG. 10 in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0042] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" used in the following description are used interchangeably to facilitate the preparation of the specification and do not have any distinguishing meaning or function. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related known technology is deemed to interfere with the gist of the embodiments disclosed herein, such detailed description will be omitted. Furthermore, the accompanying drawings are provided to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be limited by the accompanying drawings, and should be understood to include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0043] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0044] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly "coupled" or "connected" to the other component, and that there may be other components between them. On the other hand, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components between them.

[0045] A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0046] In this application, the use of terms such as "comprise" or "have" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth in the specification, but should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0047] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0048] -Comparative Example-

[0049] FIG. 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0050] Referring to FIG. 1, the circuit board of the comparative example includes an insulating layer 10.

[0051] A first circuit pattern 20 is disposed on the upper surface of the insulating layer 10. The first circuit pattern 20 includes pads. The circuit board of the comparative example also includes through electrodes that penetrate the insulating layer 10. A first protective layer 30 having first openings 35 that vertically overlap the pads of the first circuit pattern 20 is disposed on the upper surface of the insulating layer 10.

[0052] At this time, the circuit board is coupled to a semiconductor device or an external board, and the pads of the first circuit pattern 20 refer to pads coupled to a main board.

[0053] As a result, the pads of the first circuit pattern 20 have a relatively large width. For example, the width w1 of the pads of the first circuit pattern 20 is 70 μm or more. In addition, the spacing w2 between adjacent pads among the multiple pads is 70 μm or more.

[0054] In this case, since the pad has a relatively large width, the first opening 35 of the first protective layer 30 generally has an SMD type. That is, the width of the first opening 35 of the first protective layer 30 is smaller than the width of the pad. Therefore, at least a part of the upper surface of the pad is covered by the first protective layer 30 without vertically overlapping with the first opening 35.

[0055] Recently, problems have arisen with the bonding strength between the circuit board and the main board, and therefore the size of the connecting members (e.g., solder balls) placed on the pads to connect the main board has become larger.

[0056] However, the width of the first opening 35 of the first protective layer 30 in the comparative example is smaller than the width of the pad, which limits the ability to increase the contact area between the connecting member and the pad simply by increasing the size of the connecting member, and therefore limits the ability to improve the bonding strength between the circuit board and the main board simply by increasing the size of the connecting member.

[0057] In this case, the spacing w2 between the pads is relatively large, at 70 μm or more. Therefore, the problem of short circuits between multiple connecting members arranged on adjacent pads may be relatively low. However, as the size of connecting members gradually increases, the amount of connecting members arranged within the first opening 35 of the first protective layer 30 also increases. As a result, when connecting members are arranged within the first opening 35 of the first protective layer 30, the amount of connecting members that overflows outside the first opening 35 of the first protective layer 30 also increases. Therefore, even connecting members arranged on pads with a relatively large spacing w2 may be interconnected, causing short circuits due to the increased amount of overflow.

[0058] Furthermore, when the first opening 35 of the first protective layer 30 is applied as an NSMD type, the first protective layer 30 does not come into contact with the pad, which causes a problem of reduced adhesion between the insulating layer 10 and the pad.

[0059] The comparative circuit board also includes a second circuit pattern 40 disposed below the insulating layer 10, and a second protective layer 50 disposed below the insulating layer 10 and including a second opening 45 that vertically overlaps the second circuit pattern 40.

[0060] In this case, the second opening 45 also has an SMD type corresponding to the first opening 35. As a result, in the comparative example, the connection area between the connection member and the second circuit pattern 40 is reduced, which causes a problem of a decrease in the adhesion between the connection member and the second circuit pattern 40.

[0061] Furthermore, if the second opening 45 is of the NSMD type, the adhesion between the insulating layer 10 and the second circuit pattern 40 can be reduced. Furthermore, the second circuit pattern 40 is a pad connected to a semiconductor device, and therefore can be a fine pattern with fine line widths and spacing. Therefore, if the second opening 45 is of the SMD type, there is a problem that the contact area with the connecting member cannot be secured. If the second opening 45 is of the NSMD type, there is a problem that the second circuit pattern 40 is not supported by the second protective layer 50, and therefore the second circuit pattern 40 may peel off from the insulating layer 10.

[0062] Below, we provide a circuit board with a new structure that can solve the problems that the circuit board of the comparative example has.

[0063] -Electronic Devices-

[0064] Prior to describing the embodiments, an electronic device including a semiconductor package according to the embodiments will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package according to the embodiments. Various chips may be mounted on the semiconductor package. Mainly, various elements or chips may be mounted on the semiconductor package. The elements or chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPUs), graphics processors (e.g., GPUs), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and application-specific integrated circuits (ASICs).

[0065] Alternatively, the device or chip may include active and passive devices.

[0066] An active element refers to an element that actively utilizes the nonlinear portion of signal characteristics. A passive element refers to an element that does not utilize nonlinear signal characteristics even if both linear and nonlinear signal characteristics exist. For example, active elements may include transistors, IC semiconductor elements, etc., while passive elements may include capacitors, resistors, inductors, etc. Passive elements may increase the signal processing speed of active semiconductor chips or perform filtering functions. Furthermore, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communications.

[0067] On the other hand, the product group to which the semiconductor package of the embodiment is applied may be any of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited to these.

[0068] In this case, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0069] -Circuit boards and semiconductor packages-

[0070] The circuit board and semiconductor package according to the embodiment will be described below.

[0071] 2 is a cross-sectional view showing the circuit board according to Example 1. The overall structure of the circuit board of Example 1 will be described below with reference to FIG.

[0072] Referring to FIG. 2, the circuit board 100 has at least one chip mounted thereon. The circuit board 100 of the embodiment is mounted on a main board of an electronic device. The main board may refer to a motherboard of the electronic device. The circuit board 100 may be connected to the at least one chip and the motherboard to form a first package.

[0073] Additionally, a first package including the circuit board 100 of the embodiment can be coupled to a second package. The second package can be a memory package. In one embodiment, the circuit board 100 can be coupled to a memory board of the second package. In another embodiment, the circuit board can be coupled to an interposer coupled to the memory board.

[0074] The circuit board 100 includes an insulating layer 110. The insulating layer 110 may include multiple layers. In one embodiment, the insulating layer 110 may have, but is not limited to, a three-layer structure.

[0075] In one embodiment, the circuit board 100 may be a core board. For example, the circuit board 100 may include a core layer. For example, the insulating layer 110 of the circuit board 100 of the embodiment may include a third insulating layer 113 corresponding to the core layer including reinforcing fibers.

[0076] The circuit board 100 may have a structure in which at least one insulating layer is stacked on each of the upper and lower sides of the third insulating layer 113. In one embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side of the third insulating layer 113 may have a symmetrical structure. In another embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side of the third insulating layer 113 may have an asymmetrical structure.

[0077] In the following description, the circuit board 100 of the embodiment is a core board, and therefore the third insulating layer 113 is a core layer. However, the embodiment is not limited to this. For example, the circuit board 100 of another embodiment may be a coreless board that does not include a core layer.

[0078] On the other hand, the structural feature of the circuit board of the embodiment is the open structure of the protective layer. The protective layer and the circuit layer described below can be applied to a coreless substrate. Furthermore, at least one of the outermost circuit layers of the embodiment can have an ETS (Embedded Trace Substrate) structure embedded in the surface of the insulating layer 110.

[0079] The insulating layer 110 of the circuit board 100 of the embodiment may include a first insulating layer 111 , a second insulating layer 112 , and a third insulating layer 113 .

[0080] The third insulating layer 113 may refer to an inner insulating layer disposed on the inside of the plurality of insulating layers. The third insulating layer 113 may be disposed between the first insulating layer 111 and the second insulating layer 112. The third insulating layer 113 may include prepreg. The third insulating layer 113 may include reinforcing fibers.

[0081] The first insulating layer 111 may be disposed on the third insulating layer 113. For example, the first insulating layer 111 may be disposed on the upper surface of the third insulating layer 113. The first insulating layer 111 may refer to the first outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the first insulating layer 111 may refer to the insulating layer disposed on the uppermost side in the insulating layer 110 of the circuit board 100. The first insulating layer 111 may provide a mounting area on which at least one chip is mounted or a first bonding area to which a first external substrate is bonded. The first external substrate may be a main board of an electronic device.

[0082] The second insulating layer 112 may be disposed below the third insulating layer 113. The second insulating layer 112 may refer to the second outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the second insulating layer 112 may refer to the insulating layer disposed at the bottom of the insulating layer 110 of the circuit board 100. The second insulating layer 112 may provide a mounting area on which at least one chip is mounted, or a second bonding area on which a second external substrate is bonded. The second external substrate may be a memory substrate or an interposer.

[0083] The first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. Specifically, the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the second insulating layer 112 may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 111 and the second insulating layer 112 may include sapphire.

[0084] Furthermore, the first insulating layer 111 and the second insulating layer 112 may include an optically isotropic film. For example, the first insulating layer 111 and the second insulating layer 112 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), an optically isotropic polymethyl methacrylate (PMMA), or the like.

[0085] Furthermore, first insulating layer 111 and second insulating layer 112 may be formed of a material containing an inorganic filler and an insulating resin. For example, first insulating layer 111 and second insulating layer 112 may include a structure in which an inorganic filler such as silica or alumina is dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. For example, first insulating layer 111 and second insulating layer 112 may include Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imagable Dielectric resin (PID), BT, etc.

[0086] Each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 15 μm to 40 μm.

[0087] If the thickness of the first insulating layer 111 or the second insulating layer 112 is less than 10 μm, the circuit layers included in the circuit board 100 may not be stably protected. Furthermore, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit board 100 may increase, thereby increasing the thickness of the semiconductor package. Furthermore, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit layers and the through electrodes may increase accordingly. Furthermore, if the thickness of the circuit layers and the through electrodes increases, miniaturization may become difficult and the circuit integration density may decrease. Furthermore, the signal transmission distance may increase, resulting in increased signal transmission loss.

[0088] The exemplary circuit board 100 includes a circuit layer disposed on a surface of an insulating layer 110 .

[0089] For example, the circuit board 100 may include a first circuit layer 120 disposed on an upper surface of the first insulating layer 111. For example, the circuit board 100 may include a second circuit layer 130 disposed on a lower surface of the second insulating layer 112. The circuit board 100 may also include a third circuit layer 140 disposed between the lower surface of the first insulating layer 111 and the upper surface of the third insulating layer 113. For example, the circuit board 100 may include a fourth circuit layer 150 disposed between the upper surface of the second insulating layer 112 and the lower surface of the third insulating layer 113.

[0090] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be manufactured using conventional printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi-Additive Process), and SAP (Semi-Additive Process), and detailed description thereof will be omitted here.

[0091] The first circuit layer 120 may refer to a circuit layer disposed on the first outermost layer of the circuit board 100. The second circuit layer 130 may refer to a circuit layer disposed on the second outermost layer of the circuit board 100.

[0092] The first circuit layer 120 may include a plurality of pads disposed on the first insulating layer 111 .

[0093] In this case, in one embodiment, the first circuit layer 120 may include only pads connected to the main board. However, the embodiment is not limited thereto. For example, the first circuit layer 120 may include first pads connected to the main board and second pads connected to the semiconductor device. The first pads and second pads on the first circuit layer 120 may have different widths. The following description will focus on the pads on the first circuit layer 120 connected to the main board.

[0094] The pads on the first circuit layer 120 may be connected to the main board. Therefore, the pads on the first circuit layer 120 may have a width corresponding to the electrodes provided on the main board. For example, the width of the pads on the first circuit layer 120 may be 70 μm or more. For example, the width of the pads on the first circuit layer 120 may be 80 μm or more. For example, the width of the pads on the first circuit layer 120 may be 90 μm or more. For example, the width of the pads on the first circuit layer 120 may be 100 μm or more.

[0095] On the other hand, the pads on the second circuit layer 130 may have a width smaller than that of the pads on the first circuit layer 120. For example, the width of the pads on the second circuit layer 130 may be 25 μm to 65 μm. Preferably, the width of the pads on the second circuit layer 130 may be 30 μm to 60 μm. More preferably, the width of the pads on the second circuit layer 130 may be 32 μm to 55 μm.

[0096] If the width of the pads on the second circuit layer 130 is less than 25 μm, the bonding strength with the semiconductor element may be reduced. If the width of the pads on the second circuit layer 130 is less than 25 μm, the performance of the semiconductor element mounted on the circuit board may be degraded. If the width of the pads on the second circuit layer 130 is more than 65 μm, it may be difficult to arrange all the pads connected to the semiconductor element within a limited space. For example, if the width of the pads on the second circuit layer 130 is more than 65 μm, the circuit integration density may be reduced.

[0097] On the other hand, the width of the pads on the first circuit layer 120 may be larger than the width of the pads on the second circuit layer 130. Preferably, the width of the pads on the first circuit layer 120 corresponds to the width of the electrodes provided on the main board, but is not limited to this, as will be described in more detail below.

[0098] Meanwhile, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be formed of copper (Cu), which is relatively inexpensive.

[0099] Meanwhile, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 5 μm to 30 μm. For example, the first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 6 μm to 25 μm. The first circuit layer 120 and the second circuit layer 130 may have a thickness in the range of 7 μm to 20 μm. If the thickness of the first circuit layer 120 and the second circuit layer 130 is less than 5 μm, resistance and signal transmission loss may increase. If the thickness of the first circuit layer 120 and the second circuit layer 130 exceeds 30 μm, miniaturization may be difficult, which may result in a decrease in circuit integration density.

[0100] The circuit board 100 of the embodiment may include a through electrode. The through electrode may penetrate the insulating layer 110.

[0101] For example, the circuit board 100 may include a first through electrode 161 that penetrates the first insulating layer 111. The circuit board 100 may also include a second through electrode 162 that penetrates the second insulating layer 112. The circuit board 100 may also include a third through electrode 163 that penetrates the third insulating layer 113.

[0102] The first through electrode 161, the second through electrode 162, and the third through electrode 163 may be disposed in through holes that penetrate at least one insulating layer. For example, the first through electrode 161, the second through electrode 162, and the third through electrode 163 may be formed by filling the through holes with a conductive material.

[0103] The through holes can be formed by any of the following processing methods: mechanical, laser, and chemical processing. The through holes can be formed by mechanical processing methods such as milling, drilling, and routing. The through holes can also be formed using UV or CO2 laser methods. The through holes can also be formed using chemical processing methods using chemicals including silane, ketones, etc.

[0104] On the other hand, the circuit board 100 of the embodiment includes a protective layer.

[0105] Specifically, a first protective layer 170 can be disposed on the first insulating layer 111 .

[0106] The first protective layer 170 may include an opening 175 .

[0107] The opening 175 of the first protective layer 170 can be defined as a groove. For example, the opening 175 of the first protective layer 170 can not penetrate the first protective layer 170. Preferably, the first protective layer 170 can include an upper surface and a lower surface. The bottom surface of the opening 175 of the first protective layer 170 can be positioned higher than the lower surface of the first protective layer 170. For example, the opening 175 of the first protective layer 170 can also be defined as a groove that is concave from the upper surface toward the lower surface of the first protective layer 170.

[0108] The openings 175 of the first protective layer 170 may vertically overlap the first circuit layer 120. Preferably, the openings 175 of the first protective layer 170 may vertically overlap the pads of the first circuit layer 120. In this case, the openings 175 of the first protective layer 170 may have a width greater than that of the pads of the first circuit layer 120. This means that the top surfaces of the pads of the first circuit layer 120 do not need to be covered by the first protective layer 170.

[0109] Furthermore, the bottom surface of the opening 175 in the first protective layer 170 can be located lower than the upper surface of the pads on the first circuit layer 120, while being located higher than the lower surface of the pads on the first circuit layer 120.

[0110] Therefore, at least a portion of the pad of the first circuit layer 120 may horizontally overlap the opening 175 of the first protective layer 170. As a result, the side of the pad of the first circuit layer 120 may include a first portion that is covered by the first protective layer 170. In addition, the side of the pad of the first protective layer 170 may include a second portion that is not covered by the first protective layer 170 while horizontally overlapping the opening 175 of the first protective layer 170.

[0111] Meanwhile, the circuit board 100 may further include a second protective layer 180 disposed on the lower surface of the second insulating layer 112 .

[0112] The second protective layer 180 may include at least one opening 185. For example, the second protective layer 180 may include an opening 185 that vertically overlaps at least a portion of the second circuit layer 130. The opening in the second protective layer 180 may fully or partially vertically overlap a pad of the second circuit layer 130 that is connected to a chip.

[0113] For example, the opening 185 of the second protective layer 180 may have an SMD type. Specifically, the opening 185 of the second protective layer 180 may be provided with a different type from the opening 175 of the first protective layer 170.

[0114] The following description will focus on the structure of the opening 175 in the first protective layer 170.

[0115] Meanwhile, the first protective layer 170 and the second protective layer 180 may include an insulating material, and may include various materials that can be cured by heating after being applied to protect the surfaces of the insulating layer and the circuit layer.

[0116] The first protective layer 170 and the second protective layer 180 may be solder resist layers containing an organic polymer material. For example, the first protective layer 170 and the second protective layer 180 may include an epoxy acrylate resin. In particular, the first protective layer 170 and the second protective layer 180 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the first protective layer 170 and the second protective layer 180 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0117] The thickness of the first protective layer 170 and the second protective layer 180 may be 1 μm to 20 μm. The thickness of the first protective layer 170 and the second protective layer 180 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 170 and the second protective layer 180 may be 5 μm to 20 μm. If the thickness of the first protective layer 170 and the second protective layer 180 exceeds 20 μm, the overall thickness of the circuit board and the semiconductor package may increase.

[0118] Here, the thickness of the first protective layer 170 and the thickness of the second protective layer 180 may refer to the thickness of the portion of the protective layer that protrudes from the surface of the reference circuit layer.

[0119] For example, the thickness of the first protective layer 170 may refer to the vertical distance from the upper surface of the first circuit layer 120 to the upper surface of the first protective layer 170. For example, the thickness of the second protective layer 180 may refer to the vertical distance from the lower surface of the second circuit layer 130 to the lower surface of the second protective layer 180.

[0120] Meanwhile, a surface treatment layer may be disposed on the pads of the first circuit layer 120 exposed through the openings 175 of the first protective layer 170. The surface treatment layer may be an organic solderability preservative (OSP) layer. For example, the surface treatment layer may be an organic coating layer coated with an organic substance such as benzimidazole. However, the embodiment is not limited thereto. For example, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer, and a gold (Au) plating layer.

[0121] The following will specifically describe the configuration of a portion of the circuit board 100 shown in FIG.

[0122] 3 is a plan view of the circuit board of FIG. 2 with the first protective layer removed, FIG. 4 is a plan view of the circuit board of FIG. 2, and FIG. 5 is an enlarged view of a portion of FIG. 2.

[0123] 3, a first circuit layer 120 may be disposed on the first insulating layer 111. For example, the first circuit layer 120 may include a plurality of pads.

[0124] The width W1 of the pads on the first circuit layer 120 may be 70 μm or more, 80 μm or more, 90 μm or more, or 100 μm or more.

[0125] For example, the width W1 of the pads on the first circuit layer 120 can be in the range of 70 μm to 150 μm. For example, the width W1 of the pads on the first circuit layer 120 can be in the range of 75 μm to 145 μm. For example, the width W1 of the pads on the first circuit layer 120 can be in the range of 80 μm to 140 μm.

[0126] If the width W1 of the pad on the first circuit layer 120 is less than 70 μm, the contact area between the pad and the connecting member may be reduced. This reduction in the contact area may result in physical and / or electrical reliability issues, such as the connecting member becoming separated from the pad. This reduction in the contact area may also reduce the bonding strength between the circuit board and the main board. Furthermore, if the width W1 of the pad on the first circuit layer 120 is less than 70 μm, the difference in width between the pad and the electrode on the main board may be large. This large difference in width may result in reduced physical and / or electrical characteristics between them. For example, this large difference in width may increase the transmission loss of electrical signals transmitted therethrough.

[0127] On the other hand, if the width W1 of the pads of the first circuit layer 120 exceeds 150 μm, the overall planar area of ​​the circuit board can be increased accordingly.

[0128] On the other hand, the pads of the first circuit layer 120 may have a circular planar shape. When the planar shape of the pads of the first circuit layer 120 is circular, the width W1 may refer to the diameter of the pads of the first circuit layer 120.

[0129] In other embodiments, the planar shape of the pads on the first circuit layer 120 may be square or rectangular. When the planar shape of the pads on the first circuit layer 120 is square or rectangular, the width W1 may refer to the smaller of the width and length of the pads on the first circuit layer 120 in the width direction and the length direction.

[0130] In another embodiment, the planar shape of the pad on the first circuit layer 120 may be elliptical. When the planar shape of the pad on the first circuit layer 120 is elliptical, the width W1 may refer to the diameter of the elliptical pad in the minor axis direction.

[0131] Meanwhile, the pads of the first circuit layer 120 may be spaced apart at a predetermined interval W2, which may refer to the distance between the most adjacent pads among the pads.

[0132] The spacing W2 between the pads on the first circuit layer 120 may have a range corresponding to the width W1 of the pads on the first circuit layer 120.

[0133] In other embodiments, the spacing W2 may be smaller than the width W1 of the pads on the first circuit layer 120.

[0134] For example, the spacing W2 between the pads on the first circuit layer 120 can be in the range of 20% to 90% of the pad width W1. Preferably, the spacing W2 between the pads on the first circuit layer 120 can be in the range of 23% to 88% of the pad width W1. More preferably, the spacing W2 between the pads on the first circuit layer 120 can be in the range of 25% to 85% of the pad width W1.

[0135] If the spacing W2 between the pads on the first circuit layer 120 is less than 20% of the pad width, a short circuit may occur between the pads depending on the process capability in manufacturing the circuit board 100, thereby reducing the electrical reliability of the circuit board 100. Furthermore, if the spacing W2 between the pads on the first circuit layer 120 is less than 20% of the pad width W1, interference may occur between signals transmitted through the pads. If interference occurs, signal transmission loss may increase, thereby reducing signal transmission characteristics.

[0136] On the other hand, if the spacing W2 between the pads on the first circuit layer 120 exceeds 90% of the pad width W1, it may be difficult to arrange all the pads connected to the main board within the limited space.

[0137] 4, the first protective layer 170 may be disposed entirely on the first insulating layer 111. For example, the first protective layer 170 may be disposed to entirely cover the upper surface of the first insulating layer 111.

[0138] Furthermore, the first protective layer 170 may include an opening 175. The opening 175 of the first protective layer 170 may vertically overlap the pad of the first circuit layer 120. For example, the opening 175 of the first protective layer 170 may include a region having a width greater than the width W1 of the pad of the first circuit layer 120. In this case, the opening 175 of the first protective layer 170 of the circuit board of the first embodiment may not have a step. Therefore, the opening 175 of the first protective layer 170 in the first embodiment may have a width greater than the width W1 of the pad of the first circuit layer 120 over the entire region.

[0139] Therefore, the top surfaces of the pads of the first circuit layer 120 may not be in contact with the first protective layer 170. Preferably, the pads of the first circuit layer 120 may entirely overlap the openings 175 of the first protective layer 170 vertically.

[0140] As a result, the embodiment can improve the contact area between the pad and the connecting member disposed on the pad of the first circuit layer 120. That is, in the comparative example, the width of the opening is smaller than the width of the pad, and therefore the contact area between the pad and the connecting member is smaller than the planar area of ​​the pad.

[0141] In contrast, the contact area between the pad and the connection member in the circuit board of the first embodiment is equal to or greater than the planar area of ​​the pad. Therefore, the embodiment can improve the bonding strength between the pad and the connection member. This can solve the physical and / or electrical reliability problem of the connection member being separated from the pad. Therefore, the embodiment can improve the product characteristics of the circuit board. Furthermore, the embodiment can improve the bonding strength with a main board that is bonded to the circuit board.

[0142] On the other hand, the width W3 of the opening 175 in the first protective layer 170 can be in the range of 105% to 150% of the width W1 of the pad on the first circuit layer 120. The width W3 of the opening 175 in the first protective layer 170 can be in the range of 110% to 145% of the width W1 of the pad on the first circuit layer 120. The width W3 of the opening 175 in the first protective layer 170 can be in the range of 115% to 140% of the width W1 of the pad on the first circuit layer 120.

[0143] If the width W3 of the opening 175 in the first protective layer 170 is less than 105% of the width W1 of the pad on the first circuit layer 120, the synergistic effect of the contact area between the pad and the connection member may be insufficient.

[0144] Furthermore, if the width W3 of the opening 175 of the first protective layer 170 exceeds 150% of the width W1 of the pad of the first circuit layer 120, a short circuit problem may occur in which the connecting members arranged on adjacent pads are electrically connected to each other.

[0145] Preferably, the width W3 of the opening 175 of the first protective layer 170 can be determined based on the spacing W2 between the pads of the first circuit layer 120.

[0146] Referring to FIG. 5, the pads of the first circuit layer 120 may be disposed on the first insulating layer 111 .

[0147] In this case, the first circuit layer 120 may be composed of at least two metal layers, and the first through electrode 161 may include two metal layers corresponding to the first circuit layer 120.

[0148] That is, the pads of the first circuit layer 120 may include a first metal layer 120-1 and a second metal layer 120-2.

[0149] Furthermore, the first through-electrode 161 may include a third metal layer 161-1 corresponding to the first metal layer 120-1 of the first circuit layer 120 and a fourth metal layer 161-2 corresponding to the second metal layer 120-2.

[0150] In this case, the first metal layer 120-1 and the third metal layer 161-1 may essentially mean one layer, which may be divided according to their positions, and the second metal layer 120-2 and the fourth metal layer 161-2 may also essentially mean one metal layer, which may be divided according to their positions.

[0151] Alternatively, the first metal layer 120-1 may be substantially two layers, that is, the first metal layer 120-1 may be two metal layers including the same metal layer as the third metal layer 161-1 on copper foil (Cu foil).

[0152] Alternatively, the first metal layer 120-1 may be a layer of copper foil (Cu foil).

[0153] Therefore, only the first metal layer 120-1 and the second metal layer 120-2 will be described below.

[0154] The first metal layer 120-1 of the first circuit layer 120 may be a seed layer. The first metal layer 120-1 of the first circuit layer 120 may be a chemical copper plating layer. The first metal layer 120-1 of the first circuit layer 120 may be a copper foil layer. The first metal layer 120-1 of the first circuit layer 120 may include both a copper foil layer and a chemical copper plating layer.

[0155] The thickness of the first metal layer 120-1 of the first circuit layer 120 can be in the range of 1.0 μm to 3.0 μm. Preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 can be in the range of 1.2 μm to 2.8 μm. More preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 can be in the range of 1.5 μm to 2.5 μm.

[0156] If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, the first metal layer 120-1 of the first circuit layer 120 may not function as a seed layer. If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, it may be difficult to form the first metal layer 120-1 with a uniform thickness on the upper surface of the first insulating layer 110.

[0157] If the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the process time for forming the first metal layer 120-1 of the first circuit layer 120 increases, which may result in a decrease in yield. Furthermore, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching time for the first metal layer 120-1 in the process of forming the first circuit layer 120 may increase. Furthermore, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, deformation of the second metal layer 120-2 of the first circuit layer 120 may occur during etching of the first metal layer 120-1 of the first circuit layer 120. Here, the deformation of the second metal layer 120-2 of the first circuit pattern layer 120 may mean that the side portions of the second metal layer 120-2 are also etched when the first metal layer 120-1 is etched, increasing the difference between the width of the top surface and the width of the bottom surface of the second metal layer 120-2. Furthermore, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer 120-1 increases, which may increase the depth of recesses (e.g., undercuts) formed in the side portions of the first metal layer 120-1 and the second metal layer 120-2. For example, if the etching amount in the etching process of the first metal layer 120-1 increases, the difference between the width of the first metal layer 120-1 and the width of the second metal layer 120-2 may increase. If the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 becomes large, the electrical characteristics may be degraded due to increased signal transmission loss. Furthermore, if the difference between the widths of the first metal layer 120-1 and the second metal layer 120-2 becomes large, dendrites may be formed due to electromigration, which may degrade the electrical and / or physical characteristics of the first circuit layer 120.

[0158] The second metal layer 120-2 of the first circuit layer 120 may be an electroplated layer formed by electroplating using the first metal layer 120-1 as a seed layer. The second metal layer 120-2 of the first circuit layer 120 may be formed to a uniform thickness on the first metal layer 120-1. The second metal layer 120-2 of the first circuit layer 120 may include, but is not limited to, the same metal as the first metal layer 120-1 of the first circuit layer 120. As an example, the first metal layer 120-1 and the second metal layer 120-2 of the first circuit layer 120 may each include copper.

[0159] The thickness of the second metal layer 120-2 of the first circuit layer 120 can correspond to the value obtained by subtracting the thickness of the first metal layer 120-1 from the thickness range of the first circuit layer 120. The thickness range of the first circuit layer 120 has been described above, so further description will be omitted. That is, the thickness T1 of the first circuit layer 120 can be in the range of 5 μm to 30 μm. For example, the thickness T1 of the first circuit layer 120 can be in the range of 6 μm to 25 μm. For example, the thickness T1 of the first circuit layer 120 can be in the range of 7 μm to 20 μm.

[0160] Meanwhile, a first protective layer 170 may be disposed on the first insulating layer 111. The first protective layer 170 may include an opening 175 having a width greater than the width W1 of the pad of the first circuit layer 120. In this case, the first protective layer 170 may include a sidewall 175S of the opening 175 and a bottom surface 175B of the opening 175.

[0161] In this case, the sidewall 175S of the first protective layer 170 may be spaced apart from the side surface of the pad on the first circuit layer 120 by a constant distance W4. In this case, the distance between the side surface of the pad on the first circuit layer 120 and the sidewall 175S of the opening 175 in the first protective layer 170 may vary along the circumferential direction of the side surface of the pad on the first circuit layer 120. The distance W4 may refer to the distance between the farthest apart portions along the circumferential direction.

[0162] The distance W4 from the side surface of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 can be determined based on the distance W2 between the pads on the first circuit layer 120. Preferably, the distance W4 from the side surface of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 can be in the range of 5% to 45% of the distance W2 between the pads on the first circuit layer 120. For example, the distance W4 from the side surface of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 can be in the range of 8% to 40% of the distance W2 between the pads on the first circuit layer 120. For example, the distance W4 from the side surface of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 can be in the range of 10% to 35% of the distance W2 between the pads on the first circuit layer 120.

[0163] If the distance W4 from the side of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 is less than 5% of the distance W2 between the multiple pads on the first circuit layer 120, the effect of increasing the contact area between the pad and the connecting member in the embodiment may be insufficient.

[0164] Furthermore, if the distance W4 from the side of the pad on the first circuit layer 120 to the sidewall 175S of the first protective layer 170 exceeds 45% of the distance W2 between the pads on the first circuit layer 120, a short circuit problem may occur due to the connecting members arranged on adjacent pads being electrically connected to each other.

[0165] Meanwhile, the bottom surface 175B of the opening 175 in the first protective layer 170 may be located lower than the upper surface of the pad on the first circuit layer 120. Also, the bottom surface 175B of the opening 175 in the first protective layer 170 may be located higher than the lower surface of the pad on the first circuit layer 120.

[0166] As a result, with respect to the bottom surface 175B of the opening 175, a portion of the side surface of the pad on the first circuit layer 120 may be covered with the first protective layer 170, and the remaining portion may not be covered with the first protective layer 170. Preferably, the remaining portion of the side surface of the pad may horizontally overlap the opening 175 of the first protective layer 170.

[0167] Meanwhile, the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 can be determined based on the thickness T1 of the pad on the first circuit layer 120. For example, the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 can be in the range of 20% to 90% of the thickness T1 of the pad on the first circuit layer 120. For example, the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 can be in the range of 25% to 85% of the thickness T1 of the pad on the first circuit layer 120. For example, the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 can be in the range of 30% to 80% of the thickness T1 of the pad on the first circuit layer 120.

[0168] For example, if the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 is less than 20% of the thickness T1 of the pad on the first circuit layer 120, the area of ​​the side surface of the pad on the first circuit layer 120 covered by the first protective layer 170 may be reduced. This may reduce the bonding strength between the pad on the first circuit layer 120 and the first insulating layer 111. Furthermore, if the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 exceeds 90% of the thickness T1 of the pad on the first circuit layer 120, a process error in the process of forming the opening 175 may cause the upper surface of the pad on the first circuit layer 120 to be covered by the first protective layer 170, resulting in a reliability problem.

[0169] As described above, the embodiment can improve the contact area between the pad and the connecting member disposed on the pad of the first circuit layer 120. That is, in the comparative example, the width of the opening is smaller than the width of the pad, and therefore the contact area between the pad and the connecting member is smaller than the planar area of ​​the pad.

[0170] In contrast, the contact area between the pad and the connection member in the circuit board of the first embodiment is equal to or greater than the planar area of ​​the pad. Therefore, the embodiment can improve the bonding strength between the pad and the connection member. This can solve the physical and / or electrical reliability problem of the connection member being separated from the pad. Therefore, the embodiment can improve the product characteristics of the circuit board. Furthermore, the embodiment can improve the bonding strength with a main board that is bonded to the circuit board.

[0171] FIG. 6 is a diagram showing a first modified example of the circuit board of FIG. 5, and FIG. 7 is a diagram showing a second modified example of the circuit board of FIG.

[0172] Referring to FIG. 6, the first protective layer 170 may include an opening 175, including a sidewall 175S and a bottom surface 175B of the opening 175.

[0173] The first protective layer 170 may include a recess 175U formed between the sidewall 175S and the bottom surface 175B. The recess 175U may be recessed toward the inside of the first protective layer 170 between the sidewall 175S and the bottom surface 175B. Furthermore, in some embodiments, the size of the recess 175U may be minimized by controlling the height of the bottom surface 175B of the first protective layer 170. That is, the vertical distance T2 from the bottom surface 175B of the opening 175 in the first protective layer 170 to the lower surface of the first protective layer 170 may be in the range of 20% to 90%, 25% to 85%, or 30% to 80% of the thickness T1 of the pad of the first circuit layer 120. This minimizes the horizontal distance from the sidewall 175S of the first protective layer 170 to the innermost surface of the recess 175U.

[0174] Meanwhile, referring to FIG. 7 , in the embodiment, an opening 175 may be formed in the first protective layer 170 through a thickness-thinning removal process. As an example, the thickness-thinning removal process may be referred to as a thinning process. Furthermore, since the opening 175 in the first protective layer 170 is formed through a thickness-thinning removal process, the embodiment allows for easy adjustment of the height of the bottom surface 175B of the opening 175. For example, in the past, an opening was formed through an exposure and development process, and it was therefore impossible to adjust the height of the bottom surface of the opening formed thereby. In contrast, in the embodiment, the opening 175 is formed through a thickness-thinning removal process, allowing for easy adjustment of the height of the bottom surface 175B.

[0175] Therefore, the sidewall of the opening 175 of the first protective layer 170 may have a slope. For example, the first protective layer 170 may include an inclined wall 175IS having a certain slope angle, which is provided between the sidewall 175S and the bottom surface 175B of the opening 175. In this case, the inclined wall 175IS may be closer to the pad of the first circuit layer 120 as it extends from the sidewall 175S toward the bottom surface 175B. Therefore, the embodiment may improve the flowability of the connecting member in the process of arranging the connecting member, thereby improving the bonding strength between the pad and the connecting member.

[0176] FIG. 8 is a cross-sectional view showing a circuit board according to the second embodiment, and FIG. 9 is an enlarged view of a portion of FIG.

[0177] 8 and 9, the circuit board of the second embodiment may differ from the circuit board of Fig. 2 in that the openings provided in the first protective layer have steps. Hereinafter, descriptions of parts that are substantially the same as those of the circuit board of Fig. 2 will be omitted.

[0178] The circuit board 100A of the second embodiment may include a first protective layer 170A disposed on the first insulating layer 111 and including an opening 175A.

[0179] The opening 175A of the first protective layer 170A may have a step. In this case, the opening 175A having a step may mean that the opening 175A of the first protective layer 170A includes a region where the width of the opening 175A changes in the vertical direction.

[0180] For example, the opening 175A of the first protective layer 170A may be divided into a plurality of portions, and at least a portion of the opening 175A of the first protective layer 170A may have a width greater than the width of the pad of the first circuit layer 120.

[0181] The opening 175A of the first protective layer 170A can include a first part 175A1 and a second part 175A2.

[0182] Specifically, the opening 175A of the first protective layer 170A may include a first part 175A1 adjacent to the top surface of the first protective layer 170A. The width of the first part 175A1 of the first protective layer 170A may be greater than the width of the pad of the first circuit layer 120.

[0183] Furthermore, the opening 175A of the first protective layer 170A may include a second part 175A2 that is closer to the pad of the first circuit layer 120 than the first part 175A1. In this case, the second part 175A2 of the opening 175A of the first protective layer 170A may have a width smaller than the width of the pad of the first circuit layer 120.

[0184] Therefore, the first protective layer 170A may cover at least a portion of the upper surface of the pad of the first circuit layer 120. However, in the second embodiment, the opening 175A of the first protective layer 170A may have a step while covering a portion of the upper surface of the pad of the first circuit layer 120. Therefore, in the embodiment, the first protective layer 170A may cover a portion of the pad, thereby improving the bonding strength between the first insulating layer 111 and the pad of the first circuit layer 120. Furthermore, in the embodiment, the opening 175A of the first protective layer 170A has a step, thereby preventing the connection member disposed on the pad from overflowing. As a result, the embodiment may solve the problem of a circuit short caused by the connection members disposed on adjacent pads being electrically connected to each other.

[0185] Meanwhile, the first protective layer 170A may include a first sidewall 175A1S of a first part 175A1 of the opening 175A. The first protective layer 170A may also include a second sidewall 175A2S of a second part 175A2 of the opening 175A. The first protective layer 170A may also include a stepped portion 175A1B connecting the first sidewall 175A1S and the second sidewall 175A2S. The height of the stepped portion 175A1B may be higher than the upper surface of the pad. For example, a height T3 from the lower surface of the first protective layer 170A to the stepped portion 175A1B may be higher than the upper surface of the pad. In this case, the height T3 from the lower surface of the first protective layer 170A to the stepped portion 175A1B can be in the range of 110% to 140%, 112% to 135%, or 115% to 130% of the thickness T1 of the pad of the first circuit layer 120. The stepped portion 175A1B can also be said to be the bottom surface of the first part 175A1 of the first opening 175A.

[0186] If the height T3 from the lower surface of the first protective layer 170A to the step portion 175A1B is less than 110% of the thickness T1 of the pad of the first circuit layer 120, a problem may occur in which the upper surface of the pad of the first circuit layer 120 is not covered by the first protective layer 170A due to process errors in the process of forming the opening 175A in the first protective layer 170A.

[0187] If the height T3 from the underside of the first protective layer 170A to the step portion 175A1B exceeds 140% of the thickness T1 of the pad of the first circuit layer 120, the degree of blocking of the overflow of the connection member placed in the opening 175A can be reduced, or the total thickness of the first protective layer 170A can be increased to improve the degree of blocking.

[0188] In addition, in the embodiment, the opening in the protective layer may have a step. A connecting member, such as solder, is disposed in the opening in the protective layer. When the connecting member is disposed on a pad, a metal bonding layer may be formed between the connecting member and the pad. By forming the opening in the protective layer with a step, the length of the sidewall of the opening between the upper surface of the first protective layer and the metal bonding layer may be increased. For example, in the comparative example, the sidewall of the opening connecting the upper surface of the protective layer and the metal bonding layer (IMC) had a structure without an inflection portion. Therefore, in the comparative example, the thickness of the protective layer had to be increased to increase the distance of the inner wall of the opening between the upper surface of the protective layer and the metal bonding layer (IMC).

[0189] In contrast, in an embodiment, by forming a step in the opening, the length of the sidewall of the opening between the metal bonding layer IMC and the upper surface of the first protective layer can be increased without increasing the thickness of the first protective layer, thereby improving the physical reliability of the metal bonding layer IMC.

[0190] FIG. 10 is an enlarged view of a partial area of ​​the circuit board according to the third embodiment.

[0191] 10, the circuit board of the third embodiment may differ from the circuit board of FIG 2 in that the openings formed in the first protective layer have steps. Hereinafter, descriptions of parts that are substantially the same as those of the circuit board of FIG 2 will be omitted.

[0192] The circuit board 100A of the third embodiment may include a first protective layer 170B disposed on the first insulating layer 111 and including an opening 175B.

[0193] The opening 175B of the first protective layer 170B may have a step. In this case, the opening 175B having a step may mean that the opening 175B of the first protective layer 170B includes a region where the width thereof changes in the vertical direction.

[0194] For example, the opening 175B of the first protective layer 170B may be divided into a plurality of parts, and at least some of the openings 175B of the first protective layer 170B may have a width greater than the width of the pads of the first circuit layer 120.

[0195] The opening 175B of the first protective layer 170B can include a first part 175B1 and a second part 175B2.

[0196] Specifically, the opening 175B of the first protective layer 170B may include a first part 175B1 adjacent to the top surface of the first protective layer 170B. The width of the first part 175B1 of the first protective layer 170B may be greater than the width of the pad of the first circuit layer 120.

[0197] Furthermore, the opening 175B of the first protective layer 170B may include a second part 175B2 that is closer to the pad of the first circuit layer 120 than the first part 175B1. In this case, the second part 175B2 of the opening 175B of the first protective layer 170B may have a width greater than the width of the pad of the first circuit layer 120.

[0198] Therefore, the first protective layer 170B can leave the top surface of the pads of the first circuit layer 120 entirely open.

[0199] Meanwhile, the first protective layer 170B may include a first sidewall 175B1S of a first part 175B1 of the opening 175B. The first protective layer 170B may also include a second sidewall 175B2S of a second part 175B2 of the opening 175B. The first protective layer 170B may also include a first bottom surface 175B1B of the first part 175B1 of the opening 175B connected to the first sidewall 175B1S. The first bottom surface 175B1B may be located higher than the top surfaces of the pads of the first circuit layer 120.

[0200] The first protective layer 170B may also include a second bottom surface 175B2B of the second part 175B2 of the opening 175B connected to the second sidewall 175B2S. The second bottom surface 175B2B may be positioned lower than the upper surfaces of the pads of the first circuit layer 120 and higher than the lower surfaces of the pads.

[0201] FIG. 11 is an enlarged view of a partial area of ​​the circuit board according to the fourth embodiment.

[0202] 11, the circuit board of the fourth embodiment may differ from the circuit board of FIG 2 in that the openings formed in the first protective layer have steps. Hereinafter, descriptions of parts that are substantially the same as those of the circuit board of FIG 2 will be omitted.

[0203] The circuit board 100A of the fourth embodiment may include a first protective layer 170C disposed on the first insulating layer 111 and including an opening 175C.

[0204] The opening 175C of the first protective layer 170C may have a step. In this case, the opening 175C having a step may mean that the opening 175C of the first protective layer 170C includes a region where the width of the opening 175C changes in the vertical direction.

[0205] For example, the opening 175C of the first protective layer 170C may be divided into a plurality of parts, and at least a portion of the opening 175C of the first protective layer 170C may have a width greater than the width of the pad of the first circuit layer 120.

[0206] In this case, the first protective layer 170C may be composed of multiple layers. For example, the first protective layer 170C may include a first layer 170C1 and a second layer 170C2. The opening 175C may be provided with a step in the first layer 170C1 and the second layer 170C2 of the first protective layer 170C.

[0207] The opening 175C of the first protective layer 170C can include a first part 175C1 and a second part 175C2.

[0208] Specifically, the opening 175C of the first protective layer 170C may include a first part 175C1 adjacent to the upper surface of the first protective layer 170C. Specifically, the opening 175C of the first protective layer 170C may include a first part 175C1 provided in a second layer 170C2 of the first protective layer 170C.

[0209] The width of the first part 175C1 of the first protective layer 170C may be larger than the width of the pads of the first circuit layer 120.

[0210] In addition, the opening 175C of the first protective layer 170C may include a second part 175C2 provided in the first layer 170C1. In this case, the second part 175C2 of the opening 175C provided in the first layer 170C1 of the first protective layer 170C may have a width greater than the width of the pad of the first circuit layer 120.

[0211] FIG. 12a is a cross-sectional view showing a circuit board according to a fifth embodiment, FIG. 12b is a cross-sectional view showing a circuit board according to a sixth embodiment, and FIG. 12c is a cross-sectional view showing a circuit board according to a seventh embodiment.

[0212] Referring to FIG. 12a, the circuit board 100A of the fifth embodiment may have a difference in the openings provided in the second protective layer compared to the circuit board of FIG.

[0213] For example, the opening 185 provided in the second protective layer 180 in the first embodiment has a width smaller than the width of the second circuit layer 130. That is, the opening 185 provided in the second protective layer 180 in the first embodiment is of an SMD type.

[0214] The circuit board 100 A of the fifth embodiment may have a shape corresponding to the opening 175 A provided in the first protective layer 170 .

[0215] Specifically, the circuit board 100A may include a second protective layer 180A. The second protective layer 180A may include an opening 185A. The opening 185A may have a width greater than the width of the pad of the second circuit layer 130.

[0216] In this case, the opening 185A in the second protective layer 180A has a width greater than the pads of the second circuit layer 130 and can cover at least a portion of the side surface of the second circuit layer 130. For example, the second protective layer 180A can be in direct contact with at least a portion of the side surface of the second circuit layer 130. The second protective layer 180A can include the opening 185A without contacting the remaining portion of the side surface of the second circuit layer 130. The opening 185A can overlap the bottom surface of the second circuit layer 130 vertically while overlapping the remaining portion of the side surface of the second circuit layer 130 horizontally.

[0217] Referring to FIG. 12b, the protective layer of the sixth embodiment may have a structure in which a plurality of openings of different types are mixed.

[0218] For example, the circuit board 100B of the sixth embodiment may include a first protective layer 170B. The first protective layer 170B may include an opening. In this case, the opening of the first protective layer 170B may include a plurality of openings of different types.

[0219] For example, the first protective layer 170B may include a first opening 175B1 and a second opening 175B2. The first opening 175B1 may correspond to the opening 175 described in the first embodiment. The second opening 175B2 may have a different type from the first opening 175B1. For example, the second opening 175B2 may have a width smaller than the width of the pad of the first circuit layer 120. That is, the second opening 175B2 may have an SMD type.

[0220] In this case, the openings of the first protective layer 170B may have a structure in which different types of first openings 175B1 and second openings 175B2 are mixed.

[0221] The first opening 175B1 and the second opening 175B2 may be provided at different positions in the circuit board. Preferably, the first opening 175B1 may be provided in an inner region of the first protective layer 170B, and the second opening 175B2 may be provided in an outer region adjacent to a side surface of the first protective layer 170B.

[0222] That is, in the embodiment, the second opening 175B2 is provided in an outer region or edge region adjacent to the side surface of the first protective layer 170B, and the first opening 175B1 is provided in the inner region. Through this, the embodiment can solve the problem of warpage occurring at the outside of the circuit board. For example, in the embodiment, the width of the second opening 175B2 provided in the outer region of the first protective layer 170B is smaller than the width of the first opening 175B1 provided in the inner region. As a result, the area of ​​the first protective layer 170B in the outer region may be larger than the area of ​​the inner region. Through this, the embodiment can solve the problem of warpage occurring in the circuit board.

[0223] For example, depending on the direction of warpage occurring in the circuit board, the second opening 175B2 may be provided in an SMD type. For example, if the circuit board warps in a first vertical direction, the second opening 175B2 may have an SMD type.

[0224] Furthermore, the second protective layer 180B may also include a first opening 185B1 and a second opening 185B2. The first opening 185B1 of the second protective layer 180B may be of a type corresponding to the first opening 175B1 of the first protective layer 170B. Furthermore, the second opening 185B2 of the second protective layer 180B may be of a type corresponding to the second opening 175B2 of the first protective layer 170B.

[0225] 12c, the circuit board 100C of the seventh embodiment may include a first protective layer 170C. The first protective layer 170C may include an opening. In this case, the opening of the first protective layer 170C may include a plurality of openings of different types.

[0226] For example, the first protective layer 170C may include a first opening 175C1 and a second opening 175C2. The first opening 175C1 may correspond to the opening 175 described in the first embodiment. The second opening 175C2 may have a different type from the first opening 175C1. For example, the second opening 175C2 may have a width greater than the width of the pad of the first circuit layer 120. The second opening 175C2 may not contact the pad of the first circuit layer 120. That is, the second opening 175C2 may have an NSMD type.

[0227] In this case, the openings of the first protective layer 170C may have a structure in which different types of first openings 175C1 and second openings 175C2 are mixed.

[0228] That is, depending on the direction of warpage occurring in the circuit board, the second opening 175C2 can be provided as an NSMD type.

[0229] For example, if the circuit board warps in a second vertical direction opposite to the first vertical direction, the second opening 175C2 provided in the first protective layer 170C may have an NSMD type instead of an SMD type.

[0230] Furthermore, the second protective layer 180C may also include a first opening 185C1 and a second opening 185C2. The first opening 185C1 of the second protective layer 180C may be of a type corresponding to the first opening 175C1 of the first protective layer 170C. Furthermore, the second opening 185C2 of the second protective layer 180C may be of a type corresponding to the second opening 175C2 of the first protective layer 170C.

[0231] Meanwhile, the openings provided in the first protective layer may further include an SMD-type opening and an NSMD-type opening in addition to the openings in Fig. 2. For example, the first protective layer may further include a second opening 175C2 in Fig. 12c in addition to the first opening 175B1 and second opening 175B2 shown in Fig. 12b.

[0232] The openings provided in the second protective layer may further include a second opening 185C2 shown in FIG. 12c in addition to the first opening 185B1 and the second opening 185B2 shown in FIG. 12b.

[0233] Meanwhile, the first and second protective layers of the embodiments may have openings according to different combinations of the above-mentioned embodiments. For example, the first protective layer may include the opening of the circuit board of the first embodiment, and the second protective layer may include the opening of the fifth embodiment.

[0234] A semiconductor package according to an embodiment will be described below.

[0235] FIG. 13 is a diagram showing a semiconductor package according to a first embodiment, FIG. 14a is a diagram showing a semiconductor package according to a second embodiment, FIG. 14b is a diagram showing a semiconductor package according to a third embodiment, and FIG. 14c is a diagram showing a semiconductor package according to a fourth embodiment.

[0236] 13, the semiconductor package includes the circuit board 100 of FIG. 2. The semiconductor package of the first embodiment may have a structure in which a plurality of chips and a first external substrate are combined on the circuit board 100. In this case, the plurality of chips in the semiconductor package of the first embodiment may be mounted only on the lower part of the circuit board 100.

[0237] Alternatively, referring to FIGS. 14a to 14c, the semiconductor package may have a structure in which a chip is further mounted on the circuit board.

[0238] 13 and 14a, the semiconductor package may include a first connection portion 310 disposed on a pad of a first circuit layer 120. The first connection portion 310 may have a hexahedral shape. For example, the cross section of the first connection portion 310 may be quadrangular. The cross section of the first connection portion 310 may be rectangular or square. For example, the first connection portion 310 may be spherical. For example, the cross section of the first connection portion 310 may be circular or semicircular. For example, the cross section of the first connection portion 310 may be partially or entirely rounded. The cross-sectional shape of the first connection portion 310 may be flat on one side and curved on the other side. The first connection portion 310 may be, but is not limited to, a solder ball.

[0239] The semiconductor package may include a first chip 320 disposed on the first connection portion 310. The first chip 320 may include terminals 325. The terminals 325 of the first chip 320 may be electrically coupled to pads of the first circuit layer 120 via the first connection portion 310.

[0240] The semiconductor package may include a second connection portion 330 disposed below the first group of pads on the second circuit layer 130. A second chip 340 may be mounted on the second connection portion 330. The second chip 340 may include terminals 345. The terminals 345 of the second chip 340 may be electrically connected to the first group of pads via the second connection portion 330.

[0241] The semiconductor package may include a third connection portion 350 disposed under the second group of pads on the second circuit layer 130. A third chip 360 may be mounted on the third connection portion 350. The third chip 360 may include terminals 365. The terminals 365 of the third chip 360 may be electrically connected to the second group of pads via the third connection portion 350.

[0242] The semiconductor package may include a fourth connection portion 370 disposed under the third group of pads on the second circuit layer 130. A fourth chip 380 may be mounted on the fourth connection portion 370. The fourth chip 380 may include terminals 385. The terminals 385 of the fourth chip 380 may be electrically connected to the third group of pads via the fourth connection portion 370.

[0243] At least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a logic chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an application processor chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an analog-to-digital converter or an application-specific integrated circuit (ASIC). For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc. At least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include at least one of a drive IC chip, a diode chip, a power IC chip, a touch sensor IC chip, a multilayer ceramic condenser (MLCC) chip, a ball grid array (BGA) chip, and a chip capacitor. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may be an active element, and at least one of the others may be a passive element.

[0244] The semiconductor package may also include a connection member 210. The connection member 210 may be disposed on a pad of the first circuit layer 120.

[0245] The semiconductor package may include a first external substrate 220 disposed on the connection member 210. The first external substrate 220 may be a main board. For example, the first external substrate 220 may be a motherboard of an electronic device. Electrodes 225 of the first circuit substrate 220 may be coupled to the first circuit layer 120 via the connection member 210.

[0246] The first external substrate 220 may include a third protective layer 230. The third protective layer 230 may include an opening that exposes at least a portion of the lower surface of the electrode 225 provided on the first external substrate 220.

[0247] The opening formed in the third protective layer 230 may be of an SMD type. The width W5 of the opening formed in the third protective layer 230 may be different from the width W3 of the opening formed in the first protective layer 170. Preferably, the width W5 of the opening formed in the third protective layer 230 may be larger than the width W3 of the opening formed in the first protective layer 170. For example, the width W5 of the opening formed in the third protective layer 230 may be in the range of 110% to 160%, 115% to 155%, or 120% to 150% of the width W5 of the opening formed in the first protective layer 170. As a result, the embodiment allows the connection member 210, which joins the first external substrate 220 and the circuit board, to be stably disposed between the first external substrate 220 and the circuit board. For example, the embodiment may minimize the occurrence of cracks in the connection member 210. Furthermore, the embodiment can solve the short circuit problem caused by the diffusion or spreading of the connection members 210, which may lead to the connection between the plurality of connection members 210.

[0248] That is, the semiconductor package includes a first protective layer 170, a second protective layer 180, and a third protective layer 230, each of which includes an opening. The opening provided in the first protective layer 170 may have a first type, and the openings provided in the second protective layer 180 and the third protective layer 230 may have a second type, which is an SMD type different from the first type.

[0249] The semiconductor package may include a first molding layer 390 .

[0250] The first molding layer 390 can mold the first chip 320 and the connecting member 210 .

[0251] The semiconductor package may include a second molding layer 395 .

[0252] A second molding layer 395 may be disposed on the lower surface of the second insulating layer 112. The second molding layer 395 may mold the second chip 340, the third chip 360, and the fourth chip 380.

[0253] First molding layer 390 and second molding layer 395 may be, but are not limited to, EMC (Epoxy Mold Compound).

[0254] In this case, first molding layer 390 and second molding layer 395 may have a low dielectric constant to enhance heat dissipation characteristics. For example, first molding layer 390 and second molding layer 395 may have a dielectric constant Dk of 0.2 to 10. For example, first molding layer 390 and second molding layer 395 may have a dielectric constant Dk of 0.5 to 8. For example, first molding layer 390 and second molding layer 395 may have a dielectric constant Dk of 0.8 to 5. In this embodiment, first molding layer 390 and second molding layer 395 have a low dielectric constant, so that heat generated in first to fourth chips 320, 340, 360, and 380 can be efficiently dissipated to the outside.

[0255] Referring to FIG. 14b, the semiconductor package of the third embodiment may have a different type of opening provided in the second protective layer compared to the semiconductor package of the second embodiment of FIG. 14a.

[0256] That is, the semiconductor package of the third embodiment may include a second protective layer 180 .

[0257] That is, the second protective layer 180 may include an opening that vertically overlaps the circuit layer on which the chip is mounted. In this case, the opening of the second protective layer provided in the semiconductor package of FIG. 14a is of the SMD type.

[0258] Alternatively, the second protective layer 180 provided in the semiconductor package of the third embodiment may have the same type of opening as the first protective layer 170 .

[0259] Thus, in the embodiment, in the process of forming an opening in the first protective layer 170, an opening can be formed in the second protective layer 180 corresponding to the opening. Thus, in the embodiment, the opening can be formed by simultaneously processing the first protective layer 170 and the second protective layer 180, thereby improving processability and simplifying the process.

[0260] Referring to FIG. 14c, the semiconductor package of the fourth embodiment may differ from those of FIGS. 14a and 14b in the shapes of the openings formed in the first protective layer 170 and the second protective layer 180.

[0261] For example, a plurality of openings may be provided in the first protective layer 170. The plurality of openings may include a first opening that vertically overlaps the first connecting portion 310 and a second opening that vertically overlaps the connecting member 210.

[0262] The first opening of the first protective layer 170 may entirely open the area where the first connection part 310 is disposed. For example, the first protective layer 170 may entirely open the pads of the first circuit layer 120 connected to the terminals 325 of the first chip 320. For example, the pads may be commonly opened through one first opening provided in the first protective layer 170. Therefore, the pads connected to the terminals 325 of the first chip 320 and the insulating layer areas between the pads may be commonly opened through one first opening.

[0263] Meanwhile, the second opening in the first protective layer 170 can be of the first type as described.

[0264] Additionally, the second protective layer 180 may include a plurality of openings having different shapes.

[0265] For example, the second protective layer 180 may include a first opening of a first type, a second opening of a second type, and a third opening of a third type. The second type may be an SMD type, and the third type may be an NSMD-like type in which part of the side surface of the circuit layer is covered with the second protective layer 180.

[0266] That is, in the embodiments, different types of openings in the protective layer may be applied depending on the type of chip to be mounted and / or the type of external substrate to be connected, thereby improving the design flexibility of the circuit board and the semiconductor package including the same.

[0267] FIG. 15 is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0268] Referring to FIG. 15, the semiconductor package according to the fifth embodiment may have a structure in which a second external substrate 420 is further disposed in the semiconductor package according to the second embodiment.

[0269] For this purpose, the second circuit layer 130 may include post bumps 135. The sixth connection portions 410 may be disposed on the lower surfaces of the post bumps 135.

[0270] For this purpose, the second molding layer 395 may include an open region that exposes the lower surface of the post bump 135 .

[0271] A second external substrate 420 may be coupled to the sixth connector 410. The second external substrate 420 may be a memory package. To this end, the second external substrate 420 may include a memory chip 430.

[0272] However, the embodiment is not limited thereto, and the second external substrate 420 may be an interposer disposed between the memory package and the post bumps 135 .

[0273] In this case, the second protective layer 180 of the fifth embodiment may include first and second openings of different types. For example, the second protective layer 180 may include a first opening corresponding to an area where the post bump 135 is disposed. The first opening of the second protective layer 180 may be of an SMD type. The second protective layer 180 may also include a second opening corresponding to an area where a chip is disposed. The second opening of the second protective layer 180 may be of an NSMD type or an NSMD-like type, rather than an SMD type.

[0274] -Circuit board manufacturing method-

[0275] Figures 16 to 24 are diagrams for explaining, in order of steps, a method for manufacturing the circuit board of the first embodiment shown in Figure 2. Figures 25 to 28 are diagrams for explaining, in order of steps, a method for manufacturing the circuit board of the third embodiment shown in Figure 10.

[0276] The following description will focus on the process of forming the first circuit layer 120 and the first protective layer 170 on the first insulating layer 111 in the circuit board.

[0277] Referring to FIG. 16 , in an embodiment, a first insulating layer 111 is prepared. Preferably, the step of preparing the first insulating layer 111 may refer to a step of laminating the first insulating layer 111 on the third insulating layer 113 with the third circuit layer 140 disposed on the third insulating layer 113. Next, in an embodiment, a first metal layer 120-1 may be formed on the first insulating layer 111. The first metal layer 120-1 may refer to a copper foil layer disposed on the first insulating layer 111. Alternatively, the first metal layer 120-1 may be an electroless plated layer formed by electroless plating on the first insulating layer 111. For example, the first metal layer 120-1 may be a chemical copper plated layer. Alternatively, the first metal layer 120-1 may include both a copper foil layer and a chemical copper plated layer.

[0278] 17, in an embodiment, a first mask M1 is formed on the first metal layer 120-1. The first mask M1 may include an open area OR1 that opens an area where the first circuit layer 120 is to be formed.

[0279] Next, referring to FIG. 18, in this embodiment, a second metal layer 120-2 is formed to fill the open area OR1 of the first mask M1 using the first metal layer 120-1 as a seed layer.

[0280] Next, referring to FIG. 19, an embodiment may perform a step of removing the first mask M1.

[0281] Next, referring to FIG. 20, in the embodiment, a process of removing a portion of the first metal layer 120-1 that does not vertically overlap the second metal layer 120-2 by etching may be performed.

[0282] 21, in an embodiment, a step of forming a first resist layer 170R on the first insulating layer 111 may be performed. The first resist layer 170R may refer to a layer before the opening 175 is formed in the first protective layer 170 in the embodiment.

[0283] 22, in an embodiment, a process of partially exposing the first resist layer 170R may be performed. Through this, in an embodiment, a process of partially curing the first resist layer 170R may be performed. Specifically, in an embodiment, the first resist layer 170R may include a first region 170R1 that has been cured by exposure and a second region 170R2 that is not cured.

[0284] 23, in an embodiment, a removal process may be performed to thin the uncured second region 170R2. Specifically, in an embodiment, the removal process may be performed on the uncured second region 170R2 using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline). In this case, in an embodiment, the second region 170R2 does not need to be entirely removed. Specifically, in an embodiment, the removal process may be performed to thin the second region 170R2 so that at least a portion of the second region 170R2 remains on the first insulating layer 111.

[0285] 24 , in an embodiment, when the second region 170R2 has a desired thickness after the thinning removal process, the thinning removal process may be terminated, and a process may be performed to harden the unremoved second region 170R2. Through this, in an embodiment, the first protective layer 170 having the opening 175 may be disposed on the first insulating layer 111.

[0286] On the other hand, in the embodiment, the removal step for thinning the thickness is performed multiple times, so that the first protective layer can have an opening with a step.

[0287] Specifically, referring to FIG. 25, an embodiment may perform a removal step to reduce the primary thickness and form the first part 175B1 of the opening 175B in the second region 170R2.

[0288] 26, the embodiment may then perform a process of partially exposing and curing the second region 170R2, whereby the second region 170R2 may include an exposed and cured 2-1 region 170R21 and an uncured 2-2 region 170R22.

[0289] Next, referring to FIG. 27, in this embodiment, a removal process for reducing the secondary thickness of the 2-2 region 170R22 may be performed to form a second part 175B2 connected to the first part 175B1.

[0290] 28, in an embodiment, when the second-2 region 170R22 has been removed to a desired thickness, a process of hardening the second-2 region 170R22 may be performed. Through this, in an embodiment, the first protective layer 170B having the stepped opening 175B may be disposed on the first insulating layer 111.

[0291] Meanwhile, when a circuit board having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention functions as a semiconductor package, it can safely protect the semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when it functions as a signal transmission device, it can solve noise problems. As a result, the circuit board having the above-described inventive features can maintain stable functionality in IT devices and home appliances, and the entire product and the circuit board to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0292] When a circuit board having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board to which the present invention is applied can be functionally integrated or technically linked with each other.

[0293] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0294] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a first pad disposed on an upper surface of the insulating layer; a first protective layer disposed on the upper surface of the insulating layer and having an opening vertically overlapping the first pad; the opening in the first protective layer includes a region having a horizontal width greater than a horizontal width of the first pad; The first protective layer is provided to cover at least a portion of a side surface of the first pad.

2. a second pad disposed on the lower surface of the insulating layer; The circuit board of claim 1 , further comprising: a second protective layer disposed on the lower surface of the insulating layer and including an opening that vertically overlaps the second pad.

3. The first pad is provided in plurality, 2. The circuit board according to claim 1, wherein the spacing between the first pads is in the range of 20% to 90% of the width of each of the first pads.

4. 4. The circuit board according to claim 1, wherein the width of the region of the opening in the first protective layer is in the range of 105% to 150% of the width of the first pad.

5. The first protective layer is a sidewall that defines the opening and a bottom surface of the opening that is connected to the sidewall; The circuit board according to claim 3 , wherein the bottom surface is positioned lower than an upper surface of the first pad and higher than a lower surface of the first pad.

6. The first protective layer is The circuit board according to claim 5 , further comprising a recess provided between the sidewall and the bottom surface, the recessed recess being recessed toward an inner side of the first protective layer away from the first pad.

7. The first protective layer is The circuit board of claim 5 , further comprising an inclined wall provided between the side wall and the bottom surface, the inclined wall inclining from the side wall toward the bottom surface toward an outer surface of the first pad.

8. 6. The circuit board according to claim 5, wherein the vertical distance from the lower surface of the first protective layer to the bottom surface is in the range of 20% to 90% of the thickness of the first pad.

9. The horizontal separation distance from the outer surface of the first pad to the sidewall of the opening in the first protective layer is:

6. The circuit board according to claim 5, wherein the first pads are spaced apart from each other by 5% to 45% of the spacing between the first pads.

10. The circuit board according to claim 1 , wherein the opening in the first protective layer has a step whose width changes along the vertical direction.

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