Stacked FET standard cell architecture

Abstract

A cell layout for implementing stacked transistors is disclosed. The cell layout utilizes both topside metal routing and bottomside metal routing. Various connection routes can be formed between the transistor components (e.g., gate, source, and drain) and either the topside metal routing or the bottomside metal routing. The specific connection routes can be determined based on the desired device structure. Thus, the disclosed cell layout allows various devices to be built based on the basic cell structure.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The embodiments described herein relate to power and signal routing for semiconductor devices. More particularly, the embodiments described herein relate to power and signal routing through both top and bottom layers for integrated circuit cells having multiple transistors. [Background technology]

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logic functions, memory functions, etc. The current trend in standard cell methodology is to reduce the size of the standard cell while increasing the complexity within the standard cell (e.g., circuit density and number of components or transistors). However, as standard cell designs become smaller, it becomes more difficult to provide access (e.g., connections) to the components within the standard cell within the design / manufacturing constraints of the standard cell. Summary of the Invention

[0003] The features and advantages of the method and apparatus of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred, but nevertheless exemplary, embodiments in accordance with the embodiments described in this disclosure, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a top plan view of a standard cell according to some embodiments.

[0005] [Figure 2] 1 illustrates a backside plan view of a standard cell according to some embodiments.

[0006] [Figure 3] 3 shows a cross-sectional view of the standard cell taken along line 3-3 shown in FIG.

[0007] [Figure 4] 4 shows a cross-sectional view of the standard cell taken along line 4-4 shown in FIG. 2.

[0008] [Figure 5] 5 shows a cross-sectional view of a standard cell taken along line 5-5 shown in both FIG. 1 and FIG.

[0009] [Figure 6] 6 shows a cross-sectional view of a standard cell taken along line 6-6 shown in both FIG. 1 and FIG.

[0010] [Figure 7] 1 illustrates a top plan view of a cell with alternate vias along its boundary, according to some embodiments.

[0011] [Figure 8] 1 is a cross-sectional view of a cell showing connections to a source region according to some embodiments.

[0012] [Figure 9] 1 is a cross-sectional view of a cell showing connections to a drain region according to some embodiments.

[0013] [Figure 10] 10A-10C illustrate cross-sectional views of stacked transistor control signal connections within a cell implementing via pillars according to some embodiments.

[0014] [Figure 11] 1 illustrates a cross-sectional view of stacked transistor control signal connections in a common gate configuration according to some embodiments.

[0015] [Figure 12] 1 illustrates a cross-sectional view of stacked transistor control signal connections in a cross-coupled gate configuration according to some embodiments.

[0016] [Figure 13] 1 illustrates a top plan view of a NAND cell, according to some embodiments.

[0017] [Figure 14] 1 illustrates a backside plan view of a NAND cell, according to some embodiments.

[0018] [Figure 15] 15 shows a cross-sectional view of a NAND cell taken along line AA' shown in FIGS. 13 and 14. FIG.

[0019] [Figure 16] 15 shows a cross-sectional view of the NAND cell taken along line BB' shown in FIGS. 13 and 14. FIG.

[0020] [Figure 17] 15 shows a cross-sectional view of the NAND cell taken along line CC' shown in FIGS. 13 and 14. FIG.

[0021] [Figure 18] 15 shows a cross-sectional view of a NAND cell taken along line DD' shown in FIGS. 13 and 14. FIG.

[0022] [Figure 19] 1 shows a schematic diagram of a memory cell.

[0023] [Figure 20] 1 illustrates a top plan view of a memory cell having stacked transistors according to some embodiments.

[0024] [Figure 21] 1 illustrates a backside plan view of a memory cell having stacked transistors according to some embodiments.

[0025] [Figure 22] 20 and 21 show cross-sectional views of the memory cell taken along line AA'.

[0026] [Figure 23] 20 and 21 show cross-sectional views of the memory cell taken along line BB'.

[0027] [Figure 24] 20 and 21 show cross-sectional views of the memory cell taken along line CC'.

[0028] [Figure 25] 1 illustrates an exemplary block diagram of a memory device according to some embodiments.

[0029] [Figure 26] 1 illustrates a top plan view of an area having dummy cells according to some embodiments.

[0030] [Figure 27] 1 illustrates a backside plan view of an area having dummy cells according to some embodiments.

[0031] [Figure 28] 26 and 27 show cross-sectional views of the area having dummy cells taken along line AA' shown in both FIG.

[0032] [Figure 29] 26 and 27 show cross-sectional views of the area having dummy cells taken along line BB' shown in both FIG.

[0033] [Figure 30] 1 illustrates a top plan view of an area having dummy cells according to some embodiments.

[0034] [Figure 31] 1 illustrates a backside plan view of an area having dummy cells according to some embodiments.

[0035] [Figure 32] 30 and 31 show cross-sectional views of the area having dummy cells taken along line AA' shown in both FIG.

[0036] [Figure 33] 30 and 31 show cross-sectional views of the area having dummy cells taken along line BB' shown in both FIG.

[0037] [Figure 34] 1 shows a schematic diagram of a column I / O cell according to some embodiments.

[0038] [Figure 35] 1 illustrates a layout of a column I / O cell, according to some embodiments.

[0039] [Figure 36] 1 illustrates a perspective view of a contemplated vertical transistor device according to some embodiments.

[0040] [Figure 37] 1 illustrates a perspective view of another contemplated vertical transistor device, according to some embodiments.

[0041] [Figure 38] 1 illustrates a perspective view of an inverter cell structure according to some embodiments.

[0042] [Figure 39] 1 illustrates a top plan view of an inverter cell structure according to some embodiments.

[0043] [Figure 40] 1 illustrates a backside plan view of an inverter cell structure according to some embodiments.

[0044] [Figure 41] 41 illustrates a cross-sectional view of an inverter cell structure taken along line 41-41 shown in FIG. 39, according to some embodiments.

[0045] [Figure 42] 42 illustrates a cross-sectional view of an inverter cell structure taken along line 42-42 shown in FIG. 39, according to some embodiments.

[0046] [Figure 43] 1 illustrates a perspective view of a NAND cell structure, according to some embodiments.

[0047] [Figure 44] 1 illustrates a top plan view of a NAND cell structure, according to some embodiments.

[0048] [Figure 45] 1 illustrates a backside plan view of a NAND cell structure, according to some embodiments.

[0049] [Figure 46] 46 illustrates a cross-sectional view of a NAND cell structure taken along line 46-46 shown in FIG. 44, according to some embodiments.

[0050] [Figure 47] 47-47 shown in FIG. 44, in accordance with some embodiments.

[0051] [Figure 48] 1 illustrates a perspective view of a MUX cell structure, according to some embodiments.

[0052] [Figure 49] 1 illustrates a top plan view of a MUX cell structure according to some embodiments.

[0053] [Figure 50] 1 illustrates a backside plan view of a MUX cell structure according to some embodiments.

[0054] [Figure 51] 51 illustrates a cross-sectional view of a MUX cell structure taken along line 51-51 shown in FIG. 49, according to some embodiments.

[0055] [Figure 52] 52 illustrates a cross-sectional view of a MUX cell structure taken along line 52-52 shown in FIG. 49, according to some embodiments.

[0056] [Figure 53] 1 shows a perspective view of a device according to some embodiments.

[0057] [Figure 54] 54 shows a cross-sectional view of a device taken along line 54-54 shown in FIG. 53, according to some embodiments.

[0058] [Figure 55] FIG. 1 is a block diagram of one embodiment of an exemplary system. DETAILED DESCRIPTION OF THE INVENTION

[0059] While the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, the present application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure, as defined by the appended claims.

[0060] As used herein, the term "standard cell" refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. For example, an individual standard cell may be one cell in a library of cells from which various appropriate cells may be selected to implement a particular cell design. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. Embodiments of the circuit design cells described herein may be implemented in various implementations of logic or memory integrated circuits.

[0061] Many current designs of cells provide connections and routing for power or signals to transistors or other structures in the area above the transistors. For example, connections and routing for power or signals may be provided on an upper layer of the device. As used herein, the term "upper side" refers to an area in the device that is vertically above the active layer of the device (e.g., above the transistor region of the device when viewed in a typical cross-sectional view). For example, upper side may refer to components such as contacts or layers that are vertically above the transistor region, as shown in the figures and described herein. In some cases, the term "front side" may be used interchangeably with the term "upper side."

[0062] Some recent developments for standard cell design have moved the connections and routing for power connections to metal layers below the transistors. For example, the connections and routing for power may be provided in the backside layer of the device. As used herein, the term "backside" refers to the area within a device that is vertically below the active layer of the device (e.g., below the transistor region of the device when viewed in a typical cross-sectional view). For example, the backside may refer to components such as contacts or layers that are vertically below the transistor region, as shown in the figures and described herein. Note that, as used herein, backside elements located below the active layer may be above, within, or below the silicon substrate on which the active layer is fabricated. That is, as used herein, "backside" refers to the active layer rather than the silicon substrate.

[0063] The present disclosure is directed to various implementations of stacked or vertical transistors within integrated circuit cells (e.g., standard cells) that utilize connections to both top and bottom metal layers. The inventors have recognized that the top and bottom layers can be utilized in particular ways to provide technical and space-saving advantages to cell layouts that implement stacked or vertical transistors. The disclosed embodiments implement top and bottom metal layers to provide advantageous cell layouts and routing (e.g., paths) for control or power signals within the cell layout. Stacked transistor standard cell design

[0064] Stacked transistors (e.g., two transistor active areas stacked vertically above a substrate) can offer various technical and space-saving advantages due to the proximity of devices within the transistor. However, implementing stacked transistors in standard cells is difficult due to design and manufacturing constraints associated with standard cell structures. For example, standard cells that utilize only topside routing typically do not have sufficient paths to route to both transistors without expanding the size of the standard cell. Standard cells that are limited to topside routing for control signals and backside routing for power signals may also lack the necessary routing and connection availability for two stacked transistors without changing the size of the standard cell.

[0065] The present disclosure contemplates various techniques for implementing routing in both top and bottom metal layers that allow two stacked transistors to be placed within a standard cell. Various embodiments of standard cell configurations are disclosed that provide basic building blocks for many different types of devices, from simple devices (e.g., inverters and NAND devices) to more complex devices (e.g., complex FETs). The disclosed embodiments provide a compact standard cell structure that allows stacked transistors to be implemented in a variety of circuit logic schemes.

[0066] Certain embodiments disclosed herein have four broad elements: 1) a first metal layer (e.g., a top metal layer) located above a transistor region of an integrated circuit cell structure, 2) a second metal layer (e.g., a back metal layer) located below the transistor region, 3) a pair of vertically stacked transistors within the transistor region, and 4) various possible connection paths for both control and power signals between either the first or second metal layer and the first and second transistors. In certain embodiments, the pair of vertically stacked transistors comprises heterogeneous transistors (e.g., complementary transistor types such as PMOS and NMOS transistors). In some embodiments, the pair of vertically stacked transistors comprises homogeneous transistors (e.g., the transistors are the same type).

[0067] In various embodiments, control signal and power signal connections are made to implement logic associated with a particular integrated circuit device having multiple transistors for the standard cell configuration described herein. For example, examples of inverter devices or NAND gate devices that may be implemented based on the standard cell configuration are described below. Various possible connection embodiments for control signal and voltage signals to stacked transistors within the standard cell configuration are also described. Those skilled in the art will appreciate that combinations of these various possible connections can be implemented based on stacked transistor structures within the standard cell configuration to generate many different desired circuits.

[0068] In summary, the inventors have recognized that providing various routing paths within a standard cell structure enables the implementation of connections to both top and bottom metal layers for control and power signals from stacked transistors disposed within the standard cell structure. The routing paths described herein enable the standard cell configuration to be utilized in creating a variety of both simple and complex integrated circuit logic devices based on stacked transistors within the cell. Additionally, the standard cell structure with stacked transistors described herein provides a scalable template that can be implemented into devices having multiple integrated circuit cells. The standard cell structure with stacked transistors of the present disclosure further enables the construction of cells that can be implemented within current manufacturing constraints and without modifying the size or parameters of current standard cells. As used herein, the term "routing" refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments may be contemplated in which the metal in "routing" is replaced with an alternative conductive material. For example, the metal in "routing" may be replaced with a superconducting material, a semiconductor material, or a non-metallic conductor.

[0069] 1-6 show diagrams of a standard cell having stacked transistors and both top-layer and bottom-layer connections, according to some embodiments. FIG. 1 shows a top plan view of standard cell 100, according to some embodiments. FIG. 2 shows a backside plan view of standard cell 100, according to some embodiments. FIG. 3 shows a cross-sectional view of standard cell 100 along line 3-3 shown in FIG. 1. FIG. 4 shows a cross-sectional view of standard cell 100 along line 4-4 shown in FIG. 2. FIG. 5 shows a cross-sectional view of standard cell 100 along line 5-5 shown in both FIGS. 1 and 2. FIG. 6 shows a cross-sectional view of standard cell 100 along line 6-6 shown in both FIGS. 1 and 2.

[0070] For ease of illustration, the representations of cells disclosed herein show only components relevant to the present disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein. For example, in FIG. 1 , various connections (such as vias or contacts described herein) may be visible in some depictions. Additionally, some transparency of materials is provided to allow visibility of underlying components in top and back plan views for better understanding of the disclosed embodiments. For example, in FIGS. 1 and 2 , substrate 102 has some transparency to provide visibility of the underlying transistor gates and active regions, and top metal layer 112 and back metal layer 120 have some transparency to provide visibility of contact 114 and back via 122, respectively.

[0071] In various embodiments, as shown in Figures 1-6, standard cell 100 includes a substrate 102. In particular embodiments, substrate 102 is a silicon substrate, although other semiconductor substrates are contemplated. Substrate 102 may include additional components or features for implementation within cell 100. For example, substrate 102 may include one or more insulating layers (e.g., oxide layers), diffusion (e.g., oxide diffusion) regions, or doped regions for implementation within cell 100. For simplicity of illustration, substrate 102 is depicted as a material that fills the volume of standard cell 100.

[0072] In various embodiments, a first active region 104 and a second active region 106 are formed in the substrate 102. In particular embodiments, the active region 104 is disposed vertically above the active region 106 within the cell 100. For example, the active region 104 may be disposed at the top of the cell 100, and the active region 106 may be disposed at the bottom of the cell. It should be noted that the active regions 104 and 106 are not necessarily disposed directly above / below each other. For example, a portion of the active region 104 or the active region 106 may be outside the boundary of the other active region. Thus, when describing the active region 104 as being above the active region 106, it may refer to at least some portion of the active region 104 being above at least some portion of the active region 106, or vice versa.

[0073] In particular embodiments, active area 104 is the active area of ​​a first transistor in cell 100, and active area 106 is the active area of ​​a second transistor in the cell. For example, in one contemplated embodiment, active area 104 is the active area of ​​an NMOS transistor having one or more NMOS gates, and active area 106 is the active area of ​​a PMOS transistor having one or more PMOS gates. Alternatively, active area 104 may be the active area of ​​a PMOS transistor, while active area 106 is the active area of ​​an NMOS transistor. While transistor stacks having these complementary transistor types (e.g., heterogeneous transistors) are described with reference to FIGS. 1-6 , it should be understood that additional embodiments may be contemplated in which both transistors are the same type (e.g., homogeneous transistors). Additionally, while the disclosed embodiments describe silicon-based transistors, such as NMOS and PMOS transistors, other types of semiconductor-based transistors may be contemplated without departing from the scope of the present disclosure. Still further, any type of transistor structure may be contemplated. For example, the transistors formed may include, but are not limited to, transistors such as FinFETs, nanosheet FETs (NSHs), or GAAFETs ("gate-all-around" FETs).

[0074] In various embodiments, a transistor having active region 104 includes an upper gate 108 and source / drain regions 124, while a transistor having active region 106 includes a lower gate 116 and source / drain regions 124. The transistor may be disposed between insulated gates 110, as shown in FIGS. 1-4. Cell 100 may also include contacts 126 that provide connections for source / drain regions 124. Cell 100 includes two upper gates 108A-B, two lower gates 116A-B, six source / drain regions 124A-F (three source / drain regions 124A-C in the upper transistor and three source / drain regions 124D-F in the lower transistor), and six contacts 126A-F disposed between insulated gates 110 within cell 100, as shown in FIGS. 1-6. However, the embodiment of cell 100 shown in FIGS. 1-6 is one example of a possible configuration of transistor components within a cell. For example, it should be understood that cell 100 may include any number of transistor components that fit within the boundaries of the cell in accordance with the design and manufacturing constraints of the cell (e.g., standard cell design and manufacturing constraints) without departing from the scope of the present disclosure.

[0075] The top gate 108 and the bottom gate 116 may be, for example, poly lines (e.g., polysilicon layers) or high-k / metal gates. In certain embodiments, the top gate 108 and the bottom gate 116 include gate spacers (not shown for simplicity of the drawings). For example, the gate spacers may be disposed between the gates 108 / 116 and the source / drain regions 124. In various embodiments, the gate spacers are formed as part of the gates 108 / 116 (e.g., the gates and spacers are formed in the same process flow). The source / drain regions 124 may be, for example, epitaxial layers grown on a fin or nanosheet stack or any 2D (two-dimensional) channel material. Various embodiments may also be contemplated in which the source / drain regions 124 are at least partially disposed within the substrate 102.

[0076] In addition to the transistor components described above, various connections to the gate and / or source / drain regions may be made within cell 100. The connections may include, for example, contacts or vias that provide a connection between the transistor components within cell 100 and the top metal layer 112 or the backside metal layer 120. Contact 114 (shown in FIGS. 1, 3, and 5) is an example of a gate contact that provides a connection between top gate 108A and top metal layer 112B. Backside via 122 (shown in FIGS. 2, 4, and 6) is an example of a via that provides a connection between source / drain region 124F and backside metal layer 120B.

[0077] In various embodiments, contacts 114 are top vias that provide connections from various portions of the transistor (e.g., source / drain regions, gates, etc.) to the top metal layer 112, while backside vias 122 provide connections from various portions of the transistor to the backside metal layer. Contacts 114 and backside vias 122 are provided as non-limiting examples of possible connections in cell 100. For example, any number or combination of contacts or vias (along with any horizontal routing) may be implemented in cell 100 to provide connections between various top and backside metal layers and transistor components within the cell (e.g., top gate 108, bottom gate 116, and source / drain regions 124). Connections may also be made depending on whether control or power signals are intended for components within the transistors of cell 100. For example, in the embodiment shown in FIGS. 1-6, contact 114 may provide a control signal connection to top gate 108A, while backside via 122 provides a power signal connection to source / drain region 124F. The number, type, and positioning of contacts and vias may be determined based on the desired device to be constructed using the structure of components within cell 100. For example, an inverter device will have different connections than a NAND device (as shown by way of example in FIGS. 13-18).

[0078] As shown in FIGS. 1-6 , cell 100 includes four top metal tracks (top metal layers 112A-D) and three back metal tracks (back metal layers 120A-C). It should be understood that cell 100 may include any number of top and back metal tracks permitted by the cell's design and manufacturing constraints. For example, the number of metal tracks may be greater or less depending on the cell's design and manufacturing constraints, such as height, pitch, and width. Additionally, the top and back metal tracks may not be aligned with one another. For example, as clearly shown in FIGS. 5-6 , top metal layer 112 is not aligned with back metal layer 120. However, embodiments having aligned top and back metal layers may be contemplated.

[0079] 4, the backside metal layer 120 is formed on or near the bottom surface of the substrate 102. In particular embodiments, the backside metal layer 120 comprises one or more backside layers of an active layer in the cell 100 (e.g., the backside metal layer is vertically below the active region 106). In some embodiments, the backside metal layer 120 comprises one or more buried layers in the substrate 102 (e.g., the metal layer is buried or embedded below the bottom surface of the substrate). In some embodiments, the backside metal layer 120 is buried below a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments may be contemplated in which the backside metal layer 120 is not located within the substrate 102.

[0080] Metal tracks may also be selected for use as control signal tracks (e.g., control signal rails) or power signal tracks (e.g., power signal rails) based on the desired device application of cell 100. Control signal tracks may provide input or output signal connections to transistor components within cell 100, while power signal tracks may provide power routing to / from Vdd (e.g., supply voltage) and Vss (e.g., ground), as well as other contemplated power connections. The selection of tracks for use as control signal or power signal tracks may also determine the connections made to the metal tracks. For example, in the illustrated embodiment of cell 100, top metal layer 112B is a control signal track connected to top gate 108A by contact 114, while backside metal layer 120B is a power signal track connected to source / drain region 124F by backside via 122. It should be noted that in various contemplated embodiments, any of backside metal layers 120A-C may be used as a power signal track. The remaining upper metal tracks (e.g., upper metal layers 112A, 112C, 112D) may be used for either additional upper control signal tracks or upper power signal tracks. Similarly, the remaining backside metal tracks (e.g., backside metal layers 120A and 120C) may be used for either additional backside power signal tracks or backside control signal tracks. For example, in one contemplated embodiment, one of upper metal layers 112A, 112C, 112D may be an upper power signal track having a contact to a source / drain region (e.g., one of source / drain regions 124A-C) in the upper portion of cell 100 to provide a power signal connection to the upper transistor having active area 104. Additionally, one of backside metal layers 120A and 120C may be a backside control signal track having a contact to a lower gate 116B (e.g., the lower gate in a split-gate configuration) in the lower portion of cell 100 to provide a control signal connection to the lower transistor having active area 106.

[0081] In various contemplated embodiments, when a metal track is used as a power rail (e.g., a power signal track), one or more upper metal tracks (e.g., upper metal layers 112A-D) may be merged. For example, in some embodiments, when a metal track along a cell edge (e.g., upper metal layer 112A or upper metal layer 112D) is used as a power rail, the metal track may be merged with a metal cell track from an adjacent cell. For example, as shown in FIG. 1, upper metal layer 112D′ may be in an adjacent cell in the cell height direction (above cell 100 in the depiction of FIG. 1). A power rail merge layer 109 (dashed box) may then be implemented to merge upper metal layer 112A in cell 100 with upper metal layer 112D′ in the adjacent cell above. In various embodiments, power rail merge layer 109 is a metal layer that connects upper metal layer 112A and upper metal layer 112D′. In some contemplated embodiments, upper metal layer 112A, upper metal layer 112D', and power rail merge layer 109 may be a single metal track formed within cell 100 and adjacent cells.

[0082] In other contemplated embodiments of merging metal tracks, metal tracks used as power rails at or near the center of a cell may be merged. For example, as shown in FIG. 1 , if upper metal layer 112B and upper metal layer 112C are used as power rails, a power rail merge layer 111 (dashed box) may be implemented to merge these layers. Power rail merge layer 111 may be, for example, a metal connecting upper metal layer 112B and upper metal layer 112C. In some cases, upper metal layer 112B, upper metal layer 112C, and power rail merge layer 111 may be a single metal track within cell 100.

[0083] It should be noted that in the embodiment of cell 100 shown in Figures 1-6, additional contacts for control and power signals are not shown for simplicity of the drawings, with the understanding that various connections can be made between the illustrated metal tracks and transistor components within the cell. For example, any metal track (e.g., any one of top metal layers 112A, 112C, 112D, or any one of backside metal layers 120A and 120C) can be connected to any gate (e.g., top gate 108 or bottom gate 116) or source / drain region 124 within cell 100, as needed for the desired device structure. Thus, the illustrated structure of cell 100 in Figures 1-6 with its components (e.g., gates 108 / 116 and source / drain region 124) and metal tracks (e.g., top metal layer 112 and backside metal layer 120) provides a basic building block structure from which different variations of connections between components and metal tracks can be made to generate many different types of devices.

[0084] As shown in FIGS. 1-6, the top gate 108 and the bottom gate 116 can be formed in the cell 100 with different gate-to-gate relationships within the stacked transistor structure. Two possible gate relationship embodiments are shown in FIGS. 3 and 4. In a first contemplated embodiment, the top gate 108A is merged with the bottom gate 116A to establish connectivity between the gates. The connectivity established by merging the gates allows a single control signal to be provided to both gates. For example, as shown in FIGS. 3 and 4, due to the connectivity between the gates, a control signal provided to the top gate 108A from the upper metal layer 112B through the contact 114 can be passed through and used as the control signal for the bottom gate 116A. Note that the merged gate configuration is also shown in the cross-sectional view of FIG. 5. A second contemplated embodiment includes the top gate 108B separated (e.g., split) from the bottom gate 116B. By separating the top gate 108B and the bottom gate 116B, the gates remain electrically disconnected. Thus, the top gate 108B and bottom gate 116B will require separate control signals as the control signals cannot pass between the gates due to the separation / splitting between the gates.

[0085] Although not shown in FIGS. 1-6 , in various embodiments, the source / drain regions 124 may also be merged between the upper and lower transistors. Examples of merged source / drain regions are shown in FIGS. 13-16 , described below. Merging the source / drain regions 124 may allow a single power signal to connect power to both the upper and lower transistors, or a single control signal (e.g., a single output signal from the drain) to connect to both the upper and lower transistors. Similar to splitting the gate, when the source / drain regions 124 are split (as shown in FIGS. 1-6 ), separate connections must be made to the split source / drain regions.

[0086] In particular embodiments, power routing for transistors (e.g., upper and lower transistors) in cell 100 is split between upper metal layer 112 and backside metal layer 120. For example, as shown in FIGS. 2, 4, and 6, backside metal layer 120B is connected to source / drain region 124F through backside via 122. Thus, in particular embodiments, power to lower gate 116B in the lower transistor (e.g., transistor having active area 206) is routed from backside metal layer 120B. To split the power, power to upper gate 108B may be routed from one of the upper metal layers not used for control signals (e.g., upper metal layer 112C, etc.). Thus, upper gate 108B and lower gate 116B have separate power rails supplying power to the gates / transistors. Splitting power routing between upper metal layer 112 and backside metal layer 120 may result in more efficient power routing within cell 100.

[0087] Additional embodiments may be contemplated in which power routing is provided from one or other of the top metal layer 112 and the backside metal layer 120, but not from both layers. For example, as described above, the source / drain regions may be merged, and a single power signal from either the top or backside may be supplied to the merged region. In another contemplated embodiment, power may be supplied into the cell 100 through a backside metal layer (such as the backside metal layer 120A), and vias may route power from the backside metal layer to one of the top metal layers, which then connects to the source / drain regions in the upper transistor. The vias may be disposed in an open channel in the cell 100 between the top and backside metal layers. An example of a via is shown in FIG. 6, where a via 600 (dashed line) is optionally routed between the top metal layer 112A and the backside metal layer 120A in the space (e.g., the channel) outside the source / drain regions 124C / 124F. The upper metal layer 112A can then connect (directly or through another upper metal layer) to the source / drain regions 124C to provide power to the upper transistor. Note that vias 600, as shown in Figure 6, can also be used to route signals between the upper and backside metal layers.

[0088] Yet another alternative for routing power from the backside layer to the top may include extending the source / drain regions 124C to intersect and connect with the vias 600, as shown by the dotted lines extending from the source / drain regions 124C in Figure 6. This extension establishes a direct connection between the vias 600 and the source / drain regions 124C. Other examples of extensions (for both gate and source / drain regions) are provided below with reference to Figures 7-12, which describe implementations of via pillars within a cell (e.g., on the periphery of the cell).

[0089] As described above, the embodiment of cell 100 shown in FIGS. 1-6 provides the basis for a compact standard cell structure implementing two vertically stacked transistors. The transistors can be heterogeneous (e.g., two different types of transistors) or homogeneous (e.g., the same type of transistor). Cell 100 implements the availability of connections from either the top metal layer and the bottom metal layer to any of the various transistor components, including the gate and source / drain regions. The flexibility in connections for both control signals and power for the transistor components allows the basic structure of cell 100 to be adapted to a wide range of logic schemes for implementing different integrated circuit devices using stacked transistors. The compactness of cell 100 allows cells with stacked transistors to be implemented within current standard cell design and manufacturing constraints.

[0090] In some cases, placing cell 100 next to an adjacent cell can cause manufacturing problems due to routing tracks along the cell's boundary. If the routing tracks are along the boundary, vias from the routing tracks can cause spacing issues between adjacent cells. One possible solution to this boundary problem is to replace the routing tracks along the edge with via tracks, where the vias alternate between being used by the current cell and the adjacent cell.

[0091] FIG. 7 illustrates a top plan view of a cell with alternate vias along its boundary, according to some embodiments. In cell 700, three upper metal layers 112A, 112B, and 112C are disposed between via tracks 705A and 705B. Via tracks 705A and 705B are disposed along the boundary (e.g., edge) of cell 700. Via tracks 705A and 705B include via pillars 710. In particular embodiments, for via pillars 710A and 710B, via pillar 710A belongs to cell 700, while via pillar 710B belongs to an adjacent cell. In various embodiments, via pillars 710 disposed around the periphery of the cell are utilized to route either control or power signals to the interior of cell 700. It should be noted that adjacent cells may have a mirror image configuration relative to cell 700 to accommodate the alternating via pillar placement.

[0092] Various embodiments may be contemplated for connecting to the via pillar 710A in the cell 700 shown in FIG. 7. Embodiments may include routing connections to the gate or source / drain regions in the cell 700. FIGS. 8 and 9 show cross-sectional views of source and drain connections in a cell implementing via pillars, according to some embodiments. FIG. 8 is a cross-sectional view of the cell 800 showing connections to the source regions 124A, 124B, and FIG. 9 is a cross-sectional view of the cell 800 showing connections to the drain regions 124C, 124D.

[0093] In various embodiments, as shown in FIG. 8 , the source regions 124A, 124B are directly connected to the upper metal layer 112B and the backside metal layer 120A, respectively, by contacts 114. The upper metal layer 112B and the backside metal layer 120A can then be routed to a power supply (e.g., Vdd) or ground (e.g., Vss) for power connection to the source regions 124A, 124B. For the drain regions 124C, 124D, the contacts 114 are routed horizontally to a via pillar 710A, as shown in FIG. 9 . The via pillar 710A can then be routed to the upper metal layer 112 or the backside metal layer 120 for signal connection. In some embodiments, the contacts 114 for the drain regions 124C, 124D can be replaced by extending the drain regions 124C, 124D horizontally to connect to the via pillar 710A.

[0094] 10 illustrates a cross-sectional view of stacked transistor control signal connections within a cell implementing via pillars, according to some embodiments. In FIG. 10, cell 1000 includes source / drain regions 124A, 124B connected to top metal layer 112C and back metal layer 120B, respectively, by contacts 114. Top metal layer 112C and back metal layer 120B can be routing for control signals provided to source / drain regions 124A, 124B.

[0095] The via pillar 710A may also provide routing for control signals from the gates in various embodiments of stacked transistors. The gates may be coupled, for example, as common gates or split gates (e.g., as used in transmission gates). FIG. 11 illustrates a cross-sectional view of stacked transistor control signal connections in a common gate configuration, according to some embodiments. In cell 1100, the top gate 108A and the bottom gate 116A extend to cross and connect with the via pillar 710A for a common connection to the gates. FIG. 12 illustrates a cross-sectional view of stacked transistor control signal connections in a split gate configuration, according to some embodiments. In cell 1200, the top gate 108A is connected to the upper metal layer 112C by the contact 114, and the bottom gate 116A extends to cross and connect with the via pillar 710A. The upper metal layer 112C and the via pillar 710A may then be cross-coupled to cross-couple the top gate 108A and the bottom gate 116A. Exemplary NAND Cell with Stacked Transistors

[0096] 13-18 show diagrams of an exemplary NAND cell, according to some embodiments. FIG. 13 shows a top plan view of a NAND cell 1300, according to some embodiments. FIG. 14 shows a back plan view of a NAND cell 1300, according to some embodiments. FIG. 15 shows a cross-sectional view of the NAND cell 1300 along line A-A' shown in FIGS. 13 and 14. FIG. 16 shows a cross-sectional view of the NAND cell 1300 along line B-B' shown in FIGS. 13 and 14. FIG. 17 shows a cross-sectional view of the NAND cell 1300 along line C-C' shown in FIGS. 13 and 14. FIG. 18 shows a cross-sectional view of the NAND cell 1300 along line D-D' shown in FIGS. 13 and 14.

[0097] In a particular embodiment, Figure 13 illustrates (from the top) the structure associated with the active area 104 of the upper transistor (e.g., an NMOS active area), and Figure 14 illustrates (from the bottom) the structure associated with the active area 106 of the lower transistor (e.g., a PMOS active area) in a vertically stacked transistor. In the illustrated embodiment, the upper metal layer 112D is a ground rail (e.g., a VSS rail), and the bottom metal layer 120B is a power rail (e.g., a VDD rail). The remaining upper metal layers (e.g., upper metal layers 112A, 112B, 112C) and bottom metal layers (e.g., bottom metal layers 120A, 120C) may be used for signal routing and / or internal routing within the NAND cell 1300, as described below.

[0098] In the illustrated embodiment, as shown in Figure 13, NAND cell 1300 includes top gate 108A and top gate 108B, which are active NMOS gates disposed within the cell. Insulated gates 110A, 110B (e.g., dummy gates) are disposed at opposite ends of cell 1300 in the gate pitch direction, with top contact 126A disposed between insulated gate 110A and top gate 108A, top contact 126B disposed between top gate 108A and top gate 108B, and top contact 126C disposed between top gate 108B and insulated gate 110B, also in the gate pitch direction. Furthermore, in the illustrated embodiment, as shown in Figure 14, NAND cell 1300 includes bottom gate 116A and bottom gate 116B, which are active PMOS gates disposed within the cell. In the gate pitch direction, bottom contact 126D is located between insulated gate 110A and bottom gate 116A, bottom contact 126E is located between bottom gate 116A and bottom gate 116B, and bottom contact 126F is located between bottom gate 116B and insulated gate 110B.

[0099] In various embodiments, as shown in Figures 13 and 15, contact 114A provides a connection between contact 126A and upper metal layer 112D (e.g., a ground rail). Contact 126A is also connected to source / drain region 124A of upper gate 108A. Note that Figures 15-18 show six source / drain regions 124A-F in NAND cell 1300, with source / drain regions 124A-C being upper source / drain regions and source / drain regions 124D-F being lower source / drain regions. In NAND cell 1300, upper source / drain regions 124A-C are separated from lower source / drain regions 124D-F. Additionally, the upper source / drain regions 124A-C and upper gates 108A, 108B comprise an upper channel 1304, while the lower source / drain regions 124D-F and lower gates 116A, 116B comprise a lower channel 1306.

[0100] 13 and 16 provides a connection between the top gate 108A and the upper metal layer 112B, which may be a route for an input signal to the device of the NAND cell 1300. The NAND cell 1300 further includes a contact 114D (shown in FIGS. 13 and 18) connecting the contact 126C to the upper metal layer 112A, which may be a route for an output signal from the device of the NAND cell 1300.

[0101] In a contemplated embodiment of NAND cell 1300, the top and bottom gates are merged. For example, as shown in FIG. 16 , top gate 108A is merged into bottom gate 116A. Thus, contact 114B provides a connection (e.g., an input signal route) between the merged top and bottom gates 108A, 116A, and upper metal layer 112B. Top gate 108B and bottom gate 116B may also be merged and connected to contact 114C (shown in FIG. 13 ), which then provides a connection to upper metal layer 112C, which may be a second route for an input signal to the NAND cell 1300 device.

[0102] In various embodiments, the NAND cell 1300 includes backside via 122A and backside via 122C, as shown in Figures 14, 15, 17, and 18. Backside via 122A provides a connection between bottom contact 126D and backside metal layer 120C, as shown in Figures 14 and 15. Backside metal layer 120C is also connected to bottom contact 126F by backside via 122C, as shown in Figures 14 and 18. Thus, backside metal layer 120C provides an internal (into the cell) route path between bottom contact 126D (connected to bottom source / drain region 124D of bottom gate 116A) and bottom contact 126F (connected to bottom source / drain region 124F of bottom gate 116B).

[0103] In a particular embodiment, NAND cell 1300 includes via 1302A and via 1302B. Via 1302A and via 1302B are top-to-back vias connecting top contact 126C to bottom contact 126F, as shown in FIGS. 13, 14, and 18. Thus, via 1302A and via 1302B provide a connection between the top source / drain region 124C of top gate 108B and the bottom source / drain region 124F of bottom gate 116B. Note that in the depictions of FIGS. 13 and 14, via 1302A and via 1302B may be partially hidden from view by contact 114D and backside via 122C, respectively.

[0104] 14 and 17. Backside via 122B provides a power connection (from backside metal layer 120B, which is the power rail) to lower source / drain region 124E, which is shared by lower gate 116A and lower gate 116B in lower active area 106. Thus, power is provided to all active gates through backside via 122B, as lower gate 116A and lower gate 116B merge with upper gate 108A and upper gate 108B, respectively. Complementary FET SRAM cell

[0105] In various embodiments, stacked transistors as described herein can be implemented in memory cells such as SRAM cells. FIG. 19 shows a schematic diagram of a memory cell. Cell 1700 is, for example, a 6T SRAM memory cell. Cell 1700 includes two inverters 1710A, 1710B that are cross-coupled to provide inputs and outputs at nodes 1712 and 1714. Node 1712 is coupled to the output of pass gate 1720, and node 1714 is coupled to the output of pass gate 1722. Pass gates 1720, 1722 are sometimes referred to as "access gates" or "transmission gates." A word line 1730 is coupled to pass gate 1720 and pass gate 1722 to provide control signals to the pass gates. A bit line 1740 is coupled to pass gate 1720 to read / write data from the pass gate. A bit line 1742, complementary to bit line 1740, is coupled to pass gate 1722 to read / write data from the pass gate.

[0106] Cell 1700 includes six transistors (two for each inverter and one for each pass gate) using inverter 1710A, inverter 1710B, pass gate 1720, and pass gate 1722. In a particular embodiment, inverter 1710 includes two complementary transistors, e.g., each inverter includes an NMOS transistor and a PMOS transistor. Pass gates 1720, 1722 may be the same type of transistor. In one embodiment, both pass gates are NMOS transistors. Thus, in various embodiments, cell 1700 includes four NMOS transistors and two PMOS transistors.

[0107] The present disclosure contemplates various techniques for implementing stacked transistors within a memory cell. For example, stacked transistors as described above may be implemented within a 6T SRAM memory cell as shown in FIG. 19. Utilizing disclosed embodiments of stacked transistors within a memory cell provides the ability to minimize spacing along with multiple transistors within the memory cell. Thus, disclosed embodiments of a memory cell include multiple transistors at a small scale factor.

[0108] Certain embodiments disclosed herein have five broad elements: 1) a first transistor region having parallel first and second active regions; 2) a second transistor region having parallel third and fourth active regions, the second transistor region being disposed vertically below the first transistor region; 3) a first inverter formed by a transistor in the first active region and a transistor in the third active region; 4) a second inverter formed by a transistor in the second active region and a transistor in the fourth active region; and 5) a cross-coupling between the first inverter and the second inverter. In certain embodiments, the source / drain regions in the inverters are merged. For example, the source / drain regions on opposite sides of the gates of the two transistors in the first inverter may be merged. In a particular embodiment, the cross-coupling is achieved by coupling a horizontally extending portion of a gate of a transistor in the third active region to a source / drain region of a transistor in the fourth active region, and coupling a horizontally extending portion of a gate of a transistor in the fourth active region to a source / drain region of a transistor in the third active region.

[0109] In various embodiments, the horizontally extending portion of the gate for the cross-coupling is a portion that extends toward and possibly into other active regions (e.g., the gate of a transistor in a third active region has a portion that extends into a fourth active region). Extending the gate as described herein allows for cross-coupling connections in an area of ​​the cell vertically below the active area of ​​the memory cell. The cross-coupling may also be located vertically above any backside layer routing. This area is available for the cross-coupling by removing material in the inactive portions of the third and fourth active regions.

[0110] In summary, the inventors have recognized that stacked transistors can be implemented within a memory cell while removing material in the inactive portions of the active region to allow for cross-coupling of the inverters formed by the transistors within the memory cell. Cross-coupling of the inverters in areas intended for the inactive portions provides a memory cell structure that maintains current design principles while also reducing the cell height relative to typical memory cells. Utilizing cross-coupling in areas below the active regions can reduce the cell height because it allows the active regions to be positioned closer together vertically. Thus, minimizing the vertical spacing between the active regions allows the overall height of the memory cell to be reduced.

[0111] FIG. 20 shows a top plan view of a memory cell 1800 having stacked transistors, according to some embodiments. FIG. 21 shows a back plan view of a memory cell 1800 having stacked transistors, according to some embodiments. FIG. 22 shows a cross-sectional view of memory cell 1800 along line A-A' shown in both FIGS. 20 and 21. FIG. 23 shows a cross-sectional view of memory cell 1800 along line B-B' shown in both FIGS. 20 and 21. FIG. 24 shows a cross-sectional view of memory cell 1800 along line C-C' shown in both FIGS. 20 and 21.

[0112] For simplicity of illustration, the representations of cells disclosed herein show only components relevant to the present disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein. For example, in FIGS. 20 and 21 , various connections (such as vias or contacts described herein) may be visible in some depictions. Additionally, some transparency of materials is provided to allow visibility of underlying components in the top and back plan views for better understanding of the disclosed embodiments. For example, in FIGS. 20 and 21 , the gate (e.g., poly lines) and source / drain regions have some transparency to provide visibility of the vias / contacts and active regions in the area underlying the transistor, and in FIGS. 20 and 21 , the top and back metal layers have transparency to provide visibility of the transistor that would be hidden in the plan view. In the cross-sectional views of FIGS. 22-24 , the depth of the various components is more clearly visible. It should be noted that the top metal layer is not shown in the cross-sectional views of FIGS. 22-24 to further simplify the drawings.

[0113] In the illustrated embodiment, cell 1800 includes two upper active regions 1810, 1820 (shown in FIG. 20 ) and two lower active regions 1830, 1840 (shown in FIG. 21 ). In particular embodiments, the upper active regions 1810, 1820 are active regions for NMOS transistors, and the lower active regions 1830, 1840 are active regions for PMOS transistors. The lower active regions 1830, 1840 may include inactive portions 1833, 1842 (shown by the sloped fill pattern in the active regions in FIG. 21 ). The inactive portions 1833, 1842 may be formed by either not providing diffusion material in those portions (e.g., by either removing diffusion material or not depositing diffusion material in those portions) or by cutting the diffusion material from the active portions of the lower active regions 1830, 1840 (e.g., by an isolation structure or mechanism).

[0114] Upper active region 1810 is separated from upper active region 1820 by diffusion spacing distance 1815. Similarly, lower active region 1830 is separated from lower active region 1840 by diffusion spacing distance 1835. In some embodiments, distance 1815 and distance 1835 are substantially the same distance.

[0115] In the illustrated embodiment, upper active region 1810 includes an upper gate 1812 between source / drain regions 1814A and 1814B and an upper gate 1816 between source / drain regions 1814B and 1814C. Upper active region 1820 includes an upper gate 1822 between source / drain regions 1824A and 1824B and an upper gate 1826 between source / drain regions 1824B and 1824C. Upper gates 1812, 1816, 1822, and 1826 may be poly gates or other types of gates for FET transistor devices. In one embodiment, upper gates 1812, 1816, 1822, and 1826 are NMOS gates.

[0116] In particular embodiments, top gate 1812 is separated from top gate 1822, and top gate 1816 is separated from top gate 1826. For example, the poly for top gate 1812 is not connected to the poly for top gate 1822. Similarly, the poly for top gate 1816 is not connected to the poly for top gate 1826. The top gates can be separated either by cutting the poly between the top gates (e.g., cutting the poly between top active region 1810 and top active region 1820) or by forming the top gates from separate poly layers in top active region 1810 and top active region 1820. The separation of the top gates between top active region 1810 and top active region 1820 provides differentiation between the transistors formed by these top gates, allowing them to form transistors for inverters and pass gates as described herein.

[0117] In the illustrated embodiment, lower active region 1830 includes lower gate 1832 between source / drain region 1834A and source / drain region 1834B. Lower active region 1840 includes lower gate 1846 between source / drain region 1844B and source / drain region 1844C. It should be noted that there are only two gate regions in lower active regions 1830, 1840 due to the presence of inactive portions 1833, 1842 and because only two transistors are required in combination with the four transistors in the upper active region to form a memory cell device. Lower gates 1832, 1846 may be poly gates or other types of gates for FET transistor devices. In one embodiment, lower gates 1832, 1846 are PMOS gates.

[0118] In particular embodiments, as shown in FIG. 21 , portions of the lower gate 1832 and the lower gate 1846 extend across the separation distance 1835 between the lower active region 1830 and the lower active region 1840. Portions of the lower gate 1832 and the lower gate 1846 extend across the separation distance, and are also visible in the gap between the upper active region 1810 and the upper active region 1820 in the depiction of FIG. 20 . In some embodiments, portions of the lower gate 1832 and the lower gate 1846 extend across the separation distance 1835 and below the transistor region of the other lower active region. For example, as shown in FIGS. 20 and 21 , the lower gate 1832 extends into the transistor region around the lower active region 1840, which is below the transistor region around the upper active region 1820. Similarly, the lower gate 1846 extends into the transistor region around the lower active region 1830, which is below the transistor region around the upper active region 1810. In some embodiments, portions of bottom gate 1832 and bottom gate 1846 extend below transistor regions that define pass gates in the upper active region, as described in more detail below. The extension of bottom gate 1832 and bottom gate 1846 across the active region provides capability for cross-coupled connections within cell 1800, also as described in more detail below.

[0119] An exemplary embodiment of a 6T (six transistor) SRAM memory cell that may be implemented in cell 1800 will now be described with reference to various connections made within the cell to implement six transistors (e.g., four NMOS transistors and two PMOS transistors) arranged as inverters and pass gates. It should be understood that various additional embodiments of the memory cell may be contemplated based on the disclosed structure of cell 1800. As shown in FIG. 19 , the 6T SRAM memory cell includes two NMOS transistors and two PMOS transistors arranged to form two inverters, which are then cross-coupled. The two NMOS transistors are then arranged to form a pass gate connected to the inverters.

[0120] Returning to cell 1800, top gate 1812, as shown in FIG. 20, together with source / drain region 1814A and source / drain region 1814B can form first NMOS transistor 1850 of inverter 1710A. Next, as shown in FIG. 21, bottom gate 1832, together with source / drain region 1834A and source / drain region 1834B can form first PMOS transistor 1852 of inverter 1710A. To form inverter 1710A using transistor 1850 and transistor 1852, source / drain region 1814A is merged with source / drain region 1834A by S / D merge 1860A. S / D merge 1860A can be, for example, a via or other substantially vertical connection formed between source / drain region 1814A and source / drain region 1834A. Merging source / drain region 1814A and source / drain region 1834A merges the power connections between transistor 1850 and transistor 1852.

[0121] Additionally, for transistors 1850 and 1852, source / drain region 1814B is merged to source / drain region 1834B by S / D merge 1860B (as shown in FIG. 22). Merging source / drain region 1814B with source / drain region 1834B merges the outputs of transistors 1850 and 1852. The inputs of transistors 1850 and 1852 can be merged by merging top gate 1812 to bottom gate 1832 using gate merge 1862A. Gate merge 1862A may be a via or other substantially vertical connection formed between top gate 1812 and bottom gate 1832, as shown in FIG. 23. When the inputs and outputs of transistors 1850 and 1852 are merged, these transistors form inverter 1710A.

[0122] 19 may similarly be formed by a second NMOS transistor 1854 and a second PMOS transistor 1856, as shown in FIGS. 20 and 21. Transistor 1854 may be formed by combining an upper gate 1826 with source / drain regions 1824B and 1824C, as shown in FIG. 20. Transistor 1856 may be formed by combining a lower gate 1846 with source / drain regions 1844B and 1844C, as shown in FIG. 21. Source / drain region 1814A is merged with source / drain region 1834A by S / D merge 1860A.

[0123] To form inverter 1710B using transistor 1854 and transistor 1856, source / drain region 1824B is merged to source / drain region 1844B by S / D merge 1860C (also shown in FIG. 22), and source / drain region 1824C is merged to source / drain region 1844C by S / D merge 1860D (also shown in FIG. 24). Merging source / drain region 1824B with source / drain region 1844B merges the outputs of transistors 1854 and 1856, while merging source / drain region 1824C with source / drain region 1844C merges the power connections between transistors 1854 and 1856. The inputs of transistors 1854 and 1856 are then merged by merging top gate 1826 with bottom gate 1846 using gate merge 1862B. When the inputs and outputs of transistor 1854 and transistor 1856 are merged, these transistors form inverter 1710B.

[0124] In various embodiments, cell 1800 provides utility for forming pass gates 1720 and 1722, in addition to inverters 1710A and 1710B. For example, as shown in FIG. 20 , pass gate 1720 can be formed using a third NMOS transistor 1858, and pass gate 1722 is formed using a fourth NMOS transistor 1859. It should be noted that both transistors 1858 and 1859 are formed without an underlying PMOS transistor (e.g., over an inactive portion of a lower active region). In the illustrated embodiment, transistor 1858 is formed by upper gate 1822 and source / drain regions 1824A and 1824B. Transistor 1859 is formed by upper gate 1816 and source / drain regions 1814B and 1814C.

[0125] Both top gate 1816 and top gate 1822 may be coupled to a word line (e.g., word line 1730) for transmission of control signals to the gates. A read / write data connection to a bit line (e.g., bit line 1742) for top gate 1816 may be provided through source / drain region 1814C, while a read / write data connection to a bit line (e.g., bit line 1740) for top gate 1822 may be provided through source / drain region 1824A. The output of transistor 1859 (corresponding to pass gate 1722) is provided through source / drain region 1814B, and this output is also the output of transistor 1850 and is merged with the output of transistor 1852 in inverter 1710A. Correspondingly, the output of transistor 1858 (corresponding to pass gate 1720) is provided via source / drain region 1824B, which is also the output of transistor 1854, and is merged with the output of transistor 1856 in inverter 1710B. Transistors 1858, 1859 thus provide pass gate transistors 1720, 1722 that are coupled to inverter 1710A and inverter 1710B according to the schematic diagram of FIG.

[0126] As mentioned above, in particular embodiments, bottom gate 1832 (of transistor 1852 of inverter 1710A) and bottom gate 1846 (of transistor 1856 of inverter 1710B) extend toward the inactive portions of the active regions of the opposing transistor regions. These extensions provide the ability to provide cross-coupling between the inverters below the active region of cell 1800. For example, as shown in FIG. 23 , bottom gate 1832 extends below gate 1822 formed in active region 1820. The extension of bottom gate 1832 allows cross-coupling 1864B to be coupled between bottom gate 1832 (the merged PMOS transistor gate in inverter 1710A) and source / drain region 1844B (the merged PMOS source / drain region in inverter 1710B). Cross-coupling 1864B therefore cross-couples the input of inverter 1710A and the output of inverter 1710B. Similarly, cross-coupling portion 1864A shown in Figures 20-22 can be implemented to cross-couple the input of inverter 1710B (by coupling to an extension of bottom gate 1846) and the output of inverter 1710A (by coupling to source / drain region 1834B as shown in Figure 22).

[0127] In certain embodiments, the cross-couplings 1864A, 1864B are located below the active areas in the cell 1800 and above the backside metal layer 120. For example, as shown in FIGS. 22 and 23, the cross-couplings 1864A, 1864B are coupled to the backside (e.g., bottom) of the lower gate and source / drain regions in the lower transistor region of a PMOS transistor. The cross-couplings 1864A, 1864B can be located in this area due to the removal of material in the inactive portions 1833, 1842 of the lower active regions 1830, 1840. The use of the cross-couplings 1864A, 1864B in the cell 1800 reduces the cell height relative to a typical SRAM cell while maintaining current design principles for SRAM cells. For example, cross-couples 1864A, 1864B implemented using bottom gate 1832 and bottom gate 1846 provide better area scaling in cell 1800 by allowing both upper active regions 1810, 1820 and lower active regions 1830, 1840 to be closer together. For example, in some embodiments, both upper active regions 1810, 1820 and lower active regions 1830, 1840 can be positioned with minimal spacing between diffusion regions within the active regions. Implementing minimal spacing can reduce the height of cell 1800 to approximately half the typical height of a 6T SRAM cell. Macro SRAM Cell

[0128] In various embodiments, the stacked transistors described herein may be implemented in peripheral cells associated with SRAM cells, in addition to being implemented in memory cells such as SRAM cells (e.g., SRAM bit cells). For example, this disclosure contemplates various techniques for implementing column input / output logic cells that include stacked transistors. The implementation of stacked transistors in peripheral cells, such as column input / output logic cells, may enable the use of both topside and backside routing in memory devices containing various types of SRAM cells, including various embodiments of the SRAM cells described herein.

[0129] Certain embodiments disclosed herein have four broad elements: 1) a plurality of bit cells formed in first and second transistor regions arranged vertically relative to one another; 2) a first metal layer (e.g., a top metal layer) located above the bit cells and a second metal layer (e.g., a bottom metal layer) located below the bit cells; 3) a first column input / output logic cell coupled to the first array of bit cells; and 4) a second column input / output logic cell coupled to the second array of bit cells, the second array of bit cells being closer to the logic cells than the first array of bit cells. In certain embodiments, the first metal layer includes first routing coupling the first array of bit cells to the first column input / output logic cell, while the second metal layer includes second routing coupling the second array of bit cells to the second column input / output logic cell. In some embodiments, the column input / output logic cell implements stacked transistors as described herein.

[0130] Thus, in various embodiments, a first column input / output logic cell provides column I / O logic to bit cells further away from the peripheral region of the device, and a second column input / output logic cell provides column I / O logic to bit cells closer to the peripheral region of the device. Splitting routing between the top metal layer and the bottom metal layer reduces routing congestion compared to utilizing only topside routing or only bottomside routing for routing logic within the memory device. In various embodiments, dummy cells may be utilized for localized routing of bit line signals between the top metal layer and the bottom metal layer. For example, dummy cells may be utilized for localized routing near bit cells of the first array (e.g., bit cells far away from logic cells).

[0131] In summary, the inventors have recognized that memory devices can utilize routing for column I / O logic in both top and bottom metal layers to alleviate metal congestion in the memory device. Additionally, when both top and bottom metal layers are used to route logic between bit cells and logic cells, various techniques are implemented to reduce any area penalty associated with front-to-back transitions (or vice versa). In some embodiments, various routing paths provide reduced resistance paths for logic within the memory device. Disclosed embodiments of memory devices can have strong signal connectivity with improved read / write speeds and therefore improved performance through implementation of the various disclosed techniques.

[0132] 25 shows an exemplary block diagram of a memory device according to some embodiments. In the illustrated embodiment, memory device 2300 includes a memory cell region 2310 and a logic cell region 2320. Memory cell region 2310 includes a plurality of bit cells that may be divided into a far bit cell array 2312A and a near bit cell array 2312B. The bit cells in the array may be, for example, SRAM cells 1800, as described above. As shown in FIG. 25, far bit cell array 2312A includes a plurality of bit cells that are positioned further away from logic cell region 2320 than the bit cells in near bit cell array 2312B.

[0133] In various embodiments, logic cell area 2320 includes a plurality of column input / output (I / O) logic cells 2322. Column I / O cells 2322 may manage reads / writes from bit cell array 2312, for example. Column I / O cells 2322 may also include portions of sense amplifiers. It should be understood that logic cell area 2320 may include other logic cells in addition to column input / output (I / O) logic cells 2322. For example, logic cell area 2320 may also include power switch logic cells, word line logic cells, local I / O circuit cells, global I / O circuit cells, etc. In some embodiments, logic cell area 2320 may be referred to as a peripheral area of ​​memory device 2300.

[0134] In contemplated embodiments, logic circuit cell region 2320 includes an individual column I / O logic cell 2322 for each bit cell array in memory cell region 2310. For example, in the illustrated embodiment, memory cell region 2310 has two bit cell arrays 2312A, 2312B, and therefore logic circuit cell region 2320 includes a first column I / O logic cell 2322A and a second column I / O logic cell 2322B.

[0135] In various embodiments, a first column I / O logic cell 2322A provides column I / O logic for the far bit cell array 2312A, and a second column I / O logic cell 2322B provides column I / O logic for the near bit cell array 2312B. Routing in both the top metal layer 112 and the back metal layer 120 may be utilized in memory device 2300 to alleviate metal congestion in the memory device. This disclosure contemplates routing methods that reduce any front-to-back transition area penalty when utilizing both the top metal layer 112 and the back metal layer 120 in routing logic between bit cells and logic cells.

[0136] In particular embodiments, memory device 2300 utilizes both top metal layer 112 and back metal layer 120 for bit line routing within the memory device. For example, top metal layer 112 may be utilized for bit line routing between near bit cell array 2312B and second column I / O logic cells 2322B, and back metal layer 120 may be utilized for bit line routing between far bit cell array 2312A and first column I / O logic cells 2322A. In the illustrated embodiment, bit lines 1740A and 1742A provide bit line routing within far bit cell array 2312A, and bit lines 1740B and 1742B provide bit line routing within near bit cell array 2312B. Bit lines 1740 and 1742 may be complementary bit lines, as described herein.

[0137] 25, bit lines 1740A and 1742A in far bit cell array 2312A are coupled to bit line outputs 2314A and 2316A, respectively. Bit line output 2314A is then coupled to back side bit line routing 2330, and bit line output 2316A is coupled to back side bit line routing 2332. In a particular embodiment, bit lines 1740A and 1742A are in the top metal layer 112. For example, as shown in FIGS. 19 and 20, the outputs of the pass gate transistors are in the upper transistor region and are coupled to the top metal layer 112. Because bit lines 1740A and 1742A are routed in the top metal layer 112, as shown in FIG. 25, a transition needs to be made from the top metal layer to the back side metal layer 120, where back side bit line routing 2330 and back side bit line routing 2332 are located.

[0138] In particular embodiments, dummy cells 2340A, 2340B are located at or near bitline outputs 2314A, 2316A, respectively. Dummy cell 2340A comprises a connection between bitline 1740A in the top metal layer 112 and backside bitline routing 2330 in the backside metal layer 120. Dummy cell 2340B comprises a connection between bitline 1742A in the top metal layer 112 and backside bitline routing 2332 in the backside metal layer 120. Figure 26 shows a top plan view of an area having dummy cells 2340, according to some embodiments. Figure 27 shows a backside plan view of an area having dummy cells 2340, according to some embodiments. Figure 28 shows a cross-sectional view of an area having dummy cells 2340, taken along line A-A' shown in both Figures 26 and 27. FIG. 29 shows a cross-sectional view of the area having dummy cells 2340 taken along line BB' shown in both FIGS.

[0139] In various embodiments, as shown in FIG. 26 , top metal layer 112 in region 2400 includes routing for ground signal 2401 and word line 2402 in addition to bit line 1740A and bit line 1742A. In various embodiments, as shown in FIG. 27 , backside metal layer 120 in region 2400 includes routing for signal 2500 and power signal 2502 in addition to backside bit line routing 2330 and backside bit line routing 2332. In particular embodiments, dummy gates 2410 are positioned adjacent to active gates 2440 on either side of region 2400. Dummy gates 2410 can be, for example, gate cuts or other gates that isolate the areas between the dummy gates. Isolation can include, for example, preventing connection to any gate activity in the areas between dummy gates 2410.

[0140] In a particular embodiment, dummy cells 2340A, 2340B include trench metal 2420 formed between bitline 1740A and backside bitline routing 2330 and between bitline 1742A and backside bitline routing 2332, as shown in Figures 26-29. Bitline 1740A, 1742A may be coupled to trench metal 2420 by via 2430 (shown in Figures 26 and 28-29), and backside bitline routing 2330, 2332 may be coupled to trench metal 2420 by via 2530 (shown in Figures 27-29).

[0141] The use of trench metal 2420 for connections between bit lines 1740A, 1742A and backside bit line routing 2330, 2332 provides a low electrical resistance path for bit line signals to transition from the top metal layer 112 to the backside metal layer 120. Dummy cells 2340 provide localized traffic management for bit line signals at or near the far bit cell array 2312A. While dummy cells 2340 have some area penalty in memory device 2300, the area penalty is small because the dummy cells are localized in a shallow metal layer and are not associated with any global routing.

[0142] 25 , after the bit line signals are routed to backside bit line routing 2330 and backside bit line routing 2332, respectively, in dummy cells 2340A, 2340B, the backside bit line routing carries the signals to bit line input 2324A and bit line input 2326A, respectively, in first column I / O cell 2322A. As explained below, bit line input 2324A and bit line input 2326A in first column I / O cell 2322A (and bit line input in second column I / O cell 2322B) are inputs in the backside metal layer. Therefore, no additional transitions between top metal layer 112 and backside metal layer 120 are required to convey the bit line signals from backside bit line routing 2330 and backside bit line routing 2332 to bit line input 2324A and bit line input 2326A in first column I / O cell 2322A.

[0143] Referring now to near bit cell array 2312B, bit line 1740B and bit line 1742B are coupled to bit line output 2314B and bit line output 2316B, respectively. Bit line output 2314B and bit line output 2316B are then coupled to upper bit line routing 2334 and upper bit line routing 2336, respectively. Because both bit lines 1740B, 1742B and upper bit line routing 2334, 2336 are disposed in the upper metal layer 112, no transition between the upper metal layer and the backside metal layer 120 is needed near near bit cell array 2312B.

[0144] In the illustrated embodiment, upper bitline routing 2334 and upper bitline routing 2336 carry bitline signals from near bitcell array 2312B to bitline input 2324B and bitline input 2326B, respectively, in second column I / O cell 2322B. As mentioned above and described below, bitline input 2324B and bitline input 2326B are disposed in backside metal layer 120. Thus, a transition from upper metal layer 112 to backside metal layer 120 may be required at bitline input 2324B and bitline input 2326B.

[0145] In particular embodiments, dummy cell 2350 is located at or near bitline inputs 2324B, 2326B. Dummy cell 2350 includes a connection between upper bitline routing 2334 in the upper metal layer 112 and bitline input 2324B in the backside metal layer 120, and a connection between upper bitline routing 2336 in the upper metal layer 112 and bitline input 2326B in the backside metal layer 120. FIG. 30 shows a top plan view of an area having dummy cell 2350, according to some embodiments. FIG. 31 shows a backside plan view of an area having dummy cell 2350, according to some embodiments. FIG. 32 shows a cross-sectional view of an area having dummy cell 2350 along line A-A' shown in both FIGS. 30 and 31. FIG. 33 shows a cross-sectional view of an area having dummy cell 2350 along line B-B' shown in both FIGS. 30 and 31.

[0146] 30, the top metal layer 112 in region 2800 includes routing for ground signal 2802 and signal 2804, in addition to upper bitline routing 2334 and upper bitline routing 2336. In various embodiments, the backside metal layer 120 in region 2800 includes routing for signal 2900 and power signal 2902, in addition to bitline in 2324B and bitline in 2326B, as shown in FIG. 31. In particular embodiments, dummy gates 2810 are positioned adjacent to active gates 2840 on either side of region 2800. Dummy gates 2810 can be, for example, gate cuts or other gates that isolate the areas between the dummy gates. Isolation can include, for example, preventing connection to any gate activity in the areas between dummy gates 2810.

[0147] In a particular embodiment, dummy cell 2350 includes trench metal 2820 formed between upper bitline routing 2334 and bitline input 2324B, and between upper bitline routing 2336 and bitline input 2326B, as shown in Figures 30-33. Upper bitline routing 2334, 2336 may be coupled to trench metal 2820 by vias 2830 (shown in Figures 30 and 32-33), and bitline inputs 2324B, 2326B may be coupled to trench metal 2820 by vias 2930 (shown in Figures 31-33).

[0148] Similar to dummy cells 2340, the use of trench metal 2820 for connections between the upper bitline routing 2334, 2336 and the backside bitline inputs 2324B, 2326B provides a low electrical resistance path for the bitline signals to transition from the upper metal layer 112 to the backside metal layer 120. Dummy cells 2350 provide localized traffic management for the bitline signals within logic cell region 2320 (e.g., within the peripheral region).

[0149] 25 , like first column I / O cell 2322A, bit line inputs 2324B, 2326B in second column I / O cell 2322B are inputs that are in backside metal layer 120. Therefore, second column I / O cell 2322B can receive the bit line signal in the appropriate metal layer after the bit line signal is routed to bit line input 2324B and bit line input 2326B by dummy cell 2350. Due to the various routing of bit line signals from memory cell region 2310 to logic circuit cell region 2320 through combinations of top metal layer 112 and backside metal layer, in various embodiments, column logic I / O cells 2322 in the logic circuit cell region can have unipolar connectivity in a simple fabrication scheme.

[0150] In various embodiments, column I / O cell 2322 may implement stacked transistors to provide connectivity for the various routings described above for memory device 2300. FIG. 34 shows a schematic diagram of column I / O cell 2322, according to some embodiments. In the illustrated embodiment, cell 2322 includes five PMOS transistors and two NMOS transistors. The PMOS transistors include PMOS1 transistor 3210, PMOS2 transistor 3220, PMOS3 transistor 3230, PMOS4 transistor 3240, and PMOS5 transistor 3250. The NMOS transistors include NMOS1 transistor 3260 and NMOS2 transistor 3270.

[0151] 34, various routing and connections for the transistors in cell 2322 are provided by top metal layer 112 (solid lines) and back metal layer 120 (dashed lines). In a particular embodiment, cell 2322 includes Vdd 3202, Vss 3203, PCH 3204, Rcs 3206, Wcs 3208, wordline outputs 3280A, 3280B, and sense outputs 3282A, 3282B. Vdd 3202 provides routing to the power supply for cell 2322, and Vss 3203 provides routing to ground. PCH 3204 couples PMOS1 transistor 3210, PMOS2 transistor 3220, and PMOS3 transistor 3230 to form a precharge circuit. Rcs 3206 couples PMOS4 transistor 3240 and PMOS5 transistor 3250 for the read column select circuit, and Wcs 3208 couples NMOS1 transistor 3260 and NMOS2 transistor 3270 for the write column select circuit. Wordline outputs 3280A, 3280B provide the write output from cell 2322, and sense outputs 3282A, 3282B provide the read output from cell 2322.

[0152] In particular embodiments, the transistors in cell 2322 may be formed by stacked transistors as described herein. For example, a PMOS transistor is formed in a lower transistor region and an NMOS transistor is formed in an upper transistor region. Figure 35 shows a layout of cell 2322, according to some embodiments. In Figure 35, the top view is a top plan view of the upper transistor region 3300, and the bottom view is a backside plan view of the lower transistor region 3350. The upper transistor region 3300 includes an upper active region 3302, and the lower transistor region 3350 includes a lower active region 3352.

[0153] In the illustrated embodiment of the upper transistor region 3300 of Figure 35, the upper metal layer 112 includes routing for bitline input 2324, bitline input 2326, Vss 3203, Wcs 3208, and wordline outputs 3280A, 3280B. NMOS1 transistor 3260 includes gates 3262A, 3262B, 3262C and source / drain regions 3264A, 3264B, 3264C, 3264D. NMOS2 transistor 3270 includes gates 3272A, 3272B, 3272C and source / drain regions 3267A, 3274B, 3274C, 3274D. A dummy gate 3310 (e.g., a gate cut) separates NMOS1 transistor 3260 and NMOS2 transistor 3270. Via 3312 connects gate 3262 and gate 3272 using Wcs 3208. Via 3312 also connects source / drain regions 3264A and 3264C to word line output 3280A and connects source / drain regions 3274B and 3274D to word line output 3280B. Yet further vias 3312 connect source / drain regions 3264B and 3264D to bit line input 2324 and connect source / drain regions 3274A and 3274C to bit line input 2326.

[0154] In the illustrated embodiment of the lower transistor region 3350 of Figure 35, the backside metal layer 120 includes routing for bitline input 2324, bitline input 2326, Vdd 3202, PCH 3204, Rcs 3206, and sense outputs 3282A, 3282B. PMOS1 transistor 3210 includes gate 3212 and source / drain regions 3214A, 3214B. PMOS2 transistor 3220 includes gate 3222 and source / drain regions 3214B, 3214C. PMOS2 transistor 3230 includes gate 3232 and source / drain regions 3214C, 3214D. A dummy gate 3320 then separates source / drain region 3214D and PMOS2 transistor 3230 from source / drain region 3244A in PMOS4 transistor 3240. PMOS4 transistor 3240 includes a gate 3242 and source / drain regions 3244A, 3244B. Another dummy gate 3320 then separates PMOS4 transistor 3240 from PMOS5 transistor 3250. PMOS5 transistor 3250 includes a gate 3252 and source / drain regions 3254A, 3254B.

[0155] Via 3322 connects gate 3212, gate 3222, and gate 3232 by PCH 3204. Via 3322 also connects gates 3242 and 3252 using Rcs 3206. A further via 3322 connects source / drain region 3244B to sense output 3282A and source / drain region 3254B to sense output 3282B. Yet further vias 3322 connect source / drain region 3214B and source / drain region 3244A to bit line input 2324 and source / drain region 3214C ​​and source / drain region 3254A to bit line input 2326. Vdd is connected to source / drain region 3214A and source / drain region 3214D by additional via 3322.

[0156] In some embodiments, source / drain region 3214B in lower transistor region 3350 is merged with source / drain region 3264B in upper transistor region 3300 by source / drain merge 3290A. Additionally, source / drain region 3254A may be merged with source / drain region 3274C by source / drain merge 3290B. These source / drain region merges provide the necessary connection between the NMOS and PMOS transistors.

[0157]

[00130] The embodiments of memory device 2300 described herein provide a memory device that can provide strong signal connectivity using current layout techniques without a significant area penalty. Routing within memory device 2300 utilizes bit line routing through top and bottom metal layers to avoid metal routing congestion within the device. Memory device 2300 also utilizes various routing and connection paths described herein to avoid typical complexities associated with unipolar device fabrication. The various connection paths described herein can also reduce resistance within memory device 2300, thus improving the read / write speed and performance of the memory device. Vertical Transistor Cell

[0158] A recent development in transistor design is the implementation of vertical transistors, in which the cell has vertical transport through vertically displaced source / drain regions, with the gate located vertically between the source / drain regions. Current vertical transistor designs typically include wide front (e.g., top) power rails at the cell boundary for power delivery. However, these wide power rails result in increased, larger standard cell heights. The increased standard cell height reduces the area efficiency of the vertical transistor while also reducing the transistor's available connectivity and performance.

[0159] The present disclosure contemplates various embodiments that utilize backside power routing in vertical transistor designs to reduce scaling, provide better connectivity, and provide better transistor performance. Particular embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) a top metal layer above the transistor region of the vertical transistor with signal routing; 3) a backside metal layer below the transistor region with power routing; and 4) a metal contact layer between the backside metal layer and the source / drain regions of the transistor. In particular embodiments, the transistors are complementary transistors. In some embodiments, vias couple the power routing in the backside metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routing may also be contemplated in various embodiments.

[0160] In various embodiments, various contacts or vias are used to form connections for control signals and power signals to implement logic associated with a particular integrated circuit device having multiple vertical transistors for the cell structures described herein. For example, examples of inverter devices, NAND devices, and MUX devices that may be implemented based on the vertical transistor cell structures are described below. Various possible connection embodiments for control signals and voltage signals to the vertical transistors within the cell structures are also described. Those skilled in the art will understand that based on the vertical transistor structures within the cell structures disclosed herein, combinations of these various possible connections can be implemented to generate many different desired circuits.

[0161] In summary, the inventors have recognized that implementing backside routing for power connections in combination with vertical transistors provides various opportunities for building specific transistor designs with reduced scaling. Additionally, various techniques are implemented to provide specific routing for control signals and power routing within cell structures having vertical transistors as described herein. Implementation of the various disclosed techniques contemplates vertical transistor cell structures that provide improved performance at small scale factors.

[0162] Figure 36 shows a perspective view of a contemplated vertical transistor device, according to some embodiments. Figure 37 shows a perspective view of another contemplated vertical transistor device, according to some embodiments. It should be noted that device 3400 shown in Figure 36 and device 3500 shown in Figure 37 are general representations of vertical transistor-based device structures and do not show the various connections that can be made to the structure. Exemplary embodiments of connected structures are further disclosed herein below with respect to Figures 38-54.

[0163] In the illustrated embodiment of FIG. 36 , device 3400 includes two vertical transistors 3410, 3420. In particular embodiments, transistors 3410, 3420 are complementary transistors. For example, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Similarly, transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, gate 3414 and gate 3424 are fin gates. In various embodiments, gate 3414 includes a gate spacer 3415, and gate 3424 includes a gate spacer 3425. To simplify the drawings, gate spacers 3415, 3425 are not labeled in the remaining figures.

[0164] 36, the lower source / drain region, the gate, and the upper source / drain region are stacked vertically across the transistor. As further shown, transistor 3410 and transistor 3420 are parallel and have a spacing (e.g., distance) between them in the horizontal (e.g., horizontal) direction of device 3400.

[0165] In particular embodiments, transistor 3410 includes a top contact 3418 coupled to top source / drain region 3416, and transistor 3420 includes a top contact 3428 coupled to top source / drain region 3426. Contact 3418 and contact 3428 may be, for example, metal contacts for contacting various resources in a first metal layer disposed above transistors 3410 and 3420. For example, as shown in FIG. 36 , contact 3418 may be routed to a resource by route 3430 (e.g., routing shown by a dotted line). Route 3430 may be, for example, a metal layer route path in the first metal layer above transistors 3410 and 3420. It should be noted that the dotted depiction of route 3430 is provided as an example of one resource (e.g., routing) in a metal layer, and that a metal layer may include multiple resources (e.g., multiple routings). Furthermore, only the first metal layer above transistor 3410 and transistor 3420 is shown; there may be multiple additional metal routings above route 3430.

[0166] In various embodiments, transistor 3410 includes a bottom contact 3419 coupled to bottom source / drain region 3412, and transistor 3420 includes a bottom contact 3429 coupled to bottom source / drain region 3422. Contacts 3419, 3429 may be, for example, metal contacts. Contacts 3419, 3429 may be utilized to route to a backside power routing layer (e.g., backside power routing 3440A or backside power routing 3440B as shown in FIG. 36 and described herein) or to various other resources within device 3400.

[0167] In a particular embodiment, device 3400 includes a backside power layer. In the illustrated embodiment of Figure 36, the backside power layer includes backside power routing 3440A and backside power routing 3440B. Routing 3440A and routing 3440B may, for example, provide routing to and from power (e.g., Vdd) and ground (e.g., Vss) resources for device 3400.

[0168] In various embodiments, gate 3414 and gate 3424 are interconnected by gate bridge 3450. Gate bridge 3450 may be formed, for example, by extending the gate material of gate 3414 and gate 3424 to join the gates together. In some embodiments, gate bridge 3450 may be formed by a single extension of gate material extending from either gate 3414 or gate 3424 to the other gate. Gate bridge 3450 may also include an extension of material for a gate spacer. Gate bridge 3450 merges gate 3414 and gate 3424 for implementation of transistor 3410 and transistor 3420 in various embodiments of CMOS devices, some examples of which are described herein. Various embodiments in which gate 3414 and / or gate 3424 extend in other directions may also be contemplated. For example, the gate may include an extension that extends toward the outer boundary of the device 3400 (eg, in the opposite direction from the gate bridge 3450, toward the outer boundary of the cell structure).

[0169] In the illustrated embodiment of FIG. 37 , device 3500 does not have a gate bridge connecting gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Various techniques for connecting transistors 3410 and 3420 without a gate bridge are contemplated. For example, in one contemplated embodiment, contact 3418 and contact 3428 may be connected by strap 3510. Strap 3510 may be, for example, a metal strap. In some embodiments, contact 3418, contact 3428, and strap 3510 may be formed as a single contact (e.g., a single strap connecting upper source / drain region 3416 and upper source / drain region 3426). Various embodiments are also contemplated in which strap 3510 extends in another direction from one of contacts 3418, 3428. For example, strap 3510 may extend orthogonally to the illustrated embodiment toward another vertical transistor or resource within device 3500.

[0170] In another contemplated embodiment, contact 3419 and contact 3429 may be connected by strap 3520. Strap 3520 may also be a metal strap. In some embodiments, strap 3520 is formed with contact 3419 and contact 3429 as a single contact. For example, strap 3520, contact 3419, and contact 3429 may be part of a single metal contact plate formed in a contact layer. Various embodiments may also be contemplated in which contact 3419 and / or contact 3429 extend outward from the bottom of transistor 3410, 3420. For example, the contact may have a portion that extends toward an outer boundary of device 3500 (e.g., toward an outer boundary of the cell structure).

[0171] While the various connection structures are shown separately in device 3400 shown in FIG. 36 and device 3500 shown in FIG. 37 , it should be understood that embodiments may be contemplated in which structures from device 3400 are combined with structures from device 3500 in a cell design. For example, a device may be contemplated that includes both gate bridge 3450 and one or both of strap 3510 and strap 3520. Various exemplary device cell configurations based on device 3400 and / or device 3500 will now be described by way of example. It should be noted that the various device cell structures are provided as examples, and that various additional device cell structures may be implemented based on the description herein.

[0172] 38-42 show diagrams of inverter cell structures, according to some embodiments. FIG. 38 shows a perspective view of an inverter cell structure, according to some embodiments. FIG. 39 shows a top plan view of an inverter cell structure, according to some embodiments. FIG. 40 shows a back plan view of an inverter cell structure, according to some embodiments. FIG. 41 shows a cross-sectional view of an inverter cell structure along line 41-41 shown in FIG. 39 (e.g., along the gate bridge) according to some embodiments. FIG. 42 shows a cross-sectional view of an inverter cell structure along line 42-42 shown in FIG. 39 (e.g., perpendicular to the gate fin of transistor 3410) according to some embodiments.

[0173] Inverter cell device 3600 can be derived from the structure of device 3400 shown in Figure 36. In the illustrated embodiment of Figures 38-42, device 3600 includes vertical transistor 3410 and vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, an upper source / drain region 3416, an upper contact 3418, and a lower contact 3419. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, an upper source / drain region 3426, an upper contact 3428, and a lower contact 3429. In the illustrated embodiment of device 3600, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0174] In a particular embodiment, device 3600 includes backside vias 3610A, 3610B. Backside via 3610A is coupled to lower source / drain region 3412 via bottom contact 3419. Backside via 3610A couples lower source / drain region 3412 to backside power routing 3440A. For device 3600, backside power routing 3440A provides power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410. Backside via 3610B is coupled to lower source / drain region 3422 via bottom contact 3429. Backside via 3610B couples lower source / drain region 3422 to backside power routing 3440B. For device 3600, backside power routing 3440B provides ground (e.g., Vss) to lower source / drain region 3422 and transistor 3420.

[0175] In various embodiments, device 3600 includes upper vias 3620A, 3620B. Upper via 3620A may be coupled to upper source / drain region 3416 via top contact 3418, and upper via 3620B may be coupled to upper source / drain region 3426 via top contact 3428. Upper vias 3620A, 3620B may provide connections to signal routing resources (e.g., routes 3430A-E) in the first metal layer above transistors 3410 and 3420. For example, in the illustrated embodiment, upper via 3620A is coupled to route 3430B, and upper via 3620B is coupled to route 3430D. Routes 3430B and 3430D may provide routes for output signals from transistors 3410 and 3420, respectively.

[0176] In particular embodiments, a route for an input signal to transistor 3410 and transistor 3420 is provided by route 3430C. As shown in Figures 38 and 39, route 3430C is coupled to gate via 3630, which is coupled to gate bridge 3450. Thus, gate via 3630 provides a connection between route 3430C (e.g., an input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. By connecting to the input signal route, the output signal route, and the power / ground route, transistor 3410 and transistor 3420 are connected to form inverter cell device 3600.

[0177] 38 and 39 show five routes 3430A-E in the first metal layer above transistors 3410 and 3420, it should be noted that the first metal layer may include additional routes. Furthermore, additional metal layers may be disposed above the first metal layer to provide various connections to either the first metal layer or device 3600. For example, in one embodiment, the metal layer above the first metal layer may include a strap (or other connector) that couples route 3430B and route 3430D such that the outputs of transistors 3410 and 3420 are merged together into a single output. Additionally, while two backside power routings (e.g., routing 3440A and routing 3440B) are shown, the backside power layer may include additional routings (e.g., routings for other power and signal resources).

[0178] The top and back plan views of device 3600 shown in Figures 39 and 40 further show gate fins that may be present on the gates of the transistor. For example, gate fin 3415 is the gate fin for gate 3414, and gate fin 3425 is the gate fin for gate 3424. Gate fin 3415 and gate fin 3425 are also shown in the cross-sectional view of device 3600 in Figure 41, and gate fin 3415 is shown in the cross-sectional view of transistor 3410 in Figure 42. Note that the cross-sectional view in Figure 42 is perpendicular to the gate fins of transistor 3410, which is in the direction of route 3430B shown in Figures 38 and 39.

[0179] 43-47 show diagrams of NAND cell structures, according to some embodiments. FIG. 43 shows a perspective view of a NAND cell structure, according to some embodiments. FIG. 44 shows a top plan view of a NAND cell structure, according to some embodiments. FIG. 45 shows a back plan view of a NAND cell structure, according to some embodiments. FIG. 46 shows a cross-sectional view of a NAND cell structure along line 46-46 shown in FIG. 44 (e.g., along gate bridge 3450′), according to some embodiments. FIG. 47 shows a cross-sectional view of a NAND cell structure along line 47-47 shown in FIG. 44 (e.g., perpendicular to the gate fins of transistor 3410 and transistor 3410′), according to some embodiments.

[0180] The NAND cell device 4100 can be derived from the structure of the device 3400 shown in FIG. 36. In the illustrated embodiment of FIGS. 43-47, the device 4100 includes a vertical transistor 3410, a vertical transistor 3420, a vertical transistor 3410', and a vertical transistor 3420'. The transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. The transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. The transistor 3410' includes a lower source / drain region 3412', a gate 3414', and an upper source / drain region 3416'. The transistor 3420' includes a lower source / drain region 3422', a gate 3424', and an upper source / drain region 3426'. In the illustrated embodiment of device 4100, transistor 3410 and transistor 3410' are PMOS transistors, and transistor 3420 and transistor 3420' are NMOS transistors.

[0181] In particular embodiments, a route for an input signal to transistor 3410, transistor 3410′, transistor 3420, and transistor 3420′ is provided by route 3430C. As shown in FIGS. 43 and 44 , route 3430C is coupled to gate via 3630A, which is coupled to gate bridge 3450, and gate via 3630B, which is coupled to gate bridge 3450′. Thus, gate via 3630A provides a connection between route 3430C (e.g., an input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Gate via 3630B provides a connection between route 3430C (e.g., an input signal route) and both gate 3414′ in transistor 3410′ and gate 3424′ in transistor 3420′.

[0182] In particular embodiments, upper source / drain region 3416 of transistor 3410 and upper source / drain region 3416' of transistor 3410' are connected by contact 3418. Similarly, upper source / drain region 3426 of transistor 3420 and upper source / drain region 3426' of transistor 3420' are connected by contact 3428. In various embodiments, device 4100 includes an upper via 3620 connected to contact 3418. Upper via 3620 can provide a connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistor 3410 and transistor 3410'.

[0183] In the illustrated embodiment, only transistor 3410, transistor 3410', and transistor 3420 are connected to the backside layer. For example, as shown in Figures 42 and 45, transistor 3410 is connected to backside power routing 3440A by contact 3419 and backside via 3610A, transistor 3410' is connected to backside power routing 3440A by contact 3419' and backside via 3610A', and transistor 3420 is connected to backside power routing 3440B by contact 3429 and backside via 3610B. In various embodiments of device 4100, backside power routing 3440A supplies power (e.g., Vdd) to lower source / drain region 3412 and transistor 3410, as well as lower source / drain region 3412' and transistor 3410', while backside power routing 3440B supplies ground (e.g., Vss) to lower source / drain region 3422 and transistor 3420.

[0184] In a particular embodiment, the lower source / drain region 3422′ in the transistor 3420′ is connected to a contact 3429′ that is not connected to the backside power routing layer. The contact 3429′ extends away from the lower source / drain region 3422′ toward the boundary of the cell, as shown in FIGS. 43, 45, and 46. The contact 3429′ is then coupled to a route 3430E by a contact via 4110. The route 3430E is a route in the first metal layer above the transistor region. The contact via 4110 is a via that belongs to the cell structure of the device 4100 and is not shared with any adjacent cells along the cell boundary. In a particular embodiment, the route 3430E is a signal route in the first metal layer for signal output from the transistor 3420′. Thus, signals in the NMOS transistors (e.g., transistor 3420 and transistor 3420') are routed from the lower source / drain region 3422 (connected to ground by backside power routing 3440B), through the transistor, and through contact via 4110 to route 3430E.

[0185] In the illustrated embodiment, route 3430E provides a route for the output signals from transistor 3420 and transistor 3420′. The output signal routed through route 3430E may be combined with the output signal from route 3430B. For example, a metal layer above the first metal layer may include a strap (or other connector) that couples route 3430B and route 3430E so that the outputs of the transistors are merged together into a single output.

[0186] The various routings and connections within device 4100 form a NAND cell device. Figures 44 and 45 show gate fins 3415, 3415', 3425, and 3425' within gates 3414, 3414', 3424, and 3424', respectively. Gate fins 3415' and 3425' are also shown in the cross-sectional view of device 4100 in Figure 46, and gate fins 3415 and 3415' are shown in the cross-sectional view of device 4100 in Figure 47. Note that the cross-sectional view in Figure 47 is perpendicular to the gate fins of transistor 3410 and transistor 3410', which is in the direction of route 3430B shown in Figure 44.

[0187] 48-52 show diagrams of MUX (multiplexer) cell structures, according to some embodiments. FIG. 48 shows a perspective view of a MUX cell structure, according to some embodiments. FIG. 49 shows a top plan view of a MUX cell structure, according to some embodiments. FIG. 50 shows a back plan view of a MUX cell structure, according to some embodiments. FIG. 51 shows a cross-sectional view of a MUX cell structure along line 51-51 shown in FIG. 49 (e.g., along gate fin 3415′ and gate fin 3425″), according to some embodiments. FIG. 52 shows a cross-sectional view of a MUX cell structure along line 52-52 shown in FIG. 49 (e.g., perpendicular to the gate fins of transistor 3410 and transistor 3410″), according to some embodiments.

[0188] MUX cell device 4600 can be derived from the structure of device 3500 shown in FIG. 37. In the illustrated embodiment of FIGS. 48-52, device 4600 includes vertical transistor 3410, vertical transistor 3420, vertical transistor 3410", and vertical transistor 3420". As in device 3500, there are gate bridges between the gates of the transistors in device 4600, such that there is no common gate between complementary transistors. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410" includes a lower source / drain region 3412", a gate 3414", and an upper source / drain region 3416". Transistor 3420'' includes a lower source / drain region 3422'', a gate 3424'', and an upper source / drain region 3426''. In the illustrated embodiment of device 4600, transistors 3410 and 3410'' are PMOS transistors, and transistors 3420 and 3420'' are NMOS transistors.

[0189] Because MUX cell device 4600 is a transfer device, neither transistor 3410 nor transistor 3410" nor transistor 3420 nor transistor 3420" is connected to any power sources within the MUX cell structure. In various embodiments of MUX cell device 4600, the lower source / drain regions of the transistors are connected together (e.g., merged together). For example, in the illustrated embodiment, contact plate 4620 is connected to lower source / drain region 3412 of transistor 3410, lower source / drain region 3412" of transistor 3410", lower source / drain region 3422 of transistor 3420, and lower source / drain region 3422" of transistor 3420".

[0190] In particular embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 may be connected to contact plate 4620 at or near the center of the contact plate. Contact via 4630 then connects to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output routing for MUX cell device 4600. Thus, contact via 4630 can be referred to as an output pin of MUX cell device 4600.

[0191] In various embodiments, gates 3414, 3414", 3424, 3424" extend toward the cell boundary to provide a surface for direct vertical connection from a route in the upper first metal layer to the gate. For example, as shown in Figures 48-52, gate 3414 includes gate extension 4640A that extends toward the cell boundary (e.g., extends horizontally toward the cell boundary). Similarly, gate 3414" includes gate extension 4640B, gate 3424 includes gate extension 4640C, and gate 3424" includes gate extension 4640D. Gate extensions 4640A-D are then connected to a route in the upper first metal layer by gate vias 3630A-D, respectively. 48 and 49, gate via 3630A connects gate extension 4640A to route 3430A, gate via 3630B connects gate extension 4640B to route 3430A, gate via 3630C connects gate extension 4640C to route 3430E, and gate via 3630D connects gate extension 4640D to route 3430E. One or both of route 3430A and route 3430E are located at the boundary of the cell and are not shared with adjacent cells. Route 3430A and route 3430E may provide input routes to device 4600.

[0192] In a particular embodiment, upper source / drain region 3416 in transistor 3410 is connected to upper source / drain region 3426 in transistor 3420 by contact 4610A. This connection merges upper source / drain region 3416 into upper source / drain region 3426. Similarly, upper source / drain region 3416" in transistor 3410" is connected to upper source / drain region 3426" in transistor 3420" by contact 4610B. These merging of upper source / drain regions and the common connection between the lower source / drain regions (and single output through contact via 4630) allow device 4600 to operate as a MUX (multiplexer), with signals input through gate vias 3630A-D and output through contact via 4630.

[0193] 49 and 50 show gate fins 3415, 3415'', 3425, and 3425'' in gates 3414, 3414'', 3424, and 3424'', respectively. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 4600 in FIG. 51, and gate fins 3415 and 3415'' are shown in the cross-sectional view of device 4600 in FIG. 52. Note that the cross-sectional view in FIG. 52 is perpendicular to the gate fins of transistor 3410 and transistor 3410'', which is in the direction of route 3430B shown in FIG. 49.

[0194] Figures 53 and 54 show diagrams of a cell device with dielectric walls, according to some embodiments. Figure 53 shows a perspective view of device 5100, according to some embodiments. Figure 54 shows a cross-sectional view of device 5100 along line 54-54 shown in Figure 53 (e.g., along gate bridge 3450'), according to some embodiments.

[0195] Device 5100 can be derived from the structure of device 3400 shown in FIG. 36. In some embodiments, device 5100 can be similar to inverter cell device 4100 shown in FIGS. 43-47. In the illustrated embodiment of FIGS. 53 and 54, device 5100 includes vertical transistor 3410 and vertical transistor 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In particular embodiments, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0196] In various embodiments, as shown in Figures 53 and 54, wall 5100A may be disposed on a first side of the cell (e.g., the side of transistor 3410) and wall 5100B may be disposed on a second side of the cell (e.g., the side of transistor 3420 opposite transistor 3410). In particular embodiments, wall 5100A and wall 5100B are dielectric walls. By disposing a dielectric wall on one or both sides of device 5100, the space required between device 5100 and another adjacent cell may be reduced. Thus, wall 5100A and wall 5100B may be implemented when device scaling needs to be reduced. Exemplary Computer System

[0197] Referring now to FIG. 55, a block diagram of one embodiment of a system 5300 is shown, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the system 5300 includes at least one instance of a system on chip (SoC) 5306, which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or other types of processing units, a communications fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors in the SoC 5306 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 5306 is coupled to external memory 5302, peripherals 5304, and a power supply 5308.

[0198] A power supply 5308 is also provided to provide a supply voltage to the SoC 5306 and to provide one or more supply voltages to the memory 5302 and / or peripherals 5304. In various embodiments, the power supply 5308 represents a battery (e.g., a rechargeable battery in a smartphone, laptop or tablet computer, or other device). In some embodiments, more than one instance of the SoC 5306 is included (and more than one external memory 5302 is included as well).

[0199] The memory 5302 may be any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices may be coupled to a circuit board to form a memory module, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the devices may be mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0200] The peripherals 5304 may include any desired circuitry, depending on the type of system 5300. For example, in one embodiment, the peripherals 5304 include devices for various wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. In some embodiments, the peripherals 5304 also include additional storage, including RAM storage, solid-state storage, or disk storage. The peripherals 5304 include user interface devices, such as a display screen, including a touch or multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc.

[0201] As shown, the system 5300 is shown to have broad application. For example, the system 5300 may be utilized as part of a chip, circuit, component, etc. in a desktop computer 5310, a laptop computer 5320, a tablet computer 5330, a cellular or mobile phone 5340, or a television 5350 (or a set-top box coupled to a television). Also illustrated is a smartwatch and a health monitoring device 5360. In some embodiments, a smartwatch may include various general-purpose computing-related functions. For example, a smartwatch may provide access to email, mobile phone service, a user calendar, etc. In various embodiments, a health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, a health monitoring device may monitor a user's vital signs, track a user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any health monitoring-related functions. Other wearable devices are also contemplated, such as devices worn around the neck, devices implantable in the human body, and glasses designed to provide an augmented and / or virtual reality experience.

[0202] The system 5300 may further be used as part of cloud-based service(s) 5370. For example, the aforementioned devices and / or other devices may access computing resources (i.e., remotely located hardware and / or software resources) in the cloud. Furthermore, the system 5300 may be utilized in one or more devices in a home 5380 other than those described above. For example, appliances in the home may monitor and detect noteworthy conditions. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) may monitor the device status and alert the homeowner (or a repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the home's temperature and automate adjustments to the heating / cooling system based on the homeowner's historical responses to various conditions. Also illustrated in FIG. 55 is the application of the system 5300 to various modes of transportation 5390. For example, the system 5300 may be used in control and / or entertainment systems for airplanes, trains, buses, rental cars, private automobiles, watercraft ranging from private boats to cruise ships, scooters (rented or owned), etc. In various cases, system 5300 can be used to provide automated guidance (e.g., for autonomous vehicles), general system control, and other methods. Many other embodiments of any of these are possible and contemplated. Note that the devices and applications illustrated in Figure 55 are merely exemplary and are not intended to be limiting. Other devices are possible and contemplated. ***

[0203] The present disclosure includes references to "one embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different implementations or examples of the disclosed concepts. References to "one embodiment," "one embodiment," "particular embodiment," etc. do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, as well as modifications or alternatives that are within the spirit or scope of the present disclosure, are contemplated.

[0204] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all of the potential advantages. Whether advantages are realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation within the scope of the claims may not exhibit some or all of any disclosed advantages. For example, a particular implementation may include other circuitry outside the scope of this disclosure that, in conjunction with one of the disclosed embodiments, negates or reduces one or more of the disclosed advantages. Furthermore, suboptimal design practices of a particular implementation (e.g., implementation techniques or tools) may also negate or reduce a disclosed advantage. Even assuming skilled practice, realization of advantages may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, resulting in the benefits of that solution not being realized. Given the existence of factors external to the present disclosure that may arise, it is expressly intended that any potential advantages described herein should not be construed as claim limitations that must be met in order to demonstrate infringement. Rather, the identification of such potential advantages is intended to illustrate the type(s) of improvement available to a designer having the benefit of the present disclosure. The fact that such advantages are permissibly described (e.g., a statement that a particular advantage "may result") is not intended to convey any doubt as to whether such advantage can actually be realized, but rather to recognize the technological reality that realization of such advantages often depends on additional factors.

[0205] Unless otherwise specified, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, not limiting, unless a statement to the contrary is present in the present disclosure. The above description is intended to enable claims that cover not only the disclosed embodiments, but also alternatives, modifications, and equivalents that will be apparent to those skilled in the art having the benefit of this disclosure.

[0206] For example, features of the present application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority to this application) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with features of other dependent claims as appropriate, including claims that are dependent on other independent claims. Similarly, features from each independent claim may be combined as appropriate.

[0207] Thus, the accompanying dependent claims may each be drafted to depend on a single other claim, although additional dependencies are also contemplated. Any combination of features in the dependent claims consistent with this disclosure is contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically recited in the accompanying claims.

[0208] Where appropriate, it is contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is also intended to support a corresponding claim in another format or statutory type (e.g., method). ***

[0209] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The public is hereby notified that the definitions provided in the following paragraphs, as well as throughout this disclosure, will be used in interpreting the claims made based on this disclosure.

[0210] Reference to a singular item (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more" unless the context clearly indicates otherwise. Thus, a reference to an "item" in a claim does not exclude additional instances of the item without context. A "plurality" of an item refers to a set of two or more items.

[0211] The word "may" is used herein in a permissive sense (i.e., having the possibility, being able to do), not in an obligatory sense (i.e., not required).

[0212] The terms "comprising" and "including" and their forms are open-ended and mean "including, but not limited to."

[0213] When the term "or" is used in this disclosure in reference to a list of alternatives, it will generally be understood to be used in an inclusive sense unless the context clearly indicates otherwise. Thus, a list of "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase "either x or y, but not both" makes clear that "or" is used in an exclusive sense.

[0214] The enumeration of "w, x, y, z, or any combination thereof," or "...at least one of w, x, y, and z" is intended to encompass all possibilities, including single elements, up to the total number of elements in the set. For example, for the set [w, x, y, z], these expressions encompass any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element of the set [w, x, y, z], thereby encompassing all possible combinations of this list of elements. This phrase should not be interpreted as requiring that there be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0215] In this disclosure, various "labels" may precede nouns or noun phrases. Unless the context clearly indicates otherwise, various labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Furthermore, when applied to features, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0216] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based only on the specified factors, or on the specified factors as well as other unspecified factors. Consider the phrase "determining A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover an embodiment in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0217] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either together with the particular factor or independently of the specified factor. That is, the effect may depend only on these factors, or on the specified factor as well as other unspecified factors. Consider the phrase "performing A in response to B." By this phrase, B is a factor that triggers the execution of A or triggers a particular result for A. This phrase does not exclude that the execution of A may also be in response to other factors, such as C. This phrase also does not exclude that performing A may be in response to both B and C. This phrase is intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to." ***

[0218] Within this disclosure, various entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This phrase "entity" configured to perform one or more tasks is used herein to refer to a structure (i.e., a physical thing). More specifically, this phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently operating. In this manner, an entity described or explained as being "configured" to perform a task refers to a physical thing, such as a device, a circuit, a system having a processor unit and a memory storing executable program instructions to perform the task. This phrase is not used herein to refer to an intangible thing.

[0219] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations, and even if not specifically described, it will be understood that those entities are "configured to" perform those tasks / operations.

[0220] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered to be "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After appropriate programming, the FPGA can then be said to be "configured" to perform a particular function.

[0221] For purposes of U.S. patent applications based on this disclosure, reciting in a claim that a structure is "configured to" perform one or more tasks is expressly intended to invoke 35 U.S.C. §112(f) for that claim element. not present If an applicant, based on this disclosure, wishes to invoke Section 112(f) during prosecution of a U.S. patent application, it would use "means for" to recite claim elements.

[0222] Various "circuits" may be described in this disclosure. These circuits or "circuitry" comprise hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Particular types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0223] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform this function. This specification of this function is sufficient to suggest a set of possible configurations of the circuit to one skilled in the computer arts.

[0224] In various embodiments, as described in the previous paragraph, circuits, units, and other elements are defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to one another and the way they interact form a microarchitecture definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with a microarchitecture definition provided in accordance with this disclosure can, without undue experimentation, implement the structure by coding the circuit / unit / component description into a hardware description language (HDL), such as Verilog or VHDL, using ordinary techniques. HDL descriptions are often expressed in a manner that appears to be functional. However, to those skilled in the art, this HDL description is the method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions may take the form of behavioral-level code (which is typically not synthesizable), register transfer language (RTL) code (which, in contrast to behavioral-level code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry to generate masks and ultimately manufacture the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuit.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected together to realize a hardware circuit, and / or some embodiments may use discrete elements. Alternatively, the HDL design may be integrated into or implemented in a programmable logic array, such as a field programmable gate array (FPGA). This decoupling between the design of a group of circuits and the subsequent lower-level implementation of those circuits generally results in a scenario where the circuit or logic designer does not specify any particular set of structures for the lower-level implementation other than describing how the circuit is configured, since this process is performed at a different stage in the circuit implementation process.

[0225] The fact that many different low-level combinations of circuit elements can be used to implement the same specification for a circuit results in numerous equivalent structures for that circuit. As noted above, these low-level circuit implementations may vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methods to generate these different implementations may be arbitrary.

[0226] Furthermore, for a given embodiment, it is common for a single implementation of a circuit's particular functional specifications to include a large number of devices (e.g., millions of transistors). Thus, this absolute amount of information makes it impractical to exhaustively enumerate the low-level structures used to implement a single embodiment, let alone the vast number of equivalent possible implementations. For this reason, this disclosure describes the structure of a circuit using functional abbreviations used in the industry.

Claims

1. a first transistor formed within a transistor region of the integrated circuit cell structure, the first transistor having a first active region, a first gate, and first source / drain regions within the transistor region; a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, and second source / drain regions within the transistor region, at least a portion of the second active region disposed vertically below the first active region and perpendicular to the transistor region; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including a first signal routing connected to the first transistor; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including second signal routing connected to the second transistor and including power routing connected to the second transistor.

2. 2. The apparatus of claim 1, wherein the first signal routing in the first metal layer is connected to a signal input of the first gate in the first transistor.

3. 2. The device of claim 1, wherein the second signal routing in the second metal layer is connected to at least one second source / drain region in the second transistor.

4. The device of claim 1 , wherein the power routing in the second metal layer is connected to at least one second source / drain region in the second transistor.

5. 2. The device of claim 1, wherein a portion of the first active region that forms the first gate contacts a portion of the second active region that forms the second gate.

6. 6. The apparatus of claim 5, wherein the first signal routing in the first metal layer is connected to a signal input of the first gate in the first transistor.

7. 2. The device of claim 1, wherein the portion of the first active region that forms the first gate is separated from the portion of the second active region that forms the second gate.

8. 8. The apparatus of claim 7, wherein the first signal routing in the first metal layer is connected to a signal input of the first gate in the first transistor, and the second signal routing in the second metal layer is connected to a signal input of the second gate in the second transistor.

9. The apparatus of claim 1 , wherein the first metal layer includes power routing connected to the first transistor.

10. a via connected to the power routing or the signal routing in the second metal layer and arranged in a horizontal direction perpendicular to the vertical direction outside the first active area and the second active area, the via connecting the power routing or the signal routing in the second metal layer to the power routing or the signal routing in the first metal layer; a contact via coupled between the power routing or the signal routing in the first metal layer and at least one first source / drain region in the first transistor, such that the power routing or the signal routing in the second metal layer is connected to the first transistor; The apparatus of claim 1 further comprising:

11. 2. The apparatus of claim 1, wherein the first transistor and the second transistor are complementary transistor types.

12. a via connected to the power routing or the signal routing in the second metal layer and arranged in a horizontal direction perpendicular to the vertical direction outside the second active area; source / drain contacts connected to at least one second source / drain region, the source / drain contacts being disposed in the vertical direction above the second active region and at least a portion of the source / drain contacts extending in the horizontal direction outside the second active region, such that the source / drain contacts connect to the vias, which connect the power routing or the signal routing in the second metal layer to the at least one second source / drain region; The apparatus of claim 1 further comprising:

13. A plurality of integrated circuit cell structures, at least one of the integrated circuit cell structures comprising: a first transistor formed within a transistor region of the integrated circuit cell structure, the first transistor having a first active region, a first gate, and first source / drain regions within the transistor region; a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, and second source / drain regions within the transistor region, at least a portion of the second active region disposed vertically below the first active region and perpendicular to the transistor region; and a first metal layer positioned in the vertical direction above the transistor region; a second metal layer positioned in the vertical direction below the transistor region; a plurality of via pillars disposed on the periphery of the integrated circuit cell structure, the via pillars extending in the vertical direction through the transistor region between the first metal layer and the second metal layer, at least some of the via pillars being disposed on both sides of the first active area and the second active area, with alternating via pillars on one side belonging alternately to the at least one integrated circuit cell structure and an adjacent integrated circuit cell structure; An apparatus comprising:

14. 14. The apparatus of claim 13, wherein the first metal layer includes a first signal routing connected to the first transistor, and the second metal layer includes a second signal routing connected to the second transistor.

15. 14. The apparatus of claim 13, wherein the first metal layer includes a first power routing connected to the first transistor, and the second metal layer includes a second power routing connected to the second transistor.

16. 14. The apparatus of claim 13, further comprising a contact between a signal input of the first gate and at least one of the via pillars belonging to the at least one integrated circuit cell structure, the contact formed in the transistor region.

17. 14. The apparatus of claim 13, further comprising a contact between a signal input of the second gate and at least one of the via pillars belonging to the at least one integrated circuit cell structure, the contact being formed in the transistor region.

18. 14. The apparatus of claim 13, further comprising a contact between a drain region of the first transistor and at least one of the via pillars belonging to the at least one integrated circuit cell structure, the contact being formed in the transistor region.

19. 14. The apparatus of claim 13, further comprising a contact between a drain region of the second transistor and at least one of the via pillars belonging to the at least one integrated circuit cell structure, the contact being formed in the transistor region.

20. a first transistor formed within a transistor region of the integrated circuit cell structure, the first transistor having a first active region, a first gate, one or more first source regions, and one or more first drain regions within the transistor region; a second transistor formed in the transistor region, the second transistor having a second active region, a second gate, one or more second source regions, and one or more second drain regions within the transistor region, at least a portion of the second active region disposed vertically below the first active region and perpendicular to the transistor region; a first metal layer positioned in the vertical direction above the transistor region, a first set of signal routing paths; and a first metal layer including a first set of power routing paths; a second metal layer positioned in the vertical direction below the transistor region, a second set of signal routing paths; and a second metal layer including a second set of power routing paths; at least one gate contact formed in the transistor region, the at least one gate contact providing a connection between a signal input for one of the first gate or the second gate and a signal routing path from one of the first set of signal routing paths or the second set of signal routing paths; at least one source power contact formed in the transistor region, the at least one source power contact providing a connection between a source region from one of the first source region or the second source region and a power routing path from one of the first set of power routing paths or the second set of power routing paths; at least one drain power contact formed in the transistor region, the at least one drain power contact providing a connection between a drain region from one of the first drain region or the second drain region and a power routing path from one of the first set of power routing paths or the second set of power routing paths; An apparatus comprising:

21. a first transistor region of an integrated circuit cell structure, the first transistor region having a first active area and a second active area parallel to the first active area, the second active area having a first distance separating the first and second active areas; a second transistor region of the integrated circuit cell structure, the second transistor region having a third active region and a fourth active region parallel to the third active region, the fourth active region having a second distance separating the third active region and the fourth active region, at least a portion of the second transistor region being disposed vertically of the integrated circuit cell structure below the first transistor region, the second transistor region being complementary to the first transistor region; a first inverter, a first transistor having a first gate formed in the first active region, the first gate having a first source / drain region and a second source / drain region on either side of the first gate; a second transistor having a second gate formed in the third active region, the second gate having a third source / drain region and a fourth source / drain region on either side of the second gate, the third source / drain region merging into the first source / drain region and the fourth source / drain region merging into the second source / drain region, and a portion of the second gate extending below the first transistor region; a second inverter, a third transistor having a third gate formed in the second active region, the third gate having a fifth source / drain region and a sixth source / drain region on either side of the third gate; a fourth transistor having a fourth gate formed in the fourth active region, the fourth gate having seventh and eighth source / drain regions on either side of the fourth gate, the seventh source / drain region merging into the fifth source / drain region, the eighth source / drain region merging into the sixth source / drain region, and a portion of the fourth gate extending below the first transistor region; the first inverter is cross-coupled to the second inverter by a first coupling between the portion of the second gate that extends below the second active region and the seventh source / drain region and a second coupling between the portion of the fourth gate that extends below the first active region and the fourth source / drain region, the first coupling and the second coupling being disposed in the vertical direction below the second transistor region; Memory device.

22. 22. The memory device of claim 21 further comprising: a first pass gate coupled to a word line, the first pass gate formed in the second active area and having the fifth source / drain region and a ninth source / drain region on either side of the first pass gate, the ninth source / drain region coupled to a first bit line.

23. 23. The memory device of claim 22, wherein the portion of the second gate that extends below the first transistor region is disposed below the first pass gate.

24. 23. The memory device of claim 22, further comprising: a second pass gate coupled to the word line, the second pass gate formed in the first active area and having the second source / drain region and a tenth source / drain region on either side of the second pass gate, the tenth source / drain region coupled to a second bit line, the second bit line being complementary to the first bit line.

25. 25. The memory device of claim 24, wherein the portion of the fourth gate that extends below the first transistor region is disposed below the second pass gate.

26. 22. The memory device of claim 21, further comprising a metal layer positioned vertically below the second transistor region, the metal layer including power routing connected to the first inverter and the second inverter.

27. a first backside via coupling the power routing in the metal layer to the third source / drain region; a second backside via coupling the power routing in the metal layer to the eighth source / drain region; 27. The memory device of claim 26, further comprising:

28. 22. The memory device of claim 21, further comprising a metal layer positioned vertically above the first transistor region, the metal layer including signal routing connected to the first inverter and the second inverter.

29. 22. The memory device of claim 21, wherein the first inverter is cross-coupled to the second inverter such that an output of the first inverter is provided as an input to the second inverter and an output of the second inverter is provided as an input to the first inverter.

30. 22. The memory device of claim 21, wherein the third active area is disposed below the first active area and the fourth active area is disposed below the second active area.

31. 22. The memory device of claim 21, wherein the first distance is substantially the same as the second distance.

32. 22. The memory device of claim 21, wherein the portion of the second gate that extends below the first transistor region extends to an inactive portion of the fourth active region.

33. 22. The memory device of claim 21, wherein the portion of the fourth gate that extends below the first transistor region extends to an inactive portion of the third active region.

34. 34. The memory device of claim 33, wherein the inactive portion of the third active region is free of diffusion material.

35. a first gate merge via connecting the first gate and the second gate; a second gate merge via coupling the third gate and the fourth gate; 22. The memory device of claim 21 further comprising:

36. a first transistor region of an integrated circuit cell structure, the first transistor region having a first active area and a second active area parallel to the first active area, the second active area having a first distance separating the first and second active areas; a second transistor region of the integrated circuit cell structure, the second transistor region having a third active region and a fourth active region parallel to the third active region, the fourth active region having a second distance separating the third active region and the fourth active region, at least a portion of the second transistor region being disposed vertically of the integrated circuit cell structure below the first transistor region, the second transistor region being complementary to the first transistor region; a first pass gate formed in the second active region, the first pass gate coupled to a word line and a source / drain region of the first pass gate coupled to a first bit line; a second pass gate formed in the first active region, the second pass gate coupled to the word line, the source / drain regions of the second pass gate coupled to a second bit line complementary to the first bit line; a first inverter formed by a first transistor in the first active area and a second transistor in the third active area, wherein inputs of the first transistor and the second transistor are merged, outputs of the first transistor and the second transistor are merged, and a portion of the second transistor extends in the vertical direction below the first pass gate; a second inverter formed by a third transistor in the second active area and a fourth transistor in the fourth active area, wherein inputs of the third transistor and the fourth transistor are merged, outputs of the third transistor and the fourth transistor are merged, and a portion of the fourth transistor extends in the vertical direction below the second pass gate; a first coupling between the portion of the second transistor extending below the second pass gate and a source / drain region of the fourth transistor, the first coupling being disposed in the vertical direction below the second transistor region; a second coupling between the portion of the fourth transistor extending below the first pass gate and a source / drain region of the second transistor, the second coupling being disposed in the vertical direction below the second transistor region; and A memory device comprising:

37. 37. The memory device of claim 36, wherein the first inverter is cross-coupled to the second inverter by the first coupling and the second coupling.

38. 37. The memory device of claim 36, further comprising a metal layer positioned vertically below the second transistor region, the metal layer including power routing connected to the first inverter and the second inverter.

39. 39. The memory device of claim 38, wherein the first coupling and the second coupling are disposed in the vertical direction between the metal layer and the second transistor region.

40. 37. The memory device of claim 36, wherein the outputs of the third transistor and the fourth transistor are provided as the inputs of the first transistor and the second transistor, and the outputs of the first transistor and the second transistor are provided as the inputs of the third transistor and the fourth transistor.

41. a plurality of bit cells, the bit cells including a first set of first transistors formed in a first transistor region and a second set of second transistors formed in a second transistor region, the second transistor region disposed vertically below the first transistor region and perpendicular to the plurality of bit cells, the plurality of bit cells being divided into at least a first array of bit cells and a second array of bit cells; a first metal layer positioned in the vertical direction below the plurality of bit cells, the first metal layer including first routing coupled to bit line outputs of the first array of bit cells; a second metal layer positioned in the vertical direction above the plurality of bit cells, the second metal layer including second routing coupled to bit line outputs of the second array of bit cells; a first column input / output logic cell coupled to the bit line outputs of the first array of bit cells by the first routing; a second column input / output logic cell coupled to the bit line outputs of the second array of bit cells by the second routing; the first array of bit cells is positioned further away from the first column input / output logic cells and the second column input / output logic cells than the second array of bit cells. Memory device.

42. 42. The memory device of claim 41, wherein an output of the first column input / output logic cell is coupled to an output of the second column input / output logic cell.

43. 42. The memory device of claim 41, wherein the bit line outputs of the first array of bit cells comprise outputs from pairs of complementary bit lines coupled to the first array of bit cells.

44. 42. The memory device of claim 41, wherein the bit line outputs of the second array of bit cells comprise outputs from pairs of complementary bit lines coupled to the second array of bit cells.

45. 42. The memory device of claim 41, wherein the bit line outputs of the first array of bit cells and the bit line outputs of the second array of bit cells are outputs of at least some of the first transistors.

46. the bit line outputs of the first array of bit cells are coupled to pairs of bit lines disposed in the second metal layer, and the memory device comprises:

42. The memory device of claim 41, further comprising a first pair of connections between the bit lines in the second metal layer and the first routing in the first metal layer near the first array of bit cells.

47. 47. The memory device of claim 46, wherein the first pair of connections are located within a first pair of dummy cells near a boundary between the first array of bit cells and the second array of bit cells.

48. a second pair of connections between the second routing in the second metal layer near the second column input / output logic cell and an input of the second column input / output logic cell, the input of the second column input / output logic cell being disposed within the second transistor region; 42. The memory device of claim 41 further comprising:

49. 49. The memory device of claim 48, wherein the second pair of connections are located within a second dummy cell near the boundary between the first column input / output logic cell and the second column input / output logic cell.

50. 42. The memory device of claim 41, wherein the first array of bit cells is adjacent to the second array of bit cells in a horizontal direction perpendicular to the vertical direction, and the first column input / output logic cells are adjacent to the second column input / output logic cells in the horizontal direction.

51. The first column input / output logic cell comprises: a third set of first transistors formed within the first transistor region; a fourth set of second transistors formed in the second transistor region; 42. The memory device of claim 41, wherein the input of the first transistor and the input of the second transistor are merged and coupled to the bit line output of the first array of bit cells by the first routing.

52. 52. The memory device of claim 51, wherein the gates of at least two of the first transistors are coupled by routing in the second metal layer.

53. 52. The memory device of claim 51, wherein the third set of first transistors includes two first transistors and the fourth set of second transistors includes five second transistors.

54. At least one of the bit cells includes four first transistors and two second transistors, the bit cell comprising: a first pass gate formed by a first one of the first transistors; a second pass gate formed by a second one of the first transistors; a first inverter formed by a third one of the first transistors and a first one of the second transistors; a second inverter formed by a fourth one of the first transistors and a second one of the second transistors; 42. The memory device of claim 41, wherein an input of the first inverter is cross-coupled to an output of the second inverter, and an input of the second inverter is cross-coupled to an output of the first inverter.

55. 1. An input / output logic cell for a memory device, comprising: a pair of first transistors formed in a first transistor region, the first transistors including a first input source / drain region, a first output source / drain region, and a first gate; a set of five second transistors formed in a second transistor region, the second transistors including second input source / drain regions, second output source / drain regions, and second gates, the second transistor region being vertically disposed below the first transistor region; and a first metal layer positioned in the vertical direction below the second transistor region, the first metal layer including first routing coupled to bit line outputs of a first array of bit cells; a second metal layer disposed in the vertical direction above the first transistor region; the first input source / drain region of the first transistor and the second input source / drain region of the second transistor are merged, and the merged source / drain region is coupled to the bit line output of the first array of bit cells by the first routing; an input / output logic cell, wherein the gates of the pair of first transistors are coupled by routing within the second metal layer, and the gates of at least two of the second transistors are coupled by routing within the first metal layer.

56. and a second input / output logic cell for the memory device, the second input / output logic cell comprising: a second pair of first transistors formed within the first transistor region; a second set of five second transistors formed in said second transistor region.

57. 57. The input / output logic cell of claim 56, wherein the second metal layer includes a second routing coupled to the bit line outputs of a second array of bit cells, and wherein the merged source / drain regions in the second input / output logic cells are coupled to the bit line outputs of the second array of bit cells by the second routing.

58. a plurality of bit cells, the bit cells including a first set of first transistors formed in a first transistor region and a second set of second transistors formed in a second transistor region, the second transistor region disposed vertically below the first transistor region and perpendicular to the plurality of bit cells, the plurality of bit cells being divided into at least a first array of bit cells and a second array of bit cells; a first metal layer positioned in the vertical direction below the plurality of bit cells, the first metal layer including first routing; a second metal layer positioned in the vertical direction above the plurality of bit cells, the second metal layer including second routing coupled to bit line outputs of the second array of bit cells; a pair of bit lines disposed in the second metal layer, the pair of bit lines coupled to the bit line outputs of the first array of bit cells; a pair of connections between the bit lines in the second metal layer and the first routing in the first metal layer near the first array of bit cells; A memory device comprising:

59. 59. The memory device of claim 58, wherein the pair of connections is located within a pair of dummy cells near a boundary between the first array of bit cells and the second array of bit cells.

60. 60. The memory device of claim 59, wherein the pair of connections comprises trench metal within the pair of dummy cells.

61. a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having the vertically stacked lower source / drain region, a second gate, and an upper source / drain region, the second vertical transistor being parallel to the first vertical transistor and having at least some horizontal spacing between the vertical transistors; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including signal routing; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including power routing; a third metal layer disposed below the lower source / drain regions and above the second metal layer, the third metal layer including at least one metal portion contacting at least one of the lower source / drain regions; An apparatus comprising:

62. 62. The apparatus of claim 61, wherein the first vertical transistor and the second vertical transistor are complementary transistor types.

63. 62. The apparatus of claim 61, wherein the signal routing comprises signal input routing and signal output routing for the first vertical transistor and the second vertical transistor.

64. 62. The apparatus of claim 61, further comprising: a first via coupled between the at least one metal portion in the third metal layer and the power routing in the second metal layer.

65. 62. The device of claim 61, further comprising at least one via coupled between at least one upper source / drain region and the signal routing in the first metal layer.

66. 62. The device of claim 61 , wherein the at least one metal portion contacting at least one of the lower source / drain regions contacts at least one additional region of the lower source / drain regions.

67. a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, the fourth metal layer including at least one metal portion in contact with at least one of the upper source / drain regions; 62. The apparatus of claim 61, further comprising:

68. 68. The device of claim 67, wherein the at least one metal portion contacts an upper source / drain region of at least one additional vertical transistor in the integrated circuit cell structure.

69. the second vertical transistor is a complementary transistor type to the first vertical transistor, and the second gate is merged into the first gate; The third metal layer comprises: a first metal contact coupled to the lower source / drain region of the first vertical transistor; a second metal contact coupled to the lower source / drain region of the second vertical transistor; a first via coupled between the first metal contact and the power routing in the second metal layer; a second via coupled between the second metal contact and the power routing in the second metal layer; 62. The apparatus of claim 61, further comprising:

70. a first via coupled between the upper source / drain region of the first vertical transistor and the signal routing in the first metal layer; a second via coupled between the upper source / drain region of the second vertical transistor and the signal routing in the first metal layer; 70. The apparatus of claim 69, further comprising:

71. a gate bridge extending across at least some of the spacing between the vertical transistors, the gate bridge merging the first gate into the second gate; a gate via coupled between the gate bridge and the signal routing in the first metal layer; 70. The apparatus of claim 69, further comprising:

72. a first dielectric wall disposed in the horizontal direction on a first side of the first vertical transistor; a second dielectric wall disposed in the horizontal direction on a second side of the second vertical transistor, the second side of the second vertical transistor being distal from the first side of the first vertical transistor in the device; 62. The apparatus of claim 61, further comprising:

73. a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having the vertically stacked lower source / drain region, a second gate, and an upper source / drain region, the second gate being merged into the first gate, the second vertical transistor being parallel to the first vertical transistor, and having at least some first spacing between the vertical transistors in a horizontal direction; a third vertical transistor formed in the transistor region of the integrated circuit cell structure, the third vertical transistor having the vertically stacked lower source / drain region, a third gate, and an upper source / drain region; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a vertically stacked lower source / drain region, a fourth gate, and an upper source / drain region, the fourth gate being merged with the third gate, the fourth vertical transistor being parallel to the third vertical transistor, and having at least some of the first spacing between the vertical transistors in the horizontal direction; the second vertical transistor and the fourth vertical transistor are of a transistor type complementary to the first vertical transistor and the third vertical transistor, the third vertical transistor and the fourth vertical transistor are parallel to the first vertical transistor and the second vertical transistor and have at least some second spacing in the horizontal direction, the second spacing being perpendicular to the first spacing; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including signal routing; a second metal layer positioned in the vertical direction below the transistor region, the second metal layer including power routing; a third metal layer disposed below the lower source / drain region and above the second metal layer, a first metal contact coupled to the lower source / drain region of the first vertical transistor; a second metal contact coupled to the lower source / drain region of the second vertical transistor; and a third metal layer including a third metal contact coupled to the lower source / drain region of the third vertical transistor; a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, a first metal strap coupled between the upper source / drain region of the first vertical transistor and the upper source / drain region of the third vertical transistor; and a fourth metal layer including a second metal strap coupled between the upper source / drain region of the second vertical transistor and the upper source / drain region of the fourth vertical transistor; a first via coupled between the first metal contact and the power routing in the second metal layer; a second via coupled between the second metal contact and the power routing in the second metal layer; a third via coupled between the third metal contact and the power routing in the second metal layer; An apparatus comprising:

74. 74. The device of claim 73, wherein the third metal layer includes a fourth metal contact coupled to the lower source / drain region of the fourth vertical transistor, the fourth metal contact extending toward a boundary of the integrated circuit cell structure, the device further comprising a contact via coupled between the fourth metal contact and power routing and / or signal routing in the first metal layer.

75. 74. The apparatus of claim 73, further comprising a first via coupled between the first metal strap and the signal routing in the first metal layer.

76. a first gate bridge extending across at least some of the first spacing between the first vertical transistor and the second vertical transistor, the first gate merging into the second gate; a second gate bridge extending across at least some of the first spacing between the third vertical transistor and the fourth vertical transistor, the second gate bridge merging the third gate into the fourth gate; a first gate via coupled between the first gate bridge and the signal routing in the first metal layer; a second gate via coupled between the second gate bridge and the signal routing in the first metal layer; 74. The apparatus of claim 73, further comprising:

77. a first vertical transistor formed in a transistor region of the integrated circuit cell structure, the first vertical transistor having a vertically stacked lower source / drain region, a first gate, and an upper source / drain region; a second vertical transistor formed in the transistor region, the second vertical transistor having the vertically stacked lower source / drain region, a second gate, and an upper source / drain region, the second vertical transistor being parallel to the first vertical transistor and having at least some first spacing therebetween in a horizontal direction; a third vertical transistor formed in the transistor region of the integrated circuit cell structure, the third vertical transistor having the vertically stacked lower source / drain region, a third gate, and an upper source / drain region; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source / drain region, a fourth gate, and an upper source / drain region stacked in the vertical direction, the fourth vertical transistor being parallel to the third vertical transistor and having at least some of the first spacing between the vertical transistors in the horizontal direction; the second vertical transistor and the fourth vertical transistor are of a transistor type complementary to the first vertical transistor and the third vertical transistor, the third vertical transistor and the fourth vertical transistor are parallel to the first vertical transistor and the second vertical transistor and have at least some second spacing in the horizontal direction, the second spacing being perpendicular to the first spacing; a first metal layer positioned in the vertical direction above the transistor region, the first metal layer including signal routing; a third metal layer disposed below the lower source / drain region; a third metal layer including metal contact plates coupled to the lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor; a fourth metal layer disposed above the upper source / drain regions and below the first metal layer, a first metal strap coupled between the upper source / drain region of the first vertical transistor and the upper source / drain region of the second vertical transistor; and a fourth metal layer including a second metal strap coupled between the upper source / drain region of the third vertical transistor and the upper source / drain region of the fourth vertical transistor; An apparatus comprising:

78. a first gate extension extending in the horizontal direction from the first gate toward a boundary of the integrated circuit cell; a second gate extension extending in the horizontal direction from the second gate toward the boundary of the integrated circuit cell, the second gate extension extending toward the boundary in an opposite direction from the first gate extension; a third gate extension extending in the horizontal direction from the third gate toward the boundary of the integrated circuit cell, the third gate extension extending toward the boundary in the same direction as the first gate extension; a fourth gate extension extending in the horizontal direction from the fourth gate toward the boundary of the integrated circuit cell, the fourth gate extension extending toward the boundary in the same direction as the second gate extension; 78. The apparatus of claim 77, further comprising:

79. a first gate via coupled between the first gate extension and the signal routing in the first metal layer; a second gate via coupled between the second gate extension and the signal routing in the first metal layer; a third gate via coupled between the third gate extension and the signal routing in the first metal layer; a fourth gate via coupled between the fourth gate extension and the signal routing in the first metal layer; 79. The apparatus of claim 78, further comprising:

80. 78. The apparatus of claim 77, further comprising a contact via coupled between the metal contact plate and the signal routing in the first metal layer.

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