Package and device including the package

Abstract

1. A package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS)

[0001] This application claims priority to and the benefit of non-provisional patent application Ser. No. 17 / 952,163, filed with the United States Patent and Trademark Office on September 23, 2022, the entire contents of which are incorporated herein by reference as if fully set forth below and for all applicable purposes. [Background technology]

[0002] Field Various aspects relate to a package comprising an integrated device, a chiplet, and a metallization portion.

[0003] background

[0003] A package may include a substrate, an integrated device, and a passive device. These components are coupled together to provide a package that can perform various electrical functions. How the integrated device, the substrate, and the passive devices are coupled together affects how the package functions as a whole. There is a continuing need to provide packages with better performance. Summary of the Invention

[0004] Various features relate to a package that includes an integrated device, a chiplet, and a metallization portion.

[0005]

[0005] One example provides a package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located within the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.

[0006]

[0006] Another example provides a package comprising: a first metallization portion, a first chiplet coupled to the first metallization portion, an encapsulation layer coupled to the first metallization portion and the first chiplet, a plurality of encapsulation interconnects located within the encapsulation layer, a second metallization portion coupled to the encapsulation layer, the first chiplet, and the plurality of encapsulation interconnects, a second chiplet coupled to the second metallization portion, and a first integrated device coupled to the second chiplet and the second metallization portion such that the second chiplet is located between the first integrated device and the second metallization portion, the first integrated device being coupled to the second chiplet via a plurality of solder interconnects.

[0007]

[0007] Another example provides a package comprising a substrate including at least one dielectric layer and a plurality of interconnects, a bridge located within the substrate, a first chiplet coupled to the substrate, a second chiplet, an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet, a plurality of encapsulation interconnects located within the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects, and a first integrated device coupled to the metallization portion. [Brief explanation of the drawings]

[0008]

[0008] Various features, properties, and advantages may become apparent by reading the "Form for Implementing the Invention" set forth below in conjunction with the drawings in which like reference characters identify corresponding parts throughout. [Figure 1]

[0009] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 2]

[0010] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 3]

[0011] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 4]

[0012] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 5]

[0013] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 6]

[0014] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 7]

[0015] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 8]

[0016] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 9]

[0017] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 10]

[0018] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 11]

[0019] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 12]

[0020] 1 shows a cross-sectional side view of a package with an integrated device, metallization portions, and chiplets. [Figure 13]

[0021] 1 shows a cross-sectional side view of a deep trench capacitor. [Figure 14A]

[0022] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 14B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 14C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 15A]

[0023] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 15B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 15C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 16A]

[0024] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 16B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 16C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 16D] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 17A]

[0025] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 17B] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 17C] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 17D] 1 illustrates an exemplary sequence for fabricating a package comprising multiple integrated devices and metallization portions. [Figure 18A]

[0026] 1 illustrates an exemplary sequence for fabricating a substrate. [Figure 18B] 1 illustrates an exemplary sequence for fabricating a substrate. [Figure 19]

[0027] 1 shows an exemplary flow diagram of a method for fabricating a substrate. [Figure 20]

[0028] Illustrated are various electronic devices that may integrate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0029] In the following description, specific details are set forth to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will understand that aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0010]

[0030] The present disclosure describes a package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located within the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion. The package may provide a configuration with reduced electrical paths between components. Reducing the electrical paths between the first integrated device, the first chiplet, the second integrated device, and / or the second chiplet may help reduce signal and / or current latency, thereby improving package performance. As described further below, instead of one integrated device performing all of the package's functions, various functions of the package may be performed by different integrated devices and / or different chiplets. By redistributing the functionality of the package among different integrated devices and / or different chiplets, cost reductions can be achieved in producing the package while still providing a package with high performance capabilities.

[0011] Exemplary Package with Integrated Device and Chiplet

[0031] 1 shows a cross-sectional side view of a package 100 containing an integrated device and a chiplet. Package 100 includes a substrate 102, a metallization portion 104, an integrated device 107, an integrated device 109, a chiplet 101, a chiplet 103, a chiplet 105, an encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0012]

[0032] The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may be a package substrate. The chiplet 101 is coupled to the substrate 102 via a plurality of solder interconnects 110 such that a back side of the chiplet 101 faces the substrate 102. The chiplet 105 is coupled to the substrate 102 via a plurality of solder interconnects 150 such that a back side of the chiplet 105 faces the substrate 102. The chiplet 103 is coupled to the chiplet 101 and the chiplet 105 such that a front side of the chiplet 103 faces the front side of the chiplet 101 and the front side of the chiplet 105. A plurality of solder interconnects 129 are coupled to the substrate 102. The plurality of solder interconnects 129 are coupled to the plurality of interconnects 122.

[0013]

[0033] The encapsulation layer 108 is bonded to the substrate 102, the chiplet 101, the chiplet 103, and the chiplet 105. The encapsulation layer 108 may encapsulate the chiplet 101, the chiplet 103, the chiplet 105, and the plurality of encapsulation interconnects 182. The metallization portion 104 is bonded to the encapsulation layer 108 and to a rear surface of the chiplet 103. The metallization portion 104 is also bonded to the plurality of encapsulation interconnects 182. The metallization portion 104 includes at least one dielectric layer 140 (e.g., a metallization dielectric layer) and the plurality of metallization interconnects 142. The plurality of encapsulation interconnects 182 may be bonded to a front surface of the metallization portion 104 and the chiplet 105. The chiplet 101, the chiplet 103, and the chiplet 105 are located between the substrate 102 and the metallization portion 104.

[0014]

[0034] Integrated device 107 is coupled to the surface of metallization portion 104 via a plurality of solder interconnects 170. Integrated device 109 is coupled to the surface of metallization portion 104 via a plurality of solder interconnects 190.

[0015]

[0035] The chiplet 103 includes a die substrate 130, a plurality of through-substrate vias 131, an active area 132, and a die interconnect portion 134. The die interconnect portion 134 includes at least one dielectric layer 135 (e.g., a die dielectric layer) and a plurality of die interconnects 136. The active area 132 may be located within and / or on the die substrate 130. The active area 132 may include transistors and / or logic cells. The plurality of through-substrate vias 131 may extend through the thickness of the die substrate 130. The plurality of through-substrate vias 131 may be coupled to a plurality of die interconnects 136. The plurality of through-substrate vias 131 may be coupled to the active area 132. For example, the plurality of through-substrate vias 131 may be coupled to one or more transistors and / or one or more logic cells. The chiplet 103 may have a front surface and a back surface. The front side of chiplet 103 can be the side that includes die interconnects 134, and the rear side of chiplet 103 can be the side that includes die substrate 130. An electrical path through chiplet 103 can include multiple through-substrate vias 131, active area 132, and / or multiple die interconnects 136. Thus, when an electrical path includes a chiplet, as described herein, the electrical path can include at least one through-substrate via, the active area of ​​the chiplet, and / or at least one die interconnect. Other chiplets described herein can be similar to chiplet 103 and, therefore, can include the same or similar components, configurations, and / or structures. In some implementations, a chiplet may be devoid of transistors and / or logic cells. Additionally, as illustrated in at least FIG. 13 , a chiplet can include deep trench capacitors.

[0016]

[0036] Chiplet 101 may be similar to chiplet 103. For example, chiplet 101 may also include a die substrate, a plurality of through-substrate vias, an active area, and a die interconnect portion, where the die interconnect portion of chiplet 101 includes at least one dielectric layer and a plurality of die interconnects.

[0017]

[0037] Chiplet 105 may be similar to chiplet 103. For example, chiplet 105 may also include a die substrate, a plurality of through-substrate vias, and a die interconnect portion, where the die interconnect portion of chiplet 105 includes at least one dielectric layer and a plurality of die interconnects. Chiplet 105 may be devoid of transistors and / or logic cells.

[0018]

[0038] The configuration and arrangement shown in FIG. 1 provides several ways in which one or more electrical paths may extend.

[0019]

[0039] The electrical path between integrated device 107 and integrated device 109 may include at least one solder interconnect from the plurality of solder interconnects 170, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects 190.

[0020]

[0040] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0021]

[0041] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 101, chiplet 103, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0022]

[0042] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 105, chiplet 103, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0023]

[0043] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, the chiplet 105, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0024]

[0044] Chiplet 101, chiplet 105, and / or chiplet 103 may utilize any of the electrical paths described above to be electrically coupled to integrated device 107 and / or integrated device 109. As described above, electrical paths that include (e.g., pass through) a chiplet may include die interconnects and / or through-substrate vias.

[0025]

[0045] In some implementations, the electrical path between the integrated device (e.g., 107, 109) and the chiplet 101 may include at least one solder interconnect from the plurality of solder interconnects 110, at least one interconnect from the plurality of interconnects 122, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0026]

[0046] In some implementations, the electrical path between the integrated device (e.g., 107, 109) and the chiplet 105 may include at least one solder interconnect from the plurality of solder interconnects 150, at least one interconnect from the plurality of interconnects 122, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0027]

[0047] As described further below, the orientation of chiplet 101, chiplet 103, and / or chiplet 105 within the package may be rearranged for different implementations. In some implementations, a first chiplet may be coupled to a second chiplet such that the front surface of the first chiplet faces the front surface of the second chiplet. In some implementations, a first chiplet may be coupled to a second chiplet such that the front surface of the first chiplet faces the rear surface of the second chiplet. In some implementations, a first chiplet may be coupled to a second chiplet such that the rear surface of the first chiplet faces the rear surface of the second chiplet. Thus, in this disclosure, any chiplet may be coupled to another chiplet front-to-front, rear-to-rear, or front-to-rear. A chiplet may be coupled to another chiplet via hybrid bonding, where interconnects from one chiplet directly contact interconnects from another chiplet. Furthermore, in this disclosure, any chiplet may be coupled to a substrate or metallization portion through the front surface of the chiplet or through the rear surface of the chiplet. Thus, the illustrations in this disclosure are merely examples of the many ways in which one or more chiplets may be coupled to another component of a package.

[0028]

[0048] 2 shows a cross-sectional side view of a package 200 including an integrated device and a chiplet. Package 200 includes substrate 102, metallization portion 104, integrated device 107, integrated device 109, chiplet 101, chiplet 103, chiplet 105, encapsulation layer 108, and a plurality of encapsulation interconnects 182. The plurality of encapsulation interconnects 182 are coupled to substrate 102 via a plurality of solder interconnects 280.

[0029]

[0049] Chiplet 101 is coupled to substrate 102 via a plurality of solder interconnects 110, such that the rear surface of chiplet 101 faces substrate 102. Chiplet 105 is coupled to substrate 102 via a plurality of solder interconnects 150, such that the rear surface of chiplet 105 faces substrate 102. Chiplet 103 is coupled to chiplet 101 and chiplet 105, such that the front surface of chiplet 103 faces the front surface of chiplet 101 and the front surface of chiplet 105. A plurality of solder interconnects 129 are coupled to substrate 102. A plurality of solder interconnects 129 are coupled to a plurality of interconnects 122.

[0030]

[0050] The encapsulation layer 108 is bonded to the substrate 102, the chiplet 101, the chiplet 103, and the chiplet 105. The encapsulation layer 108 may encapsulate the chiplet 101, the chiplet 103, the chiplet 105, and the plurality of encapsulation interconnects 182. The metallization portion 104 is bonded to the encapsulation layer 108 and to a rear surface of the chiplet 103. The metallization portion 104 is also bonded to the plurality of encapsulation interconnects 182. The metallization portion 104 includes at least one dielectric layer 140 (e.g., a metallization dielectric layer) and a plurality of metallization interconnects 142. The plurality of encapsulation interconnects 182 may be bonded to the metallization portion 104 and to a front surface of the chiplet 105. The rear surface of the chiplet 103 is bonded to the metallization portion 104 via a plurality of solder interconnects 230. The package 200 also includes an encapsulation layer 288 positioned between the encapsulation layer 108 and the substrate 102. The encapsulation layer 288 may be considered part of the encapsulation layer 108. The encapsulation layer 288 may encapsulate the plurality of solder interconnects 110, the plurality of solder interconnects 150, and / or the plurality of solder interconnects 280.

[0031]

[0051] Integrated device 107 is coupled to the surface of metallization portion 104 via a plurality of pillar interconnects 270. Integrated device 109 is coupled to the surface of metallization portion 104 via a plurality of pillar interconnects 290.

[0032]

[0052] The electrical path between integrated device 107 and integrated device 109 may include at least one pillar interconnect from the plurality of pillar interconnects 270, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one pillar interconnect from the plurality of pillar interconnects 290.

[0033]

[0053] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one pillar interconnect from the plurality of solder interconnects (e.g., 270, 290).

[0034]

[0054] An electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 101, chiplet 103, at least one solder interconnect from the plurality of solder interconnects 230, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one pillar interconnect from the plurality of pillar interconnects (e.g., 270, 290).

[0035]

[0055] An electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 105, chiplet 103, at least one solder interconnect from the plurality of solder interconnects 230, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one pillar interconnect from the plurality of pillar interconnects (e.g., 270, 290).

[0036]

[0056] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, the chiplet 105, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one pillar interconnect from the plurality of pillar interconnects (e.g., 270, 290).

[0037]

[0057] 3 shows a cross-sectional side view of a package 300 including an integrated device and a chiplet. Package 300 includes substrate 102, metallization portion 104, integrated device 107, integrated device 109, chiplet 301, chiplet 303, chiplet 305, encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0038]

[0058] Chiplet 301 is coupled to substrate 102 via a plurality of solder interconnects 110, with the rear surface of chiplet 301 facing substrate 102. Chiplet 305 is coupled to metallization portion 104, with the rear surface of chiplet 305 facing metallization portion 104. Chiplet 305 is also coupled to chiplet 301, with the front surface of chiplet 305 facing the front surface of chiplet 301. Chiplet 303 is coupled to chiplet 301 and metallization portion 104, with the front surface of chiplet 303 facing the front surface of chiplet 301 and the rear surface of chiplet 303 facing metallization portion 104. Chiplet 301, chiplet 303, and chiplet 305 are located between substrate 102 and metallization portion 104. A plurality of solder interconnects 129 are coupled to substrate 102. A plurality of solder interconnects 129 are coupled to the plurality of interconnects 122 .

[0039]

[0059] The encapsulation layer 108 is bonded to the substrate 102, the chiplet 301, the chiplet 303, and the chiplet 305. The encapsulation layer 108 may encapsulate the chiplet 301, the chiplet 303, the chiplet 305, and the plurality of encapsulation interconnects 182. The metallization portion 104 is bonded to the encapsulation layer 108, the rear surface of the chiplet 303, and the rear surface of the chiplet 305. The metallization portion 104 is also bonded to the plurality of encapsulation interconnects 182. The metallization portion 104 includes at least one dielectric layer 140 (e.g., a metallization dielectric layer) and the plurality of metallization interconnects 142. The plurality of encapsulation interconnects 182 may be bonded to the metallization portion 104 and the front surface of the chiplet 301.

[0040]

[0060] Integrated device 107 is coupled to the surface of metallization portion 104 via a plurality of solder interconnects 170. Integrated device 109 is coupled to the surface of metallization portion 104 via a plurality of solder interconnects 190.

[0041]

[0061] Chiplet 303 may be similar to chiplet 103. For example, chiplet 301 may also include a die substrate, a plurality of through-substrate vias, an active area, and a die interconnect portion, where the die interconnect portion of chiplet 303 includes at least one dielectric layer and a plurality of die interconnects.

[0042]

[0062] Chiplet 305 may be similar to chiplet 103. For example, chiplet 301 may also include a die substrate, a plurality of through-substrate vias, an active area, and a die interconnect portion, where the die interconnect portion of chiplet 305 includes at least one dielectric layer and a plurality of die interconnects.

[0043]

[0063] Chiplet 301 may be similar to chiplet 103. For example, chiplet 105 may also include a die substrate, a plurality of through-substrate vias, and a die interconnect portion, where the die interconnect portion of chiplet 301 includes at least one dielectric layer and a plurality of die interconnects. Chiplet 301 may be devoid of transistors and / or logic cells.

[0044]

[0064] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 301, chiplet 303, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0045]

[0065] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, chiplet 301, chiplet 305, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0046]

[0066] The electrical path between the integrated device (e.g., 107, 109) and the substrate 102 may include at least one interconnect from the plurality of interconnects 122, the chiplet 301, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and at least one solder interconnect from the plurality of solder interconnects (e.g., 170, 190).

[0047]

[0067] An electrical path between substrate 102 and metallization portion 104 may extend through chiplet 301 and chiplet 303. The electrical path may extend through the rear surface of chiplet 301, through the front surface of chiplet 301, through the front surface of chiplet 303, and through the rear surface of chiplet 303.

[0048]

[0068] An electrical path between substrate 102 and metallization portion 104 may extend through chiplet 301 and chiplet 305. The electrical path may extend through the rear surface of chiplet 301, through the front surface of chiplet 301, through the front surface of chiplet 305, and through the rear surface of chiplet 305.

[0049]

[0069] An electrical path between substrate 102 and metallization portion 104 may extend through chiplet 301 and encapsulation interconnects from multiple encapsulation interconnects 182. The electrical path may extend through the rear surface of chiplet 301, through the front surface of chiplet 301, and through encapsulation interconnects from multiple encapsulation interconnects 182.

[0050]

[0070] FIG. 4 shows a package 400 including a substrate 102, a metallization portion 104, a metallization portion 106, an encapsulation layer 108, an integrated device 107, an integrated device 109, a chiplet 401, a chiplet 405, a chiplet 407, a chiplet 409, a plurality of encapsulation interconnects 182, a plurality of encapsulation interconnects 482, and / or an encapsulation layer 408, and an encapsulation layer 480.

[0051]

[0071] Chiplet 401 and chiplet 405 are located between metallization portion 104 and metallization portion 106. A rear surface of chiplet 401 is coupled to metallization portion 104 via a plurality of solder interconnects 410. A rear surface of chiplet 405 is coupled to metallization portion 104 via a plurality of solder interconnects 450. Chiplet 401 and chiplet 405 are coupled to metallization portion 106 such that a front surface of chiplet 401 and a front surface of chiplet 405 face metallization portion 106. Chiplet 401 and chiplet 405 are coupled to metallization portion 106 such that a rear surface of chiplet 401 and a rear surface of chiplet 405 face metallization portion 104. An encapsulation layer 480 is located between metallization portion 106 and substrate 102.

[0052]

[0072] Chiplet 407 and chiplet 409 are coupled to metallization portion 104 such that the front surface of chiplet 407 and the front surface of chiplet 409 face metallization portion 104. Chiplet 407 is coupled to integrated device 107 via a plurality of solder interconnects 170 such that the rear surface of chiplet 407 faces integrated device 107. Chiplet 409 is coupled to integrated device 109 via a plurality of solder interconnects 190 such that the rear surface of chiplet 409 faces integrated device 109. Integrated device 107 is coupled to metallization portion 104 via a plurality of pillar interconnects 470. Integrated device 109 is coupled to metallization portion 104 via a plurality of pillar interconnects 490.

[0053]

[0073] The encapsulation layer 408 is bonded to the metallization portion 104, the integrated device 107, the integrated device 109, the chiplet 407, and the chiplet 409. The encapsulation layer 408 may encapsulate the integrated device 107, the integrated device 109, the chiplet 407, the chiplet 409, the plurality of pillar interconnects 470, and the plurality of pillar interconnects 490.

[0054]

[0074] The electrical pathway between the metallization portion 104 and the integrated device 107 may include solder interconnects from the plurality of solder interconnects 170, the chiplet 407, and metallization interconnects from the plurality of metallization interconnects 142. The electrical pathway between the metallization portion 104 and the integrated device 107 may include pillar interconnects from the plurality of pillar interconnects 470, and metallization interconnects from the plurality of metallization interconnects 142.

[0055]

[0075] The electrical pathway between the metallization portion 104 and the integrated device 109 may include solder interconnects from the plurality of solder interconnects 190, chiplets 409, and metallization interconnects from the plurality of metallization interconnects 142. The electrical pathway between the metallization portion 104 and the integrated device 109 may include pillar interconnects from the plurality of pillar interconnects 490, and metallization interconnects from the plurality of metallization interconnects 142.

[0056]

[0076] 5 shows a cross-sectional side view of a package 500 including an integrated device and a chiplet. Package 500 is similar to package 100. However, package 500 does not include metallization portion 104 of package 100. Package 500 includes substrate 102, integrated device 107, integrated device 109, chiplet 101, chiplet 103, chiplet 105, encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0057]

[0077] The encapsulation layer 108 is bonded to the substrate 102, the chiplet 101, the chiplet 103, and the chiplet 105. The encapsulation layer 108 may encapsulate the chiplet 101, the chiplet 103, the chiplet 105, and the plurality of encapsulation interconnects 182.

[0058]

[0078] Integrated device 107 is coupled to chiplet 103 and to multiple encapsulation interconnects 182 via multiple solder interconnects 170. Integrated device 109 is coupled to chiplet 103 and to multiple encapsulation interconnects 182 via multiple solder interconnects 190.

[0059]

[0079] The electrical pathway between substrate 102 and integrated device 107 may include chiplet 101, chiplet 103, and at least one solder interconnect from plurality of solder interconnects 170. The electrical pathway between substrate 102 and integrated device 109 may include chiplet 101, chiplet 103, and at least one solder interconnect from plurality of solder interconnects 190. The electrical pathway between substrate 102 and integrated device 109 may include chiplet 101, an encapsulation interconnect from plurality of encapsulation interconnects 182, and at least one solder interconnect from plurality of solder interconnects 190.

[0060]

[0080] 6 shows a cross-sectional side view of a package 600 including an integrated device and a chiplet. Package 600 is similar to package 100. Package 600 includes substrate 102, metallization portion 104, integrated device 107, integrated device 109, chiplet 101, chiplet 103, chiplet 105, encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0061]

[0081] Package 600 shows that there is no electrical path through the rear surface of chiplet 103. Thus, chiplet 103 may be configured to be electrically coupled to one or more integrated devices (e.g., 107, 109) via an electrical path that includes chiplet 101, interconnects from substrate 102, encapsulation interconnects from multiple encapsulation interconnects 182, metallization interconnects from metallization portion 104, and solder interconnects from multiple solder interconnects (e.g., 170, 190). In some implementations, chiplet 103 may be configured to be electrically coupled to one or more integrated devices (e.g., 107, 109) via an electrical path that includes chiplet 105, encapsulation interconnects from multiple encapsulation interconnects 182, metallization interconnects from metallization portion 104, and solder interconnects from multiple solder interconnects (e.g., 170, 190).

[0062]

[0082] 7 shows a cross-sectional side view of a package 700 including an integrated device and a chiplet. Package 700 is similar to package 600. However, package 700 does not include metallization portion 104. Package 700 includes substrate 102, integrated device 107, integrated device 109, chiplet 101, chiplet 103, chiplet 105, encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0063]

[0083] Package 700 shows that there is no electrical path through the rear surface of chiplet 103. Thus, chiplet 103 may be configured to be electrically coupled to one or more integrated devices (e.g., 107, 109) via an electrical path that includes chiplet 101, interconnects from substrate 102, encapsulation interconnects from the plurality of encapsulation interconnects 182, and solder interconnects from the plurality of solder interconnects (e.g., 170, 190). In some implementations, chiplet 103 may be configured to be electrically coupled to one or more integrated devices (e.g., 107, 109) via an electrical path that includes chiplet 105, encapsulation interconnects from the plurality of encapsulation interconnects 182, and solder interconnects from the plurality of solder interconnects (e.g., 170, 190).

[0064]

[0084] FIG. 8 shows a package 800 including a substrate 102, a metallization portion 104, a bridge 801, a bridge 803, a chiplet 103, a chiplet 807, a chiplet 809, an integrated device 107, an integrated device 109, an encapsulation layer 108, and a plurality of encapsulation interconnects 182.

[0065]

[0085] Bridge 801 and bridge 803 are located (e.g., embedded) in substrate 102. Substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. Substrate 102 may include bridge 801 and bridge 803.

[0066]

[0086] Chiplet 103, chiplet 807, and chiplet 809 are located between substrate 102 and metallization 104. Chiplet 103 is coupled to substrate 102 via a plurality of solder interconnects 830, such that a front surface of chiplet 103 faces substrate 102 and a rear surface of chiplet 103 faces metallization 104. Chiplet 807 is coupled to substrate 102 via a plurality of solder interconnects 870, such that a front surface of chiplet 807 faces substrate 102 and a rear surface of chiplet 807 faces metallization 104. Chiplet 809 is coupled to substrate 102 via a plurality of solder interconnects 890, such that a front surface of chiplet 809 faces substrate 102 and a rear surface of chiplet 809 faces metallization 104.

[0067]

[0087] A plurality of encapsulation interconnects 182 may be bonded to the substrate 102 and the metallization portion 104. A plurality of encapsulation interconnects 182 may be bonded to bridges (e.g., 801, 803) of the substrate 102 and the metallization portion 104. A plurality of encapsulation interconnects 182 are bonded to the chiplet 807 and the metallization portion 104. A plurality of encapsulation interconnects 182 are bonded to the chiplet 809 and the metallization portion 104. The metallization portion 104 is bonded to the encapsulation layer 108. The integrated device 107 is bonded to the metallization portion 104 via a plurality of solder interconnects 170. The integrated device 109 is bonded to the metallization portion 104 via a plurality of solder interconnects 190.

[0068]

[0088] Chiplet 103 is configured to be electrically coupled to chiplet 807 via bridge 801 such that the electrical path between chiplet 103 and chiplet 807 includes a solder interconnect from the plurality of solder interconnects 830, at least one bridge interconnect from bridge 801, and a solder interconnect from the plurality of solder interconnects 870.

[0069]

[0089] Chiplet 103 is configured to be electrically coupled to chiplet 809 via bridge 803 such that the electrical path between chiplet 103 and chiplet 809 includes a solder interconnect from the plurality of solder interconnects 810, at least one bridge interconnect from bridge 803, and a solder interconnect from the plurality of solder interconnects 890.

[0070]

[0090] The chiplet 103 is configured to be electrically coupled to the integrated device 107 such that an electrical path between the chiplet 103 and the integrated device 107 includes a solder interconnect from the plurality of solder interconnects 830, at least one bridge interconnect from the bridge 801, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and a solder interconnect from the plurality of solder interconnects 170.

[0071]

[0091] The chiplet 103 is configured to be electrically coupled to the integrated device 109 such that an electrical path between the chiplet 103 and the integrated device 109 includes a solder interconnect from the plurality of solder interconnects 830, at least one bridge interconnect from the bridge 803, at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and a solder interconnect from the plurality of solder interconnects 190.

[0072]

[0092] The chiplet 807 is configured to be electrically coupled to the integrated device 107 such that an electrical path between the chiplet 807 and the integrated device 107 includes at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and a solder interconnect from the plurality of solder interconnects 170.

[0073]

[0093] The chiplet 809 is configured to be electrically coupled to the integrated device 109 such that an electrical path between the chiplet 809 and the integrated device 109 includes at least one encapsulation interconnect from the plurality of encapsulation interconnects 182, at least one metallization interconnect from the plurality of metallization interconnects 142, and a solder interconnect from the plurality of solder interconnects 190.

[0074]

[0094] 9 shows a package 900 including a substrate 102, a metallization portion 104, an integrated device 107, an integrated device 109, chiplets 101, 103, and 105, an encapsulation layer 108, and a plurality of encapsulation interconnects 182. Chiplets 101, 103, and 105 are located between the substrate 102 and the metallization portion 104. The rear surface of chiplet 103 is bonded to the metallization portion 104. The front surface of chiplet 103 is bonded to the rear surface of chiplet 101. Chiplet 101 is bonded to the substrate 102 via a plurality of solder interconnects 110, such that the front surface of chiplet 101 faces the substrate 102.

[0075]

[0095] Chiplet 105 is coupled to substrate 102 via a plurality of solder interconnects 150 such that the rear surface of chiplet 105 faces substrate 102. The front surface of chiplet 105 faces metallization portion 104. The front surface of chiplet 105 is coupled to the front surface of chiplet 103.

[0076]

[0096] 10 shows a package 1000 that includes a substrate 102, an integrated device 107, an integrated device 109, chiplets 101, 103, an encapsulation layer 108, and a plurality of encapsulation interconnects 182. Chiplet 103 is bonded to integrated device 107 and integrated device 109 such that the rear surface of chiplet 103 faces integrated device 107 and integrated device 109. The front surface of chiplet 103 is bonded to the front surface of chiplet 101. The rear surface of chiplet 101 is bonded to substrate 102 via a plurality of solder interconnects 110.

[0077]

[0097] 11 shows a package 1100 including a substrate 102, a metallization portion 104, an integrated device 107, an integrated device 109, chiplets 101, 103, an encapsulation layer 108, and a plurality of encapsulation interconnects 182. Chiplets 101 and 103 are located between the substrate 102 and the metallization portion 104. Chiplet 103 is bonded to the metallization portion 104 such that the rear surface of chiplet 103 faces the metallization portion 104. The front surface of chiplet 103 is bonded to the rear surface of chiplet 101. The rear surface of chiplet 101 is bonded to the substrate 102 via a plurality of solder interconnects 110.

[0078]

[0098] FIG. 12 shows a package 1200 including a substrate 102, a metallization portion 104, a metallization portion 106, a metallization portion 1206, a chiplet 401, a chiplet 405, a chiplet 407, a chiplet 409, an encapsulation layer 108, an encapsulation layer 1208, an encapsulation layer 1290, a plurality of encapsulation interconnects 182, and a plurality of encapsulation interconnects 1282.

[0079]

[0099] Integrated device 107 is coupled to metallization portion 104 via a plurality of solder interconnects 170. Integrated device 109 is coupled to metallization portion 104 via a plurality of solder interconnects 190. Chiplet 407 and chiplet 409 are located between metallization portion 104 and metallization portion 106. A rear surface of chiplet 407 is coupled to metallization portion 104 via a plurality of solder interconnects 1270. A front surface of chiplet 407 is coupled to metallization portion 106. A rear surface of chiplet 409 is coupled to metallization portion 104 via a plurality of solder interconnects 129. A front surface of chiplet 409 is coupled to metallization portion 106.

[0080]

[0100] Chiplet 401 and chiplet 405 are located between metallization portion 1206 and metallization portion 106. The rear surface of chiplet 401 is coupled to metallization portion 106 via a plurality of solder interconnects 410. The front surface of chiplet 401 is coupled to metallization portion 1206. The rear surface of chiplet 405 is coupled to metallization portion 106 via a plurality of solder interconnects 450. The front surface of chiplet 405 is coupled to metallization portion 1206. Metallization portion 1206 is coupled to substrate 102 via a plurality of solder interconnects 1280. Encapsulation layer 1290 is located between metallization portion 1206 and substrate 102.

[0081]

[0101] It should be noted that components of a package may be electrically coupled to one another through several electrical paths within the package. An electrical path between two components may include any of the electrical paths described above and / or any interconnect directly or indirectly coupled to another interconnect. The electrical paths described in this disclosure are exemplary. Thus, an electrical path between two interconnects (e.g., metallization interconnects, pillar interconnects, solder interconnects, encapsulation interconnects) shown in the figures of this disclosure as contacting each other may be possible. Different implementations may use different electrical paths.

[0082] Exemplary Chiplet with Trench Capacitor

[0102] In some implementations, the chiplet may include a deep trench capacitor. FIG. 13 shows a cross-sectional side view of a chiplet 1300 configured as a trench capacitor device. The chiplet 1300 may be an integrated passive device including multiple trench capacitors (e.g., deep trench capacitors). The chiplet 1300 may be a means for trench capacitance. The chiplet 1300 may represent any of the chiplets described in this disclosure. Thus, some of the structures of the chiplets described in this disclosure may differ from the structure of the chiplet 103 described in FIG. 1. The chiplet 1300 may replace any of the chiplets described in this disclosure. The chiplet 1300 includes a front surface and a back surface. The front surface of the chiplet 1300 may include multiple trench capacitors.

[0083]

[0103] Chiplet 1300 includes a chiplet substrate 1302 and a plurality of trench capacitors 1305. A plurality of solder interconnects (not shown) may be coupled to chiplet 1300. Chiplet substrate 1302 may include silicon (Si). Chiplet substrate 1302 may include a plurality of trenches and / or cavities upon which capacitors may be formed.

[0084]

[0104] The plurality of trench capacitors 1305 includes trench capacitor 1305a and trench capacitor 1305b. Trench capacitor 1305a and trench capacitor 1305b may be configured to be part of the same capacitor (e.g., a first capacitor, a first trench capacitor). Trench capacitor 1305a and trench capacitor 1305b may be coupled to and / or configured to be part of a first power distribution network (PDN). Trench capacitor 1305a and trench capacitor 1305b may be configured to be part of a first electrical path for a first power for the package. Trench capacitor 1305a and trench capacitor 1305b may be configured to be coupled to integrated device(s).

[0085]

[0105] 13, chiplet 1300 includes a chiplet substrate 1302, an oxide layer 1304, a first conductive layer 1306, a dielectric layer 1308, and a second conductive layer 1310. First conductive layer 1306 and / or second conductive layer 1310 may include polysilicon. Oxide layer 1304 and / or dielectric layer 1308 may include SiO (e.g., low-pressure chemical vapor deposition (LPCVD) SiO) or SiN (e.g., LPCVD SiN). Portions of oxide layer 1304, first conductive layer 1306, dielectric layer 1308, and second conductive layer 1310 may be located within trenches and / or cavities in chiplet substrate 1302. It should be noted that chiplet substrate 1302 may be considered to have trenches or cavities even if the trenches or cavities are filled with one or more materials.

[0086]

[0106] Trench capacitor 1305a (e.g., first trench capacitor, first capacitor, means for first trench capacitance) may be defined by (i) a first portion of oxide layer 1304, (ii) a first portion of first conductive layer 1306, (iii) a first portion of dielectric layer 1308, and (iv) a first portion of second conductive layer 1310 located within a trench (e.g., a first trench) in chiplet substrate 1302.

[0087]

[0107] Trench capacitor 1305b (e.g., second trench capacitor, second capacitor, means for second trench capacitance) may be defined by (i) a second portion of oxide layer 1304, (ii) a second portion of first conductive layer 1306, (iii) a second portion of dielectric layer 1308, and (iv) a second portion of second conductive layer 1310 located within a trench (e.g., a second trench) in chiplet substrate 1302. Note that trench capacitor 1305b may be part of the same capacitor as trench capacitor 1305a. That is, trench capacitor 1305a and trench capacitor 1305b may be configured to be electrically coupled together to form a capacitor (e.g., a first capacitor) having a larger capacitance.

[0088]

[0108] Chiplet 1300 also includes interconnect 1309, interconnect 1392, and interconnect 1394. Interconnect 1309 is coupled to interconnect 1392 and interconnect 1394. Interconnect 1309 may be a through-substrate via extending through chiplet substrate 1302. Interconnect 1392 may be a pad interconnect. Interconnect 1394 may be a pad interconnect. Interconnect 1392 may be located on the front side of chiplet 1300. Interconnect 1392 may be located on the rear side of chiplet 1300. Interconnect 1309 may be a chiplet through-substrate interconnect. A chiplet may include at least one chiplet through-substrate interconnect.

[0089]

[0109] The integrated device (e.g., 107, 109) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 107, 109) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a chiplet. Chiplets may be fabricated using processes that offer better yields compared to other processes used to fabricate other types of integrated devices, thereby lowering the overall cost of fabricating the chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As described above, using several chiplets to perform several functions may reduce the overall cost of the package relative to using a single chip to perform all of the package's functions.In some implementations, one or more of the chiplets (e.g., 101, 103) and / or one or more of the integrated devices (e.g., 107, 109) described herein may be fabricated using the same technology node or two or more different technology nodes. For example, the integrated device (e.g., 107) may be fabricated using a first technology node, and the chiplet (e.g., 103) may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, the integrated device (e.g., 107) may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet (e.g., 103) may include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is larger than the first minimum size. In some implementations, the integrated device 107 and the integrated device 109 of the package may be fabricated using the same technology node or different technology nodes. In some implementations, a chiplet (eg, 103) and another chiplet (eg, 105) in a package may be fabricated using the same technology node or different technology nodes.

[0090]

[0110] As an example, in some implementations, a first integrated device (e.g., 107) may include a first plurality of die interconnects including a first minimum spacing, and a second integrated device (e.g., 109) may include a second plurality of die interconnects including a second minimum spacing. A chiplet (e.g., 101, 103, 105) may include a plurality of interconnects including a third minimum spacing. In some implementations, the third minimum spacing may be different from the first minimum spacing and / or the second minimum spacing. As another example, in some implementations, an integrated device (e.g., 107, 109) may include a plurality of die interconnects including a first minimum spacing, and a chiplet (e.g., 101, 103, 105) may include a plurality of interconnects including a second minimum spacing. In yet another example, in some implementations, an integrated device (e.g., 107, 109) may include a first plurality of transistors including a first minimum spacing, and a chiplet (e.g., 101, 103, 105) may include a second plurality of transistors including a second minimum spacing. In some implementations, the first minimum spacing is smaller than the second minimum spacing. In some implementations, the first minimum spacing may be the same as the second minimum spacing.

[0091]

[0111] The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may include a redistribution portion. The plurality of metallization interconnects 142 may include a plurality of redistribution interconnects. The metallization portion 104 may be a means for metallization interconnects. The plurality of metallization interconnects 142 may be coupled to the rear surface of the chiplet and / or the front surface of the chiplet.

[0092]

[0112] The metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162. The metallization portion 106 may include a redistribution portion. The plurality of metallization interconnects 162 may include a plurality of redistribution interconnects. The metallization portion 106 may be a means for metallization interconnects. The plurality of metallization interconnects 162 may be coupled to the rear surface of the chiplet and / or the front surface of the chiplet.

[0093]

[0113] Metallization portion 1206 includes at least one dielectric layer 1260 and a plurality of metallization interconnects 1262. Metallization portion 1206 may include a redistribution portion. The plurality of metallization interconnects 1262 may include a plurality of redistribution interconnects. Metallization portion 1206 may be a means for metallization interconnects. The plurality of metallization interconnects 1262 may be coupled to a rear surface of the chiplet and / or a front surface of the chiplet.

[0094]

[0114] The metallization portions (e.g., 104, 106, 1206) may include redistribution portions including redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The redistribution interconnects may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" are interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shapes of the interconnects and / or redistribution interconnects. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have top and bottom portions. The bottom portion of a U-shaped interconnect (or V-shaped interconnect) may be bonded to the top portion of another U-shaped interconnect (or V-shaped interconnect).

[0095]

[0115] The sealing layer (e.g., 108, 208, 408) may include a mold, a resin, and / or an epoxy. The sealing layer may be a means for sealing. The sealing layer may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0096]

[0116] The location and / or placement of the chiplet near the integrated device helps to reduce signal and / or current latency between the integrated device and the chiplet, thereby helping to improve the performance of the integrated device and / or package. The chiplet may be configured as a deep trench capacitor. However, different implementations may use chiplets configured to perform other operations and / or functionality.

[0097]

[0117] The use of integrated devices, chiplets, and metallization portions in the package of Figure 1, and at least those described in Figures 1-12, provides several advantages. First, it can result in cost reductions for the package by redistributing various functions of the package across at least one integrated device and at least one chiplet. The integrated devices and chiplets can be fabricated using different technology nodes, which may have different costs.

[0098]

[0118] A technology node may refer to a particular fabrication process and / or technology used to fabricate integrated devices and / or chiplets. A technology node may specify the smallest possible size (e.g., minimum size) that can be fabricated (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces components (e.g., traces, transistors) with fine details may be more expensive and have higher yield losses than a technology node that produces components (e.g., traces, transistors) with less fine details. Thus, a more advanced technology node may be more expensive and have higher yield losses than a less advanced technology node. If all of the functionality of a package is realized within a single integrated device, the same technology node is used to fabricate the entire integrated device, even if some of the functionality of the integrated device need not be fabricated using that particular technology node. Thus, an integrated device is locked to one technology node. To optimize package costs, some of the functions may be realized in different integrated devices and / or chiplets, and the different integrated devices and / or chiplets may be fabricated using different technology nodes to reduce overall cost. For example, functions requiring the use of a leading-edge technology node may be realized in an integrated device, while functions that can be implemented using a less advanced technology node may be realized in another integrated device and / or one or more chiplets. One example is an integrated device fabricated using a first technology node (e.g., a leading-edge technology node) configured to provide a computing application and at least one chiplet fabricated using a second technology node configured to provide other functionality, where the second technology node is less expensive than the first technology node and where the second technology node fabricates components having a minimum size that is larger than the minimum size of components fabricated using the first technology node.Example computational applications may include high-performance computing and / or processing, which may be achieved by fabricating and packing as many transistors as possible in an integrated device; integrated devices configured for computational applications may be fabricated using the most advanced technology node available, while other chiplets may be fabricated using less advanced technology nodes because these chiplets may not require as many transistors as fabricated in the chiplet. Thus, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets may reduce the overall cost of the package compared to using a single integrated device to perform all of the functions of the package.

[0099]

[0119] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign every single integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve the package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or differently configured first integrated device. This saves costs by not having to redesign the first chiplet when a package with an improved integrated device is created.

[0100]

[0120] Furthermore, chiplets can be coupled to the integrated device via copper-to-copper hybrid bonds or via solder interconnects so that the chiplets are very close to the integrated device. For example, the chiplets and integrated device can be implemented using metallization (e.g., rewiring) to position the chiplets as close as possible to the integrated device, thereby reducing the electrical path between the chiplets and the integrated device. This helps improve the performance of the integrated device and the power delivered to the integrated device.

[0101]

[0121] Additionally, chiplets including trench capacitors offer several technical advantages. Trench capacitors and / or trench capacitor devices provide capacitors with high capacitance and / or high capacitance density. Capacitors with higher capacitance density allow for more compact form factors for packaging, as these capacitors may occupy less space but provide the same and / or comparable capacitance as larger-sized capacitors. The compact form factor of trench capacitors allows them to be located very close to integrated devices, which can help improve power delivery performance to integrated devices. Furthermore, because these trench capacitors have a small form factor, they can be implemented using metallization instead of being implemented within the package substrate. Thus, high-capacitance capacitors can be implemented during package fabrication instead of when the package is bonded to the substrate.

[0102]

[0122] High capacitance capacitors are particularly important in certain types of processing operations, such as computing applications (e.g., high performance processing). The use of chiplets, integrated devices, and metallization portions as described in this disclosure helps to improve inter-die communication, which helps to improve the overall performance of the integrated device(s) and package.

[0103]

[0123] A bridge (e.g., 801, 803) may include a die substrate (e.g., a bridge substrate) and a plurality of bridge interconnects. The bridge may include a dielectric layer (e.g., a bridge dielectric layer). The bridge dielectric layer may be formed on the bridge substrate and the plurality of bridge interconnects.

[0104]

[0124] 1-12 illustrate various packages that include at least one chiplet located near an integrated device. The use of chiplets and integrated devices with metallization portion(s) provides several advantages. First, the chiplets can be fabricated using a different fabrication process (e.g., technology node) than the integrated device. This helps reduce costs because the chiplets may not need to be fabricated using the most expensive fabrication process. Furthermore, the use of chiplets with metallization portion(s) helps improve electrical performance between the integrated device and / or chiplets because the chiplets and / or integrated device can be located near each other.

[0105]

[0125] As described above, the package may include several metallization portions. Any of the metallization portions may be a first metallization portion and / or any of the metallization portions may be a second metallization portion. For example, in some implementations, metallization portion 104 may be considered a first metallization portion and metallization portion 106 may be considered a second metallization portion. In some implementations, metallization portion 106 may be considered a first metallization portion and metallization portion 104 may be considered a second metallization portion.

[0106]

[0126] As described above, the chiplet may include a trench capacitor and / or may be configured to operate as a trench capacitor device. The trench capacitor and / or trench capacitor device provides a capacitor having a high capacitance and / or a high capacitance density. Capacitors having a higher capacitance density can provide the same and / or comparable capacitance as larger sized capacitors but with less space occupied by these capacitors, enabling a more compact form factor for the package. The compact form factor of the trench capacitors allows them to be located very close to the integrated device, which can help improve the power supply performance to the integrated device. Further, because these trench capacitors have a small form factor, they can be implemented using metallization portions instead of being implemented within the package substrate.

[0107] Exemplary sequence for fabricating a package comprising an integrated device and a chiplet

[0127] FIGS. 14A - 14C illustrate an exemplary sequence for providing or fabricating a package that includes an integrated device and a chiplet. In some implementations, the sequence of FIGS. 14A - 14C may be used to provide or fabricate package 800 of FIG. 8, or any of the packages described in this disclosure.

[0108]

[0128] Note that the sequence of FIGS. 14A - 14C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure. The sequence of FIGS. 14A - 14C may be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0109]

[0129] Stage 1, as shown in Figure 14A, illustrates the state after a substrate 102 is provided. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects. The substrate 102 also includes a bridge 801 and a bridge 803. The bridge 801 and the bridge 803 are embedded in the substrate 102. The substrate 102 may also include a solder resist layer.

[0110]

[0130] Stage 2 shows the state after the plurality of encapsulation interconnects 182 have been formed and bonded to the substrate 102. A masking and plating process may be used to form the plurality of interconnects 182. The plurality of encapsulation interconnects 182 are bonded to the bridge 801 and the bridge 803. For example, the plurality of encapsulation interconnects 182 are bonded to the bridge interconnects of the bridge 801 and the bridge interconnects of the bridge 803. In some implementations, the plurality of encapsulation interconnects 182 are bonded to the plurality of interconnects 122 of the substrate 102.

[0111]

[0131] Stage 3 shows the state after multiple chiplets have been bonded to substrate 102. For example, chiplet 103 is bonded to substrate 102 via multiple solder interconnects 830. Chiplet 807 is bonded to substrate 102 via multiple solder interconnects 870. Chiplet 809 is bonded to substrate 102 via multiple solder interconnects 890. A pick-and-place process may be used to bond the chiplets to the substrate.

[0112]

[0132] Stage 4 shows the state after the encapsulation layer 108 is formed and bonded to the substrate 102. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for sealing. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 may be overmolded, and then a portion of the encapsulation layer 108 may be removed.

[0113]

[0133] 14B, after the plurality of encapsulating interconnects 1482 have been formed and bonded to chiplet 807, chiplet 809, and the plurality of encapsulating interconnects 182. A masking and plating process may be used to form the plurality of encapsulating interconnects 1482.

[0114]

[0134] Stage 6 shows the state after the encapsulation layer 1408 is formed and bonded to the encapsulation layer 108. The encapsulation layer 1408 may include a mold, a resin, and / or an epoxy. The encapsulation layer 1408 may be a means for sealing. The encapsulation layer 1408 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 1408 may be overmolded, and then a portion of the encapsulation layer 1408 may be removed.

[0115]

[0135] Stage 7 shows the state after metallization portion 104 has been formed and bonded to encapsulation layer 108. Encapsulation layer 108 may represent encapsulation layer 108 and encapsulation layer 1408. Metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The plurality of metallization portions may be bonded to a plurality of encapsulation interconnects 182. The plurality of encapsulation interconnects 182 may represent a plurality of encapsulation interconnects 182 and / or a plurality of encapsulation interconnects 1482.

[0116]

[0136] 14C, after integrated device 107 has been bonded to metallization 104 via a plurality of solder interconnects 170. Stage 8 also shows integrated device 109 after integrated device 109 has been bonded to metallization 104 via a plurality of solder interconnects 190. A solder reflow process may be used to bond the integrated device to metallization 104.

[0117]

[0137] Stage 9 shows the state after a plurality of solder interconnects 129 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 129 to the plurality of interconnects 122 of the substrate 102.

[0118] Exemplary sequence for fabricating a package comprising an integrated device and a chiplet

[0138] FIGS. 15A-15C show an exemplary sequence for providing or fabricating a package including an integrated device and a chiplet. In some implementations, the sequence of FIGS. 15A-15C may be used to provide or fabricate the package 100 of FIG. 1 or any of the packages described in this disclosure.

[0119]

[0139] Note that the sequence of FIGS. 15A-15C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be exchanged or replaced without departing from the scope of this disclosure. The sequence of FIGS. 15A-15C may be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0120]

[0140] Stage 1 shows the state after the substrate 102 is provided, as shown in FIG. 15A. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects. The substrate 102 may also include a solder resist layer.

[0121]

[0141] Stage 2 shows the state after a plurality of encapsulation interconnects 182 are formed and coupled to the substrate 102. A masking and plating process may be used to form the plurality of interconnects 182. The plurality of encapsulation interconnects 182 are coupled to the plurality of interconnects 122 of the substrate 102.

[0122]

[0142] Stage 3 shows the state after multiple chiplets have been bonded to substrate 102. For example, the rear face of chiplet 101 is bonded to substrate 102 via multiple solder interconnects 110. The rear face of chiplet 105 is bonded to substrate 102 via multiple solder interconnects 150. A pick-and-place process may be used to bond the chiplets to the substrate.

[0123]

[0143] Stage 4 shows the state after chiplet 103 is bonded to chiplet 101 and chiplet 105. The front side of chiplet 103 may be bonded to the front side of chiplet 101 and to the front side of chiplet 103. A hybrid bonding process may be used to bond the chiplets together so that the interconnects from the chiplets contact each other.

[0124]

[0144] Stage 5, as shown in Figure 15B, depicts the state after a plurality of encapsulating interconnects 1582 have been formed and bonded to the chiplets 105. A masking and plating process may be used to form the plurality of interconnects 1582.

[0125]

[0145] Stage 6 shows the state after the encapsulation layer 108 has been formed and bonded to the substrate 102. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for sealing. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 may be overmolded, and then a portion of the encapsulation layer 108 may be removed.

[0126]

[0146] Stage 7 shows the state after metallization portion 104 has been formed and bonded to encapsulation layer 108. Encapsulation layer 108 may represent encapsulation layer 108 and encapsulation layer 1408. Metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The plurality of metallization portions may be bonded to a plurality of encapsulation interconnects 182. The plurality of encapsulation interconnects 182 may represent a plurality of encapsulation interconnects 182 and / or a plurality of encapsulation interconnects 1582.

[0127]

[0147] 15C, stage 8 shows the state after integrated device 107 has been bonded to metallization portion 104 via a plurality of solder interconnects 170. Stage 8 also shows the state after integrated device 109 has been bonded to metallization portion 104 via a plurality of solder interconnects 190. A solder reflow process may be used to bond the integrated device to metallization portion 104.

[0128]

[0148] Stage 9 shows the state after the plurality of solder interconnects 129 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 129 to the plurality of interconnects 122 of the substrate 102.

[0129] Exemplary Sequence for Fabricating a Package with Integrated Devices and Chiplets

[0149] 16A-16D show an example sequence for providing or fabricating a package including an integrated device and chiplets. In some implementations, the sequence of FIG. 16A-16D can be used to provide or fabricate package 200 of FIG. 2 or any of the packages described in this disclosure.

[0130]

[0150] Note that the sequences of FIGS. 16A to 16D may combine one or more steps to simplify and / or clarify the sequences for providing or fabricating packages. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of the present disclosure. The sequences of FIGS. 16A to 16D can be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0131]

[0151] Step 1 shows the state after the integrated device 107 and the integrated device 109 are provided on the carrier 1600, as shown in FIG. 16A. A pick-and-place process can be used to place the back surfaces of the integrated device 107 and the integrated device 109 on the carrier 1600. The carrier 1600 can include a tape. The integrated device 107 can include a plurality of pillar interconnects 270. The integrated device 109 can include a plurality of pillar interconnects 290.

[0132]

[0152] Step 2 shows the state after the encapsulation layer 208 is formed over the carrier 1400, the integrated device 107, and the integrated device 109. The encapsulation layer 108 is bonded to the carrier 1400, the integrated device 107, and the integrated device 109. The encapsulation layer 208 can encapsulate the plurality of pillar interconnects 270 and the plurality of pillar interconnects 290. The encapsulation layer 208 can include a mold, resin, and / or epoxy. The encapsulation layer 208 can be a means for encapsulation. The encapsulation layer 208 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 208 is provided, and then a polishing and / or grinding process is performed to remove a portion of the encapsulation layer 208 and / or a portion of the pillar interconnects 270 of the integrated device 107 and / or a portion of the pillar interconnects 290 of the integrated device 109, thereby creating a flat surface.

[0133]

[0153] Stage 3 shows the state after metallization portion 104 has been formed and bonded to encapsulation layer 108. Metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The plurality of metallization interconnects 142 may be bonded to integrated devices (e.g., 107, 109) via a plurality of pillar interconnects (e.g., 270, 290).

[0134]

[0154] Stage 4 shows the state after a plurality of encapsulation interconnects 182 have been formed and bonded to the metallization portion 104. A masking and plating process may be used to form the plurality of interconnects 182. The plurality of encapsulation interconnects 182 may be bonded to the plurality of metallization interconnects 142 of the metallization portion 104.

[0135]

[0155] Stage 5, as shown in FIG. 16B , depicts the state after chiplet 103 has been bonded to metallization interconnects 142 of metallization portion 104 via solder interconnects 230. A rear surface of chiplet 103 may be bonded to metallization portion 104. A solder reflow process may be used to bond chiplet 103 to metallization portion 104.

[0136]

[0156] Stage 6 shows the state after the encapsulation layer 108 is formed over the metallization portion 104, the chiplets 103, and the plurality of encapsulation interconnects 182. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 108 and / or portions of the encapsulation interconnects 182, thereby creating a flat surface.

[0137]

[0157] Stage 7 shows the state after the plurality of sealing interconnects 1682 have been formed and bonded to the plurality of sealing interconnects 182. A masking and plating process may be used to form the plurality of interconnects 1682.

[0138]

[0158] Stage 8, as shown in FIG. 16C , illustrates the state after chiplet 101 and chiplet 105 are bonded to chiplet 103. A hybrid bonding process may be used to bond chiplet 101 and chiplet 105 so that the chiplet interconnects are in direct contact without the need for solder interconnects. The front surface of chiplet 101 may be bonded to the front surface of chiplet 103. The front surface of chiplet 105 may be bonded to the front surface of chiplet 103. However, in some implementations, the rear surface of the chiplet may be bonded to the front surface of the chiplet. In some implementations, the rear surface of the chiplet may be bonded to the rear surface of the chiplet. The plurality of encapsulation interconnects 182 may represent the plurality of encapsulation interconnects 182 and the plurality of encapsulation interconnects 1682.

[0139]

[0159] Stage 9 illustrates the state after an encapsulation layer 1608 is formed over the encapsulation layers 108, 104, the chiplets 103, 101, 105, and the plurality of encapsulation interconnects 182. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 1608 and / or portions of the encapsulation interconnects 182, thereby creating a flat surface.

[0140]

[0160] Stage 10 shows the state after carrier 1600 has been debonded from encapsulation layer 208. Encapsulation layer 108 may refer to encapsulation layer 108 and encapsulation layer 1608.

[0141]

[0161] Step 11 of FIG. 16D shows the state after the package is coupled to the substrate 102 via a plurality of solder interconnects 280. The chiplet 101 and the chiplet 105 are coupled to the substrate 102 via a plurality of solder interconnects 280. The plurality of encapsulation interconnects 182 are coupled to the substrate 102 via a plurality of solder interconnects 280. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122.

[0142]

[0162] Step 12 shows the state after the encapsulation layer 1680 is provided between the encapsulation layer 108 and the substrate 102. The encapsulation layer 1680 may be regarded as part of the encapsulation layer 108. Step 12 also shows the state after a plurality of solder interconnects 129 are coupled to the substrate 102. A solder reflow process may be used to couple the plurality of solder interconnects 129 to the plurality of interconnects 122 of the substrate 102.

[0143] Exemplary sequence for fabricating a package comprising an integrated device and a chiplet

[0163] FIGS. 17A-17D show an exemplary sequence for providing or fabricating a package including an integrated device and a chiplet. In some implementations, the sequence of FIGS. 17A-17D may be used to provide or fabricate the package 400 of FIG. 4, or any of the packages described in the present disclosure.

[0144]

[0164] Note that the sequence of FIGS. 17A-17D may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be exchanged or replaced without departing from the scope of the present disclosure. The sequence of FIGS. 17A-17D may be used to fabricate one package or, simultaneously, several packages (as part of a wafer).

[0145]

[0165] Stage 1 shows the state after integrated device 107 and integrated device 109 are provided on carrier 1700, as shown in Figure 17A. A pick-and-place process can be used to place the rear surface of integrated device 107 and the rear surface of integrated device 109 on carrier 1600. Carrier 1600 can include tape.

[0146]

[0166] Stage 2 shows the state after multiple pillar interconnects 470 have been formed and coupled to integrated device 107, and multiple pillar interconnects 490 have been formed and coupled to integrated device 109. Masking and plating processes may be used to form the multiple pillar interconnects.

[0147]

[0167] Stage 3 shows the state after chiplet 407 has been bonded to integrated device 107 via a plurality of solder interconnects 170. A solder reflow process may be used to bond chiplet 407 to integrated device 107. Stage 3 also shows the state after chiplet 409 has been bonded to integrated device 109 via a plurality of solder interconnects 190. A solder reflow process may be used to bond chiplet 409 to integrated device 109.

[0148]

[0168] Stage 4 shows the state after the encapsulation layer 408 is formed over the carrier 1400, the integrated device 107, the integrated device 109, the plurality of pillar interconnects 470, the plurality of pillar interconnects 490, the chiplets 407, and the chiplets 409. The encapsulation layer 108 is bonded to the carrier 1400, the integrated device 107, the integrated device 109, the plurality of pillar interconnects 470, the plurality of pillar interconnects 490, the chiplets 407, and the chiplets 409. The encapsulation layer 408 may include a mold, a resin, and / or an epoxy. The encapsulation layer 408 may be a means for encapsulation. The encapsulation layer 408 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, an encapsulation layer 408 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 408 and / or portions of the pillar interconnects 470 and / or portions of the pillar interconnects 490, thereby creating a flat surface.

[0149]

[0169] Stage 5 shows the state after metallization portion 104 has been formed and bonded to encapsulation layer 408, multiple pillar interconnects 470, multiple pillar interconnects 490, chiplet 407, and chiplet 409. Metallization portion 104 includes at least one dielectric layer 140 and multiple metallization interconnects 142. Multiple metallization interconnects 142 can be bonded to integrated devices (e.g., 107, 109) via multiple pillar interconnects (e.g., 470, 490).

[0150]

[0170] 17B, ​​represents the state after a plurality of encapsulation interconnects 182 have been formed and bonded to the metallization portion 104. A masking and plating process may be used to form the plurality of interconnects 182. The plurality of encapsulation interconnects 182 may be bonded to the plurality of metallization interconnects 142 of the metallization portion 104.

[0151]

[0171] Stage 7 shows the state after chiplet 401 has been bonded to the plurality of metallization interconnects 142 of metallization portion 104 via the plurality of solder interconnects 410. The rear surface of chiplet 401 may be bonded to metallization portion 104. A solder reflow process may be used to bond chiplet 401 to metallization portion 104.

[0152]

[0172] Stage 7 also shows the state after chiplet 405 has been bonded to the plurality of metallization interconnects 142 of metallization portion 104 via the plurality of solder interconnects 450. The rear surface of chiplet 405 may be bonded to metallization portion 104. A solder reflow process may be used to bond chiplet 405 to metallization portion 104.

[0153]

[0173] Stage 8 shows the state after the encapsulation layer 108 is formed over the metallization portion 104, the chiplets 401, 405, and the plurality of encapsulation interconnects 182. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 108 is provided, and then a polishing and / or grinding process is performed to remove portions of the encapsulation layer 108 and / or portions of the encapsulation interconnects 182, thereby creating a flat surface.

[0154]

[0174] 17C, after metallization portion 106 has been formed and bonded to encapsulation layer 108, chiplets 401, and chiplets 405. Metallization portion 106 includes at least one dielectric layer 160 and a plurality of metallization interconnects 162.

[0155]

[0175] Stage 10 shows the state after the carrier 1700 has been debonded from the encapsulation layer 408 .

[0156]

[0176] 17D shows the state after the package has been coupled to the substrate 102 via a plurality of solder interconnects 280. The metallization portion 106 may be coupled to the substrate 102 via a plurality of solder interconnects 280. A plurality of metallization interconnects 162 are coupled to the substrate 102 via a plurality of solder interconnects 280. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122.

[0157]

[0177] Stage 12 shows the state after an encapsulation layer 1780 has been provided between the substrate 102 and the metallization portion 106. Stage 12 also shows the state after a plurality of solder interconnects 129 have been bonded to the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 129 to the plurality of interconnects 122 of the substrate 102.

[0158]

[0178] Any of the metallization portions may be a first metallization portion and / or any of the metallization portions may be a second metallization portion. For example, in some implementations, metallization portion 104 may be considered a first metallization portion and metallization portion 106 may be considered a second metallization portion. In some implementations, metallization portion 106 may be considered a first metallization portion and metallization portion 104 may be considered a second metallization portion.

[0159] Exemplary Sequence for Fabricating Metallization Portions

[0179] In some implementations, fabricating a substrate includes several processes. FIGS. 18A-18B show an exemplary sequence for providing or fabricating a metallization portion. In some implementations, the sequence of FIGS. 18A-18B can be used to provide or fabricate the metallization portion 104. However, the processes of FIGS. 18A-18B can be used to fabricate any of the metallization portions described in this disclosure. In some implementations, the processes of FIGS. 18A-18B can be used to fabricate a substrate.

[0160]

[0180] Note that the sequence of FIGS. 18A-18B can combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more of the processes can be exchanged or replaced without departing from the scope of this disclosure.

[0161]

[0181] Step 1 shows the state after a carrier 1800 is provided, as shown in FIG. 18A. The seed layer 1801 and the interconnect 1802 can be located on the carrier 1800. The interconnect 1802 can be located on the seed layer 1801. A plating process and an etching process can be used to form the interconnect 1802. In some implementations, the carrier 1800 can be provided with a metal layer patterned to form the seed layer 1801 and the interconnect 1802. The interconnect 1802 can represent at least some of the interconnects from a plurality of interconnects 192.

[0162]

[0182] Stage 2 shows the state after dielectric layer 1820 is formed over carrier 1800, seed layer 1801, and interconnects 1802. A deposition process and / or lamination process may be used to form dielectric layer 1820. Dielectric layer 1820 may include prepreg and / or polyimide. Dielectric layer 1820 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0163]

[0183] Stage 3 shows the state after multiple cavities 1810 have been formed in the dielectric layer 1820. The multiple cavities 1810 can be formed using a photolithography process or a laser process.

[0164]

[0184] Stage 4 shows the state after interconnects 1812 have been formed in and on dielectric layer 1820, including in and on the plurality of cavities 1810. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0165]

[0185] Stage 5 shows the state after dielectric layer 1822 is formed over dielectric layer 1820 and interconnects 1812. A deposition process and / or lamination process may be used to form dielectric layer 1822. Dielectric layer 1822 may include prepreg and / or polyimide. Dielectric layer 1822 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0166]

[0186] Stage 6, as shown in Figure 18B, shows the state after a plurality of cavities 1830 have been formed in the dielectric layer 1822. The plurality of cavities 1830 can be formed using a photolithography process or a laser process.

[0167]

[0187] Stage 7 shows the state after interconnects 1814 have been formed in and on dielectric layer 1822, including in and on a plurality of cavities 1830. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0168]

[0188] Stage 8 depicts the state after carrier 1800 has been debonded (e.g., detached, removed, ground) from at least one dielectric layer 1820 and seed layer 1801, and portions of seed layer 1801 have been removed (e.g., etched away) to leave metallization portion 104 including at least one dielectric layer 1820 and multiple interconnects 192. At least one dielectric layer 140 may represent dielectric layer 1820 and / or dielectric layer 1822. Multiple metallization interconnects 142 may represent interconnects 1802, 1812, and / or 1814.

[0169]

[0189] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0170] 1 is an exemplary flow diagram of a method for fabricating a metallization portion;

[0190] In some implementations, fabricating the substrate includes several processes. Figure 19 shows an example flow diagram of a method 1900 for providing or fabricating a metallization portion. In some implementations, the method 1900 of Figure 19 can be used to provide or fabricate a substrate(s) of the present disclosure. For example, the method 1900 of Figure 19 can be used to fabricate the metallization portion 104.

[0171]

[0191] 19 may combine one or more processes to simplify and / or clarify the method of providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0172]

[0192] The method provides (at 1905) a carrier (e.g., 1800). Different implementations may use different materials for the carrier 1800. The carrier 1800 may include a seed layer (e.g., 1801). The seed layer 1801 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or carrier tape. Step 1 of FIG. 18A illustrates and describes one example of a carrier with a provided seed layer.

[0173]

[0193] The method forms and patterns interconnects (at 1910) on the carrier 1800 and the seed layer 1801. A metal layer can be patterned to form the interconnects. A plating process can be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer can include a metal layer. A metal layer overlies the seed layer, and the metal layer can be patterned to form the interconnects (e.g., 192). Step 1 of FIG. 18A illustrates and describes one example of forming and patterning interconnects on a seed layer and a carrier.

[0174]

[0194] The method forms / provides (at 1915) a dielectric layer 1820 over the seed layer 1801, the carrier 1800, and the interconnects 1802. A deposition process and / or a lamination process may be used to form the dielectric layer 1820. The dielectric layer 1820 may include prepreg and / or polyimide. The dielectric layer 1820 may include a photoimageable dielectric. Forming the dielectric layer 1820 may also include forming a plurality of cavities (e.g., 1810) in the dielectric layer 1820. The plurality of cavities may be formed using photolithography or a laser process. Steps 2-3 of FIG. 18A illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0175]

[0195] The method forms (at 1920) interconnects in and on the dielectric layer. For example, interconnects 1812 may be formed in and on dielectric layer 1820. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects may also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 18A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0176]

[0196] The method forms / provides (at 1925) a dielectric layer 1822 over the dielectric layer 1820 and the interconnects 1812. A deposition process and / or a lamination process may be used to form the dielectric layer 1822. The dielectric layer 1822 may include a prepreg and / or a polyimide. The dielectric layer 1822 may include a photoimageable dielectric. Forming the dielectric layer 1822 may also include forming a plurality of cavities (e.g., 1830) in the dielectric layer 1822. The plurality of cavities may be formed using a photolithography process or a laser process. Steps 5-6 of Figures 18A-18B illustrate and describe one example of forming the dielectric layer and the cavities in the dielectric layer.

[0177]

[0197] The method forms (at 1930) interconnects in and on the dielectric layer. For example, interconnect 1814 can be formed in and on dielectric layer 1822. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or within the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Step 7 of FIG. 18B illustrates and describes one example of forming interconnects in and on the dielectric layer. The method can form additional dielectric layer(s) and additional interconnects, as described at 1925 and 1930.

[0178]

[0198] In some implementations, once all of the dielectric layer(s) and additional interconnects have been formed, the method may debond (at 1935) the carrier (e.g., 1800) from the seed layer (e.g., 1801). The carrier 1800 may be removed and / or ground away. The method may also remove (at 1935) portions of the seed layer (e.g., 1801). An etching process may be used to remove portions of the seed layer 1801. Step 8 of FIG. 18B illustrates and describes one example of carrier debonding and seed layer removal.

[0179]

[0199] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s).

[0180] Exemplary Electronic Devices

[0200] FIG. 20 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 2002, a laptop computer device 2004, a fixed location terminal device 2006, a wearable device 2008, or an automotive vehicle 2010 may include a device 2000 as described herein. The device 2000 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 2002, 2004, 2006, and 2008, and the vehicle 2010 shown in FIG. 20 are merely exemplary. Other electronic devices may also be equipped with device 2000, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, eyeglasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0181]

[0201] One or more of the components, processes, features, and / or functions shown in Figures 1-13, 14A-14C, 15A-15C, 16A-16D, 17A-17D, 18A-18B, and / or 19-20 may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. Also, it should be noted that Figures 1-13, 14A-14C, 15A-15C, 16A-16D, 17A-17D, 18A-18B, and / or 19-20 and their corresponding descriptions in this disclosure are not limited to die and / or ICs. 1-13, 14A-14C, 15A-15C, 16A-16D, 17A-17D, 18A-18B, and / or 19-20, and their corresponding descriptions, may be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0182]

[0202] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the location, position, size, and / or shape of various parts and / or components in the figures may be exemplary. In some implementations, various components and / or parts in the figures may be optional.

[0183]

[0203] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the term “aspect” does not require all aspects of the present disclosure to include the described feature, advantage, or mode of operation. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other even though they are not in direct physical contact with each other. An object coupled to another object may also be coupled to at least a portion of the other object. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can propagate between the two objects. Two objects that are electrically coupled may or may not propagate current between them. Use of the terms “first,” “second,” “third,” and “fourth” (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The term “encapsulating” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A top component may be located above a bottom component. A top component may also be considered a bottom component, and vice versa.As described in this disclosure, a first component "over" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being located above another component, the term "over" as used herein can be used to refer to a component that is on and / or within (e.g., on the surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but not in direct contact with the second component, (2) that the first component is present on (e.g., on the surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component located "in" a second component can be partially located within the second component or completely located within the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within 10 percent of "value X." For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0184]

[0204] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0185]

[0205] It should also be noted that various disclosures contained herein may be described as a process, which is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process terminates when its operations are completed.

[0186]

[0206] In the following, further examples are described to facilitate understanding of the present invention.

[0187]

[0207] Aspect 1: A package comprising: a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.

[0188]

[0208] Aspect 2: The package of aspect 1, wherein the first chiplet includes a first front surface and a first rear surface, the second chiplet includes a second front surface and a second rear surface, and the first front surface of the first chiplet is coupled to the second front surface of the second chiplet.

[0189]

[0209] Aspect 3: The package of Aspect 1 or 2, wherein the first chiplet includes a first plurality of through-substrate vias and the second chiplet includes a second plurality of through-substrate vias.

[0190]

[0210] Embodiment 4: The package of embodiments 1-3, further comprising a third chiplet coupled to the substrate.

[0191]

[0211] Embodiment 5: The package of embodiment 4, wherein the second chiplet is coupled to a third chiplet.

[0192]

[0212] Aspect 6: The package of Aspect 5, wherein the first chiplet includes a first front surface and a first rear surface, the second chiplet includes a second front surface and a second rear surface, the second chiplet includes a third front surface and a third rear surface, the first front surface of the first chiplet being bonded to the second front surface of the second chiplet, and the third front surface of the third chiplet being bonded to the second front surface of the second chiplet.

[0193]

[0213] Embodiment 7: The package of embodiment 6, wherein the third chiplet includes a deep trench capacitor.

[0194]

[0214] Embodiment 8: The package of embodiment 4, wherein the first chiplet is coupled to a third chiplet.

[0195]

[0215] Aspect 9: The package of aspect 8, wherein the first chiplet includes a first front surface and a first rear surface, the second chiplet includes a second front surface and a second rear surface, the second chiplet includes a third front surface and a third rear surface, the first front surface of the first chiplet is bonded to the second front surface of the second chiplet, and the third front surface of the third chiplet is bonded to the first front surface of the first chiplet.

[0196]

[0216] Embodiment 10: The package of embodiments 1-9, wherein the electrical path between the substrate and the first integrated device includes an interconnect from the first chiplet and an interconnect from the second chiplet.

[0197]

[0217] Aspect 11: A package comprising: a first metallization portion; a first chiplet coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion and the first chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a second metallization portion coupled to the encapsulation layer, the first chiplet, and the plurality of encapsulation interconnects; a second chiplet coupled to the second metallization portion; and a first integrated device coupled to the second chiplet and the second metallization portion such that the second chiplet is located between the first integrated device and the second metallization portion, the first integrated device being coupled to the second chiplet via a plurality of solder interconnects.

[0198]

[0218] Aspect 12: A package as described in aspect 11, wherein the first chiplet includes a first front surface and a first rear surface, the second chiplet includes a second front surface and a second rear surface, the first front surface of the first chiplet being coupled to the second metallization portion via a first plurality of solder interconnects, and the second front surface of the second chiplet being coupled to the second metallization portion via a second plurality of solder interconnects.

[0199]

[0219] Aspect 13: The package of aspect 11 or 12, wherein the first chiplet and the second chiplet are configured to be coupled to a power distribution network.

[0200]

[0220] Aspect 14: A device comprising: a package including a substrate including at least one dielectric layer and a plurality of interconnects; a bridge located in the substrate; a first chiplet coupled to the substrate; a second chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.

[0201]

[0221] Aspect 15: The device of aspect 14, wherein the first chiplet includes a first front surface and a first rear surface, and the first front surface of the first chiplet is coupled to a bridge located in the substrate.

[0202]

[0222] Embodiment 16: The device of embodiment 14 or 15, wherein at least one sealing interconnect from the plurality of sealing interconnects is coupled to a bridge.

[0203]

[0223] Embodiment 17: The device of embodiments 14-16, wherein at least one encapsulating interconnect from the plurality of encapsulating interconnects is coupled to the second chiplet.

[0204]

[0224] Example 18: The device of Examples 14-17, wherein the first chiplet is configured to be coupled to a power distribution network.

[0205]

[0225] Embodiment 19: The device of embodiments 14-18, wherein the first chiplet and / or the second chiplet comprises a deep trench capacitor.

[0206]

[0226] Aspect 20: The device described in aspects 14 to 19, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0207]

[0227] Various features of the present disclosure described herein can be implemented in a variety of systems without departing from the present disclosure. It should be noted that the above-described aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and is not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, a substrate including at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located within the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; a first integrated device coupled to the metallization portion.

2. the first chiplet includes a first front surface and a first rear surface; the second chiplet includes a second front surface and a second rear surface; The package of claim 1 , wherein the first front surface of the first chiplet is coupled to the second front surface of the second chiplet.

3. the first chiplet includes a first plurality of through-substrate vias; The package of claim 1 , wherein the second chiplet includes a second plurality of through-substrate vias.

4. The package of claim 1 further comprising a third chiplet coupled to the substrate.

5. The package of claim 4 , wherein the second chiplet is coupled to the third chiplet.

6. the first chiplet includes a first front surface and a first rear surface; the second chiplet includes a second front surface and a second rear surface; the second chiplet includes a third front surface and a third rear surface; the first front surface of the first chiplet is coupled to the second front surface of the second chiplet; The package of claim 5 , wherein the third front surface of the third chiplet is coupled to the second front surface of the second chiplet.

7. The package of claim 6 , wherein the third chiplet comprises a deep trench capacitor.

8. The package of claim 4 , wherein the first chiplet is coupled to the third chiplet.

9. the first chiplet includes a first front surface and a first rear surface; the second chiplet includes a second front surface and a second rear surface; the second chiplet includes a third front surface and a third rear surface; the first front surface of the first chiplet is coupled to the second front surface of the second chiplet; The package of claim 8 , wherein the third front surface of the third chiplet is coupled to the first front surface of the first chiplet.

10. The package of claim 1 , wherein an electrical path between the substrate and the first integrated device includes an interconnect from the first chiplet and an interconnect from the second chiplet.

11. A package, a first metallization portion; a first chiplet coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion and the first chiplet; a plurality of encapsulation interconnects located within the encapsulation layer; a second metallization portion coupled to the encapsulation layer, the first chiplet, and the plurality of encapsulation interconnects; a second chiplet coupled to the second metallization portion; the first integrated device coupled to the second chiplet and the second metallization portion such that the second chiplet is located between the first integrated device and the second metallization portion, the first integrated device being coupled to the second chiplet via a plurality of solder interconnects.

12. the first chiplet includes a first front surface and a first rear surface; the second chiplet includes a second front surface and a second rear surface; the first front surface of the first chiplet is coupled to the second metallization portion via a first plurality of solder interconnects; The package of claim 11 , wherein the second front surface of the second chiplet is coupled to the second metallization portion via a second plurality of solder interconnects.

13. The package of claim 11 , wherein the first chiplet and the second chiplet are configured to be coupled to a power distribution network.

14. A device, A package, a substrate including at least one dielectric layer and a plurality of interconnects; a bridge located within the substrate; a first chiplet coupled to the substrate; a second chiplet; and an encapsulation layer coupled to the substrate, the first chiplet, and the second chiplet; a plurality of encapsulation interconnects located within the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet, and the plurality of encapsulation interconnects; a first integrated device coupled to the metallization portion.

15. the first chiplet includes a first front surface and a first rear surface; The device of claim 14 , wherein the first front surface of the first chiplet is coupled to the bridge located in the substrate.

16. The device of claim 14 , wherein at least one sealing interconnect from the plurality of sealing interconnects is coupled to the bridge.

17. The device of claim 14 , wherein at least one encapsulation interconnect from the plurality of encapsulation interconnects is coupled to the second chiplet.

18. The device of claim 14 , wherein the first chiplet is configured to be coupled to a power distribution network.

19. The device of claim 14 , wherein the first chiplet and / or the second chiplet comprise a deep trench capacitor.

20. 15. The device of claim 14, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

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