Stacked FET contact formation

Abstract

The semiconductor device and method for making the same includes a first lower device and a second lower device on a substrate. The first upper device is on top of the first lower device and the second upper device is on top of the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with the top and sidewall surfaces of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with the top and sidewall surfaces of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.

Description

[Technical Field]

[0001] The present invention relates generally to semiconductor device manufacturing, and more particularly to stacked transistor devices. [Background technology]

[0002] Forming transistor devices on top of each other can help increase the areal density of integrated circuits, for example, by forming complementary field-effect transistors using two connected devices of opposite polarity. However, when forming transistor devices on top of each other, forming contacts to the underlying device can be difficult, especially with tight pitch between horizontally adjacent devices. When forming stacked devices, the contacts may need to penetrate multiple layers to reach the underlying device. While a large surface area at the interface between the contact and the device helps reduce electrical resistance, it can be difficult to increase the size of the underlying device with adjacent devices in close proximity. Furthermore, electrical contacts formed for devices very close to each other create a risk of electrical shorts between the contact and the upper device, as well as the risk of creating shorts with adjacent devices. Summary of the Invention

[0003] The semiconductor device includes a first lower device and a second lower device on a substrate. The first upper device is located on top of the first lower device, and the second upper device is located on top of the second lower device. A first lower contact extends from a height above the first upper device, making electrical contact with the top and sidewalls of the first lower device, and extending laterally below the first upper device. A second lower contact extends from a height above the second upper device, making electrical contact with the top and sidewalls of the second lower device, and extending laterally below the second upper device. The first lower contact extends from a height above the first upper device, making electrical contact with the top and sidewalls of the first lower device. The second lower contact extends from a height above the second upper device, making electrical contact with the top and sidewalls of the second lower device. An insulating barrier is located between the first lower contact and the second lower contact. The insulating barrier provides reliable electrical isolation between the contacts to the underlying device without risk of shorting between adjacent structures. Additionally, the lateral extension of the lower contact underneath the upper device increases the surface area of ​​the interface between the lower contact and the underlying device, thereby reducing resistance.

[0004] A method for forming a semiconductor device includes forming a placeholder structure above a first lower device and a second lower device on a substrate. The first upper device and the second upper device are formed on a dielectric layer above the respective first and second lower devices. The placeholder structure is selectively etched away to expose the top and sidewall surfaces of each of the first and second lower devices. A conductive material is deposited that makes electrical contact with the top and sidewall surfaces of each of the first and second lower devices. A trench is etched in the conductive material, separating the conductive material into a first lower contact and a second lower contact. A partition structure is formed in the trench, electrically isolating the first lower contact and the second lower contact. The partition structure provides reliable electrical isolation between the contacts to the lower devices without risk of shorting between adjacent structures. Additionally, the placeholder structure creates space for lateral extension of the lower contact below the upper device, thereby increasing the surface area of ​​the interface between the lower contact and the lower device and reducing resistance.

[0005] A method for forming a semiconductor device includes forming a pair of lower devices and a placeholder structure therebetween. A dielectric layer is formed on top of the placeholder structure. The placeholder structure is etched away, leaving a gap between the pair of lower devices and the dielectric layer. A conductor is deposited to fill the gap. Trenches are etched in the conductor to form contacts to each of the pair of lower devices. The trenches provide reliable electrical isolation between the contacts to the lower devices without risking shorting between adjacent structures. Additionally, the placeholder provides lateral extension for the lower contacts underlying the upper device, thereby increasing the surface area and reducing resistance of the interface between the lower contacts and the lower devices.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which should be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0007] The following description provides details of preferred embodiments with reference to the following drawings:

[0008] [Figure 1] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating the use of shallow trench isolation to form separate device platform regions on a semiconductor substrate, in accordance with one embodiment of the present invention.

[0009] [Figure 2] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a pair of vertically stacked semiconductor devices illustrating the formation of a pair of lower devices on respective device plateau regions of a semiconductor substrate in accordance with one embodiment of the present invention.

[0010] [Figure 3] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating the formation of sacrificial placeholder structures that make contact with the top and side surfaces of each of the underlying devices, in accordance with one embodiment of the present invention.

[0011] [Figure 4] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating the formation of upper layers on top of a placeholder structure according to one embodiment of the present invention.

[0012] [Figure 5] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating the formation of upper semiconductor devices in an upper layer vertically aligned on top of respective lower devices in accordance with one embodiment of the present invention.

[0013] [Figure 6]1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating etching through upper layers and exposing the top surfaces of placeholder structures according to one embodiment of the present invention.

[0014] [Figure 7] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices illustrating etching to remove placeholder structures and leave gaps exposing the top and sidewall surfaces of the underlying devices, in accordance with one embodiment of the present invention.

[0015] [Figure 8] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices, illustrating the deposition of conductive material in the gap left by removing a placeholder structure to form a central contact structure, in accordance with one embodiment of the present invention.

[0016] [Figure 9] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a pair of vertically stacked semiconductor devices, illustrating the formation of a trench in the conductive material of a central contact structure to separate the central contact structure into two separate contacts, in accordance with one embodiment of the present invention.

[0017] [Figure 10] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a pair of vertically stacked semiconductor devices, illustrating the formation of an electrical barrier structure within the trench that provides further electrical isolation between the two contacts, in accordance with one embodiment of the present invention.

[0018] [Figure 11] 1 is a block / flow diagram of a method for forming a semiconductor device having vertically stacked transistor devices according to one embodiment of the present invention.

[0019] [Figure 12]1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices, showing back-end-of-line layers in electrical communication with the device contacts, according to one embodiment of the present invention.

[0020] [Figure 13] 1A-1C are cross-sectional views of stages in the fabrication of contacts to a set of vertically stacked semiconductor devices, showing back-end-of-line layers in electrical communication with the device contacts, in which the device contacts are formed off-center, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Stacking field effect transistors (FETs) can increase the areal density of integrated chips as devices are formed on multiple vertically stacked layers of the chip. Vias can be formed through the overlying layers to make electrical contact to the embedded devices. The vias can be filled with a conductive material that makes contact with the underlying devices.

[0022] However, when forming devices close to each other, conductive vias to underlying devices can be made thin to reduce the risk of creating shorts between adjacent devices. Thinner vias are more likely to contain defects, such as voids, in their metal fill, which can interfere with device functionality. Additionally, narrow vias can be difficult to position, thereby reducing the contact area between the via and the underlying device. Electrical contact to the sidewalls of the underlying device can also be difficult, further reducing the potential electrical contact area.

[0023] Rather than using narrow vias, contacts to underlying devices can be made by splitting a relatively thick via into two contacts that connect to different respective devices. The thick via can be etched to form a trench that separates the conductive material into two separate vias, with a dielectric liner formed between them to prevent shorting. The relatively thick original contact structure reduces the risk of voids in the deposition of the conductive material and also allows electrical contact to be made along the sidewalls of the underlying devices, reducing contact resistance.

[0024] 1, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. Shown is a semiconductor substrate 102 divided into device regions 104 by shallow trench isolation (STI) regions 106. The device regions 104 establish locations where semiconductor devices may be formed in subsequent stages.

[0025] The semiconductor substrate 102 may be a bulk semiconductor substrate. In one example, the bulk semiconductor substrate may be a silicon-containing material. Illustrative examples of silicon-containing materials suitable for bulk semiconductor substrates include, but are not limited to, silicon, silicon germanium, silicon germanium carbide, silicon carbide, polysilicon, epitaxial silicon, amorphous silicon, and multilayers thereof. While silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be employed, including, but not limited to, germanium, gallium arsenide, gallium nitride, cadmium telluride, and zinc selenide. Although not shown in this figure, the semiconductor substrate 102 may also be a semiconductor-on-insulator (SOI) substrate.

[0026] The STI region 106 may be formed by any suitable process. For example, a photolithographic patterning process may be used to define a mask that covers the device region 104 and leaves other portions of the substrate 102 exposed. A timed, selective, anisotropic etch, such as reactive ion etch (RIE), may be used to remove the substrate material in the exposed regions, leaving trenches in the substrate 102. The trenches in the substrate 102 may then be filled with any suitable dielectric material, such as silicon dioxide, which may be deposited using a chemical vapor deposition (CVD) process and then polished to the level of the top surface of the substrate 102 (or any other suitable height) using a chemical mechanical planarization (CMP) process.

[0027] In a photolithography process, a pattern can be created by applying a photoresist to the surface to be etched. The photoresist is for patterning radiation. The pattern is then developed into the photoresist using a resist developer. Once the photoresist patterning is complete, the sections covered by the photoresist are protected, while the exposed areas are removed using a selective etching process that removes the unprotected areas.

[0028] RIE is a form of plasma etching in which the surface to be etched is placed on a radio frequency powered electrode during etching. Furthermore, during RIE, the surface to be etched is subjected to an electric potential that accelerates etching species extracted from the plasma toward the surface, where a chemical etching reaction occurs in a direction perpendicular to the surface. Other examples of anisotropic etching include ion beam etching, plasma etching, or laser ablation.

[0029] As used herein, the term "selective" in relation to a material removal process indicates that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied.

[0030] CMP may be performed, for example, using a chemical or granular slurry and mechanical force to gradually remove upper layers of the device. The slurry may be formulated, for example, to be unable to dissolve the work function metal layer material, thereby preventing the CMP process from progressing any farther than that layer.

[0031] 2, there is shown a cross-sectional view of a stage in the fabrication of a stacked semiconductor device. A set of subdevices 200 are formed on respective device regions 104 of a substrate 102. It should be understood that the cross-section is taken through a source / drain portion 202 of the device 200; other portions of the device, such as the channel and gate stack, are present but not shown.

[0032] The source / drain portions 202 may be formed of epitaxially grown semiconductor material that extends laterally from the channel of the device 200. For example, the device 200 may be a nanosheet FET in which thin sheets of semiconductor material are formed in a vertically stacked arrangement with gate stacks between and around the thin sheets of semiconductor material, and epitaxially grown source / drain material conductively connecting the sheets to their respective transistor devices. Other types of devices are also contemplated, including finFETs and nanowire FETs, which use different channel geometries.

[0033] As used herein, the terms "epitaxial growth" and / or "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the grown semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemical reactants are controlled and the system parameters are set correctly, the deposited atoms move around the surface and arrive at the deposition surface with enough energy to orient themselves relative to the crystalline arrangement of the atoms on the deposition surface. Thus, in some instances, an epitaxial film deposited on a {100} crystalline surface will adopt a {100} orientation.

[0034] Device 200 can be formed from any suitable semiconductor material. For example, the nanosheet channel (not shown) of device 200 can be formed from silicon or silicon germanium, and the source / drain regions 202 can be formed from the same semiconductor material or a similar compatible material that may include n-type or p-type dopants. The source / drain regions 202 can be doped in situ during formation or later doped by an ion implantation process.

[0035] 3, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. An interlayer dielectric 302 may be deposited on top of and around the device 200 to a height above the height of the device 200. The interlayer dielectric 302 may be formed from any suitable dielectric material, such as silicon dioxide, and may be deposited using any suitable deposition process. While CVD is specifically contemplated, any other deposition process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or gas cluster ion beam (GCIB) deposition, may be used instead.

[0036] CVD is a deposition process in which deposition species are formed as a result of a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., about 25°C to about 900°C). A solid product of the reaction is deposited on a surface, forming a film, coating, or layer of the solid product. Variations on CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metal organic CVD (MOCVD), and combinations thereof may also be employed. In an alternative embodiment using PVD, the sputtering equipment may include a direct current diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In an alternative embodiment using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In an alternative embodiment using GCIB deposition, high-pressure gases are expanded in a vacuum and then condensed into clusters. The clusters may be ionized and directed onto the surface, providing highly anisotropic deposition.

[0037] Portions of interlayer insulating film 302 may be etched away using, for example, a photolithographic patterning process and a selective anisotropic etch such as RIE. The etch may form a gap that exposes the top surface of device 200. While the entire top surface of device 200 is shown to be exposed by the gap, it should be understood that any amount of the top surface may be exposed.

[0038] The gap may then be filled with a placeholder material selected to be selectively etchable with respect to device 200 and interlayer dielectric 302. The placeholder material may be deposited by any suitable process, such as CVD, and polished to the level of the top surface of interlayer dielectric 302 using a CMP process to form placeholder 304. Exemplary placeholder materials may include titanium oxide or aluminum oxide, which may be cleanly removed without damaging the semiconductor structure of device 200.

[0039] It is specifically contemplated that the placeholder structure 304 may be limited to the regions above and between the source / drain portions 202 of the device 200. Because the placeholder structure 304 defines the area where the underlying contacts will ultimately be formed, the placeholder structure should not contact more than one region of a particular device 200 unless those contacted regions are intended to be electrically connected to one another. Thus, the placeholder structure 304 may contact the source, drain, or gate of the underlying device 200, and in some cases may contact the gate and one of the source and drain regions, but in most cases may not contact all three regions.

[0040] 4, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. Additional interlayer dielectric material is deposited on top of the placeholder 304 to form an interlayer dielectric 402, increasing the height of the interlayer dielectric 402 above the placeholder structure 304. A bonding layer 404, formed from, for example, a suitable dielectric oxide material, is then deposited on top of the interlayer dielectric 402 using any suitable deposition process. A layer of semiconductor material 406 is then deposited on top of the bonding layer 404 by any suitable process. The layer of semiconductor material 406 is used in subsequent stages to form upper layers of the device.

[0041] Referring now to FIG. 5 , a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. A layer of semiconductor material 406 is processed to form upper device 502. Like lower device 200, this cross-sectional view shows a cut through the source / drain portion of upper device 502. Upper device 502 may be fabricated by a similar process to lower device 200, or may be different. For example, upper device 502 may be a FET formed around a fin channel structure, or may include a nanosheet or nanowire channel structure. Like lower device 200, upper device 502 may include any suitable gate stack and source / drain composition. Upper interlayer dielectric 504 may be formed on top of and around upper device 502 to a height above the height of upper device 502 using any suitable deposition method and dielectric material.

[0042] 6, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. Contact openings 602 / 604 are etched into interlayer dielectric 402 and 504 using any suitable patterning process, followed by an anisotropic etch such as RIE. For example, an upper contact opening 604 may be formed that exposes the top surface of the source / drain region of upper device 502. A center contact opening 602 may also be formed through bonding layer 404 and interlayer dielectric 402 / 504 to expose the top surface of placeholder structure 304 in the region between source / drain portions 202 of lower device 200.

[0043] The top surface of the source / drain region of the upper device 502 may be exposed, while the source / drain portion 202 of the lower device 200 is protected by the placeholder structure 304. The exposed source / drain surface may be selectively modified to make good electrical contact for the upper device.

[0044] Electrical contacts between dissimilar conductive materials can have an interfacial contact resistance that impedes current flow. The interfacial contact resistance is inversely proportional to the contact area and proportional to a property of the interface materials called the specific contact resistivity. The specific contact resistivity between elemental metals is 1e-12 to 1e-11 Ω-cm.2 Between metal compounds such as silicides, germanosilicides, and metal nitrides or carbides, the specific contact resistivity can be in the range of 1e-11 to 1e-10 Ω-cm. 2 Between the doped semiconductor and the metal compound or metal, the specific contact resistivity can be in the range of 3e-9 to 1e-7 Ω-cm 2 The range may be:

[0045] Low specific interfacial resistivity e-9 Ω-cm due to the dominance of metal-semiconductor contact resistance 2 The interface can be engineered to obtain a resistivity in the range of . Interface engineering can include the addition of dopant atoms to the semiconductor surface and non-equilibrium activation of the surface dopants and the formation of suitable metal compounds at the interface. Complementary metal-oxide-semiconductor (CMOS) technology can include at least two sets of electronic devices of opposite polarity, such as n-type FETs (nFETs) and p-type FETs (pFETs). The interfacial contact engineering for these sets of devices can be different because surface modifiers that reduce the specific contact resistivity for one device type can degrade the specific contact resistivity for the other device type.

[0046] In one embodiment, the upper devices may have the same polarity. Accordingly, their exposed source / drain top surfaces may be modified by adding a surface dopant of the same polarity, such as boron, gallium, or indium for pFETs, or phosphorus, arsenic, or antimony for nFETs. Other elements may also be added to the source / drain top surfaces to further reduce the specific contact resistivity. In one example, germanium and / or tin may be added to pFETs, or carbon, niobium, lanthanum, and / or scandium may be added to nFETs. These electrically neutral elements may reduce the scattering of electrical carriers at the semiconductor-metal interface and may aid in the activation of surface dopants via non-equilibrium processes. For example, germanium and tin pin the semiconductor valence band to the metal Fermi level, reducing the interface Schottky barrier for p-type contacts. Niobium, lanthanum, and scandium may help reduce the interface Schottky barrier for n-type contacts. Like dopants of opposite polarity, these elements may only be useful in one device type and degrade the other type.

[0047] Dopants and additional elements can be introduced into the exposed top surface of the source / drain via low-temperature (<500°C) epitaxy, surface ion implantation, surface plasma treatment, and / or gas doping. At the end of this processing step, about 3 nm to about 10 nm of the exposed top surface of the source / drain can be modified. Low-temperature epitaxy conditions can be selected to allow selective growth, so that there is no continuous growth film on the structure 304 and other dielectric surfaces.

[0048] In one example, low-temperature selective epitaxy can be a CVD process using high-order silicon or germanium precursors, such as disilane or digermane. Such high-order precursors enable low-temperature (<500°C) epitaxial growth on exposed semiconductor surfaces and help preserve any metastable surface compounds that may have formed. Enhanced epitaxial selectivity can be achieved using an in-situ deposition-etch sequence.

[0049] The epitaxial growth process can also function as a non-equilibrium dopant activation process in which dopants are forced to lock into substitutional positions in the semiconductor lattice. Alternatively, surface dopants can be introduced at approximately 1e21 cm -3 The dopant may need to be activated to produce a highly degenerate semiconductor with active electrical carriers (electrons or holes). The non-equilibrium dopant activation process may involve amorphization of the exposed semiconductor top surface followed by regrowth of the amorphized region. The regrowth process works similarly to epitaxial growth, with the dopants being fixed into substitutional positions in the semiconductor lattice during thermally driven atomic rearrangement.

[0050] The surface amorphization process can be performed through ion implantation of dopants of the correct polarity or electrically neutral elements such as argon, xenon, or germanium. To promote amorphization at low doses, the ion implantation can be performed at room temperature or below. The ion implantation energy is selected to produce an amorphous layer of the desired thickness, which can be less than about 10 nm to avoid interaction with the internal device structure of the overlying device 502. Thermally driven surface recrystallization can be performed immediately after the process flow or at a later stage in the process flow.

[0051] In this recrystallization process, a short-duration anneal, such as a laser or flash anneal, is preferred, with an exemplary duration ranging from tens of milliseconds to tens of nanoseconds, and a peak anneal temperature may be selected to complete the recrystallization. In some cases, the recrystallization process may involve melting of the semiconductor top surface. In this embodiment, all exposed source / drain top surfaces of the upper device 502 may be modified using a selected process sequence beneficial to the polarity of the upper device 502. The top surfaces of the placeholder structures 304 in the regions between the source / drain portions 202 of the lower device 200 may remain exposed.

[0052] In other embodiments, the upper device 502 may be of mixed polarity, with both nFETs and pFETs present within the upper level. In such embodiments, the sequence for modifying the source / drain top surfaces is different. Patterning may be used to block one device polarity during a processing step and expose devices of the other polarity, followed by new patterning for the next processing step. Blocking may involve using a suitable hard mask material, such as silicon nitride, to prevent nucleation of low-temperature CVD epitaxy. After sequentially modifying the exposed source / drain top surfaces of the upper device 502 using selected process sequences beneficial for devices of each polarity, the top surfaces of the placeholder structures 304 in the regions between the source / drain portions 202 of the lower device 200 remain exposed.

[0053] 7, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. The placeholder structures 304, along with any contaminants introduced during surface modification, are etched away using any suitable isotropic etch, such as a wet or dry chemical etch. The etch removes material from between the lower source / drain structures 202 and the lower interlayer dielectric 402, exposing the top surfaces of the lower source / drain structures 202 as well as the sidewalls of the lower source / drain structures 202 and leaving a gap 702. Thus, removal of the placeholder structures 304 creates a gap 702 between and above the source / drain structures 202, although at least one sidewall of each of the lower source / drain structures 202 may remain covered by the lower interlayer dielectric 402.

[0054] The exposed surfaces of the underlying source / drain structures 202 may be selectively modified to make good electrical contact with the underlying device, with an exemplary specific contact resistivity of 1e-9 Ω-cm 2The surface modification process may include chemical deposition and treatment that may penetrate the gap 702 and modify the exposed horizontal surfaces of the lower source / drain 202. Furthermore, the presence of the exposed modified surface of the upper source / drain 502 imposes additional constraints on the surface modification process of the lower source / drain structures, such that they have a specific contact resistivity of 1e-9 Ω-cm or less. 2 5A does not prevent the formation of electrical contacts to the upper source / drain structures 502 that are 502 or less.

[0055] In one embodiment, all of the lower devices may have the same polarity. Low-temperature (<500°C) selective epitaxy may be employed to modify the surfaces of the lower source / drain structures 202 according to their polarity, as described above, while preserving the modified surface of the upper source / drain structures 502 as well as the dielectric surface. Low-temperature epitaxy allows epitaxial growth on the exposed semiconductor surfaces of the lower source / drain structures 202, but not on the modified surface of the upper source / drain structures due to the different semiconductor materials employed in the source / drain structures of the upper and lower devices, such as silicon versus silicon germanium. Epitaxy selectivity may be further improved by maintaining the modified surface of the upper source / drain structures 502 in an amorphous state after the ion implantation amorphization process and throughout this selective epitaxy step.

[0056] Although epitaxial growth is prevented or prevented on the modified surface of the upper source / drain structures 501, the surface may be contaminated with dopants or elements of a different polarity. Low-temperature epitaxial growth limits this contamination to within 3 nm of the surface. A directional etching process, such as RIE, can be performed after selective epitaxial growth to remove contaminated surface material from the modified surface of the upper source / drain structures 502 while preserving the grown epitaxy on the surface of the lower source / drain structures 202. The epitaxial growth process on the surface of the lower source / drain structures 202 can also serve as a non-equilibrium dopant activation process, as mentioned above. A short-duration anneal, such as a laser or flash anneal, can be performed to further activate the dopants in the grown epitaxial layer and recrystallize any amorphous layer that may still be present in the source / drain structures.

[0057] Referring now to Figure 8, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. A first conductive material is deposited to form an interfacial contact with the modified semiconductor surface. The first conductive material may be in the form of a thin liner only a few nanometers thick. The purpose of the first conductive material is to form a suitable metal compound at the interface with the adjacent semiconductor, thereby increasing the specific contact resistivity of these semiconductor-metal interfaces to, for example, 1e-9 Ω-cm. 2 The bulk resistivity of the first conductive material is not critical as long as it allows for low contact resistance.

[0058] The first conductive material can be the same or different for the lower and upper devices. In embodiments in which the first conductive material is different for the lower and upper devices, the first material type can be first deposited by a directional deposition process such as PVD, followed by conformal deposition of the second material type using a CVD or ALD process. The first material type coats only exposed horizontal surfaces and is absent in the gaps 702 and on vertical surfaces, while the second material type coats all surfaces. In embodiments in which all upper devices are of a first polarity and all lower devices are of a second polarity, the first conductive material type can be employed to independently reduce the specific contact resistivity of the semiconductor-metal interface of different polarities. For example, if all upper devices are pFETs and all lower devices are nFETs, the first material type can be a PVD-deposited thin layer of nickel or platinum, while the second material type can be a CVD-deposited thin layer of titanium. In this case, the nFET contact interface will be between the titanium silicide and the degenerate n-type semiconductor, while the pFET contact interface will be between the nickel and / or platinum germanosilicide and the degenerate p-type semiconductor.

[0059] In some embodiments, the first conductive material is the same for the lower and upper devices. For example, if all upper devices are pFETs and all lower devices are nFETs, the common first conductive material can be a thin CVD-deposited layer of titanium. In this case, the nFET contact interface is between titanium silicide and the degenerate n-type semiconductor, and the pFET contact interface is between titanium germanosilicide and the degenerate p-type semiconductor.

[0060] A second conductive material may be deposited using a conformal deposition process, such as CVD or ALD, to coat the first conductive material in upper trench 604 and central trench 602 and in gap 702, filling gap 702. The second conductive material fills these spaces and may then be polished down to the level of upper interlayer dielectric 504 to create composite upper contact 802 and composite central contact structure 804.

[0061] The second conductive material reduces the bulk resistivity of the contact structures. Accordingly, the second conductive material may be selected from metals and metal compounds having low effective bulk resistivity (bulk resistivity tailored for small trench and gap dimensions). The second conductive material of the upper contact composite structure 802 and the center contact composite structure 804 may be formed from any suitable conductive metal, such as tungsten, nickel, titanium, molybdenum, tantalum, copper, platinum, silver, gold, ruthenium, iridium, rhenium, rhodium, cobalt, and alloys thereof. The first and second conductors may be separated by a thin (e.g., <2 nm) conductive diffusion barrier to prevent intermixing. In some cases, the first and second conductors may be made from the same material or alloy that forms respective interfacial silicides and germanosilicides at the semiconductor interface.

[0062] The central contact composite structure 804 makes electrical contact to both the top surface of the lower source / drain regions 202 and along their sidewalls, potentially providing a resistance of 1e-9 Ω-cm across the metal-semiconductor interface. 2 The central composite contact structure 804 allows for a low specific contact resistivity, which is lower than that of a semiconductor-metal interface. Because the metal-metal specific contact resistivity is at least an order of magnitude lower than that of a semiconductor-metal interface, multiple metal-metal interfaces that may exist with the composite structure 804 do not significantly affect the overall contact resistivity. Because the width of the central contact structure 804 is relatively wide, the second conductor material with its low effective bulk resistivity allows for a low bulk resistivity. Because few metal voids should occur during the deposition process, the electrical contact between the central composite contact structure 804 and the source / drain structures 202 is improved, reducing the overall contact resistivity.

[0063] At the same time, the upper contact composite structure 802 makes electrical contact with the upper source / drain region 502, potentially providing 1e-9 Ω-cm across the metal-semiconductor interface. 2The composite structure 802 allows for a low specific contact resistivity, lower than that of a semiconductor-metal interface. Because the metal-metal specific contact resistivity is at least an order of magnitude lower than that of a semiconductor-metal interface, the multiple metal-metal interfaces that may exist with the composite structure 802 have a significant impact on the overall contact resistivity. Due to the relatively low effective bulk resistivity of the second conductor material in the composite structure 802 and the low specific contact resistivity at the interface with the upper source / drain structure 502, the upper contact composite structure 802 provides improved electrical contact to the upper source / drain structure 502 with a substantially reduced overall contact resistivity.

[0064] 9, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. A trench 902 is etched through the central contact structure 804 and down into the underlying STI region 106 using any suitable patterning process and anisotropic etching. The etching may include a non-selective etch that removes material from both the central contact structure and the STI region 106, or it may include two separate etches that are selective to the conductive material of the central contact structure 804 and the STI region 106, respectively. The trench 902 separates the central contact structure 804 into two via / contacts 904, each of which makes electrical contact with a respective lower source / drain portion 202. The trench 902 electrically isolates the two lower devices 200 from each other.

[0065] Although trench 902 is shown as being located along the centerline of central contact structure 804, with the resulting via / contact 904 being approximately equal in size, it should be understood that trench 902 could instead be located off-center. The placement of trench 902 could be selected to provide via / contact 904 that aligns with signal or power lines in subsequently added overlying back-end-of-line (BEOL) layers. Such an alternative embodiment is shown with respect to FIG.

[0066] 10, a cross-sectional view of a stage in the fabrication of a stacked semiconductor device is shown. Trench 902 is filled with an electrically insulating structure including a dielectric liner 1002 and an interlayer dielectric fill 1004. Dielectric liner 1002 and interlayer dielectric fill 1004 may each be formed using any suitable conformal deposition process, such as CVD or ALD. Before interlayer dielectric fill 1004 is deposited, the deposited liner material may be removed from horizontal surfaces by an anisotropic etch, such as RIE.

[0067] The dielectric liner 1002 may be formed from a high-k dielectric material, which may refer to a material having a higher dielectric constant than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, metal oxides such as silicon nitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The interlayer dielectric filler 1004 may be formed from any suitable dielectric material, such as silicon dioxide.

[0068] 11 , a method of fabricating a stacked device is shown. In block 1102, a lower device 200 is formed on a device region 104 of a substrate 102. The lower device 200 may be any suitable semiconductor device, although it is specifically contemplated that such a device may include a finFET, a nanosheet FET, or a nanowire FET. A placeholder structure 304 is formed in block 1104 over a portion of the lower device 200, for example, to contact the lower source / drain structure 202. An interlayer dielectric 402 may be formed on top of and around the placeholder structure 304.

[0069] In block 1106, a bonding layer 404 is formed on top of the placeholder structure 304 to demarcate the lower layer from the upper layer. In block 1108, an upper device 502 is formed on the bonding layer 404, which may be any suitable semiconductor device and may be disposed directly on top of the lower device 200. In block 1110, an upper interlayer dielectric 504 is formed on top of the upper device 502, and in block 1112, trenches are formed in the upper dielectric layer 504, including an upper trench 604 and a center trench 602 that expose the top surfaces of the upper device 502 and the placeholder structure 304, respectively.

[0070] In block 1114, the placeholder structure 304 is etched away using any suitable isotropic etch to expose the top and sidewall surfaces of the underlying device 200. Next, in block 1116, a conductive material that makes electrical contact with the underlying device 200 is deposited using a conformal deposition process to form the central conductor structure 804. In block 1118, a trench 902 is etched in the central conductor structure to separate the central conductor structure 804 into two vias / contacts 904. Next, in block 1120, the trench 902 is filled with an insulating structure that includes, for example, a dielectric liner 1002 and a dielectric fill material 1004.

[0071] 12, a cross-sectional view of a stacked semiconductor device is shown. In this view, back-end-of-line (BEOL) layers include a BEOL dielectric 1202 having metal lines 1206 and vias 1204 connecting particular metal lines 1206 to contacts 802 and 904. An electrical rail 1208 carries either a ground voltage or an operating voltage. In this embodiment, a lower contact 904 is shown as being in electrical contact with the metal line 1206, for example, for signal communication with other devices on the integrated chip.

[0072] 13, a cross-sectional view of a stacked semiconductor device is shown. In this view, the BEOL layers are shown similarly to FIG. 12. However, to make contact with the electrical rail 1208, the trench 902 and the partition structure 1002 / 1004 may be positioned off-center, such that one of the resulting lower contacts is wider than the other. The partition structure 1002 / 1004 may be positioned at any suitable point to facilitate contact between the via 1204, the lower contact 904, and any suitable conductive structure in the BEOL.

[0073] Aspects of the invention are described in terms of given example architectures; however, it is understood that other architectures, structures, substrate materials, and process features and steps may be varied within the scope of aspects of the invention.

[0074] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it is understood that it can be directly on the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is understood that it can be directly connected or coupled to the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0075] This embodiment may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., over the Internet). The stored design is then converted into a format appropriate for the manufacture of photolithography masks (e.g., GDSII), which typically include multiple copies of the chip design that will be formed on wafers. The photolithography mask is utilized to define the areas of the wafer (and / or layers thereon) that will be etched or otherwise processed.

[0076] Methods such as those described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by manufacturers in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-end applications to sophisticated computer products with displays, keyboards or other input devices, and central processing units.

[0077] It should also be understood that material compounds are described in terms of the elements listed, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe may contain Si x Ge 1-x where x is less than or equal to 1, etc. In addition, other elements may be included in the compound and still function according to the present principles. Compounds with additional elements are referred to herein as alloys.

[0078] References herein to "one embodiment" or "an embodiment," as well as other variations thereof, mean that particular features, structures, characteristics, and the like described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations thereof, appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0079] For example, in the case of "A / B," "A and / or B," and "at least one of A and B," it should be understood that the use of any of the following terms " / ," "and / or," and "at least one of" is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C," such phrases are intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This can be extended to many of the items listed, as would be readily apparent to one skilled in this and related arts.

[0080] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit example embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0081] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like are used herein for ease of description and may describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures were turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" such other elements or features. Thus, the term "below" can encompass both an orientation above and below. A device may be otherwise oriented (rotated 90 degrees or to another orientation), and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, when a layer is referred to as being "between" two layers, it will also be understood that it may be the only layer between the two layers, or that one or more intervening layers may also be present.

[0082] Terms such as "first," "second," etc. may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0083] Having described preferred embodiments of stacked FET contact formation (intended to be illustrative and not limiting), it should be noted that modifications and variations may occur to those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the specific embodiments disclosed that are within the scope of the invention and outlined by the appended claims. Thus, having described aspects of the invention with the detail and particularity required by the patent laws, what is claimed and desired to be protected by Letters Patent is set forth in the appended claims.

Claims

1. a first lower-level device and a second lower-level device on a substrate; a first upper device above the first lower device and a second upper device above the second lower device; a first lower contact extending from a level above the first upper device and making electrical contact with a top surface and a sidewall surface of the first lower device, the first lower contact extending laterally below the first upper device; a second lower contact extending from a level above the second upper device and making electrical contact with the top and sidewall surfaces of the second lower device, the second lower contact extending laterally below the second upper device; and an insulating barrier between the first lower contact and the second lower contact; A semiconductor device comprising:

2. 10. The semiconductor device of claim 1, wherein the insulating partition comprises a dielectric liner and a dielectric filler formed from distinct dielectric materials.

3. 3. The semiconductor device of claim 2, wherein the dielectric liner is formed from a high-k dielectric material and the dielectric fill is formed from silicon dioxide.

4. 2. The semiconductor device of claim 1, wherein the first lower contact has a width different from a width of the second lower contact.

5. 2. The semiconductor device of claim 1, wherein the substrate has a shallow trench isolation (STI) region between the first lower device and the second lower device, and the insulating partition extends to a depth below a top surface of the STI region.

6. 2. The semiconductor device of claim 1, wherein the sidewalls of the first lower contact at the portion extending laterally below the first upper device are sloped.

7. 2. The semiconductor device of claim 1, wherein the first lower contact makes electrical contact with a source / drain portion of the first lower device and the second lower contact makes electrical contact with a source / drain portion of the second lower device.

8. 10. The semiconductor device of claim 1, further comprising a back end of line (BEOL) layer having a first line in electrical contact with the first lower contact and a second line in electrical contact with the second lower contact.

9. The semiconductor device of claim 1 , wherein the first lower contact and the second lower contact are devoid of voids.

10. forming a placeholder structure on the substrate above the first and second lower devices; forming a first upper device and a second upper device on the dielectric layer above the first lower device and the second lower device, respectively; selectively etching away the placeholder structure to expose a top surface and a sidewall surface of each of the first underlying device and the second underlying device; depositing a conductive material that makes electrical contact with the top surface and the sidewall surfaces of each of the first and second underlying devices; etching a trench in the conductive material separating the conductive material into a first lower contact and a second lower contact; forming a barrier structure within the trench to electrically isolate the first lower contact and the second lower contact; 1. A method of forming a semiconductor device, comprising:

11. The step of forming the barrier rib structure includes: conformally depositing a first dielectric material in the trench; and depositing a second dielectric material to fill the trench; 11. The method of claim 10, comprising:

12. 12. The method of claim 11, wherein the first dielectric material is a high-k dielectric material and the second dielectric material is silicon dioxide.

13. The method of claim 10 , wherein etching the trench comprises an anisotropic etch that extends to a depth below an upper surface of the substrate.

14. 11. The method of claim 10, wherein etching the trench comprises etching the trench off-center in the conductive material such that the first lower contact is formed with a width greater than the second lower contact.

15. The step of forming the placeholder structure includes: depositing a first dielectric material over and around the first and second lower devices; etching away the first dielectric material on and between the first and second lower devices to expose a first sidewall of each of the first and second lower devices; and depositing a placeholder material over and between the first and second lower devices; 11. The method of claim 10, comprising:

16. The method of claim 15 , wherein depositing the placeholder material comprises a conformal deposition process.

17. 16. The method of claim 15, wherein etching away the first dielectric material leaves a portion of the first dielectric material covering a second sidewall of each of the first underlying device and the second underlying device.

18. forming a pair of lower device tops and a placeholder structure therebetween; forming a dielectric layer over the placeholder structure; etching away the placeholder structures to leave gaps between the pair of underlying devices and the dielectric layer; depositing a conductor to fill the gap; and etching trenches in the conductor to form contacts to each of the pair of lower devices; 1. A method of forming a semiconductor device, comprising:

19. 20. The method of claim 18, further comprising forming a barrier structure in the trench to electrically isolate the contact.

20. 20. The method of claim 18, wherein etching the trench comprises etching the trench off-center of the conductor such that a first contact is formed with a wider width than a second contact.

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