Josephson Static Random Access Memory

Abstract

Described herein are Josephson junction-based memory devices and methods of use. An exemplary Josephson junction-based memory device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The plurality of superconducting loops are configured to store or annihilate a flux quantum in one or more of the superconducting loops in response to a combination of a control signal and a single flux quantum (SFQ) pulse.

Description

[Technical Field]

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 815,358, filed July 27, 2022, the contents of which are incorporated herein by reference.

[0002] This application relates to superconducting circuits. In particular, this application discloses a static random access memory (SRAM) implemented using a plurality of superconducting Josephson junctions (JJs) and associated circuitry. Such memories are configured to transduce information in the form of magnetic flux quanta and may transfer such information based on single flux quantum (SFQ) pulses. [Background technology]

[0003] Superconducting digital systems are capable of performing computational operations at clock speeds exceeding 100 GHz. In these systems, circuits comprise superconducting wires and Josephson junctions that together form superconducting loops in which information is transformed and stored in the form of single flux quanta.

[0004] Superconducting circuits can be configured to implement conventional logic gates such as AND gates, OR gates, flip-flops, etc. These gates can be configured to implement more complex logic such as shift registers, counters, and processors.

[0005] However, there is a need for JJ-based SRAMs that are 1) sufficiently fast and dense, 2) support multiple read / write ports, and 3) can be fabricated using the same process / stackup as the corresponding JJ-based logic circuits. Summary of the Invention

[0006] In a first aspect, a Josephson junction-based memory device is provided. The Josephson junction-based memory device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The plurality of superconducting loops are configured to store or annihilate a flux quantum in one or more of the superconducting loops in response to a combination of a control signal and a single flux quantum (SFQ) pulse.

[0007] In a second aspect, a method for storing digital information in a Josephson junction-based memory device is provided. The method includes providing a combination of a control signal and a single flux quantum (SFQ) pulse to a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The method also includes storing or annihilating a flux quantum in one or more of the superconducting loops in response to the combination of the control signal and the SFQ pulse.

[0008] The above and additional features will be better understood through the following illustrative and non-limiting detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 shows a schematic diagram of a Josephson junction-based memory device according to an example embodiment. [Figure 2A] FIG. 2A illustrates a write pass sequence from a 0 state to a 1 state utilizing the Josephson junction-based memory device of FIG. 1 according to an example embodiment. [Figure 2B] FIG. 2B illustrates a write pass sequence from a 1 state to a 0 state utilizing the Josephson junction-based memory device of FIG. 1 according to an example embodiment. [Figure 3A] FIG. 3A illustrates a read pass sequence for reading one state utilizing the Josephson junction-based memory device of FIG. 1 according to an example embodiment. [Figure 3B] FIG. 3B illustrates a read pass sequence for reading a 0 state utilizing the Josephson junction-based memory device of FIG. 1 according to an example embodiment. [Figure 4] FIG. 4 illustrates a circuit diagram of the Josephson junction-based memory device of FIG. 1 according to an exemplary embodiment. [Figure 5A] FIG. 5A illustrates a flux initialization process according to an example embodiment. [Figure 5B] FIG. 5B illustrates a flux initialization process according to an example embodiment. [Figure 5C] FIG. 5C shows multiple unit cells sharing the same magnetic flux source, according to an example embodiment. [Figure 6] FIG. 6 illustrates an array of unit cells arranged in a word-organized memory fabric, according to an exemplary embodiment. [Figure 7] FIG. 7 illustrates a wave-pipelining arrangement of an array of unit cells, according to an example embodiment. [Figure 8] FIG. 8 illustrates an arrangement of divided subarrays according to an exemplary embodiment. [Figure 9A] FIG. 9A is a diagram illustrating a split unit cell with separate write and read paths, according to an example embodiment. [Figure 9B] FIG. 9B shows a unit cell with a replicated read path according to an example embodiment. [Figure 9C] FIG. 9C illustrates a unit cell with a replicated write path according to an example embodiment. [Figure 10] FIG. 10 shows a schematic diagram of an alternative Josephson junction-based memory device according to an example embodiment. [Figure 11A]FIG. 11A illustrates a read pass sequence for reading one state utilizing the alternative Josephson junction-based memory device of FIG. 10, according to an example embodiment. [Figure 11B] FIG. 11B illustrates a read pass sequence for reading a 0 state utilizing the alternative Josephson junction-based memory device of FIG. 10, according to an example embodiment. [Figure 12A] FIG. 12A illustrates a first variation of a read path utilizing the alternative Josephson junction-based memory device of FIG. 10, according to an example embodiment. [Figure 12B] FIG. 12B illustrates a second variation of the read path utilizing the alternative Josephson junction-based memory device of FIG. 10, according to an example embodiment. [Figure 12C] FIG. 12C illustrates a third variation of the read path utilizing the alternative Josephson junction-based memory device of FIG. 10, according to an example embodiment. [Figure 13A] FIG. 13A illustrates a read path sequence for reading one state using a first variation of the read path of the alternative Josephson junction-based memory device of FIG. 12A, according to an example embodiment. [Figure 13B] FIG. 13B illustrates a read path sequence for reading a 0 state using a first variation of the read path of the alternative Josephson junction-based memory device of FIG. 12A, according to an example embodiment. [Figure 14A] FIG. 14A illustrates a read path sequence for reading one state using a second variation of the read path of the alternative Josephson junction-based memory device of FIG. 12B, according to an example embodiment. [Figure 14B] FIG. 14B illustrates a read path sequence for reading a 0 state using a second variation of the read path of the alternative Josephson junction-based memory device of FIG. 12B, according to an example embodiment. [Figure 15A]FIG. 15A illustrates a read path sequence for reading one state using a third variation of the read path of the alternative Josephson junction-based memory device of FIG. 12C, according to an example embodiment. [Figure 15B] FIG. 15B illustrates a read path sequence for reading a 0 state using a third variation of the read path of the alternative Josephson junction-based memory device of FIG. 12C, according to an example embodiment. [Figure 16] FIG. 16 shows a circuit diagram of a first variation of the read path of the alternative Josephson junction-based memory device of FIG. 12A, according to an example embodiment. [Figure 17] FIG. 17 shows a circuit diagram of a second variation of the read path of the alternative Josephson junction-based memory device of FIG. 12B, according to an example embodiment. [Figure 18] FIG. 18 shows a circuit diagram of a third variation of the read path of the alternative Josephson junction-based memory device of FIG. 12C, according to an example embodiment. [Figure 19] FIG. 19 illustrates a method according to an exemplary embodiment.

[0010] All figures are schematic, not necessarily to scale, and show only those parts necessary to explain the exemplary embodiment as a whole; other parts may be omitted or merely suggested. DETAILED DESCRIPTION OF THE INVENTION

[0011] Various example systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as being exemplary is not necessarily to be construed as preferred or advantageous over other embodiments, implementations, and / or features, unless so described. Accordingly, other embodiments, implementations, and / or features may be utilized, and other changes may be made, without departing from the scope of the subject matter presented herein.

[0012] Accordingly, the examples set forth herein are not meant to be limiting. It will be readily understood that the aspects of the present disclosure, as generally described and illustrated in the Figures herein, can be arranged, substituted, combined, separated, and designed in a wide variety of different configurations.

[0013] Furthermore, unless the context suggests otherwise, the features illustrated in each of the figures may be used in combination with one another. Thus, the figures should generally be viewed as components of one or more overall embodiments, with the understanding that not all of the illustrated features are required for each embodiment.

[0014] Furthermore, the recitation of elements, blocks, or steps in the specification or claims is for clarity and, therefore, should not be construed as requiring or implying that these elements, blocks, or steps follow a particular arrangement or be performed in a particular order.

[0015] Furthermore, terms such as "substantially" or "about" that may be used herein mean that the stated characteristic, parameter, or value need not be achieved exactly, but rather that deviations or variations, including, for example, tolerances, measurement errors, limits of measurement accuracy, and other factors known to those skilled in the art, may occur in an amount that does not interfere with the effect that the characteristic is intended to provide.

[0016] Furthermore, terms such as "A coupled to B" or "A electrically coupled to B" do not necessarily mean that items A and B are directly coupled to one another. For example, a first component being electrically coupled to a second component is interpreted to mean that the components are directly coupled (e.g., via conductors) or that the components are coupled to one another through one or more resistors, capacitors, inductors, and / or other active or passive components.

[0017] The potential of superconducting digital technology as a Beyond CMOS technology stems from its high energy efficiency, high computational density, and high interconnect bandwidth. The technology is based on single flux quantum (SFQ) pulses, which enable high speed, low power, and low dispersion / loss over superconducting transmission lines. Exemplary embodiments include various combinations of manufacturing materials, density, power / clock distribution, logic and memory design, packaging, interfaces, and architectures. Logic devices based on such technology have demonstrated a power density of 400 million JJ / cm. 2 It is predicted to have a computational density comparable to state-of-the-art CMOS based on increased integration and a clock rate of 30 GHz.

[0018] High-performance logic requires on-chip memory that is 1) sufficiently fast and dense, 2) supports multiple read and write ports, and 3) can be fabricated in the same process / stackup as the logic. For conventional CMOS logic technology, static random access memory (SRAM) meets these requirements. The presently described Josephson junction static random access memory (JSRAM) meets these requirements for superconducting SFQ logic and is an analog of SRAM.

[0019] XY addressing and readout of JSRAM is achieved by transferring the stored SFQ between a serial arrangement of adjacent superconducting loops. Conventional Josephson transmission line (JTL) interconnects provide high fanout throughout the memory array. This JSRAM design is scalable to multiple read and write ports.

[0020] Because the JSRAM design avoids exotic devices such as magnets, it can be fabricated in the same process / stackup as high-performance SFQ logic. Furthermore, because JSRAM utilizes native SFQ logic signals, it does not require potentially complex conversion processes and hardware. The JSRAM design also avoids physically large components such as transformers and achieves 5MB / cm using 193i lithography. 2 Wave pipelining enables throughput equal to the clock rate of the logic, achieving a design density 500 times greater than conventional devices.

[0021] Example of a Josephson junction-based memory device 1 is a schematic diagram of a Josephson junction-based memory device 100 according to an example embodiment. The Josephson junction-based memory device 100 includes multiple superconducting loops 102. Each superconducting loop (e.g., superconducting loops 102a, 102b, 102c, 102d, or 102e) includes at least one Josephson junction (e.g., Josephson junctions 104a, 104b, 104c, and / or 104d). In such a scenario, the multiple superconducting loops 102 are electrically coupled to each other.

[0022] Additionally, the multiple superconducting loops 102 may include multiple input loops 110 and multiple readout loops 120. As shown in Figure 1, the input loop 110 of the write path overlaps with the readout loop 120 of the read path. That is, the input loop 110d and the readout loop 120a utilize the same superconducting loop, which may be referred to as a "shared loop" (e.g., shared loop 130).

[0023] 1, multiple superconducting loops 102 may be electrically coupled in a series arrangement. In some embodiments, the series arrangement may include five superconducting loops (e.g., superconducting loops 102a, 102b, 102c, 102d, and 102e), four of which are input loops (e.g., input loops 110a, 110b, 110c, and 110d), two of which are readout loops (e.g., readout loops 120a and 120b), and one of which is a shared loop (e.g., shared loop 130). In such a scenario, each superconducting loop of multiple superconducting loops 102 has one or two adjacent loops. As an example, superconducting loop 102a has one adjacent loop (superconducting loop 102b), superconducting loop 102b has two adjacent loops (superconducting loop 102a and superconducting loop 102c), superconducting loop 102c has two adjacent loops (superconducting loop 102b and superconducting loop 102d), superconducting loop 102d has two adjacent loops (superconducting loop 102c and superconducting loop 102e), and superconducting loop 102e has one adjacent loop (superconducting loop 102d). It will be understood that other arrangements of superconducting loops 102 are possible and are contemplated in connection with the present disclosure.

[0024] The Josephson junction-based memory device 100 also includes a plurality of address lines coupled to the plurality of superconducting loops 102. In some embodiments, each address line of the plurality of address lines 102 may include a Josephson transmission line and a current bias source. Additionally, the current bias source may provide an AC signal corresponding to a global resonant clock network 170, which may provide a system-wide clock that helps enable operation in a synchronized manner.

[0025] In such an embodiment, each address line of the plurality of address lines also includes a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops 102 .

[0026] The plurality of superconducting loops 102 are configured to store or annihilate a magnetic flux quantum (e.g., SFQ 140a or SFQ 140b) in one or more superconducting loops in response to a combination of a control signal and a single flux quantum (SFQ) pulse.

[0027] In an exemplary embodiment, control signals may be provided to the superconducting loops 102 by bit write control line 160, word write control line 162, word read control line 164, and / or strobe control line 166. Additionally, the multiple superconducting loops 102 are coupled to a global resonant clock network 170.

[0028] In some embodiments, the multiple superconducting loops 102 are configured to shift a magnetic flux quantum (e.g., SFQ 140a) from an initial superconducting loop (e.g., superconducting loop 102c) to an adjacent loop (e.g., superconducting loop 102b) in response to an SFQ pulse applied to the initial superconducting loop.

[0029] The write path of JSRAM involves transferring stored single flux quantum (SFQ) between superconducting loops separated by Josephson junctions (JJs), and the read path involves sensing the location of the stored SFQ. The specific write and read operations are described in more detail below.

[0030] The operating principle involves the addition of currents in Josephson junctions (e.g., Josephson junctions 104a, 104b, 104c, and 104d). If a positive signal current constructively adds to a stored SFQ, which is a persistent current in a superconducting loop, the SFQ moves one step to the left. Alternatively, if a negative signal current is added to a stored SFQ, the SFQ moves one loop to the right.

[0031] The control signals for the write operation are Word Write (WW) and Bit Write (BW), with polarity indicated by (+) or (-). Note that if the state of the cell is not being read, the strobe (S) signal passes to the output (Q) regardless of the state of the cell.

[0032] In this manner, multiple superconducting loops 102 may be configured to respond to a combination of control signals and SFQ pulses to provide information indicative of the presence of magnetic flux quanta in one or more of the superconducting loops.

[0033] 2A illustrates a write pass sequence 200 from a 0 state to a 1 state, according to an exemplary embodiment, utilizing the Josephson junction-based memory device 100 of FIG. 1. Specifically, the write pass sequence 200 illustrates the input SFQ pulse sequence required to move from a 0 state (e.g., an SFQ stored in the third superconducting loop 102c) to a 1 state (e.g., an SFQ stored in the second superconducting loop 102b).

[0034] From an initial 0 state in which the SFQ (e.g., SFQ 140a) is in the third superconducting loop (e.g., superconducting loop 102c), a positive signal current on the word write control line (e.g., word write control line 162) may act to shift the SFQ to the second superconducting loop (e.g., superconducting loop 102b).

[0035] In other words, a magnetic flux quantum stored in an initial superconducting loop (e.g., SFQ 140a) may be shifted in a first direction (e.g., left) along the serial arrangement to an adjacent loop (e.g., superconducting loop 102b) in response to a positive SFQ pulse polarity supplied to word write control line 162. Conversely, the magnetic flux quantum may be shifted in a second direction (e.g., right) along the serial arrangement from a superconducting loop (e.g., superconducting loop 102b) to an adjacent loop (e.g., superconducting loop 102c) in response to a negative SFQ pulse polarity supplied to word write control line 162. It will be understood that the principles of shifting magnetic flux quanta using SFQ pulses via control lines may be applied more generally to shift magnetic flux between adjacent superconducting loops.

[0036] 2B illustrates a write pass sequence 220 from a 1 state to a 0 state, according to an example embodiment, utilizing the Josephson junction-based memory device 100 of FIG. 1. Specifically, write pass sequence 220 illustrates the input SFQ pulse sequence required to move from a 1 state (e.g., an SFQ stored in the second superconducting loop 102b) to a 0 state (e.g., an SFQ stored in the third superconducting loop 102c).

[0037] 3A and 3B show the read path of memory device 100. In this design, a read operation requires two clock cycles to complete, although an additional parallel write operation to another cell may be performed during the second cycle.

[0038] In an exemplary embodiment, memory device 100 may provide and receive read control signals over a plurality of address lines to at least some of the plurality of superconducting loops 102. In an exemplary embodiment, the read control signals include a word read, a strobe, and an output. A read pass sequence of the control signals is shown below:

[0039] FIG. 3A illustrates a read pass sequence 300 for reading a 1 state using the Josephson junction-based memory device 100 of FIG. 1 according to an exemplary embodiment. The read pass sequence 300 provides a Josephson junction switching sequence when reading a 1 state. Similar to a write operation, the operating principle involves current summation in Josephson junctions (e.g., Josephson junctions 104a, 104b, 104c, and 104d). When a positive signal current constructively adds to the stored SFQ, which is a persistent current in the loop, the SFQ moves to the superconducting loop one to the left. When a negative signal current adds to the negative current of the stored SFQ, the SFQ moves to the superconducting loop one to the right. In a shared JJ, the currents of the SFQs stored in adjacent loops cancel each other out, so two SFQs never occupy the shared loop at the same time. A Q output is generated only when the S junction switches and the stored pulse moves between loops. The control signals for a read operation are word read (WR), strobe (S), and output (Q), with polarity indicated by (+) or (-). A WR event must surround an S event. For an AC-powered Josephson junction, where the positive and negative pulses must occur on opposite halves of the clock cycle, this means that a pair of S events can be completed within one clock cycle, but a pair of WR events requires two clock cycles.

[0040] 3B shows a read pass sequence 320 for reading the 0 state utilizing the Josephson junction-based memory device 100 of FIG. 1, according to an example embodiment. The read pass sequence 320 provides a switching sequence of the Josephson junction when reading the 0 state.

[0041] FIG. 4 shows a circuit diagram 400 of the Josephson junction-based memory device 100 of FIG. 1 according to an exemplary embodiment. The circuit diagram 400 consists of a standard Josephson transmission line (JTL) stage along the address lines. The current sources (arrows) represent AC bias, allowing both positive and negative SFQ pulses to propagate at different times during the clock cycle. The registers couple the inputs to the cell's interior. Each junction-register pair is a decision-making element. If the signal current sums with the same polarity as the SFQ current in the storage loop seen by the junction, the signal triggers the junction to generate an SFQ pulse and transfers the stored pulse to the adjacent storage loop. Otherwise, the signal voltage is lost across the register. Note that similar behavior can be achieved by replacing some or all of these coupling registers with additional Josephson junctions. The pulsed voltage sources (dots) represent SFQ sources that generate the initial state. The illustrated initial state corresponds to the 0 state, although other initial states may be used. Finally, the current sources correspond to AC biases provided by an on-chip global resonant clock network. The phase of the bias source is provided to coincide with the desired SFQ pulse timing.

[0042] In practice, it is not necessary to use a pulsed voltage source to set the initial state. An actual physical implementation uses the magnetic coupling provided by the control lines. Various methods are shown in Figures 5A, 5B, and 5C, which may help reduce the physical size of the control lines and increase the accuracy of the initial state.

[0043] 5A shows a flux initialization process 500 according to an example embodiment. In an example embodiment, both SFQs may be initialized to the rightmost loop of the unit cell so that there is only one transformer. The current required in the primary depends on the desired flux and the mutual inductance M according to the following equation:

[0044]

number

[0045] FIG. 5B illustrates a flux initialization process 520 according to an example embodiment. As an alternative to the flux initialization process 500, the flux may be initialized in a two-step flux initialization process 520. In the first step, a current of reverse polarity is applied to the primary side during cooldown before the secondary loop reaches its superconducting critical temperature. During such a scenario, the secondary loop reaches its lowest energy state where the stored flux is ideally zero, but its magnitude does not exceed half of the SFQs. In the second step of the flux initialization process 520, once the secondary loop reaches its superconducting critical temperature, the control current is turned off, allowing a precise integer number N of SFQs to be established in the loop, with the number of SFQs determined by the initial current on the primary side according to the following equation:

[0046]

number

[0047] Alternatively, the memory device 100 may include at least one magnetically coupled control line. In such a scenario, the plurality of superconducting loops 102 are configured to provide an initial flux state in response to a two-step flux initialization process. The two-step flux initialization process includes: 1) providing an initialization signal via the at least one magnetically coupled control line while cooling the Josephson junction-based memory device; and 2) turning off the initialization signal upon reaching the superconducting critical temperature of the Josephson junction-based memory device, such that the precise integer number of SFQs is stored in the one or more superconducting loops.

[0048] 5C illustrates a scenario 530 in which multiple unit cells (e.g., respective unit cells associated with inductor 532 and inductor 534) share the same magnetic flux source (e.g., magnetic flux source 536), according to an example embodiment. In some embodiments, the mutual inductance L′ shared by the loops is much smaller than the total inductance L of each loop. In such a scenario, the low L′ inductance approximates a low impedance source, thereby achieving good isolation.

[0049] FIG. 6 illustrates an array of unit cells arranged in a word-organized memory fabric 600, according to an exemplary embodiment. Because the address lines use Josephson transmission lines (JTL), the memory fabric is wave-pipelined, allowing multiple operations to occur at once. While reading and writing to the same word in the same clock cycle is not permitted, simultaneous reading and writing to different words is permitted. Unit cells may be aligned as shown in FIG. 6 to create a word-organized memory fabric. The address lines use JTL, which fan out signals to all cells in a vine-like configuration.

[0050] Stated another way, a series arrangement (e.g., Josephson junction-based memory device 100) can be thought of as a unit cell. An array of coupled unit cells can form a memory fabric that can be wave-pipelined. In such a scenario, multiple operations can be executed simultaneously across the memory fabric. In various embodiments, the unit cells of memory fabric 600 are coupled to a global resonant clock network (e.g., global resonant clock network 170).

[0051] 7 shows a wave-pipelined arrangement 700 of an array of unit cells, according to an example embodiment. Wave-pipelining through the array means that the phase of the AC bias source advances with the signal delay. In this way, multiple operations may proceed simultaneously to achieve throughput at the logic's native clock frequency.

[0052] Advancing the phase of the AC bias enables wave pipelining of the array. Figure 7 assumes that a local group of unit cells requires four of the eight clock phases (e.g., 0, 2, 4, 6) and that these phases advance from the upper left to the lower right. This is consistent with signal propagation along a Manhattan geometric path from the upper left to the lower right.

[0053] 8 illustrates a partitioned subarray arrangement 800, according to an example embodiment. In some embodiments, partitioning the array of unit cells into smaller active subarrays interconnected by passive transmission lines (black lines with arrows) can improve delay and power dissipation by confining the high activity coefficient of junctions to the subarray during read or write operations.

[0054] As described elsewhere herein, this design generalizes to multiple read ports and multiple write ports. This approach can be extended to incorporate any number of read and write ports into a single design. Figure 9A shows a split unit cell 900 with separate write and read paths, according to an example embodiment.

[0055] 9B illustrates a split unit cell 920 with a replicated read path, according to an example embodiment. In such a scenario, the read path is replicated to create two read ports. Specifically, the stored SFQ associated with the write path can be transmitted to the read path via a Josephson junction transmission line splitter network, which provides isolation and gain.

[0056] FIG. 9C shows a partitioned unit cell 930 with a replicated write path, according to an example embodiment. The write path is replicated using a one-hot multiplexer (MUX) that generates a signal BW having the logic function shown. The MUX can be constructed by placing two AND gates followed by an OR gate. Alternatively, the MUX can be constructed by placing two A-AND-NOT-B gates followed by an OR gate, with the inverted BW data input to the inverted AND input. In such a scenario, the array is also provided with a signal WW having the OR logic function shown.

[0057] Alternative Josephson Junction-Based Memory Device Embodiments FIG. 10 shows a schematic diagram of an alternative Josephson junction-based memory device 1000 according to an exemplary embodiment. In such a scenario, the series arrangement may include four superconducting loops, all of which are input loops. The alternative memory device 1000 may include a readout stage 1002. The readout stage 1002 may be coupled to a Josephson junction 1004 shared by two input loops. In such an example, the readout stage 1002 is configured to detect whether an SFQ is stored in a particular one of the input loops. In the alternative memory device 1000, the readout stage is connected to the right-most junction of the input loops and detects whether a stored pulse is in the right-most loop during a read operation. One potential advantage of the alternative memory device 1000 design is that it supports a single-cycle read, as shown and described in FIGS. 11A and 11B.

[0058] 11A shows a read pass sequence 1100 for reading a 1 state utilizing the alternative Josephson junction-based memory device 1000 of FIG. 10, according to an exemplary embodiment. The S input produces a Q output unless the stored pulse is in the rightmost loop. In contrast to the design of memory device 100, a pair of WR events and a pair of S events can all be completed within one clock cycle.

[0059] FIG. 11B illustrates a read pass sequence 1120 for reading the 0 state utilizing the alternative Josephson junction-based memory device 1000 of FIG. 10, according to an example embodiment.

[0060] 12A, 12B, and 12C show three functionally equivalent read paths compatible with the second design (e.g., alternative memory device 1000). Although three alternative read path variations are described, it will be understood that other alternatives are possible and contemplated.

[0061] 12A illustrates a first variation 1200 of a read path utilizing the alternative Josephson junction-based memory device 1000 of FIG. 10, according to an exemplary embodiment. The relative inductances of the different loops are shown. Second-order effects such as JJ inductance and leakage between loops are ignored, and approximate inductor values ​​are shown for illustrative purposes.

[0062] 12B illustrates a second variation 1220 of a read path utilizing the alternative Josephson junction-based memory device 1000 of FIG. 10, according to an exemplary embodiment. The relative inductances of the different loops are shown. Second-order effects such as JJ inductance and leakage between loops are ignored, and approximate inductor values ​​are shown for illustrative purposes.

[0063] FIG. 12C illustrates a third read path variation 1230 utilizing the alternative Josephson junction-based memory device 1000 of FIG. 10, according to an exemplary embodiment. The relative inductances of the different loops are shown. Second-order effects such as JJ inductance and leakage between loops are ignored, and approximate inductor values ​​are shown for illustrative purposes. FIGS. 13A, 13B, 14A, 14B, 15A, and 15B illustrate the read path sequence for the first, second, and third read path variations.

[0064] 13A illustrates a read path sequence 1300 for reading a 1 state utilizing the first read path variation 1200 of the alternative Josephson junction-based memory device 1000 of FIG. 12A, according to an example embodiment. In such a scenario, when reading a 1, the leftmost “2L” loop prevents the +WR signal from transitioning the output SFQ to the input loop.

[0065] 13B illustrates a read path sequence 1320 for reading a 0 state utilizing the first read path variation 1200 of the alternative Josephson junction-based memory device 1000 of FIG. 12A, according to an example embodiment. In such an embodiment, when reading a 0, a −WR signal moves the SFQ from the input stage to two 2L loops.

[0066] FIG. 14A illustrates a read pass sequence 1400 for reading a one state utilizing the second read pass variation 1220 of the alternative Josephson junction-based memory device 1000 of FIG. 12B, according to an example embodiment.

[0067] 14B illustrates a read path sequence 1420 for reading a 0 state utilizing the second read path variation 1220 of the alternative Josephson junction-based memory device 1000 of FIG. 12B, according to an example embodiment. In such a scenario, when reading a 0, the −WR signal integrates both SFQs into a “2 / 3L” loop.

[0068] FIG. 15A illustrates a read pass sequence 1500 for reading a one state utilizing the third read pass variation 1230 of the alternative Josephson junction-based memory device 1000 of FIG. 12C, according to an example embodiment.

[0069] 15B illustrates a read path sequence 1520 for reading a 0 state utilizing a third read path variation 1230 of the alternative Josephson junction-based memory device 1000 of FIG. 12C, according to an example embodiment. In such a scenario, when reading a 0, the −WR signal reverses the polarity of the half SFQ in the loop connected to the input stage.

[0070] FIG. 16 shows a circuit diagram 1600 of a first variation 1200 of the read path of the alternative Josephson junction-based memory device 1000 of FIG. 12A, according to an example embodiment.

[0071] FIG. 17 shows a circuit diagram 1700 of a second variation 1220 of the read path of the alternative Josephson junction-based memory device 1000 of FIG. 12B, according to an example embodiment.

[0072] 18 shows a circuit diagram 1800 of a third variation 1230 of the read path of the alternative Josephson junction-based memory device 1000 of FIG. 12C , according to an example embodiment. The ½ SFQ inductor loop of inductance L is implemented as two inductors in parallel, each with an inductance 2L, with full SFQ applied to one of the two inductors.

[0073] Example of the method 19 illustrates a method 1900 according to an example embodiment. The method 1900 includes a process for storing digital information in a Josephson junction-based memory device (e.g., memory device 100 or memory device 1000 as shown and described in connection with FIGS. 1 and 10).

[0074] The method 1900 includes providing a combination of a control signal and a single flux quantum (SFQ) pulse to a plurality of superconducting loops (e.g., superconducting loop 102). Each superconducting loop includes at least one Josephson junction (e.g., Josephson junctions 104a, 104b, 104c, and 104d). The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops includes a plurality of input loops (e.g., input loop 110), a plurality of readout loops (e.g., readout loop 120), and at least one shared loop (e.g., shared loop 130).

[0075] The method 1900 includes storing or annihilating magnetic flux quanta (eg, SFQs 140a and / or 140b) in one or more superconducting loops in response to a combination of a control signal and an SFQ pulse.

[0076] The method 1900 may further include shifting a magnetic flux quantum from the initial superconducting loop to an adjacent loop in response to the SFQ pulse being applied to the initial superconducting loop of the plurality of superconducting loops.

[0077] In some exemplary embodiments, a Josephson junction-based memory device may include multiple address lines coupled to multiple superconducting loops. In such a scenario, each address line of the multiple address lines may include a Josephson transmission line and a current bias source. The current bias source provides an AC signal corresponding to a global resonant clock network (e.g., global resonant clock network 170).

[0078] In various examples, the control signals may include write control signals, where the plurality of address lines are configured to provide the write control signals to at least some of the plurality of superconducting loops, and the write control signals include a word write (WW) and a bit write (BW).

[0079] In such an example, the control signals may additionally include read control signals. In such a scenario, the plurality of address lines are configured to provide read control signals to at least some of the plurality of superconducting loops. The read control signals include a word read (WR), a strobe (S), and an output.

[0080] In an example embodiment, the method 1900 may include providing an initialization signal through at least one magnetically coupled control line while cooling the Josephson junction-based memory device.

[0081] In such a scenario, the method 1900 may additionally include turning off the initialization signal when the superconducting critical temperature of the Josephson junction-based memory device is reached, such that the exact integer number of SFQs is stored in the multiple superconducting loops.

[0082] Enumerated exemplary embodiments Accordingly, embodiments of the present disclosure may relate to one of the Enumerated Exemplary Embodiments (EEEs) listed below.

[0083] EEE1 is a Josephson junction-based memory device, a plurality of superconducting loops, each superconducting loop including at least one Josephson junction, the plurality of superconducting loops being electrically coupled; Multiple superconducting loops are Multiple input loops; a plurality of read loops; At least one shared loop and Equipped with The plurality of superconducting loops includes a Josephson junction-based memory device configured to store or annihilate a flux quantum in one or more of the superconducting loops in response to a combination of a control signal and a single flux quantum (SFQ) pulse.

[0084] EEE2 includes the Josephson junction-based memory device of EEE1, wherein a plurality of superconducting loops are electrically coupled in a series arrangement, and each superconducting loop of the plurality of superconducting loops has one or two adjacent loops.

[0085] EEE3 includes the Josephson junction-based memory device of EEE2, wherein the plurality of superconducting loops are configured to shift magnetic flux quanta from an initial superconducting loop to adjacent loops in response to an SFQ pulse applied to the initial superconducting loop.

[0086] EEE4 includes the Josephson junction-based memory device of EEE3, wherein a magnetic flux quantum is shifted from an initial superconducting loop to an adjacent loop in a first direction along the series arrangement in response to a positive SFQ pulse polarity, and a magnetic flux quantum is shifted from an initial superconducting loop to an adjacent loop in a second direction along the series arrangement in response to a negative SFQ pulse polarity.

[0087] The EEE5 includes the Josephson junction-based memory device of the EEE2, with five superconducting loops, of which four are input loops, two are readout loops, and one is a shared loop.

[0088] EEE6 includes the Josephson junction-based memory device of EEE2 and further includes a readout stage, the serial arrangement including four superconducting loops, all four superconducting loops being input loops, the readout stage being coupled to the Josephson junction of one of the input loops, and the readout stage being configured to detect whether an SFQ is stored in a particular one of the input loops.

[0089] EEE7 includes the Josephson junction-based memory device of EEE2, wherein the series arrangement comprises unit cells, and the Josephson junction-based memory device comprises an array of unit cells forming a memory fabric, wherein the memory fabric is wave-pipelined such that multiple operations can be performed simultaneously across the memory fabric.

[0090] EEE8 includes the Josephson junction-based memory devices of EEE7, with the unit cells of the memory fabric coupled to a global resonant clock network.

[0091] EEE9 includes the Josephson junction-based memory device of EEE1, further comprising a plurality of address lines coupled to the plurality of superconducting loops; Each address line of the plurality of address lines is Josephson transmission line, Current bias source and Equipped with A current bias source provides a corresponding AC signal to the global resonant clock network.

[0092] EEE10 includes the Josephson junction-based memory device of EEE9, wherein each address line of the plurality of address lines further comprises a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops.

[0093] EEE11 includes EEE9 Josephson junction-based memory devices, the control signal comprises a write control signal; the plurality of address lines are configured to provide write control signals to at least a portion of the plurality of superconducting loops; The write control signal is Word writing and Bit write and Equipped with.

[0094] EEE12 includes the Josephson junction-based memory device of EEE9, wherein the plurality of superconducting loops are further configured to provide information indicative of the presence of a magnetic flux quantum in one or more of the superconducting loops in response to a combination of a control signal and an SFQ pulse.

[0095] EEE13 includes the Josephson junction-based memory device of EEE9, wherein the control signal comprises a read control signal, and the plurality of address lines are configured to provide the read control signal to at least a portion of the plurality of superconducting loops; The read control signal is Word reading and Strobe and Output and Equipped with.

[0096] EEE14 includes the Josephson junction-based memory device of EEE1 and further comprises at least one magnetically coupled control line; the plurality of superconducting loops are further configured to provide an initial flux state in response to a two-step flux initialization process; The two-step flux initialization process is providing an initialization signal via at least one magnetically coupled control line while cooling the Josephson junction-based memory device; When the superconducting critical temperature of the Josephson junction-based memory device is reached, the initialization signal is turned off so that an exact integer number of SFQs is stored in the multiple superconducting loops. Be prepared.

[0097] EEE15 is a method for storing digital information in a Josephson junction-based memory device, comprising: providing a combination of control signals and single flux quantum (SFQ) pulses to a plurality of superconducting loops, each superconducting loop comprising at least one Josephson junction, the plurality of superconducting loops being electrically coupled, the plurality of superconducting loops comprising a plurality of input loops, a plurality of readout loops, and at least one shared loop; Store or annihilate magnetic flux quanta in one or more superconducting loops in response to a combination of control signals and SFQ pulses The present invention includes a method comprising:

[0098] EEE16 includes the method of EEE15, further comprising shifting a magnetic flux quantum from an initial superconducting loop to an adjacent loop in response to an SFQ pulse being applied to an initial superconducting loop of the plurality of superconducting loops.

[0099] EEE17 includes the method of EEE15, wherein the Josephson junction-based memory device comprises a plurality of address lines coupled to a plurality of superconducting loops; Each address line of the plurality of address lines is Josephson transmission line, Current bias source and Equipped with A current bias source provides a corresponding AC signal to the global resonant clock network.

[0100] EEE18 includes the method of EEE17, wherein the control signal comprises a write control signal, and the plurality of address lines are configured to provide the write control signal to at least a portion of the plurality of superconducting loops; The write control signal is Word writing and Bit write and Equipped with.

[0101] EEE19 includes the method of EEE17, wherein the control signal comprises a read control signal, and the plurality of address lines are configured to provide the read control signal to at least a portion of the plurality of superconducting loops; The read control signal is Word Lead and Strobe and Output and Equipped with.

[0102] EEE20 includes the method of EEE15, providing an initialization signal via at least one magnetically coupled control line while cooling the Josephson junction-based memory device; When the superconducting critical temperature of the Josephson junction-based memory device is reached, the initialization signal is turned off so that an exact integer number of SFQs is stored in the multiple superconducting loops. It further comprises:

[0103] While several embodiments have been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustration and description should be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Reference signs in the claims should not be interpreted as limiting the scope.

Claims

1. 1. A Josephson junction-based memory device, comprising: a plurality of superconducting loops, each superconducting loop including at least one Josephson junction, the plurality of superconducting loops being electrically coupled; The plurality of superconducting loops Multiple input loops; a plurality of read loops; At least one shared loop; Equipped with 1. A Josephson junction-based memory device, wherein the plurality of superconducting loops are configured to store or annihilate a magnetic flux quantum in one or more of the superconducting loops in response to a combination of a control signal and a single flux quantum (SFQ) pulse.

2. 10. The Josephson junction-based memory device of claim 1, wherein the plurality of superconducting loops are electrically coupled in a series arrangement, and each superconducting loop of the plurality of superconducting loops has one or two adjacent loops.

3. 3. The Josephson junction-based memory device of claim 2, wherein the plurality of superconducting loops are configured to shift a magnetic flux quantum from the initial superconducting loop to an adjacent loop in response to an SFQ pulse applied to the initial superconducting loop.

4. 4. The Josephson junction-based memory device of claim 3, wherein the magnetic flux quantum is shifted from an initial superconducting loop to an adjacent loop in a first direction along the series arrangement in response to a positive SFQ pulse polarity, and the magnetic flux quantum is shifted from an initial superconducting loop to an adjacent loop in a second direction along the series arrangement in response to a negative SFQ pulse polarity.

5. 3. The Josephson junction-based memory device of claim 2, wherein the series arrangement comprises five superconducting loops, of which four are input loops, two are readout loops, and one is a shared loop.

6. further comprising a readout stage; the series arrangement comprises four superconducting loops, all four superconducting loops being input loops; the readout stage is coupled to a Josephson junction in one of the input loops; The Josephson junction-based memory device of claim 2 , wherein the read stage is configured to detect whether a SFQ is stored in a particular one of the input loops.

7. the series arrangement comprises a unit cell; the Josephson junction-based memory device comprises an array of unit cells forming a memory fabric; 3. The Josephson junction-based memory device of claim 2, wherein the memory fabric is wave-pipelined, allowing multiple operations to be performed simultaneously across the memory fabric.

8. The Josephson junction-based memory device of claim 7 , wherein the unit cells of the memory fabric are coupled to a global resonant clock network.

9. further comprising a plurality of address lines coupled to the plurality of superconducting loops; Each address line of the plurality of address lines comprises: Josephson transmission line, Current bias source and Equipped with The Josephson junction-based memory device of claim 1 , wherein the current bias source provides an AC signal corresponding to a global resonant clock network.

10. 10. The Josephson junction-based memory device of claim 9, wherein each address line of the plurality of address lines further comprises a resistor connected between the Josephson transmission line and a corresponding superconducting loop of the plurality of superconducting loops.

11. the control signal comprises a write control signal; the plurality of address lines are configured to provide the write control signals to at least some of the plurality of superconducting loops; The write control signal is Word writing and Bit write and 10. The Josephson junction-based memory device of claim 9, comprising:

12. 10. The Josephson junction-based memory device of claim 9, wherein the plurality of superconducting loops are further configured to provide information indicative of a presence of a magnetic flux quantum in one or more of the superconducting loops in response to a combination of a control signal and an SFQ pulse.

13. the control signal comprises a read control signal; the plurality of address lines are configured to provide the read control signals to at least some of the plurality of superconducting loops; The read control signal is Word reading and Strobe and Output and 10. The Josephson junction-based memory device of claim 9, comprising:

14. further comprising at least one magnetically coupled control line; the plurality of superconducting loops are further configured to provide an initial flux state in response to a two-step flux initialization process; The two-step flux initialization process comprises: providing an initialization signal via the at least one magnetically coupled control line while cooling the Josephson junction-based memory device; When a superconducting critical temperature of the Josephson junction-based memory device is reached, the initialization signal is turned off so that an exact integer number of SFQs is stored in the plurality of superconducting loops. The Josephson junction-based memory device of claim 1 , comprising:

15. 1. A method for storing digital information in a Josephson junction-based memory device, comprising: providing a combination of control signals and single flux quantum (SFQ) pulses to a plurality of superconducting loops, each superconducting loop comprising at least one Josephson junction, the plurality of superconducting loops being electrically coupled, the plurality of superconducting loops comprising a plurality of input loops, a plurality of readout loops, and at least one shared loop; storing or annihilating magnetic flux quanta in one or more superconducting loops in response to a combination of control signals and SFQ pulses; A method comprising:

16. 16. The method of claim 15, further comprising shifting a magnetic flux quantum from an initial superconducting loop to an adjacent loop in response to an SFQ pulse being applied to the initial superconducting loop of the plurality of superconducting loops.

17. the Josephson junction-based memory device comprises a plurality of address lines coupled to the plurality of superconducting loops; Each address line of the plurality of address lines comprises: Josephson transmission line, Current bias source and Equipped with 16. The method of claim 15, wherein the current bias source provides an AC signal corresponding to a global resonant clock network.

18. the control signal comprises a write control signal; the plurality of address lines are configured to provide the write control signals to at least some of the plurality of superconducting loops; The write control signal is Word writing and Bit write and 20. The method of claim 17, comprising:

19. the control signal comprises a read control signal; the plurality of address lines are configured to provide the read control signals to at least some of the plurality of superconducting loops; The read control signal is Word Lead and Strobe and Output and 20. The method of claim 17, comprising:

20. providing an initialization signal via at least one magnetically coupled control line while cooling the Josephson junction-based memory device; When a superconducting critical temperature of the Josephson junction-based memory device is reached, the initialization signal is turned off so that an exact integer number of SFQs is stored in the plurality of superconducting loops. The method of claim 15 further comprising:

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