Multiple precision addition and / or subtraction with carry propagation

Abstract

The processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X-bit binary portion values ​​of a first Y-bit binary value and a second Y-bit binary value, where Y is a multiple of X. The plurality of adders further generate a first carry bit. The plurality of carry bit generation circuits are respectively coupled to the plurality of adders and receive the first carry bits. The plurality of carry bit generation circuits generate a second carry bit based on the first carry bit. The plurality of adders add the first and second X-bit binary portions of the first and second Y-bit binary values ​​using the second carry bit.

Description

[Background technology]

[0001] Arbitrary-precision arithmetic (referred to herein as multi-precision arithmetic) is an important computational primitive in cryptographic applications such as Rivest-Shamir-Adleman (RSA). A significant portion of these workloads are multi-precision addition and subtraction on large integers (e.g., 4096 bits). Besides addition, multi-precision addition operations are also primitives used in other multi-precision operations, such as multiplication. Accordingly, recent competing instruction set architectures (ISAs) have defined extensions to accelerate such operations and workloads (e.g., ARM's SVE2, RISC-V's RVV).

[0002] ARM SVE2 provides a solution for multi-precision arithmetic, and ARM has vector add top / bottom with carry instructions. While these instructions may work in some cases, they do not effectively handle cases where carry propagation needs to run the full width of the data path (or more than one vector lane) (e.g., across all 512 bits) due to the lack of vector carry propagation. These instructions require additional software support to chain them together to handle such cases. Furthermore, half of the vector lanes remain unused, resulting in underutilization of the data path and therefore unrealized performance potential. RISC-V RVV also provides a solution for multi-precision arithmetic. Like the ARM SVE2 solution, RISC-RVV has a vector add with carry instruction that requires special handling of the long carry case. AVX-512F also provides a solution for multi-precision arithmetic. AVX-512F instructions are used to perform vector multi-precision addition and subtraction while handling full-width vector carry propagation. AVX-512F uses an iterative process, which means that the final carry bit used to calculate the exact sum must be calculated piece by piece based on the result of the previous step.

[0003] Current multi-precision workloads typically use libraries such as the GNU Multi-Precision (GMP) library that are based on scalar instructions, which limits their performance. Traditional approaches / circuits are impractical due to the large latency and area required to support carry propagation across a 512-bit datapath. Another problem is that to support larger integers (e.g., 1024-bit, 4096-bit), two register outputs must be supported per operation (i.e., one for the sum and one for the carry-out to feed the next most significant 512-bit calculation), but existing datapaths and ISAs only support a single destination / output per instruction. Summary of the Invention [Means for solving the problem]

[0004] Examples described herein address inefficiencies associated with the use of scalar instructions and existing support for a single destination / output per instruction, for example, providing wide addition over a Single Instruction Multiple Data (SIMD) datapath, and provide techniques for efficiently and succinctly processing carry information. In one exemplary embodiment, the processing unit includes a plurality of adders for adding first and second X-bit binary portion values ​​of a first Y-bit binary value and a second Y-bit binary value to generate a first carry bit, where Y is a multiple of X. The processing unit further includes a plurality of carry bit generation circuits respectively coupled to the plurality of adders for receiving the first carry bit and generating a second carry bit based on the first carry bit, the second carry bit being used to add the first and second X-bit binary portions of the first and second Y-bit binary values, respectively.

[0005] In some embodiments, the plurality of carry bit generation circuits are configured to receive the sum of the first and second X-bit binary portions of the first Y-bit binary value and the second Y-bit binary value, respectively, and to generate a second carry bit based on the sum of the first and second X-bit binary portions of the first and second Y-bit binary values.

[0006] In some embodiments, the first and second Y-bit binary values ​​are stored by at least one of a vector register, a memory operand, a Double Data Rate (DDR) memory, a Low-Power DDR (LPDDR), and Gen-Z. In some embodiments, a new Instruction Set Architecture (ISA) instruction is added to an existing ISA instruction set to add the first and second X-bit binary portions of the first and second Y-bit binary values.

[0007] In some embodiments, the plurality of carry bit generation circuits each include a plurality of AND logic gates, a plurality of 1-bit full adders, and a plurality of XOR logic gates. The plurality of AND logic gates are configured to receive sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the plurality of adders, respectively, and output binary values ​​to the plurality of 1-bit full adders and the plurality of XOR logic gates, respectively. The plurality of 1-bit full adders are configured to receive the binary values ​​output from the plurality of AND logic gates, first carry bits from the plurality of adders, and binary values ​​from adjacent 1-bit full adders, and output binary values. The plurality of XOR logic gates are configured to receive the binary values ​​output by the plurality of AND logic gates and the binary values ​​output by the plurality of 1-bit full adders, and output a second carry bit to the vector register.

[0008] In some embodiments, the plurality of carry bit generation circuits comprise a plurality of AND logic gates and a plurality of 1-bit Vector Carry Propagation (VCP) logic circuits. The plurality of AND logic gates are configured to receive sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the plurality of adders and output binary values ​​to the plurality of 1-bit Vector Carry Propagation (VCP) logic circuits, respectively. The plurality of 1-bit VCP logic circuits are configured to receive the binary values ​​from the plurality of AND logic gates, first carry bits from the plurality of adders, and binary values ​​output by adjacent ones of the plurality of 1-bit VCP logic circuits, output other binary values ​​to other adjacent ones of the plurality of 1-bit VCP logic circuits, and output the second carry bit to the vector register.

[0009] In some embodiments, the plurality of AND logic gates are a plurality of first AND logic gates, and the 1-bit VCP logic circuit comprises a plurality of respective OR logic gates and a plurality of respective second AND logic gates. The plurality of OR logic gates are configured to receive the binary values ​​output from the plurality of first AND logic gates and the first carry bits from the plurality of adders, respectively. The plurality of second AND logic gates are configured to receive the first carry bits from the plurality of adders and the binary values ​​output by the plurality of OR logic gates, respectively, and to output a second carry bit to the vector register.

[0010] In some embodiments, the vector register is a first vector register, and the processing unit further includes a plurality of bitwise invert / not logic gates, each coupled to the second vector register and configured to receive the second X-bit binary portion, bitwise invert the second X-bit binary portion of the second Y-bit binary value, and output the bitwise inverted X-bit binary portion of the second X-bit binary portion to the plurality of carry bit generation circuits.

[0011] In some embodiments, the plurality of carry bit generation circuits further comprise a plurality of multiplexers coupled to the second vector register configured to receive the bitwise inverted X-bit binary portion of the second Y-bit binary value from the plurality of bitwise invert / not logic gates, to receive the second X-bit binary portion, to receive binary values ​​from adjacent multiplexers, and to output binary values ​​to other adjacent multiplexers, respectively.

[0012] In another embodiment, a system includes a processing unit according to claim 1, the system including another processing unit, the another processing unit including a plurality of adders and a plurality of carry bit generation circuits.

[0013] In some embodiments, the processing unit further includes a vector register for storing an addition of the first and second X-bit binary portions of the first and second Y-bit binary values, respectively. In some embodiments, the plurality of adders are a first plurality of adders, and the processing unit includes a second plurality of adders for adding the first and second Y-bit binary values ​​from the first and second vector registers, respectively. In some embodiments, the plurality of adders add the first and second Y-bit binary values ​​from the first and second vector registers, respectively.

[0014] In another embodiment, the method includes adding, by a plurality of adders, first and second X-bit binary portion values ​​of the first and second Y-bit binary values ​​to generate a first carry bit, where Y is a multiple of X. The method further includes generating, by a plurality of carry bit generation circuits, a second carry bit based on the first carry bit, and adding, by the second carry bit, the first and second X-bit binary portions of the first and second Y-bit binary values, respectively.

[0015] In some embodiments, the method further includes receiving, by a plurality of carry bit generation circuits, an addition of the first and second X-bit binary portions of the first Y-bit binary value and the second Y-bit binary value, respectively; and generating, by the plurality of carry bit generation circuits, a second carry bit based on the addition of the first and second X-bit binary portions of the first and second Y-bit binary values.

[0016] In some embodiments, the method further includes storing the first and second Y-bit binary values ​​via at least one of a vector register, a memory operand, a double data rate (DDR) memory, a low power DDR (LPDDR), and Gen-Z.

[0017] In some embodiments, each of the carry bit generation circuits comprises a plurality of AND logic gates, a plurality of 1-bit full adders, and a plurality of XOR logic gates, and the method further includes receiving, by the plurality of AND logic gates, sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the plurality of adders, respectively; outputting, by the plurality of AND logic gates, binary values ​​to the plurality of 1-bit full adders and the plurality of XOR logic gates, respectively; receiving, by the plurality of 1-bit full adders, the binary values ​​output from the plurality of AND logic gates, the first carry bit from the plurality of adders, and binary values ​​from adjacent 1-bit full adders, respectively; outputting, by the plurality of 1-bit full adders, binary values ​​output by the plurality of 1-bit full adders, respectively; receiving, by the plurality of XOR logic gates, the binary values ​​output by the plurality of AND logic gates and the binary values ​​output by the plurality of 1-bit full adders, respectively; and outputting, by the plurality of XOR logic gates, a second carry bit to the vector register.

[0018] In some embodiments, each of the carry bit generation circuits comprises a plurality of AND logic gates and a plurality of 1-bit vector carry propagate (VCP) logic circuits, and the method further includes receiving, by the plurality of AND logic gates, the sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the plurality of adders, respectively; outputting, by the plurality of AND logic gates, the binary values ​​to the plurality of 1-bit vector carry propagate (VCP) logic circuits, respectively; receiving, by the plurality of 1-bit VCP logic circuits, the binary values ​​from the plurality of AND logic gates, the first carry bit from the plurality of adders, and the binary values ​​output by adjacent ones of the plurality of 1-bit VCP logic circuits, respectively; and outputting, by the plurality of 1-bit VCP logic circuits, other binary values ​​to other adjacent ones of the plurality of 1-bit VCP logic circuits and outputting the second carry bit to the vector register.

[0019] In some embodiments, the method further includes storing, by a vector register, the sum of the first and second X-bit binary portions of the first and second Y-bit binary values, respectively.

[0020] In another embodiment, the processing unit includes a first vector register for storing a first Y-bit binary value including a plurality of first X-bit binary portions when Y is a multiple of X. The processing unit further includes a second vector register for storing a second Y-bit binary value including a plurality of second X-bit binary portions. The processing unit also includes a plurality of adders for adding the first and second X-bit binary portion values ​​of the first Y-bit binary value and the second Y-bit binary value to generate a first carry bit, and a plurality of carry bit generation circuits respectively coupled to the plurality of adders for receiving the first carry bit and generating a second carry bit based on the first carry bit. The plurality of adders add the first and second X-bit binary portions of the first and second Y-bit binary values, respectively, using the second carry bit.

[0021] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief explanation of the drawings]

[0022] [Figure 1A] FIG. 1 illustrates an exemplary processing unit for generating / propagating carry bits for integer multi-precision addition (e.g., 512b) using one full adder (FA) and an XOR gate per vector lane, according to some embodiments. [Figure 1B] FIG. 1 illustrates an exemplary processing unit for generating / propagating carry bits for integer multi-precision addition (e.g., 512b) using one full adder (FA) and an XOR gate per vector lane, according to some embodiments. [Figure 2A] FIG. 10 illustrates another exemplary processing unit for generating / propagating carry bits for integer multiple-precision addition (e.g., 512b) using vector carry propagation (VCP) circuitry per vector lane, in accordance with some embodiments. [Figure 2B] FIG. 10 illustrates another exemplary processing unit for generating / propagating carry bits for integer multiple-precision addition (e.g., 512b) using vector carry propagation (VCP) circuitry per vector lane, in accordance with some embodiments. [Figure 3] FIG. 1C illustrates an exemplary configuration of the 1-bit VCP logic circuit shown in FIGS. 1A and 1B, according to some embodiments. [Figure 4] FIG. 2A illustrates exemplary hardware components of the processing units of FIGS. 1A-1B and 2A-2B configured to perform multi-precision 512b addition, according to some embodiments. [Figure 5A] FIG. 1 illustrates an exemplary processing unit capable of simultaneously performing carry generate / propagate for 2×256b multi-precision addition, in accordance with some embodiments. [Figure 5B] FIG. 1 illustrates an exemplary processing unit capable of simultaneously performing carry generate / propagate for 2×256b multi-precision addition, in accordance with some embodiments. [Figure 6A] FIG. 1 illustrates an exemplary processing unit for generating / propagating a carry bit for integer multiple-precision subtraction (e.g., 512b) according to some embodiments. [Figure 6B] FIG. 1 illustrates an exemplary processing unit for generating / propagating a carry bit for integer multiple-precision subtraction (e.g., 512b) according to some embodiments. [Figure 7A] FIG. 10 illustrates an exemplary processing unit for generating / propagating a carry bit for chaining multiple 512b subtraction operations, according to some embodiments. [Figure 7B]FIG. 10 illustrates an exemplary processing unit for generating / propagating a carry bit for chaining multiple 512b subtraction operations, according to some embodiments. [Figure 8A] FIG. 1 illustrates an exemplary processing unit for generating / propagating carry bits for both multiple-precision addition and subtraction, according to some embodiments. [Figure 8B] FIG. 1 illustrates an exemplary processing unit for generating / propagating carry bits for both multiple-precision addition and subtraction, according to some embodiments. [Figure 9A] FIG. 1 illustrates an exemplary processing unit capable of performing carry generate / propagate for 2×256b multiple precision addition and subtraction, according to some embodiments. [Figure 9B] FIG. 1 illustrates an exemplary processing unit capable of performing carry generate / propagate for 2×256b multiple precision addition and subtraction, according to some embodiments. [Figure 10A] FIG. 8C illustrates the processing unit shown in FIGS. 8A and 8B configured to perform multi-precision 512b addition / subtraction, according to some embodiments. [Figure 10B] FIG. 8C illustrates the processing unit shown in FIGS. 8A and 8B configured to perform multi-precision 512b addition / subtraction, according to some embodiments. [Figure 11A] FIG. 2C illustrates yet another configuration of an exemplary processing unit based on the processing unit configurations shown in FIGS. 2A and 2B for adding two multi-precision binary values ​​without first having to store the carry bit in a vector register, according to some embodiments. [Figure 11B] FIG. 2C illustrates yet another configuration of an exemplary processing unit based on the processing unit configurations shown in FIGS. 2A and 2B for adding two multi-precision binary values ​​without first having to store the carry bit in a vector register, according to some embodiments. [Figure 12] FIG. 10 illustrates an exemplary critical path for chained 512b addition, according to some embodiments. [Figure 13] FIG. 1 illustrates an exemplary method for generating a carry bit and adding first and second binary values ​​according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0023] 1-13 illustrate techniques for addressing inefficiencies associated with the use of scalar instructions and existing support for a single destination / output per instruction, for example, providing wide addition on a single instruction, multiple data (SIMD) datapath, and efficiently and concisely handling carry information. Most datapath components in modern CPUs have AVX-512 support (and other vector ISAs). While vector ISAs (by definition) do not support AVX-512, they do test against MAX_WORD, a calculation used in some multi-precision addition algorithms. MAX_WORD is a binary number containing all ones. The size of this number is defined by the data type (in this example, it is 64 bits). In some embodiments, the processing unit extends this existing datapath with a 1-bit full adder (FA) and XOR gate per vector lane, as well as an OR gate. The amount of this additional logic is small compared to the overall size of the floating-point (FP) SIMD datapath / execution unit. The latency impact of this expansion is also small, since the routing of the carry-in most significant bit (MSB) in the first vector register may overlap with the latency of the vector 64-bit adder, and the test of each adder sum against the MAX_WORD value is a 64-bit AND (or alternatively, three levels of 4-input AND gates). The 1-bit FA is combined in a ripple carry fashion, although alternative implementations are possible to optimize area / performance costs.

[0024] The processing unit also introduces a pair of new instructions that accelerate such workloads. The processing unit provides single-instruction dependency chaining for chaining multiple operations together for larger bit widths (e.g., 2048 bits or greater) and implements modest modifications to existing data paths, such as the existing AVX512 FP data path. The processing unit accelerates 512b multi-precision addition even over existing AVX-512F-based solutions. In some embodiments, the processing unit provides approximately a 5x speedup over scalar 512b addition implementations when adding 100,000 multi-precision values ​​residing in registers. These operations can be performed using the processing unit with fewer instructions while avoiding the use of scalar registers, which incur a performance penalty due to moving data between vector and scalar registers.

[0025] The processing unit performs multiple-precision addition and subtraction (add / sub) in hardware using AVX-512 registers, but in some embodiments, the processing unit uses the same approach to generate / propagate carry bits / borrows and then uses those carry bits / borrows to calculate correct multiple-precision sums / subtractions for other vector ISAs, such as ARM SVE / SVE2, ARM NEON, and RISC-V RVV. In some embodiments, the processing unit implements a 512-bit data path, but in other embodiments, the processing unit implements a narrower data path (e.g., 256b) or a wider data path (e.g., 1024b). For integer multiple-precision addition / subtraction, the processing unit utilizes hardware to 1) generate and propagate vector carry / borrows and 2) use the propagated carry bits / borrows to complete the final operation.

[0026] Also, because carry bits cannot be propagated using existing instructions, vector multiple-precision multiplication relies on reduced-base arithmetic with padded zeros to spill carry bits and then process them using a scalar-add-with-carry instruction. With these instructions and hardware support from the processing unit, the processing unit 1) does not need to perform base conversion twice, 2) can utilize all bits in the vector arithmetic-logic unit (ALU) without requiring padding, and 3) performs multiple-precision multiplication faster because there is no spill and spilled carry bits do not need to be specially processed. Thus, the processing unit also significantly accelerates multiple-precision multiplication. In some embodiments, the processing unit uses multiple-precision addition, multiplication, and subtraction operations to perform multiple-precision division and various other mathematical operators more efficiently than conventional solutions.

[0027] When traditional vector addition (e.g., vpaddd) is used, all lanes are calculated independently of the result / carry of other lanes. The result of this vector operation (i.e., the "vector sum") can differ significantly from the "real sum." In some embodiments, the processing unit addresses this deficiency by performing carry propagation across all vector lanes to provide an accurate "real sum" in a way that is not possible using traditional vector addition.

[0028] 1A and 1B, collectively referred to as FIG. 1, illustrate an exemplary processing unit 100 for generating / propagating a carry bit for an integer multiple-precision addition (e.g., 512b) using a 1-bit FA and XOR gate per vector lane. In some other embodiments, other types of multi-bit adders (e.g., carry lookahead adders) may be used for performance, energy, and area reasons. Processing unit 100 cascades the carry bit of one adder in one vector lane to another vector lane to generate a carry bit for adding two multiple-precision values ​​together. Processing unit 100 includes multiple vector lanes 101-1 through 101-8, a first vector register 110, a second vector register 120, and a third vector register 130. In some embodiments, at least one of vector registers 110, 120, and 130 is a memory operand. In some embodiments, at least one of the first, second, and third vector registers 110, 120, 130 is instead conventional memory (e.g., double data rate (DDR) memory, low power DDR (LPDDR), etc.) and / or "fabric-attached memory" (e.g., Computer Express Link (CXL) memory, Gen-Z). Each of the first, second, and third vector registers 110 (zmm1), 120 (zmm2), 130 (zmm3) includes multiple vector register portions, the number of vector register portions equal to the number of vector lanes 101-1 through 101-8.

[0029] The first vector register 110 includes vector register portions 110-1 to 110-8 arranged in vector lanes 101-1 to 101-8, the second vector register 120 includes vector register portions 120-1 to 120-8, and the third vector register 130 includes vector register portions 130-1 to 130-8. Each of the first, second, and third vector registers 110, 120, and 130 is configured to store a Y-bit binary value (not shown), and each of the vector register portions 110-1 to 110-8, 120-1 to 120-8, and 130-1 to 130-8 is configured to store an X-bit binary portion (not shown) of the Y-bit binary value. In this example, the second vector register 120 stores the multiple-precision value A, the third vector register 130 stores the multiple-precision value B, Y is 512, and X is 64, so Y is an 8x multiple of X, although other multiples are possible.

[0030] Each of the vector lanes 101-1 through 101-8 further includes a data path including a plurality of adders 140-1 through 140-8, respectively. The adders 140-1 through 140-8 are configured to add first and second X-bit binary sub-values ​​of the first Y-bit binary value and the second Y-bit binary value. The adders 140-1 through 140-8 also generate carries or carry bits 151-1 through 151-8, respectively. In addition to the adders 140-1 through 140-8, each of the vector lanes 101-1 through 101-8 further includes a plurality of carry bit generation circuits 150-1 through 150-8, respectively coupled to the plurality of adders 140-1 through 140-8, for generating carry bits 154-1 through 154-8, respectively. Starting with adder 140-8, adder 140-8 generates a carry bit that cascades to vector lane 101-7, adder 140-7 generates a carry bit that cascades to vector lane 101-6, adder 140-6 generates a carry bit that cascades to vector lane 101-5, etc. Carry bits 154-1 through 154-8 generated by carry bit generation circuits 150-1 through 150-8 are ultimately used to add the first and second Y-bit binary values, with any carry bits generated before carry bits 154-1 through 154-8 being intermediate carry bits, i.e., intermediate carry bits that are later used to formulate carry bits 154-1 through 154-8.

[0031] Each of vector lanes 101-1 through 101-8 also includes a plurality of carry bit generation circuits 150-1 through 150-8 coupled to adders 140-1 through 140-8, respectively. Carry bit generation circuits 150-1 through 150-8 receive carry bits from adjacent ones of adders 140-1 through 140-8 and generate carry bits 154-1 through 154-8, respectively, based on carry bits 151-1 through 151-8. For example, carry bit generation circuit 150-1 receives carry bit 151-2 from adder 140-2, carry bit generation circuit 150-2 receives carry bit 151-3 from adder 140-3, carry bit generation circuit 150-3 receives carry bit 151-4 from adder 140-4, and so on. Additionally, the carry bit generation circuits 150-1 to 150-8 are configured to receive the sum of the first and second X-bit binary portions of the first Y-bit binary value and the second Y-bit binary value, respectively, stored by the second and third vector registers 120, 130. The carry bit generation circuits 150-1 to 150-8 generate carry bits 154-1 to 154-8, respectively, based on the sum of the first and second X-bit binary portions of the first and second Y-bit binary values ​​stored by the second and third vector registers 120, 130.

[0032] Carry bits 154-1 through 154-8 are stored in vector register portions 110-1 through 110-8, respectively, of first vector register portion 110. Adders 140-1 through 140-8 then use the generated carry bits 154-1 through 154-8 stored by vector register portions 110-1 through 110-8 to add the first and second Y-bit binary values ​​stored by second and third vector registers 120, 130, respectively, the details of which are described in more detail below with respect to FIG.

[0033] The carry bit generation circuits 150-1 through 150-8 may take on various configurations in various embodiments, and Figure 1 shows an exemplary configuration of the carry bit generation circuits 150-1 through 150-8. In the configuration shown in Figure 1, the carry bit generation circuits 150-1 through 150-8 each include a plurality of AND logic gates 152-1 through 152-8 (e.g., 64-bit AND gates), a plurality of 1-bit FAs 153-1 through 153-8, and a plurality of XOR logic gates 154-1 through 154-8. The AND logic gates 152-1 through 152-8 are configured to receive the sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the adders 140-1 through 140-8, respectively. The AND logic gates 152-1 to 152-8 are further configured to output binary values ​​to the single-bit FAs 153-1 to 153-8 and the XOR logic gates 154-1 to 154-8, respectively. The XOR logic gates 154-1 to 154-8 are configured to receive the binary values ​​output by the AND logic gates 152-1 to 152-8 and the binary values ​​output by the single-bit FAs 153-1 to 153-8, respectively. The XOR logic gates 154-1 to 154-8 are further configured to perform logical operations on these received binary values ​​and output carry bits 154-1 to 154-8 to the first vector register 110, specifically to the vector register portions 110-1 to 110-8, respectively.

[0034] The plurality of single-bit FAs 153-1 to 153-7 are configured to receive carry bits 151-2 to 151-8 from the adders 140-2 to 140-8, and are also configured to receive carry bits 155-2 to 155-8 from adjacent single-bit FAs 152-2 to 153-7, respectively. In contrast, the single-bit FA 152-8 is configured to receive a binary value of "0" and the MSB 111 of the first vector register 110. For example, the single-bit FA 152-1 receives the carry bit 155-2 from the single-bit FA 152-2, the single-bit FA 152-2 receives the carry bit 155-3 from the single-bit FA 152-3, the single-bit FA 152-3 receives the carry bit 155-4 from the single-bit FA 152-4, and so on. The single bit FA 152-8 receives a binary "0" instead of a carry bit from the adder 140, just as do the other single bits FA 152-1 to 152-7.

[0035] 1, carry bit generation circuit 150-1 differs from carry bit generation circuits 150-2 through 150-8 in that carry bit generation circuit 150-1 includes additional logic circuitry. Carry bit generation circuit 150-1 further includes OR logic gate 142 (e.g., a 64-bit logical OR gate) that receives carry bit 151-1 from adder 140-1 and the binary value from 1-bit FA 153-1, and outputs carry bit 143 to vector register portion 110-1 of first vector register 110.

[0036] 2A and 2B, collectively referred to as FIG. 2, illustrate another exemplary processing unit 200 for generating / propagating carry bits for integer multiple-precision additions (e.g., 512b) using vector carry propagation (VCP) circuits per vector lane. Processing unit 200 includes a datapath including multiple vector lanes 201-1 through 201-8, which include an alternative configuration for carry bit generation circuits 250-1 through 250-8, each including a VCP circuit. Processing unit 200 also provides an alternative configuration for generating and propagating carry bits for 512b integer multiple-precision additions in hardware. Processing unit 400 (FIG. 4) then computes the result of value A + value B + carry, as described above for processing unit 100, and includes some of the same features as shown in FIG. 1. These same features will not be described for brevity.

[0037] The carry bit generation circuits 250-1 to 250-8 each include a plurality of AND logic gates 252-1 to 252-8 (e.g., 64-bit AND gates) and a plurality of 1-bit VCP logic circuits 253-1 to 253-8. The plurality of AND logic gates 252-1 to 252-8 are configured to receive sums of the first and second X-bit binary portions of the first and second Y-bit binary values ​​from the plurality of adders 140-1 to 140-8, respectively. The plurality of AND logic gates 252-1 to 252-8 are also configured to output binary values ​​to the plurality of 1-bit VCP logic circuits 253-1 to 253-8, respectively.

[0038] The plurality of 1-bit VCP logic circuits 253-1 to 253-8 are configured to receive the binary values ​​output from the plurality of AND logic gates 252-1 to 252-8, the carry bits from the plurality of adders 140-1 to 140-8, and the binary values ​​output by adjacent ones of the plurality of 1-bit VCP logic circuits 253-1 to 253-8, respectively. For example, carry bit generation circuit 250-1 receives carry bit 251-2 from adder 140-2, carry bit generation circuit 250-2 receives carry bit 151-3 from adder 140-3, carry bit generation circuit 250-3 receives carry bit 151-4 from adder 140-4, and so on.

[0039] The plurality of 1-bit VCP logic circuits 253-1 to 253-7 are configured to output other binary values ​​to other adjacent ones of the plurality of 1-bit VCP logic circuits 253-2 to 253-8. The plurality of 1-bit VCP logic circuits 253-1 to 253-8 output carry bits 257-1 to 252-8 to the first vector register 110, particularly to vector register portions 110-1 to 110-8, respectively, and output carry bits 255-2 to 255-8 to adjacent ones of the 1-bit VCP logic circuits 253-1 to 253-7, respectively. The carry bits 257-1 to 251-8 are arranged in the least significant bits 113-1 to 213-8 of the vector lanes 201-1 to 201-8, respectively. The 1-bit VCP logic circuit 253-8 receives a binary "0" instead of the carry bit from the adder 140, just as the other 1-bit VCP logic circuits 253-1 to 253-7 do, and also receives the MSB 111.

[0040] For example, 1-bit VCP logic circuit 253-2 outputs carry bit 255-2 to 1-bit VCP logic circuit 253-1, 1-bit VCP logic circuit 253-3 outputs carry bit 255-2 to 1-bit VCP logic circuit 253-2, 1-bit VCP logic circuit 253-4 outputs carry bit 255-3 to 1-bit VCP logic circuit 253-2, and so on.

[0041] 2, carry bit generation circuit 250-1 differs from carry bit generation circuits 250-2 through 250-8 in that carry bit generation circuit 250-1 includes additional logic circuitry. Carry bit generation circuit 250-1 further includes OR logic gate 242 (e.g., a 64-bit logical OR gate) that receives carry bit 251-1 from adder 140-1 and outputs carry bit 243 to vector register portion 110-1 of first vector register 110. In some embodiments, carry bit 243 is stored in MSB 111 of vector register portion 110-1.

[0042] 3 illustrates an exemplary configuration of 1-bit VCP logic circuits 253-1 through 253-8 shown in FIG. 2, collectively referred to as 1-bit VCP logic circuit 253. 1-bit VCP logic circuit 253 is an optimization for combining carry generation and propagation into a single (simple) logic block. 1-bit VCP logic circuit 253 includes OR logic gate 310 coupled to AND logic gate 320. OR logic gate 310 is configured to receive carry bit 251 on a first input 311 and carry bit 255 on a second input 312. OR logic gate 310 outputs carry bit 257 on output 313.

[0043] AND logic gate 320 is configured to receive on a first input 321 the carry bit 257 from the output 313 of OR logic gate 310. AND logic gate 320 is further configured to receive on a second input 322 the binary value output by AND logic gate 252. AND logic gate 320 is further configured to output carry bit 255.

[0044] FIG. 4 illustrates exemplary hardware components of the processing units 100, 200 of FIGS. 1 and 2 configured with a separate data path to perform multiple-precision 512b addition. The carry bit generation circuits 150-1 through 150-8, 250-1 through 250-8 shown in FIGS. 1 and 2, respectively, have been omitted from the diagram for simplicity. FIG. 4 illustrates the common data path component, adder 140, from FIGS. 1 and 4. After a carry bit is generated by either processing unit 100, 200 and stored in vector register portions 110-1 through 110-8 of first vector register 110, the addition of multiple-precision A and multiple-precision B can be performed by adders 140-1 through 140-8.

[0045] 4, the processing units 100, 200 calculate the result of value A (e.g., a 512-bit multiple-precision binary value stored in the second vector register 120) + value B (e.g., another 512-bit multiple-precision binary value stored in the third vector register 130) + carry. The processing unit 100 first generates and propagates the carry bit. The processing unit 100 performs the vector carry generation and propagation for this 512b addition operation. The instruction to generate / propagate a carry bit (generate_carry_512) has three input operands: a value stored in a first vector register 110 (the carry; only the most significant bit (MSB) 111 of the first vector register 110 is used; all other bits are ignored); a value stored in a second vector register 120 (a first 512-bit multiple-precision value A); and a value stored in a third vector register 130zmm3 (which stores a second 512-bit multiple-precision value B). In some embodiments, some operands may be memory operands instead of register operands. In some embodiments, the generate_carry instruction may have a version with an implicit 0 carry-in value.

[0046] The operation destination register (first vector register 110) of processing unit 100, 200 is written with 1) the "carry bit" (i.e., the carry bit used in updating a "vector sum" to a "real sum") and 2) the "carry-out" bit of a 512-bit addition operation, allowing multiple 512b additions to be chained together to perform additions to larger numbers (e.g., two 1024b additions can be chained together to perform a 512b addition). These "carry bits" are located in the least significant bits 113-1 through 113-8 of vector lanes 101-1 through 101-8, respectively. The "carry-out" bit or carry bit 143 is located in the MSB 111 of a destination register, such as first vector register 110, but may be located in other unused bits in different embodiments.

[0047] A new ISA instruction to be added to the existing ISA instruction set for performing addition using adders 140-1 to 140-8 (complete_wide_add) has three input operands, namely carry bits 154-1 to 154-8, 257-1 to 257-8 stored by a first vector register 110 in the least significant bits 113-1 to 113-8 of all vector lanes 101-1 to 101-8, 201-1 to 201-8, the MSB 111 of the first vector register 110 being used to chain the 512b addition during the generation of the carry bit is ignored, a 512b multiple precision value A is stored in a second vector register 120, and a 512b multiple precision value B is stored in a third vector register 130.

[0048] Adders 140-1 through 140-8 receive portions of multiple precision A and multiple precision B from vector lanes 101-1 through 101-8, 201-1 through 201-8, respectively. The adders also receive previously generated carry bits that were previously stored in least significant bits 113-1 through 113-8 of all vector lanes 101-1 through 101-8, 201-1 through 201-8. Adders 140-1 through 140-8 then add multiple precision A to multiple precision B using the carry bits from each of vector lanes 101-1 through 101-8, 201-1 through 201-8, respectively, to arrive at the appropriate portion of the sum of multiple precision A and multiple precision B. Processing units 100, 200 then update second vector register 120 with the correct sum for this operation. In some embodiments, the first vector register 110 should not be overwritten so that it can be preserved to provide a "carry-out" for chaining subsequent additional 512b additions. Thus, to facilitate multiple-precision additions using existing 64b adders, such as in a single instruction, multiple data (SIMD) datapath, vector lanes 101-1 through 101-8, 201-1 through 201-8 are extended with a "carry-in" carry bit provided by utilizing a bit in the first vector register 110.

[0049] Processing units 100, 200 are configured to generate / propagate carry bits for 512b multiple precision addition. However, the carry bit generation / propagation described above for multiple precision addition can be applied to smaller multiple precisions, such as greater than 64 bits but less than 512 bits. Figures 5A and 5B, collectively referred to as Figure 5, show an exemplary processing unit 500 capable of simultaneously performing carry generation / propagation for 2 x 256b multiple precision addition.

[0050] Processing unit 500 includes a data path that generates / propagates a carry bit for the result of two values ​​of A plus two values ​​of B plus a carry bit for each of the two values. Processing unit 500 includes some of the same features as shown in FIG. 1, but for brevity, they are not described. Processing unit 500 utilizes vector lanes 501-1 through 501-4 to calculate the first A+B+carry and vector lanes 501-5 through 501-8 to calculate the second A+B+carry, as described above in the singular for processing unit 200. Thus, processing unit 500 can simultaneously generate / propagate carry bits for the two additions, thereby replicating the unique features from processing unit 200.

[0051] To perform two carry bit propagations / generations simultaneously, processing unit 500 includes a second copy of carry bit generation circuit 250-1, which is shown in vector lane 501-5 as carry bit generation circuit 550-5. Thus, vector lanes 501-5 through 504 generate the carry bit for the first 256b multiple-precision addition, and vector lanes 501-5 through 501-8 generate the carry bit for the second 256b multiple-precision addition, doubled as described above with respect to FIG. 2, where processing unit 200 generates the carry bit for a single 512b multiple-precision addition. Similarly, instead of using a single one of the MSBs 111 to generate a carry bit that is stored in the least significant bits 113-1 to 113-8 of vector lanes 501-1 to 501-8, processing unit 500 uses the MSB 111 to generate a carry bit that is stored in the least significant bits 113-1 to 113-4 of vector lanes 101-1 to 101-4, and uses another valid bit 511 from vector lane 501-5 to generate a carry bit that is stored in the least significant bits 113-1 to 113-4 of vector lanes 501-1 to 501-4.

[0052] This concept can be extended to smaller multi-precision adds. In some embodiments, the instructions generate_carry_256 and generate_carry_128 can simultaneously perform 2×256b and 4×128b adds, respectively. The hardware for generate_carry_256 is shown in FIG. 5. Similarly, generate_carry_128 utilizes two more OR gates and two more bits stored in the first vector register 110. In some embodiments, these 2×256b and 4×128b add operations do not require different instructions to perform the final completion of the entire add. The same complete_wide_add instruction described above can be used after generate_carry_512 / 256 / 128.

[0053] The concepts disclosed above for multiple-precision addition can be extended to multiple-precision subtraction. Figures 6A and 6B, collectively referred to as Figure 6, illustrate an exemplary processing unit 600 for generating / propagating a carry bit for integer multiple-precision subtraction (e.g., 512b). The processing unit 600 includes a data path that generates and propagates a carry bit for multiple-precision B stored in a third vector register 130 to be subtracted from multiple-precision A stored in a second vector register 120, such as for a generate_sub_carry_512 instruction. The processing unit 600 exploits the fact that AB = A + (-B), and -B in two's complement notation can be calculated by ~B + 1 (bitwise invert / NOT of B, followed by increment). Figure 6 illustrates the data path for the generate_sub_carry_512 instruction. In some embodiments, this instruction is used for the first 512b subtraction operation in a chain of 512b subtraction operations, and the first vector register 110 is not used as an input. The initial carry 601 into the first "1b VCP" block is set to 1. The reciprocal of B is taken (one's complement). The first carry-in bit is used to represent (-B) (two's complement).

[0054] 2, and these same features will not be described here for the sake of brevity. To facilitate generating the complement of multiple precision B stored in third vector register 130 so that processing unit 600 can subtract multiple precision B from multiple precision A, processing unit 600 further includes a plurality of bitwise invert / not logic 610-1 through 610-8.

[0055] The processing unit 600 includes a plurality of bitwise inversion / not logic gates 610-1 to 610-8 for each of the vector lanes 601-1 to 601-8, respectively. The plurality of bitwise inversion / not logic gates 610-1 to 610-8 are coupled to the second vector register 120, specifically to the vector register portions 120-1 to 120-8. The plurality of bitwise inversion / not logic gates 610-1 to 610-8 are configured to receive the 64b portions of multiple precision B from the vector register portions 120-1 to 120-8 of the second vector register 120, respectively. The plurality of bitwise inversion / not logic gates 610-1 to 610-8 perform bitwise inversion of the 64b portions of multiple precision B. The plurality of bitwise inversion / not logic gates 610-1 to 610-8 further outputs the 64b portions of multiple length B to the plurality of carry bit generation circuits 250-1 to 250-8, respectively.

[0056] 7A and 7B, collectively referred to as FIG. 7, illustrate an exemplary processing unit 700 for generating / propagating a carry bit for chaining multiple 512b subtraction operations. Processing unit 700 includes a separate data path 711 for generating and propagating a carry bit for such chained operations. Processing unit 700 includes all of the hardware shown in FIG. 2. These same features will not be described here for the sake of brevity. Processing unit 700 further includes multiple bitwise invert / not logic 610-1 through 610-8 to facilitate generating the complement of multiple precision B stored in third vector register 130 so that processing unit 600 can generate / propagate a carry bit for subtracting multiple precision B from multiple precision A.

[0057] An additional carry bit can be generated using a separate generate_sub_carry_chained_512 instruction for all but the first 512b subtraction. This first instruction does not use an initial carry bit as 1, but instead uses the carry bit set in the MSB 111 of the first vector register 110 populated by the previous generate_sub_carry_(chained)_512 instruction. Thus, the carry bit generation circuit 250-8 receives the carry bit from this previous generate_sub_carry_(chained)_512 instruction via data path 711, which is from the MSB 111 of the first vector register 110. In some embodiments, these two instructions can be combined to utilize a separate static field, for example, encoded in the immediate value, that controls whether the carry-in should be forced into the first vector register 110 or whether the carry-in should be taken from the first vector register 110.

[0058] 8A and 8B, collectively referred to as FIG. 8, illustrate an exemplary processing unit 800 capable of generating / propagating carry bits for both multiple-precision addition and subtraction. Processing unit 800 includes all of the hardware shown in FIG. 6. These same features will not be described here for brevity. Processing unit 800 includes a data path further including a plurality of multiplexers 810-1 through 810-8 for each of vector lanes 801-1 through 801-8. Multiplexers 810-1 through 810-8 are coupled to second vector register 120, specifically vector register portions 120-1 through 120-8, respectively. Multiplexers 810-1 through 810-8 are configured to receive bitwise-inverted X-bit binary portions from a plurality of bitwise-invert / NOT logic gates of a plurality of bitwise-invert / NOT logic gates 610-1 through 610-8, respectively. The plurality of multiplexers 810-1 to 810-8 are further configured to receive the plurality of second X-bit binary portions from the vector register portions 120-1 to 120-8 of the second vector register 120, respectively.

[0059] The multiplexers 810-1 to 810-8 further receive binary values ​​from adjacent multiplexers 810 and output the binary values ​​to each other adjacent multiplexer 810. For example, multiplexer 810-2 receives a binary value from multiplexer 810-3 and outputs the binary value to multiplexer 810-1, multiplexer 810-3 receives a binary value from multiplexer 810-4 and outputs the binary value to multiplexer 810-2, multiplexer 810-4 receives a binary value from multiplexer 810-5 and outputs the binary value to multiplexer 810-3, and so on. Multiplexers 810-1 to 810-8 further output the multiplexed binary values ​​to adders 140-1 to 140-8, respectively. Multiplexer 810-1 differs from the other multiplexers in that it outputs only to adder 140-1 and not to another multiplexer 810. Similarly, multiplexer 810-8 differs from the other multiplexers 810 in that multiplexer 810-8 receives a control bit 811 that controls whether addition or subtraction is being performed by processing unit 800.

[0060] The processing unit 800 further includes another multiplexer, multiplexer 820. The multiplexer 820 receives a first input, a binary "1" at the MSB 111 from the first vector register 110. The multiplexer 820 also receives a control bit 821 that controls whether the processing unit 800 is processing an add operation (without chaining) or a chained operation. If the processing unit 800 is configured to perform a chained operation, the multiplexer 820 processes the MSB 111 from the first vector register 110. Otherwise, the multiplexer 820 processes a binary "1" on its other input.

[0061] Processing unit 800 is configured to generate / propagate carry bits for adding and subtracting two 512b multiple precisions, A+ / -B. However, the carry bit generation described above for multiple precision addition and subtraction may be applied to smaller multiple precisions, such as >64 bits but <512 bits. Figures 9A and 9B, collectively referred to as Figure 9, show an exemplary processing unit 900 capable of performing carry generation / propagation for adding and subtracting 2x256b multiple precisions.

[0062] Processing unit 900 calculates the result of two values ​​of A + two values ​​of B + a carry bit for each of the two values. Processing unit 900 includes some of the same features shown in FIG. 8 . These same features will not be described here for brevity. Processing unit 900 includes a data path that utilizes vector lanes 901-1 through 901-4 to calculate a first A+ / -B+ carry and vector lanes 901-5 through 901-8 to calculate a second A+ / -B+ carry, as described above in the singular for processing unit 800. Thus, processing unit 900 can simultaneously perform carry bit generation / propagation for the two additions / subtractions, thereby replicating the unique features from processing unit 800.

[0063] To simultaneously generate / propagate the carry bits for these two additions / subtractions, processing unit 900 includes a second copy of carry bit generation circuit 250-1. The second copy of carry bit generation circuit 250-1 is shown in vector lane 901-5 as carry bit generation circuit 950-5. Thus, vector lanes 901-904 generate the carry bit for the first 256b multiple-precision addition / subtraction, and vector lanes 901-5-901-8 generate the carry bit for the second 256b multiple-precision addition / subtraction, doubled as described above for FIG. 8 in which processing unit 800 generates the carry bit for the single 512b multiple-precision addition / subtraction. Similarly, instead of using a single one of the MSBs 111 to generate the carry bit stored in the least significant bits 113-1 to 113-8 of vector lanes 901-1 to 901-8, processing unit 900 uses MSB 111 to generate the carry bit stored in the least significant bits 113-1 to 113-4 of vector lanes 101-1 to 101-4, and uses another significant bit 911 from vector lane 901-5 to generate the carry bit stored in the least significant bits 113-1 to 113-4 of vector lanes 901-1 to 901-4. To perform a 128b or 256b subtraction, all multiple-precision initial carry-in bits are set to 1, as shown in Figure 9 using the example of a 2 x 256b subtraction.

[0064] 10A and 10B, collectively referred to as FIG. 10, illustrate the processing unit 800 shown in FIG. 8 configured to perform multiple-precision 512b addition / subtraction. Note that the carry bit generation circuits 250-1 through 250-8 shown in FIG. 8 are omitted for simplicity. After the carry bit is generated by the processing unit 800 and stored in the vector register portions 110-1 through 110-8 of the vector register 110, the processing unit 800 includes a data path that allows adders 140-1 through 140-8 to perform the addition / subtraction of multiple-precision A and multiple-precision B. The combination of multiplexers 810-1 through 810-8 and bitwise invert / not logic 610-1 through 610-8 controls whether a bitwise inverted version of multiple-precision B is received by adders 140-1 through 140-8 to perform the subtraction or a non-bitwise inverted version of multiple-precision B to perform the addition.

[0065] The new ISA instructions added to the existing ISA instruction set to perform addition / subtraction using adders 140-1 through 140-8 (complete_wide_add / sub) have three input operands: (1) carry bits 257-1 through 257-8 stored by the first vector register 110 in the least significant bits 113-1 through 113-8 of all vector lanes 801-1 through 801-8, with the MSB 111 of the first vector register 110 ignored and used to chain 512b the addition / subtraction while generating the carry bit; (2) a multiple-precision value A of 512b stored in the second vector register 120; and (3) a multiple-precision value B of 512b stored in the third vector register 130.

[0066] Adders 140-1 through 140-8 receive portions of multiple-precision A and multiple-precision B from vector lanes 801-1 through 801-8, respectively. Adders 140-1 through 140-8 also receive previously generated carry bits that were previously stored in least significant bits 113-1 through 113-8 of all vector lanes 801-1 through 801-8. Adders 140-1 through 140-8 then add / subtract multiple-precision A from multiple-precision B, respectively, using the carry bits from each of vector lanes 801-1 through 801-8 to arrive at their respective portions of the sum of multiple-precision A and multiple-precision B. Processing unit 800 then updates second vector register 120 with the correct sum / difference of this operation. In some embodiments, first vector register 110 should not be overwritten so that it can be preserved to provide a "carry-out" for chaining subsequent additional 512b additions / subtractions. Therefore, to facilitate multiple-precision addition / subtraction using an existing 64b adder, such as in a single instruction multiple data (SIMD) datapath, the existing 64b adder is extended with a "carry-in" or carry bit provided by utilizing a bit in the first vector register 110.

[0067] 11A and 11B, collectively referred to as FIG. 11, illustrate yet another configuration of an exemplary processing unit 1100 based on the configuration of processing unit 200 shown in FIG. 2 for adding two multiple-precision binary values ​​without first having to store the carry bit in a vector register. If the MSB 111 (zmm1) from the first vector register 110 is not needed to chain the multiple-precision calculation to a larger integer (i.e., if all operations in the calculation require <= 512b additions), then the first vector register 110 is not needed to store the carry bit for the next stage. In such cases, the processing unit 1100 can be used to include a data path for performing both the carry generation and the subsequent multiple-precision addition using a single instruction, such as zmm1 = zmm2 + zmm3.

[0068] Processing unit 1100 includes all of the hardware shown in Figure 6. These same features will not be described here for the sake of brevity. However, instead of carry bit generation circuits 250-1 through 250-8 outputting carry bits to first vector register 110, and particularly vector register portions 110-1 through 110-8, respectively, as described above with respect to Figure 2, processing unit 1100 utilizes carry bit generation circuits 250-1 through 250-8 that output carry bits to adders, such as adders 1140-1 through 1140-8. Adders 1140-1 through 1140-8 receive multiple precision A, multiple precision B, and the carry bits from carry bit generation circuits 250-1 through 250-8. Adders 1140-1 to 1140-8 can then add multiple precision A+multiple precision B using the carry bit received from carry bit generation circuits 250-1 to 250-8 to arrive at the correct sum of multiple precision A+multiple precision B.

[0069] The processing unit 1100 shows two adders 140-1 / 1140-1, 140-2 / 1140-2, 140-3 / 1140-3, 140-4 / 1140-4, 140-5 / 1140-5, 140-6 / 1140-6, 140-7 / 1140-7, 140-8 / 1140-8 (e.g., 64b+ adder blocks) for each vector lane 1101-1 to 1101-8. In one embodiment, adders 140-1 / 1140-1, 140-2 / 1140-2, 140-3 / 1140-3, 140-4 / 1140-4, 140-5 / 1140-5, 140-6 / 1140-6, 140-7 / 1140-7, and 140-8 / 1140-8 are distinct from one another, and processing unit 1100 utilizes two adders per vector lane 1101-1 through 1101-8. In another embodiment, adder 140 is the same component as adder 1140, and adder 140 is reused across instructions in a pipelined manner. Thus, in this embodiment, the same adder 140 / 1140 is used both to generate the carry bit and to add multiple-precision A+B.

[0070] Figure 12 shows an example critical path for a chained 512b addition. Although the 512b addition operation uses two instructions, chaining them together to perform additions on larger integers may be faster in terms of adds / cycles because the critical path to perform the calculation is only one instruction (generate_carry_512).

[0071] FIG. 13 shows an example method 1300 for generating a carry bit and adding first and second binary values. The method begins at block 1310. In block 1310, if Y is a multiple of X, first and second X-bit binary partial values ​​of the first Y-bit binary value and the second Y-bit binary value are used to generate a first carry bit. In some embodiments, adders 140-1 through 140-8 are used to add the first and second X-bit binary partial values ​​of the first Y-bit binary value and the second Y-bit binary value. Following the example given above, the first Y-bit binary value may be 512b multiple-precision A, and the second Y-bit binary value may be 512b multiple-precision B. In some embodiments, the first carry bit may be carry bits 151-1 through 151-8.

[0072] In block 1320, a second carry bit is generated based on the first carry bit. In some embodiments, carry bit generation circuits 150-1 through 150-8, 250-1 through 250-8 are used to generate the second carry bit. In some embodiments, the second carry bit may be carry bits 154-1 through 154-8, 257-1 through 257-8.

[0073] In block 1330, the first and second X-bit binary portions of the first and second Y-bit binary values ​​are added, respectively, using the second carry bit. In some embodiments, adders 140-1 through 140-8 use carry bits 154-1 through 154-8, 257-1 through 257-8 to add the 64-b portions of the 512-b multiple precision A and B. Adders 140-1 through 140-8 can receive carry bits 154-1 through 154-8, 257-1 through 257-8, respectively, from vector register portions 110-1 through 110-8 of first vector register 110.

[0074] Processing units 100-1100 can chain 512b operations to perform additions for multiple precisions greater than 512b, such as 1024b. The following pseudocode can be used to chain two 512b additions to perform a 1024b addition: mov zmm1,[zeros]; Set initial carry-in to zero mov zmm2,[ALO];1024b lower 512b of operand A mov zmm3,[BLO];1024b lower 512b of operand B generate_carry_512zmm1,zmm2,zmm3;zmm1=carry bit complete_wide_add zmm2,zmm3,zmm1;zmm2=sum mov zmm4,[AHI]; 1024b upper 512b of operand A mov zmm5,[BHI]; 1024b upper 512b of operand B generate_carry_512zmm1,zmm4,zmm5;zmm1=carry bit complete_wide_add zmm4,zmm5,zmm1;zmm4=sum ;DONE: sum of lower 512b of zmm2, upper 512b of zmm4 ;zmm1 holds the carry out of the 1024b addition if an additional addition is performed

[0075] In some embodiments, the above-described apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing units 100-1100 described above with reference to FIGS. 1-11. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system for operating the computer system to operate on code representing the circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC devices is stored in and accessed from the same or a different computer-readable storage medium.

[0076] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS)-based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0077] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s). The executable instructions stored on the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0078] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, that some of the particular activities or devices may not be required, that one or more additional activities may be performed, and that one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will recognize that various modifications and variations can be made without departing from the scope of the invention as set forth in the claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

[0079] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, since the disclosed invention may be modified and practiced in different, but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and that all such variations are considered within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. A processing unit, a plurality of adders for adding a first X-bit binary portion value of a first Y-bit binary value and a second X-bit binary portion value of a second Y-bit binary value to generate a first carry bit, where Y is a multiple of X; a plurality of carry bit generation circuits respectively coupled to the plurality of adders, the plurality of carry bit generation circuits receiving the first carry bit and generating a second carry bit based on the first carry bit; the second carry bit is used to add the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value. Processing unit.

2. each of the plurality of carry bit generation circuits is configured to receive an addition value of the first X-bit binary partial value of the first Y-bit binary value and the second X-bit binary partial value of the second Y-bit binary value, and to generate the second carry bit based on the addition value of the first X-bit binary partial value of the first Y-bit binary value and the second X-bit binary partial value of the second Y-bit binary value; The processing unit of claim 1.

3. the first Y-bit binary value and the second Y-bit binary value are stored by at least one of a vector register, a memory operand, a double data rate (DDR) memory, a low power DDR (LPDDR), and Gen-Z; The processing unit of claim 1.

4. a new Instruction Set Architecture (ISA) instruction is added to an existing ISA instruction set for adding the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value; The processing unit of claim 1.

5. Each of the plurality of carry bit generation circuits a plurality of AND logic gates; a plurality of 1-bit full adders; a plurality of XOR logic gates; Each of the plurality of AND logic gates receiving a sum of the first X-bit binary subvalue of the first Y-bit binary value and the second X-bit binary subvalue of the second Y-bit binary value from the plurality of adders; outputting binary values ​​to the plurality of 1-bit full adders and the plurality of XOR logic gates; and The plurality of 1-bit full adders include: receiving the binary values ​​output from the plurality of AND logic gates, the first carry bits from the plurality of adders, and binary values ​​from adjacent 1-bit full adders; Outputting a binary value; and The plurality of XOR logic gates receiving the binary values ​​output from the plurality of AND logic gates and the binary values ​​output from the plurality of 1-bit full adders; outputting the second carry bit to a vector register; configured to: The processing unit of claim 1.

6. The plurality of carry bit generation circuits include: a plurality of AND logic gates; a plurality of 1-bit vector carry propagate (VCP) logic circuits; Each of the plurality of AND logic gates receiving a sum of the first X-bit binary subvalue of the first Y-bit binary value and the second X-bit binary subvalue of the second Y-bit binary value from the plurality of adders; outputting a binary value to the plurality of 1-bit vector carry propagate (VCP) logic circuits; and The plurality of 1-bit VCP logic circuits receiving the binary values ​​from the plurality of AND logic gates, receiving the first carry bits from the plurality of adders, and receiving the binary values ​​output from adjacent ones of the plurality of 1-bit VCP logic circuits; outputting another binary value to another adjacent one of the plurality of 1-bit VCP logic circuits; outputting the second carry bit to a vector register; configured to: The processing unit of claim 1.

7. the plurality of AND logic gates are a plurality of first AND logic gates; Each of the 1-bit VCP logic circuits a plurality of OR logic gates; a plurality of second AND logic gates; the plurality of OR logic gates are configured to receive the binary values ​​output from the plurality of first AND logic gates and the first carry bit from the plurality of adders; Each of the plurality of second AND logic gates comprises: receiving the first carry bits from the plurality of adders and the binary values ​​output by the plurality of OR logic gates; outputting the second carry bit to the vector register; configured to: The processing unit of claim 6.

8. the vector register is a first vector register, The processing unit a plurality of bitwise invert / not logic gates; each of the plurality of bitwise invert / not logic gates is coupled to a second vector register and configured to receive the second X-bit binary partial value, bitwise invert the second X-bit binary partial value of the second Y-bit binary value, and output the bitwise inverted X-bit binary partial value of the second X-bit binary partial value to the plurality of carry bit generation circuits; The processing unit of claim 6.

9. The plurality of carry bit generation circuits include: a plurality of multiplexers; each of the plurality of multiplexers is coupled to a second vector register and configured to receive the bitwise inverted X-bit binary subvalue of the second Y-bit binary value from the plurality of bitwise invert / not logic gates, receive the second X-bit binary subvalue, receive a binary value from an adjacent multiplexer, and output the binary value to another adjacent multiplexer; The processing unit of claim 8.

10. A system including the processing unit of any one of claims 1 to 9, the system comprises a separate processing unit; the other processing unit comprises the plurality of adders and the plurality of carry bit generation circuits; system.

11. a vector register for storing an addition value of the first X-bit binary partial value of the first Y-bit binary value and the second X-bit binary partial value of the second Y-bit binary value; The processing unit of claim 1.

12. the plurality of adders is a first plurality of adders; The processing unit a second plurality of adders for adding the first Y-bit binary value of a first vector register and the second Y-bit binary value of a second vector register; The processing unit of claim 11.

13. the plurality of adders add the first Y-bit binary value of the first vector register and the second Y-bit binary value of the second vector register; 13. The processing unit of claim 12.

14. 1. A method comprising: a plurality of adders adding a first X-bit binary portion value of the first Y-bit binary value and a second X-bit binary portion value of the second Y-bit binary value to generate a first carry bit, where Y is a multiple of X; a plurality of carry bit generation circuits generating a second carry bit based on the first carry bit; adding a first X-bit binary portion value of the first Y-bit binary value and a second X-bit binary portion value of the second Y-bit binary value using the second carry bit. method.

15. each of the plurality of carry bit generation circuits receiving a sum of the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value; the plurality of carry bit generation circuits generating the second carry bit based on an addition value of the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value.

15. The method of claim 14.

16. at least one of a vector register, a memory operand, a double data rate (DDR) memory, a low power DDR (LPDDR), and a Gen-Z memory storing the first Y-bit binary value and the second Y-bit binary value; 15. The method of claim 14.

17. each of the carry bit generation circuits comprises a plurality of AND logic gates, a plurality of 1-bit full adders, and a plurality of XOR logic gates; The method comprises: each of the plurality of AND logic gates receiving a sum of the first X-bit binary subvalue of the first Y-bit binary value and the second X-bit binary subvalue of the second Y-bit binary value; each of the plurality of AND logic gates outputs a binary value to the plurality of 1-bit full adders and the plurality of XOR logic gates; the plurality of 1-bit full adders receiving the binary values ​​output from the plurality of AND logic gates, the first carry bits from the plurality of adders, and binary values ​​from adjacent 1-bit full adders; the plurality of 1-bit full adders outputting binary values; the plurality of XOR logic gates receiving the binary values ​​output from the plurality of AND logic gates and the binary values ​​output from the plurality of 1-bit full adders; the plurality of XOR logic gates outputting the second carry bit to a vector register.

15. The method of claim 14.

18. each of the carry bit generation circuits comprises a plurality of AND logic gates and a plurality of 1-bit vector carry propagation (VCP) logic circuits; The method comprises: each of the plurality of AND logic gates receiving an addition value of the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value from the plurality of adders; each of the plurality of AND logic gates outputting a binary value to the plurality of one-bit vector carry propagate (VCP) logic circuits; the plurality of 1-bit VCP logic circuits receiving the binary values ​​from the plurality of AND logic gates, the first carry bits from the plurality of adders, and the binary values ​​output from adjacent ones of the plurality of 1-bit VCP logic circuits; the plurality of 1-bit VCP logic circuits outputting another binary value to another adjacent one of the plurality of 1-bit VCP logic circuits and outputting the second carry bit to a vector register.

15. The method of claim 14.

19. a vector register storing an addition value of the first X-bit binary partial value of the first Y-bit binary value and the second X-bit binary partial value of the second Y-bit binary value; 15. The method of claim 14.

20. A processing unit, a first vector register for storing a first Y-bit binary value including a plurality of first X-bit binary subvalues, where Y is a multiple of X; a second vector register for storing a second Y-bit binary value including a plurality of second X-bit binary sub-values; a plurality of adders for adding the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value to generate a first carry bit; a plurality of carry bit generation circuits respectively coupled to the plurality of adders, the plurality of carry bit generation circuits receiving the first carry bit and generating a second carry bit based on the first carry bit; the plurality of adders add the first X-bit binary portion value of the first Y-bit binary value and the second X-bit binary portion value of the second Y-bit binary value using the second carry bit; Processing unit.

Images